RE: [PATCH] drm/amdgpu: correct gpu clock counter query on cyan skilfish
[AMD Official Use Only - General]
Reviewed-by: Aaron Liu
> -Original Message-
> From: Yu, Lang
> Sent: Thursday, September 21, 2023 2:06 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Liu, Aaron
> ; Zhang, Yifan ;
> sta...@vger.kernel.org
> Subject: Re: [PATCH] drm/amdgpu: correct gpu clock counter query on cyan
> skilfish
>
> O 09/21/ , Lang Yu wrote:
>
> Sorry for sending this patch twice. Please ignore this one.
>
> Regards,
> Lang
>
> > Cayn skilfish uses SMUIO v11.0.8 offset.
> >
> > Signed-off-by: Lang Yu
> > Cc: # v5.15+
> > ---
> > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 21 +
> > 1 file changed, 21 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > index 1d671c330475..c16ca611886b 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > @@ -102,6 +102,11 @@
> > #define mmGCR_GENERAL_CNTL_Sienna_Cichlid
> 0x1580
> > #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0
> >
> > +#define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish0x0105
> > +#define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish_BASE_IDX 1
> > +#define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish0x0106
> > +#define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish_BASE_IDX 1
> > +
> > #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh0x0025
> > #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX 1
> > #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh0x0026
> > @@ -7313,6 +7318,22 @@ static uint64_t
> gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
> > uint64_t clock, clock_lo, clock_hi, hi_check;
> >
> > switch (adev->ip_versions[GC_HWIP][0]) {
> > + case IP_VERSION(10, 1, 3):
> > + case IP_VERSION(10, 1, 4):
> > + preempt_disable();
> > + clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0,
> mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish);
> > + clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0,
> mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish);
> > + hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0,
> mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish);
> > + /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit
> carry over
> > +* roughly every 42 seconds.
> > +*/
> > + if (hi_check != clock_hi) {
> > + clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0,
> mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish);
> > + clock_hi = hi_check;
> > + }
> > + preempt_enable();
> > + clock = clock_lo | (clock_hi << 32ULL);
> > + break;
> > case IP_VERSION(10, 3, 1):
> > case IP_VERSION(10, 3, 3):
> > case IP_VERSION(10, 3, 7):
> > --
> > 2.25.1
> >
RE: [PATCH] drm/amdgpu/sdma4: set align mask to 255
[AMD Official Use Only - General]
Reviewed-by: Aaron Liu
> -Original Message-
> From: amd-gfx On Behalf Of Alex
> Deucher
> Sent: Tuesday, June 13, 2023 5:48 AM
> To: Deucher, Alexander
> Cc: amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/amdgpu/sdma4: set align mask to 255
>
> ping?
>
> On Wed, Jun 7, 2023 at 12:31 PM Alex Deucher
> wrote:
> >
> > The wptr needs to be incremented at at least 64 dword intervals, use
> > 256 to align with windows. This should fix potential hangs with
> > unaligned updates.
> >
> > Signed-off-by: Alex Deucher
> > ---
> > drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 ++--
> > drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 4 ++--
> > 2 files changed, 4 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> > b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> > index 1f83eebfc8a7..cd37f45e01a1 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> > @@ -2312,7 +2312,7 @@ const struct amd_ip_funcs sdma_v4_0_ip_funcs = {
> >
> > static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = {
> > .type = AMDGPU_RING_TYPE_SDMA,
> > - .align_mask = 0xf,
> > + .align_mask = 0xff,
> > .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
> > .support_64bit_ptrs = true,
> > .secure_submission_supported = true, @@ -2344,7 +2344,7 @@
> > static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = {
> >
> > static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs = {
> > .type = AMDGPU_RING_TYPE_SDMA,
> > - .align_mask = 0xf,
> > + .align_mask = 0xff,
> > .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
> > .support_64bit_ptrs = true,
> > .secure_submission_supported = true, diff --git
> > a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
> > b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
> > index 8eebf9c2bbcd..05bb0691ee0e 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
> > @@ -1823,7 +1823,7 @@ const struct amd_ip_funcs sdma_v4_4_2_ip_funcs =
> > {
> >
> > static const struct amdgpu_ring_funcs sdma_v4_4_2_ring_funcs = {
> > .type = AMDGPU_RING_TYPE_SDMA,
> > - .align_mask = 0xf,
> > + .align_mask = 0xff,
> > .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
> > .support_64bit_ptrs = true,
> > .get_rptr = sdma_v4_4_2_ring_get_rptr, @@ -1854,7 +1854,7 @@
> > static const struct amdgpu_ring_funcs sdma_v4_4_2_ring_funcs = {
> >
> > static const struct amdgpu_ring_funcs sdma_v4_4_2_page_ring_funcs = {
> > .type = AMDGPU_RING_TYPE_SDMA,
> > - .align_mask = 0xf,
> > + .align_mask = 0xff,
> > .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
> > .support_64bit_ptrs = true,
> > .get_rptr = sdma_v4_4_2_ring_get_rptr,
> > --
> > 2.40.1
> >
RE: [PATCH] drm/amdmgpu: don't enable secure display on incompatible platforms
[AMD Official Use Only - General]
Just a nit-pick for "drm/amdgpu".
With this fixed, Reviewed-by: Aaron Liu
> -Original Message-
> From: Jesse Zhang
> Sent: Friday, May 19, 2023 9:53 AM
> To: Deucher, Alexander
> Cc: Shavakh, Shadi ; Strauss, Andrew
> ; amd-gfx@lists.freedesktop.org; Zhang, Jesse(Jie)
> ; Liu, Aaron
> Subject: [PATCH] drm/amdmgpu: don't enable secure display on incompatible
> platforms
>
> [why]
> [drm] psp gfx command LOAD_TA(0x1) failed and response status is (0x7) [drm]
> psp gfx command INVOKE_CMD(0x3) failed and response status is (0x4) amdgpu
> :04:00.0: amdgpu: Secure display: Generic Failure.
>
> [how]
> don't enable secure display on incompatible platforms
>
> Suggested-by: Aaron Liu
> Signed-off-by: Jesse zhang
> ---
> drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 8 +++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
> index e1b7fca09666..5f10883da6a2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
> @@ -57,7 +57,13 @@ static int psp_v10_0_init_microcode(struct psp_context
> *psp)
> if (err)
> return err;
>
> - return psp_init_ta_microcode(psp, ucode_prefix);
> + err = psp_init_ta_microcode(psp, ucode_prefix);
> + if ((adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 1, 0)) &&
> + (adev->pdev->revision == 0xa1) &&
> + (psp->securedisplay_context.context.bin_desc.fw_version >=
> 0x2708)) {
> + adev->psp.securedisplay_context.context.bin_desc.size_bytes =
> 0;
> + }
> + return err;
> }
>
> static int psp_v10_0_ring_create(struct psp_context *psp,
> --
> 2.25.1
RE: [PATCH] drm/amdgpu: remove pasid_src field from IV entry
[AMD Official Use Only - General]
Good catch!
The PASID_SRC bit is only used in IH_COOKIE which is sent as register write to
the IH by IH_client.
But in the interrupt packet from IH to driver, the corresponding bit is always
reserved. PASID_SRC is not to be used for driver.
Reviewed-by: Aaron Liu
> -Original Message-
> From: amd-gfx On Behalf Of
> Xiaomeng Hou
> Sent: Thursday, April 27, 2023 3:17 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Ji, Ruili
> ; Hou, Xiaomeng (Matthew) ;
> Koenig, Christian
> Subject: [PATCH] drm/amdgpu: remove pasid_src field from IV entry
>
> PASID_SRC is not actually present in the Interrupt Packet, the field is taken
> as
> reserved bits now. So remove it from IV entry to avoid misuse.
>
> Signed-off-by: Xiaomeng Hou
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 1 -
> drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h | 1 -
> 2 files changed, 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
> index d58353c89e59..fceb3b384955 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
> @@ -271,7 +271,6 @@ void amdgpu_ih_decode_iv_helper(struct
> amdgpu_device *adev,
> entry->timestamp_src = dw[2] >> 31;
> entry->pasid = dw[3] & 0x;
> entry->node_id = (dw[3] >> 16) & 0xff;
> - entry->pasid_src = dw[3] >> 31;
> entry->src_data[0] = dw[4];
> entry->src_data[1] = dw[5];
> entry->src_data[2] = dw[6];
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
> index 7a8e686bdd41..1c747ac4129a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
> @@ -54,7 +54,6 @@ struct amdgpu_iv_entry {
> unsigned timestamp_src;
> unsigned pasid;
> unsigned node_id;
> - unsigned pasid_src;
> unsigned src_data[AMDGPU_IRQ_SRC_DATA_MAX_SIZE_DW];
> const uint32_t *iv_entry;
> };
> --
> 2.25.1
RE: [PATCH] drm/amdgpu: Enable doorbell selfring if resize BAR successfully
[AMD Official Use Only - General] > -Original Message- > From: Alex Deucher > Sent: Tuesday, April 25, 2023 4:20 AM > To: Koenig, Christian > Cc: Xiao, Shane ; Christian König > ; amd-gfx@lists.freedesktop.org; > Deucher, Alexander ; Zhang, Hawking > ; Kuehling, Felix ; Hou, > Xiaomeng (Matthew) ; Liu, Aaron > > Subject: Re: [PATCH] drm/amdgpu: Enable doorbell selfring if resize BAR > successfully > > On Mon, Apr 24, 2023 at 3:11 PM Christian König > wrote: > > > > Am 24.04.23 um 16:06 schrieb Xiao, Shane: > > > [AMD Official Use Only - General] > > >> -Original Message- > > >> From: Xiao, Shane > > >> Sent: Monday, April 24, 2023 6:31 PM > > >> To: Christian König ; amd- > > >> g...@lists.freedesktop.org; Deucher, Alexander > > >> ; Zhang, Hawking > > >> ; Kuehling, Felix > > >> Cc: Hou, Xiaomeng (Matthew) ; Liu, Aaron > > >> > > >> Subject: RE: [PATCH] drm/amdgpu: Enable doorbell selfring if resize > > >> BAR successfully > > >> > > >> [AMD Official Use Only - General] > > >>> -Original Message- > > >>> From: Christian König > > >>> Sent: Monday, April 24, 2023 5:07 PM > > >>> To: Xiao, Shane ; > > >>> amd-gfx@lists.freedesktop.org; Deucher, Alexander > > >>> ; Zhang, Hawking > > >>> ; Kuehling, Felix > > >>> Cc: Hou, Xiaomeng (Matthew) ; Liu, Aaron > > >>> > > >>> Subject: Re: [PATCH] drm/amdgpu: Enable doorbell selfring if > > >>> resize BAR successfully > > >>> > > >>> Am 18.04.23 um 08:54 schrieb Shane Xiao: > > >>>> [Why] > > >>>> The selfring doorbell aperture will change when we resize FB BAR > > >>>> successfully during gmc sw init, we should reorder the sequence > > >>>> of enabling doorbell selfring aperture. > > >>> That's a good catch. > > >>> > > >>>> [How] > > >>>> Move enable_doorbell_selfring_aperture from *_common_hw_init to > > >>>> *_common_late_init. > > >>> But that sounds like a bad idea. Instead the full call to > > >>> nv_enable_doorbell_aperture() should be moved around. > > >> Hi Christian, > > >> > > >> Yes, I get your idea. But as far as I can understand that, the gfx > > >> hw init will use doorbell. > > >> If so, we cannot enable doorbell after gfx hw init. > > > We have come up with two ways to resolve the issue. > > > > > > 1) Separate enable_doorbell_aperture and > > > enable_doorbell_selfring_aperture. However, the > enable_doorbell_selfring_aperture should be moved in *_common_ip_funcs- > >late_init. > > > > I'm not an expert for this part of the driver, but of hand that sounds > > like the right way of doing it. > > > > Alex any objections? > > Yeah, seems reasonable. > > Alex > enable_doorbell_aperture and enable_doorbell_selfring_aperture should be in common_*_init instead of gmc_hw_init. The order of execution of Shane's 1st way is : 1) common_sw_init 2) common_hw_init -> enable_doorbell_aperture 3) gmc_sw_init -> amdgpu_device_resize_fb_bar ///This relies gmc.real_vram_size to determine resize_fb_bar, so moving amdgpu_device_resize_fb_bar to common_sw_init is not a good idea. 4) gmc_hw_init 5) common_late_init -> enable_doorbell_selfring_aperture The 1st way looks good to me and reviewed-by me. > > > > Regards, > > Christian. > > > > > 2) The full call can be moved to gmc hw init. But it seems strange to > > > move > nbio configuration into gmc hw init. > > > > > > If neither of the above methods is suitable, could you please give us some > advice on this issue? > > > > > > Best Regards, > > > Shane > > > > > >> Best Regards, > > >> Shane > > >> > > >>> Regards, > > >>> Christian. > > >>> > > >>>> This fixes the potential issue that GPU ring its own doorbell > > >>>> when this device is in translated mode with iommu is on. > > >>>> > > >>>> Signed-off-by: Shane Xiao > > >>>> Signed-off-by: Aaron Liu > > >>>> Tested-by: Xiaomeng Hou > > >>>> --- > > >>>>drivers/gpu/drm/amd/amdgpu/nv.c| 4 +++- > &
RE: [PATCH] drm/amdkfd: To fix sdma page fault issue for GC 11.x
[AMD Official Use Only - General]
Reviewed-by: Aaron Liu
> -Original Message-
> From: Ji, Ruili
> Sent: Monday, February 6, 2023 8:58 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Kuehling, Felix
> ; Liu, Aaron ; Zhang, Yifan
> ; Ji, Ruili
> Subject: [PATCH] drm/amdkfd: To fix sdma page fault issue for GC 11.x
>
> From: Ruili Ji
>
> For the MQD memory, KMD would always allocate 4K memory, and mes
> scheduler would write to the end of MQD for unmap flag.
>
> Signed-off-by: Ruili Ji
> ---
> .../drm/amd/amdkfd/kfd_device_queue_manager.c | 20
> +++ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
> | 12 +--
> 2 files changed, 26 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> index c06ada0844ba..d682e6921438 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> @@ -2244,10 +2244,22 @@ static int allocate_hiq_sdma_mqd(struct
> device_queue_manager *dqm)
> int retval;
> struct kfd_dev *dev = dqm->dev;
> struct kfd_mem_obj *mem_obj = >hiq_sdma_mqd;
> - uint32_t size = dqm->mqd_mgrs[KFD_MQD_TYPE_SDMA]-
> >mqd_size *
> - get_num_all_sdma_engines(dqm) *
> - dev->device_info.num_sdma_queues_per_engine +
> - dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ]->mqd_size;
> + uint32_t size;
> + /*
> + * MES write to areas beyond MQD size. So allocate
> + * 1 PAGE_SIZE memory for MQD is MES is enabled.
> + */
> + if (dev->shared_resources.enable_mes) {
> + size = PAGE_SIZE *
> + get_num_all_sdma_engines(dqm) *
> + dev->device_info.num_sdma_queues_per_engine +
> + dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ]->mqd_size;
> + } else {
> + size = dqm->mqd_mgrs[KFD_MQD_TYPE_SDMA]->mqd_size
> *
> + get_num_all_sdma_engines(dqm) *
> + dev->device_info.num_sdma_queues_per_engine +
> + dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ]->mqd_size;
> + }
>
> retval = amdgpu_amdkfd_alloc_gtt_mem(dev->adev, size,
> &(mem_obj->gtt_mem), &(mem_obj->gpu_addr), diff --git
> a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
> index 623ccd227b7d..ea176a515898 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
> @@ -66,15 +66,23 @@ struct kfd_mem_obj *allocate_sdma_mqd(struct
> kfd_dev *dev, {
> struct kfd_mem_obj *mqd_mem_obj = NULL;
> uint64_t offset;
> + uint32_t size;
>
> mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL);
> if (!mqd_mem_obj)
> return NULL;
> + /*
> + * MES write to areas beyond MQD size. So allocate
> + * 1 PAGE_SIZE memory for MQD is MES is enabled.
> + */
> + if (dev->shared_resources.enable_mes)
> + size = PAGE_SIZE;
> + else
> + size = dev->dqm->mqd_mgrs[KFD_MQD_TYPE_SDMA]-
> >mqd_size;
>
> offset = (q->sdma_engine_id *
> dev->device_info.num_sdma_queues_per_engine +
> - q->sdma_queue_id) *
> - dev->dqm->mqd_mgrs[KFD_MQD_TYPE_SDMA]->mqd_size;
> + q->sdma_queue_id) * size;
>
> offset += dev->dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ]->mqd_size;
>
> --
> 2.25.1
RE: [PATCH 2/2] drm/amdgpu: correct MEC number for gfx11 APUs
[AMD Official Use Only - General]
The series is
Reviewed-by: Aaron Liu
> -Original Message-
> From: amd-gfx On Behalf Of Lang Yu
> Sent: Monday, January 16, 2023 4:20 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhang, Yifan ; Yu, Lang ;
> Koenig, Christian ; Du, Xiaojian
>
> Subject: [PATCH 2/2] drm/amdgpu: correct MEC number for gfx11 APUs
>
> There is only one MEC on these APUs.
>
> Signed-off-by: Lang Yu
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 11 +--
> 1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> index 985fe704203e..dd4e0f337f46 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> @@ -1251,10 +1251,8 @@ static int gfx_v11_0_sw_init(void *handle)
>
> switch (adev->ip_versions[GC_HWIP][0]) {
> case IP_VERSION(11, 0, 0):
> - case IP_VERSION(11, 0, 1):
> case IP_VERSION(11, 0, 2):
> case IP_VERSION(11, 0, 3):
> - case IP_VERSION(11, 0, 4):
> adev->gfx.me.num_me = 1;
> adev->gfx.me.num_pipe_per_me = 1;
> adev->gfx.me.num_queue_per_pipe = 1;
> @@ -1262,6 +1260,15 @@ static int gfx_v11_0_sw_init(void *handle)
> adev->gfx.mec.num_pipe_per_mec = 4;
> adev->gfx.mec.num_queue_per_pipe = 4;
> break;
> + case IP_VERSION(11, 0, 1):
> + case IP_VERSION(11, 0, 4):
> + adev->gfx.me.num_me = 1;
> + adev->gfx.me.num_pipe_per_me = 1;
> + adev->gfx.me.num_queue_per_pipe = 1;
> + adev->gfx.mec.num_mec = 1;
> + adev->gfx.mec.num_pipe_per_mec = 4;
> + adev->gfx.mec.num_queue_per_pipe = 4;
> + break;
> default:
> adev->gfx.me.num_me = 1;
> adev->gfx.me.num_pipe_per_me = 1;
> --
> 2.25.1
RE: [PATCH 2/2] drm/amdgpu/pm: update hwmon power documentation
[AMD Official Use Only - General] Reviewed-by: Aaron Liu > -Original Message- > From: amd-gfx On Behalf Of Alex > Deucher > Sent: Friday, January 13, 2023 12:25 AM > To: amd-gfx@lists.freedesktop.org > Cc: Deucher, Alexander > Subject: [PATCH 2/2] drm/amdgpu/pm: update hwmon power documentation > > Power reporting is socket power. On APUs this includes the CPU. Update the > documentation to clarify this. > > Signed-off-by: Alex Deucher > --- > drivers/gpu/drm/amd/pm/amdgpu_pm.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c > b/drivers/gpu/drm/amd/pm/amdgpu_pm.c > index 236657eece47..76b9ec64ca50 100644 > --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c > +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c > @@ -3059,7 +3059,7 @@ static ssize_t > amdgpu_hwmon_show_mclk_label(struct device *dev, > * > * hwmon interfaces for GPU power: > * > - * - power1_average: average power used by the GPU in microWatts > + * - power1_average: average power used by the SoC in microWatts. On APUs > this includes the CPU. > * > * - power1_cap_min: minimum cap supported in microWatts > * > -- > 2.39.0
RE: [PATCH 3/3] drm/amd: Evaluate early init for all IP blocks even if one fails
[AMD Official Use Only - General]
Series is
Reviewed-by: Aaron Liu
> -Original Message-
> From: amd-gfx On Behalf Of Mario
> Limonciello
> Sent: Monday, January 16, 2023 3:22 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Limonciello, Mario
> Subject: [PATCH 3/3] drm/amd: Evaluate early init for all IP blocks even if
> one
> fails
>
> If early init fails for a single IP block, then no further IP blocks are
> evaluated.
> This means that if a user was missing more than one firmware binary they would
> have to keep adding binaries and re-probing until they discovered the ones
> missing.
>
> To make this easier, run early init for each IP block and report a single
> failure if
> not all passed.
>
> Signed-off-by: Mario Limonciello
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 +-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 8846f026eeece..2f904bb545fe4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -2074,6 +2074,7 @@ static int amdgpu_device_ip_early_init(struct
> amdgpu_device *adev)
> struct drm_device *dev = adev_to_drm(adev);
> struct pci_dev *parent;
> int i, r;
> + bool total;
>
> amdgpu_device_enable_virtual_display(adev);
>
> @@ -2157,6 +2158,7 @@ static int amdgpu_device_ip_early_init(struct
> amdgpu_device *adev)
> if (amdgpu_sriov_vf(adev) && adev->asic_type ==
> CHIP_SIENNA_CICHLID)
> adev->pm.pp_feature &= ~PP_OVERDRIVE_MASK;
>
> + total = true;
> for (i = 0; i < adev->num_ip_blocks; i++) {
> if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
> DRM_ERROR("disabled ip block: %d <%s>\n", @@ -
> 2170,7 +2172,7 @@ static int amdgpu_device_ip_early_init(struct
> amdgpu_device *adev)
> } else if (r) {
> DRM_ERROR("early_init of IP block
> <%s> failed %d\n",
> adev->ip_blocks[i].version-
> >funcs->name, r);
> - return r;
> + total = false;
> } else {
> adev->ip_blocks[i].status.valid = true;
> }
> @@ -2201,6 +2203,8 @@ static int amdgpu_device_ip_early_init(struct
> amdgpu_device *adev)
>
> }
> }
> + if (!total)
> + return -ENODEV;
>
> adev->cg_flags &= amdgpu_cg_mask;
> adev->pg_flags &= amdgpu_pg_mask;
> --
> 2.25.1
RE: [PATCH 1/3] drm/amd: Adjust legacy IP discovery for Picasso/Raven/Raven2
[AMD Official Use Only - General]
Reviewed-by: Aaron Liu
> -Original Message-
> From: amd-gfx On Behalf Of Mario
> Limonciello
> Sent: Monday, January 16, 2023 3:22 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Limonciello, Mario
> Subject: [PATCH 1/3] drm/amd: Adjust legacy IP discovery for
> Picasso/Raven/Raven2
>
> The switch/case statement currently combines 10.0.0 and 10.0.1, but
> 10.0.1 is only used for Raven 2. So split the two cases up to make this
> clearer.
>
> Signed-off-by: Mario Limonciello
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 12
> 1 file changed, 4 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
> index c03824d0311bd..0d950ae14b27c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
> @@ -1074,15 +1074,11 @@ static const char
> *amdgpu_ucode_legacy_naming(struct amdgpu_device *adev, int bl
> }
> break;
> case IP_VERSION(10, 0, 0):
> + if (adev->apu_flags & AMD_APU_IS_PICASSO)
> + return "picasso";
> + return "raven";
> case IP_VERSION(10, 0, 1):
> - if (adev->asic_type == CHIP_RAVEN) {
> - if (adev->apu_flags & AMD_APU_IS_RAVEN2)
> - return "raven2";
> - else if (adev->apu_flags &
> AMD_APU_IS_PICASSO)
> - return "picasso";
> - return "raven";
> - }
> - break;
> + return "raven2";
> case IP_VERSION(11, 0, 0):
> return "navi10";
> case IP_VERSION(11, 0, 2):
> --
> 2.25.1
RE: [PATCH] drm/amdgpu: Renoir/Cezanne GPU power reporting issue
Reviewed-by: Aaron Liu aaron@amd.com<mailto:aaron@amd.com>
From: amd-gfx On Behalf Of Zhang,
Jesse(Jie)
Sent: Friday, January 13, 2023 10:07 AM
To: Deucher, Alexander
Cc: amd-gfx@lists.freedesktop.org
Subject: [PATCH] drm/amdgpu: Renoir/Cezanne GPU power reporting issue
[AMD Official Use Only - General]
drm/amdgpu: Correct the power calcultion for Renior/Cezanne.
From smu firmware,the value of power is transferred in units of watts.
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2321
Fixes: 137aac26a2ed ("drm/amdgpu/smu12: fix power reporting on renoir")
Acked-by: Alex Deucher
alexander.deuc...@amd.com<mailto:alexander.deuc...@amd.com>
Signed-off-by: Jesse Zhang jesse.zh...@amd.com<mailto:jesse.zh...@amd.com>
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
index 85e22210963f..96a49a3b3ad9 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
@@ -1171,6 +1171,7 @@ static int renoir_get_smu_metrics_data(struct smu_context
*smu,
int ret = 0;
uint32_t apu_percent = 0;
uint32_t dgpu_percent = 0;
+ struct amdgpu_device *adev = smu->adev;
ret = smu_cmn_get_metrics_table(smu,
@@ -1196,7 +1197,11 @@ static int renoir_get_smu_metrics_data(struct
smu_context *smu,
*value = metrics->AverageUvdActivity / 100;
break;
case METRICS_AVERAGE_SOCKETPOWER:
- *value = (metrics->CurrentSocketPower << 8) / 1000;
+ if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 1))
&& (adev->pm.fw_version >= 0x4f))
+ || ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12,
0, 0)) && (adev->pm.fw_version >= 0x373200)))
+ *value = metrics->CurrentSocketPower << 8;
+ else
+ *value = (metrics->CurrentSocketPower << 8) / 1000;
break;
case METRICS_TEMPERATURE_EDGE:
*value = (metrics->GfxTemperature / 100) *
RE: [PATCH 2/2] drm/amd: update securedisplay_cmd to ta_securedisplay_cmd
[AMD Official Use Only - General]
Squashed into one patch now.
Thanks Alex.
> -Original Message-
> From: Alex Deucher
> Sent: Thursday, January 5, 2023 11:28 AM
> To: Liu, Aaron
> Cc: amd-gfx@lists.freedesktop.org; Liu, HaoPing (Alan)
> ; Deucher, Alexander ;
> Xiao, Shane
> Subject: Re: [PATCH 2/2] drm/amd: update securedisplay_cmd to
> ta_securedisplay_cmd
>
> These two patches should be squashed together to avoid breaking the build.
>
> Alex
>
> On Wed, Jan 4, 2023 at 8:04 PM Aaron Liu wrote:
> >
> > This patch updates securedisplay_cmd to ta_securedisplay_cmd starting
> > from amd-ta_securedisplay-v27.00.00.08.
> >
> > Signed-off-by: Aaron Liu
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +-
> > drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c | 8
> > drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.h | 2 +-
> > drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 2 +-
> > 4 files changed, 7 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> > index 0706afb11577..2bebda7de604 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> > @@ -1907,7 +1907,7 @@ int psp_rap_invoke(struct psp_context *psp,
> > uint32_t ta_cmd_id, enum ta_rap_stat static int
> > psp_securedisplay_initialize(struct psp_context *psp) {
> > int ret;
> > - struct securedisplay_cmd *securedisplay_cmd;
> > + struct ta_securedisplay_cmd *securedisplay_cmd;
> >
> > /*
> > * TODO: bypass the initialize in sriov for now diff --git
> > a/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c
> > index 2c1d82fc4c34..8ed0e073656f 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c
> > @@ -77,11 +77,11 @@ void psp_securedisplay_parse_resp_status(struct
> psp_context *psp,
> > }
> > }
> >
> > -void psp_prep_securedisplay_cmd_buf(struct psp_context *psp, struct
> > securedisplay_cmd **cmd,
> > +void psp_prep_securedisplay_cmd_buf(struct psp_context *psp, struct
> > +ta_securedisplay_cmd **cmd,
> > enum ta_securedisplay_command command_id) {
> > - *cmd = (struct securedisplay_cmd *)psp-
> >securedisplay_context.context.mem_context.shared_buf;
> > - memset(*cmd, 0, sizeof(struct securedisplay_cmd));
> > + *cmd = (struct ta_securedisplay_cmd *)psp-
> >securedisplay_context.context.mem_context.shared_buf;
> > + memset(*cmd, 0, sizeof(struct ta_securedisplay_cmd));
> > (*cmd)->status = TA_SECUREDISPLAY_STATUS__GENERIC_FAILURE;
> > (*cmd)->cmd_id = command_id;
> > }
> > @@ -93,7 +93,7 @@ static ssize_t
> > amdgpu_securedisplay_debugfs_write(struct file *f, const char __u {
> > struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)-
> >i_private;
> > struct psp_context *psp = >psp;
> > - struct securedisplay_cmd *securedisplay_cmd;
> > + struct ta_securedisplay_cmd *securedisplay_cmd;
> > struct drm_device *dev = adev_to_drm(adev);
> > uint32_t phy_id;
> > uint32_t op;
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.h
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.h
> > index fe98574748f4..456ad68ed4b2 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.h
> > @@ -30,7 +30,7 @@
> > void amdgpu_securedisplay_debugfs_init(struct amdgpu_device *adev);
> > void psp_securedisplay_parse_resp_status(struct psp_context *psp,
> > enum ta_securedisplay_status status); -void
> > psp_prep_securedisplay_cmd_buf(struct psp_context *psp, struct
> > securedisplay_cmd **cmd,
> > +void psp_prep_securedisplay_cmd_buf(struct psp_context *psp, struct
> > +ta_securedisplay_cmd **cmd,
> > enum ta_securedisplay_command command_id);
> >
> > #endif
> > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
> > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
> > index ad73e5855580..8841c447d0e2 100644
> > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
> > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
> > @@ -103,7 +103,7 @@ static void
> > amdgpu_dm_crtc_notify_ta_to_read(struct work_struct *work) {
> > struct secure_display_context *secure_display_ctx;
> > struct psp_context *psp;
> > - struct securedisplay_cmd *securedisplay_cmd;
> > + struct ta_securedisplay_cmd *securedisplay_cmd;
> > struct drm_crtc *crtc;
> > struct dc_stream_state *stream;
> > uint8_t phy_inst;
> > --
> > 2.39.0
> >
0001-drm-amdgpu-update-ta_secureDisplay_if.h-to-v27.00.00.patch
Description: 0001-drm-amdgpu-update-ta_secureDisplay_if.h-to-v27.00.00.patch
RE: [PATCH 19/19] drm/amdgpu: enable PSP IP v13.0.11 support
[AMD Official Use Only - General]
Series is
Reviewed-by: Aaron Liu
> -Original Message-
> From: amd-gfx On Behalf Of Yifan
> Zhang
> Sent: Tuesday, November 22, 2022 1:50 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Huang, Tim
> ; Du, Xiaojian ; Zhang, Yifan
>
> Subject: [PATCH 19/19] drm/amdgpu: enable PSP IP v13.0.11 support
>
> From: Tim Huang
>
> Enable PSP FW loading for PSP IP v13.0.11
>
> Signed-off-by: Tim Huang
> Signed-off-by: Yifan Zhang
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 1 +
> drivers/gpu/drm/amd/amdgpu/psp_v13_0.c | 3 +++
> 2 files changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> index 7bb2de1d11ff..4670b86ebf74 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> @@ -165,6 +165,7 @@ static int psp_early_init(void *handle)
> case IP_VERSION(13, 0, 5):
> case IP_VERSION(13, 0, 8):
> case IP_VERSION(13, 0, 10):
> + case IP_VERSION(13, 0, 11):
> psp_v13_0_set_psp_funcs(psp);
> psp->autoload_supported = true;
> break;
> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
> b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
> index 2abf48f187fa..1c7eb46aa4e1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
> @@ -45,6 +45,8 @@ MODULE_FIRMWARE("amdgpu/psp_13_0_7_sos.bin");
> MODULE_FIRMWARE("amdgpu/psp_13_0_7_ta.bin");
> MODULE_FIRMWARE("amdgpu/psp_13_0_10_sos.bin");
> MODULE_FIRMWARE("amdgpu/psp_13_0_10_ta.bin");
> +MODULE_FIRMWARE("amdgpu/psp_13_0_11_toc.bin");
> +MODULE_FIRMWARE("amdgpu/psp_13_0_11_ta.bin");
>
> /* For large FW files the time to complete can be very long */ #define
> USBC_PD_POLLING_LIMIT_S 240 @@ -101,6 +103,7 @@ static int
> psp_v13_0_init_microcode(struct psp_context *psp)
> case IP_VERSION(13, 0, 3):
> case IP_VERSION(13, 0, 5):
> case IP_VERSION(13, 0, 8):
> + case IP_VERSION(13, 0, 11):
> err = psp_init_toc_microcode(psp, chip_name);
> if (err)
> return err;
> --
> 2.37.3
<>
RE: [PATCH] drm/amd/amdgpu: solve the issue of allocate continuous pages under xen dom0
[AMD Official Use Only - General]
Reviewed-by: Aaron Liu
--
Best Regards
Aaron Liu
> -Original Message-
> From: amd-gfx On Behalf Of
> Shane Xiao
> Sent: Thursday, September 22, 2022 3:12 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Xiao, Shane
> Subject: [PATCH] drm/amd/amdgpu: solve the issue of allocate continuous
> pages under xen dom0
>
> [Why]
> sg_alloc_table_from_pages alloc too large continuous PFN pages under xen
> dom0.
> However, xen should check continuous MFN pages in
> range_straddles_page_boundary.
> When range_straddles_page_boundary return false, some cases fall back
> into swiotlb process and the continuous allocable page is not enough.
>
> [How]
> In fact, xen swiotlb set max_segment default value as UINT_MAX and
> xen_swiotlb_init_early already change the value to PAGE_SIZE under xen
> dom0.
> However amdgpu driver doesn't use the value, which may cause issue such
> as swiotlb buffer full. Add amd_sg_segment_size according to iommu setting,
> the details are as follows:
> iommu setting | amd_sg_segment_size
> ---
> iommu=on| UINT_MAX
> iommu=off && swiotlb on | IO_TLB_DEFAULT_SIZE(64M)
> xen_swiotlb on | PAGE_SIZE(4K)
> ---
>
> Signed-off-by: Shane Xiao
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 22
> --
> 1 file changed, 20 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index 134575a3893c..d081fcd22d6b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -80,6 +80,23 @@ static int amdgpu_ttm_init_on_chip(struct
> amdgpu_device *adev,
> false, size_in_page);
> }
>
> +static inline unsigned int amdgpu_sg_segment_size(void) {
> + unsigned int size = swiotlb_max_segment();
> +
> + /* size=0 when amd iommu enabled */
> + if (size == 0)
> + size = UINT_MAX;
> +
> + size = rounddown(size, PAGE_SIZE);
> + /* swiotlb_max_segment_size can return 1 byte when it means one
> page. */
> + if (size < PAGE_SIZE)
> + size = PAGE_SIZE;
> +
> + return size;
> +}
> +
> +
> /**
> * amdgpu_evict_flags - Compute placement flags
> *
> @@ -760,9 +777,10 @@ static int amdgpu_ttm_tt_pin_userptr(struct
> ttm_device *bdev,
> int r;
>
> /* Allocate an SG array and squash pages into it */
> - r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages,
> 0,
> - (u64)ttm->num_pages << PAGE_SHIFT,
> + r = sg_alloc_table_from_pages_segment(ttm->sg, ttm->pages, ttm-
> >num_pages, 0,
> + (u64)ttm->num_pages << PAGE_SHIFT,
> amdgpu_sg_segment_size(),
> GFP_KERNEL);
> +
> if (r)
> goto release_sg;
>
> --
> 2.25.1
RE: [PATCH] drm/amdkfd: Match GC 11.0.1 cache info to yellow carp
[Public] Hi Yifan, Yellow carp's cache info cannot be duplicated to GC_11_0_1. Different point to GC_11_0_1: TCP L1 Cache size is 32 GL1 Data Cache size per SA is 256 Others looks good to me -- Best Regards Aaron Liu > -Original Message- > From: amd-gfx On Behalf Of > Huang, Tim > Sent: Friday, September 2, 2022 6:44 AM > To: Zhang, Yifan ; amd-gfx@lists.freedesktop.org > Cc: Deucher, Alexander ; Du, Xiaojian > > Subject: RE: [PATCH] drm/amdkfd: Match GC 11.0.1 cache info to yellow carp > > [Public] > > [Public] > > Reviewed-by: Tim Huang > > Best Regards, > Tim Huang > > > > -Original Message- > From: Zhang, Yifan > Sent: Thursday, September 1, 2022 3:30 PM > To: amd-gfx@lists.freedesktop.org > Cc: Deucher, Alexander ; Huang, Tim > ; Du, Xiaojian ; Zhang, > Yifan > Subject: [PATCH] drm/amdkfd: Match GC 11.0.1 cache info to yellow carp > > Current discovery table doesn't have cache info for GC 11.0.1, thus can't be > parsed like other GC 11, this patch to match GC 11.0.1 cache info to yellow > carp > > Signed-off-by: Yifan Zhang > --- > drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c > b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c > index 24b414cff3ec..1c500bfb0b28 100644 > --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c > +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c > @@ -1516,11 +1516,11 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev > *kdev, > case IP_VERSION(10, 3, 3): > case IP_VERSION(10, 3, 6): /* TODO: Double check these on > production silicon */ > case IP_VERSION(10, 3, 7): /* TODO: Double check these on > production silicon */ > + case IP_VERSION(11, 0, 1): /* TODO: Double check these > +on production silicon */ > pcache_info = yellow_carp_cache_info; > num_of_cache_types = > ARRAY_SIZE(yellow_carp_cache_info); > break; > case IP_VERSION(11, 0, 0): > - case IP_VERSION(11, 0, 1): > case IP_VERSION(11, 0, 2): > case IP_VERSION(11, 0, 3): > pcache_info = cache_info; > -- > 2.37.1
RE: [PATCH] drm/amdkfd: Fix isa version for the GC 10.3.7
[Public]
Reviewed-by: Aaron Liu
> -Original Message-
> From: Liang, Prike
> Sent: Wednesday, August 24, 2022 8:40 PM
> To: Liang, Prike ; amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Huang, Ray
> ; Zhang, Yifan ; Liu, Aaron
> ; Limonciello, Mario
> Subject: RE: [PATCH] drm/amdkfd: Fix isa version for the GC 10.3.7
>
> [Public]
>
> Add more for the review and awareness.
>
> Regards,
> --Prike
>
> -Original Message-
> From: Prike Liang
> Sent: Wednesday, August 24, 2022 2:41 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Huang, Ray
> ; Zhang, Yifan ; Liang,
> Prike
> Subject: [PATCH] drm/amdkfd: Fix isa version for the GC 10.3.7
>
> Correct the isa version for handling KFD test.
>
> Fixes: 7c4f4f197e0c ("drm/amdkfd: Add GC 10.3.6 and 10.3.7 KFD
> definitions")
> Signed-off-by: Prike Liang
> ---
> drivers/gpu/drm/amd/amdkfd/kfd_device.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> index fdad1415f8bd..5ebbeac61379 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> @@ -388,7 +388,7 @@ struct kfd_dev *kgd2kfd_probe(struct
> amdgpu_device *adev, bool vf)
> f2g = _v10_3_kfd2kgd;
> break;
> case IP_VERSION(10, 3, 7):
> - gfx_target_version = 100307;
> + gfx_target_version = 100306;
> if (!vf)
> f2g = _v10_3_kfd2kgd;
> break;
> --
> 2.25.1
>
RE: [PATCH] drm/amdkfd: Fix isa version for the GC 10.3.7
[Public]
Because GC_IP_VERSION 10.3.6&10.3.7 all use 1036 ISA version, one nit-pick as
below. It looks better.
case IP_VERSION(10, 3, 6):
case IP_VERSION(10, 3, 7):
gfx_target_version = 100306;
if (!vf)
f2g = _v10_3_kfd2kgd;
break;
> -Original Message-
> From: Liu, Aaron
> Sent: Thursday, August 25, 2022 8:15 AM
> To: Liang, Prike ; amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Huang, Ray
> ; Zhang, Yifan ;
> Limonciello, Mario
> Subject: RE: [PATCH] drm/amdkfd: Fix isa version for the GC 10.3.7
>
> [Public]
>
> Reviewed-by: Aaron Liu
>
> > -Original Message-
> > From: Liang, Prike
> > Sent: Wednesday, August 24, 2022 8:40 PM
> > To: Liang, Prike ; amd-gfx@lists.freedesktop.org
> > Cc: Deucher, Alexander ; Huang, Ray
> > ; Zhang, Yifan ; Liu,
> Aaron
> > ; Limonciello, Mario
> > Subject: RE: [PATCH] drm/amdkfd: Fix isa version for the GC 10.3.7
> >
> > [Public]
> >
> > Add more for the review and awareness.
> >
> > Regards,
> > --Prike
> >
> > -Original Message-
> > From: Prike Liang
> > Sent: Wednesday, August 24, 2022 2:41 PM
> > To: amd-gfx@lists.freedesktop.org
> > Cc: Deucher, Alexander ; Huang, Ray
> > ; Zhang, Yifan ; Liang,
> Prike
> >
> > Subject: [PATCH] drm/amdkfd: Fix isa version for the GC 10.3.7
> >
> > Correct the isa version for handling KFD test.
> >
> > Fixes: 7c4f4f197e0c ("drm/amdkfd: Add GC 10.3.6 and 10.3.7 KFD
> > definitions")
> > Signed-off-by: Prike Liang
> > ---
> > drivers/gpu/drm/amd/amdkfd/kfd_device.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> > b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> > index fdad1415f8bd..5ebbeac61379 100644
> > --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> > +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> > @@ -388,7 +388,7 @@ struct kfd_dev *kgd2kfd_probe(struct
> amdgpu_device
> > *adev, bool vf)
> > f2g = _v10_3_kfd2kgd;
> > break;
> > case IP_VERSION(10, 3, 7):
> > - gfx_target_version = 100307;
> > + gfx_target_version = 100306;
> > if (!vf)
> > f2g = _v10_3_kfd2kgd;
> > break;
> > --
> > 2.25.1
> >
RE: [PATCH] drm/amdgpu: Add secure display TA load for Renoir
[AMD Official Use Only - General]
Reviewed-by: Aaron Liu
> -Original Message-
> From: amd-gfx On Behalf Of
> Shane Xiao
> Sent: Monday, August 15, 2022 4:40 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Xiao, Shane
> Subject: [PATCH] drm/amdgpu: Add secure display TA load for Renoir
>
> Add secure display TA load for Renoir
>
> Signed-off-by: Shane Xiao
> ---
> drivers/gpu/drm/amd/amdgpu/psp_v12_0.c | 10 ++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
> b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
> index a2588200ea58..0b2ac418e4ac 100644
> --- a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
> @@ -101,6 +101,16 @@ static int psp_v12_0_init_microcode(struct
> psp_context *psp)
> adev->psp.dtm_context.context.bin_desc.start_addr =
> (uint8_t *)adev-
> >psp.hdcp_context.context.bin_desc.start_addr +
> le32_to_cpu(ta_hdr->dtm.offset_bytes);
> +
> + if (adev->apu_flags & AMD_APU_IS_RENOIR) {
> + adev-
> >psp.securedisplay_context.context.bin_desc.fw_version =
> + le32_to_cpu(ta_hdr-
> >securedisplay.fw_version);
> + adev-
> >psp.securedisplay_context.context.bin_desc.size_bytes =
> + le32_to_cpu(ta_hdr-
> >securedisplay.size_bytes);
> + adev-
> >psp.securedisplay_context.context.bin_desc.start_addr =
> + (uint8_t *)adev-
> >psp.hdcp_context.context.bin_desc.start_addr +
> + le32_to_cpu(ta_hdr-
> >securedisplay.offset_bytes);
> + }
> }
>
> return 0;
> --
> 2.25.1
RE: [PATCH v2] drm/amd/pm: Add get_gfx_off_status interface for yellow carp
[AMD Official Use Only - General]
Reviewed-by: Aaron Liu
> -Original Message-
> From: amd-gfx On Behalf Of
> shikai@amd.com
> Sent: Tuesday, July 26, 2022 2:29 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Liang, Prike
> ; Quan, Evan ; Liu, Aaron
>
> Subject: [PATCH v2] drm/amd/pm: Add get_gfx_off_status interface for
> yellow carp
>
> From: Shikai Guo
>
> add get_gfx_off_status interface to yellow_carp_ppt_funcs structure.
>
> Signed-off-by: Shikai Guo
> ---
> .../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c | 31
> +++
> 1 file changed, 31 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
> index 70cbc46341a3..04e56b0b3033 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
> @@ -42,6 +42,11 @@
> #undef pr_info
> #undef pr_debug
>
> +#define regSMUIO_GFX_MISC_CNTL
> 0x00c5
> +#define regSMUIO_GFX_MISC_CNTL_BASE_IDX
> 0
> +#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK
> 0x0006L
> +#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT 0x1L
> +
> #define FEATURE_MASK(feature) (1ULL << feature) #define
> SMC_DPM_FEATURE ( \
> FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ @@ -587,6 +592,31
> @@ static ssize_t yellow_carp_get_gpu_metrics(struct smu_context *smu,
> return sizeof(struct gpu_metrics_v2_1); }
>
> +/**
> + * yellow_carp_get_gfxoff_status - get gfxoff status
> + *
> + * @smu: smu_context pointer
> + *
> + * This function will be used to get gfxoff status
> + *
> + * Returns 0=GFXOFF(default).
> + * Returns 1=Transition out of GFX State.
> + * Returns 2=Not in GFXOFF.
> + * Returns 3=Transition into GFXOFF.
> + */
> +static uint32_t yellow_carp_get_gfxoff_status(struct smu_context *smu)
> +{
> + uint32_t reg;
> + uint32_t gfxoff_status = 0;
> + struct amdgpu_device *adev = smu->adev;
> +
> + reg = RREG32_SOC15(SMUIO, 0, regSMUIO_GFX_MISC_CNTL);
> + gfxoff_status = (reg &
> SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK)
> + >> SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT;
> +
> + return gfxoff_status;
> +}
> +
> static int yellow_carp_set_default_dpm_tables(struct smu_context *smu) {
> struct smu_table_context *smu_table = >smu_table; @@ -
> 1186,6 +1216,7 @@ static const struct pptable_funcs yellow_carp_ppt_funcs
> = {
> .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
> .set_driver_table_location = smu_v13_0_set_driver_table_location,
> .gfx_off_control = smu_v13_0_gfx_off_control,
> + .get_gfx_off_status = yellow_carp_get_gfxoff_status,
> .post_init = yellow_carp_post_smu_init,
> .mode2_reset = yellow_carp_mode2_reset,
> .get_dpm_ultimate_freq = yellow_carp_get_dpm_ultimate_freq,
> --
> 2.25.1
RE: [PATCH] drm/amd/pm: Add get_gfx_off_status interface
[AMD Official Use Only - General]
Shikai,
Yellow carp's SMUIO is 13_0_1.
#define regSMUIO_GFX_MISC_CNTL
0x00c5
This register in your patch is from smuio_13_0_2_offset.h and this register's
value is different to 13_0_1.
#define regSMUIO_GFX_MISC_CNTL
0x00d1
> -Original Message-
> From: amd-gfx On Behalf Of
> shikai@amd.com
> Sent: Thursday, July 21, 2022 4:58 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Liang, Prike
> ; Quan, Evan ; Guo, Shikai
>
> Subject: [PATCH] drm/amd/pm: Add get_gfx_off_status interface
>
> From: Shikai Guo
>
> add get_gfx_off_status interface to yellow_carp_ppt_funcs structure.
>
> Signed-off-by: Shikai Guo
> ---
> .../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c | 30
> +++
> 1 file changed, 30 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
> index 70cbc46341a3..2e39b629e7e6 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
> @@ -31,6 +31,7 @@
> #include "smu_v13_0_1_ppsmc.h"
> #include "smu_v13_0_1_pmfw.h"
> #include "smu_cmn.h"
> +#include "asic_reg/smuio/smuio_13_0_2_offset.h"
>
> /*
> * DO NOT use these for err/warn/info/debug messages.
> @@ -42,6 +43,9 @@
> #undef pr_info
> #undef pr_debug
>
> +#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK
> 0x0006L
> +#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT
> 0x1
> +
> #define FEATURE_MASK(feature) (1ULL << feature) #define
> SMC_DPM_FEATURE ( \
> FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ @@ -587,6 +591,31
> @@ static ssize_t yellow_carp_get_gpu_metrics(struct smu_context *smu,
> return sizeof(struct gpu_metrics_v2_1); }
>
> +/**
> + * yellow_carp_get_gfxoff_status - get gfxoff status
> + *
> + * @smu: smu_context pointer
> + *
> + * This function will be used to get gfxoff status
> + *
> + * Returns 0=GFXOFF(default).
> + * Returns 1=Transition out of GFX State.
> + * Returns 2=Not in GFXOFF.
> + * Returns 3=Transition into GFXOFF.
> + */
> +static uint32_t yellow_carp_get_gfxoff_status(struct smu_context *smu)
> +{
> + uint32_t reg;
> + uint32_t gfxOff_Status = 0;
> + struct amdgpu_device *adev = smu->adev;
> +
> + reg = RREG32_SOC15(SMUIO, 0, regSMUIO_GFX_MISC_CNTL);
> + gfxOff_Status = (reg &
> SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK)
> + >> SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT;
> +
> + return gfxOff_Status;
> +}
> +
> static int yellow_carp_set_default_dpm_tables(struct smu_context *smu) {
> struct smu_table_context *smu_table = >smu_table; @@ -
> 1186,6 +1215,7 @@ static const struct pptable_funcs yellow_carp_ppt_funcs
> = {
> .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
> .set_driver_table_location = smu_v13_0_set_driver_table_location,
> .gfx_off_control = smu_v13_0_gfx_off_control,
> + .get_gfx_off_status = yellow_carp_get_gfxoff_status,
> .post_init = yellow_carp_post_smu_init,
> .mode2_reset = yellow_carp_mode2_reset,
> .get_dpm_ultimate_freq = yellow_carp_get_dpm_ultimate_freq,
> --
> 2.25.1
RE: [PATCH] drm/amdkfd: correct the MEC atomic support firmware checking for GC 10.3.7
[AMD Official Use Only - General] Reviewed-by: Aaron Liu > -Original Message- > From: amd-gfx On Behalf Of Prike > Liang > Sent: Monday, July 11, 2022 4:55 PM > To: amd-gfx@lists.freedesktop.org > Cc: Deucher, Alexander ; Liang, Prike > ; Huang, Ray > Subject: [PATCH] drm/amdkfd: correct the MEC atomic support firmware > checking for GC 10.3.7 > > On the GC 10.3.7 platform the initial MEC release version #3 can support > atomic operation,so need correct and set its MEC atomic support version to > #3. > > Signed-off-by: Prike Liang > --- > drivers/gpu/drm/amd/amdkfd/kfd_device.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c > b/drivers/gpu/drm/amd/amdkfd/kfd_device.c > index 6ec0e9f0927d..f5853835f03a 100644 > --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c > +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c > @@ -184,6 +184,8 @@ static void kfd_device_info_init(struct kfd_dev *kfd, > /* Navi2x+, Navi1x+ */ > if (gc_version == IP_VERSION(10, 3, 6)) > kfd->device_info.no_atomic_fw_version = 14; > + else if (gc_version == IP_VERSION(10, 3, 7)) > + kfd->device_info.no_atomic_fw_version = 3; > else if (gc_version >= IP_VERSION(10, 3, 0)) > kfd->device_info.no_atomic_fw_version = 92; > else if (gc_version >= IP_VERSION(10, 1, 1)) > -- > 2.25.1
RE: [PATCH v2] mdkfd: To flush tlb for MMHUB of GFX9 series
[AMD Official Use Only - General]
Reviewed-by: Aaron Liu
> -Original Message-
> From: Ji, Ruili
> Sent: Wednesday, June 22, 2022 2:46 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Aaron ; Ji, Ruili ; Yang,
> Philip ; Deucher, Alexander
>
> Subject: [PATCH v2] mdkfd: To flush tlb for MMHUB of GFX9 series
>
> From: Ruili Ji
>
> amdgpu: [mmhub0] no-retry page fault (src_id:0 ring:40 vmid:8 pasid:32769,
> for process test_basic pid 3305 thread test_basic pid 3305)
> amdgpu: in page starting at address 0x7ff990003000 from IH client 0x12
> (VMC)
> amdgpu: VM_L2_PROTECTION_FAULT_STATUS:0x00840051
> amdgpu: Faulty UTCL2 client ID: MP1 (0x0)
> amdgpu: MORE_FAULTS: 0x1
> amdgpu: WALKER_ERROR: 0x0
> amdgpu: PERMISSION_FAULTS: 0x5
> amdgpu: MAPPING_ERROR: 0x0
> amdgpu: RW: 0x1
>
> When memory is allocated by kfd, no one triggers the tlb flush for MMHUB0.
> There is page fault from MMHUB0.
>
> v2:fix indentation
>
> Signed-off-by: Ruili Ji
> Reviewed-by: Philip Yang
> Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> index 1d0c9762ebfb..1dfd82d5d379 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> @@ -739,7 +739,8 @@ int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct
> amdgpu_device *adev, {
> bool all_hub = false;
>
> - if (adev->family == AMDGPU_FAMILY_AI)
> + if (adev->family == AMDGPU_FAMILY_AI ||
> + adev->family == AMDGPU_FAMILY_RV)
> all_hub = true;
>
> return amdgpu_gmc_flush_gpu_tlb_pasid(adev, pasid, flush_type,
> all_hub);
> --
> 2.25.1
RE: [PATCH] drm/amdgpu/pm: fix the null pointer while the smu is disabled
[AMD Official Use Only] Reviewed-by: Aaron Liu > -Original Message- > From: amd-gfx On Behalf Of > Huang Rui > Sent: Friday, April 15, 2022 12:13 PM > To: amd-gfx@lists.freedesktop.org > Cc: Deucher, Alexander ; Huang, Tim > ; Quan, Evan ; Huang, Ray > ; Du, Xiaojian > Subject: [PATCH] drm/amdgpu/pm: fix the null pointer while the smu is > disabled > > It needs to check if the pp_funcs is initialized while release the context, > otherwise it will trigger null pointer panic while the software smu is not > enabled. > > [ 1109.404555] BUG: kernel NULL pointer dereference, address: > 0078 [ 1109.404609] #PF: supervisor read access in kernel mode > [ 1109.404638] #PF: error_code(0x) - not-present page [ 1109.404657] > PGD 0 P4D 0 [ 1109.404672] Oops: [#1] PREEMPT SMP NOPTI > [ 1109.404701] CPU: 7 PID: 9150 Comm: amdgpu_test Tainted: G OEL > 5.16.0-custom #1 > [ 1109.404732] Hardware name: innotek GmbH VirtualBox/VirtualBox, BIOS > VirtualBox 12/01/2006 [ 1109.404765] RIP: > 0010:amdgpu_dpm_force_performance_level+0x1d/0x170 [amdgpu] > [ 1109.405109] Code: 5d c3 44 8b a3 f0 80 00 00 eb e5 66 90 0f 1f 44 00 00 55 > 48 > 89 e5 41 57 41 56 41 55 41 54 53 48 83 ec 08 4c 8b b7 f0 7d 00 00 <49> 83 7e > 78 > 00 0f 84 f2 00 00 00 80 bf 87 80 00 00 00 48 89 fb 0f [ 1109.405176] RSP: > 0018:af3083ad7c20 EFLAGS: 00010282 [ 1109.405203] RAX: > RBX: 9796b1c14600 RCX: 02862007 > [ 1109.405229] RDX: 97968591c8c0 RSI: 0001 RDI: > 9796a370 [ 1109.405260] RBP: af3083ad7c50 R08: 9897de00 > R09: 979688d9db60 [ 1109.405286] R10: R11: > 979688d9db90 R12: 0001 [ 1109.405316] R13: > 9796a370 R14: R15: 9796a3708fc0 [ 1109.405345] > FS: 7ff055cff180() GS:9796bfdc() > knlGS: [ 1109.405378] CS: 0010 DS: ES: CR0: > 80050033 [ 1109.405400] CR2: 0078 CR3: > 0a394000 CR4: 000506e0 [ 1109.405434] Call Trace: > [ 1109.405445] > [ 1109.405456] ? delete_object_full+0x1d/0x20 [ 1109.405480] > amdgpu_ctx_set_stable_pstate+0x7c/0xa0 [amdgpu] [ 1109.405698] > amdgpu_ctx_fini.part.0+0xcb/0x100 [amdgpu] [ 1109.405911] > amdgpu_ctx_do_release+0x71/0x80 [amdgpu] [ 1109.406121] > amdgpu_ctx_ioctl+0x52d/0x550 [amdgpu] [ 1109.406327] ? > _raw_spin_unlock+0x1a/0x30 [ 1109.406354] ? > drm_gem_handle_delete+0x81/0xb0 [drm] [ 1109.406400] ? > amdgpu_ctx_get_entity+0x2c0/0x2c0 [amdgpu] [ 1109.406609] > drm_ioctl_kernel+0xb6/0x140 [drm] > > Signed-off-by: Huang Rui > --- > drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c > b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c > index 1d63f1e8884c..428623e64e8f 100644 > --- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c > +++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c > @@ -717,7 +717,7 @@ int amdgpu_dpm_force_performance_level(struct > amdgpu_device *adev, > > AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | > > AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; > > - if (!pp_funcs->force_performance_level) > + if (!pp_funcs || !pp_funcs->force_performance_level) > return 0; > > if (adev->pm.dpm.thermal_active) > -- > 2.25.1
RE: [PATCH V2] drm/amdgpu: fix incorrect GCR_GENERAL_CNTL address
Reviewed-by: Aaron Liu
--
Best Regards
Aaron Liu
> -Original Message-
> From: amd-gfx On Behalf Of Ji, Ruili
> Sent: Monday, March 28, 2022 12:59 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhang, Yifan ; Liu, Aaron
> ; Liang, Prike ; Huang, Ray
> ; Deucher, Alexander
> ; Ji, Ruili
> Subject: [PATCH V2] drm/amdgpu: fix incorrect GCR_GENERAL_CNTL address
>
> From: Ruili Ji
>
> gfx10.3.3/gfx10.3.6/gfx10.3.7 shall use 0x1580 address for
> GCR_GENERAL_CNTL
>
> Signed-off-by: Ruili Ji
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index 99df18ae7316..e4c9d92ac381 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -3300,7 +3300,7 @@ static const struct soc15_reg_golden
> golden_settings_gc_10_3_3[] =
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x,
> 0x0280),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x,
> 0x0080),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG,
> 0x0c1807ff, 0x0242),
> - SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL,
> 0x1ff1, 0x0500),
> + SOC15_REG_GOLDEN_VALUE(GC, 0,
> mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1,
> +0x0500),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x00ff,
> 0x00e4),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0,
> 0x, 0x32103210),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1,
> 0x, 0x32103210), @@ -3436,7 +3436,7 @@ static const struct
> soc15_reg_golden golden_settings_gc_10_3_6[] =
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x,
> 0x0280),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x,
> 0x0080),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG,
> 0x0c1807ff, 0x0042),
> - SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL,
> 0x1ff1, 0x0500),
> + SOC15_REG_GOLDEN_VALUE(GC, 0,
> mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1,
> +0x0500),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x00ff,
> 0x0044),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0,
> 0x, 0x32103210),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1,
> 0x, 0x32103210), @@ -3461,7 +3461,7 @@ static const struct
> soc15_reg_golden golden_settings_gc_10_3_7[] = {
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x,
> 0x0280),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x,
> 0x0080),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG,
> 0x0c1807ff, 0x0041),
> - SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL,
> 0x1ff1, 0x0500),
> + SOC15_REG_GOLDEN_VALUE(GC, 0,
> mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1,
> +0x0500),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x00ff,
> 0x00e4),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0,
> 0x, 0x32103210),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1,
> 0x, 0x32103210),
> --
> 2.25.1
RE: [PATCH] drm/amdgpu: fix incorrect GCR_GENERAL_CNTL address
[AMD Official Use Only]
Thanks Ruili. Please remove Change-Id.
With this fixed, Reviewed-by: Aaron Liu
> -Original Message-
> From: Ji, Ruili
> Sent: Monday, March 28, 2022 11:47 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Huang, Ray
> ; Liu, Aaron ; Zhang, Yifan
> ; Liang, Prike ; Ji, Ruili
>
> Subject: [PATCH] drm/amdgpu: fix incorrect GCR_GENERAL_CNTL address
>
> From: Ruili Ji
>
> RMB shall use 0x1580 address for GCR_GENERAL_CNTL
>
> Signed-off-by: Ruili Ji
> Change-Id: I10a85891986f31411f85fa3db46970aaa8a5bd03
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index 99df18ae7316..e4c9d92ac381 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -3300,7 +3300,7 @@ static const struct soc15_reg_golden
> golden_settings_gc_10_3_3[] =
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x,
> 0x0280),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x,
> 0x0080),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG,
> 0x0c1807ff, 0x0242),
> - SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL,
> 0x1ff1, 0x0500),
> + SOC15_REG_GOLDEN_VALUE(GC, 0,
> mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1,
> +0x0500),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER,
> 0x00ff, 0x00e4),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0,
> 0x, 0x32103210),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1,
> 0x, 0x32103210), @@ -3436,7 +3436,7 @@ static const struct
> soc15_reg_golden golden_settings_gc_10_3_6[] =
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x,
> 0x0280),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x,
> 0x0080),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG,
> 0x0c1807ff, 0x0042),
> - SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL,
> 0x1ff1, 0x0500),
> + SOC15_REG_GOLDEN_VALUE(GC, 0,
> mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1,
> +0x0500),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER,
> 0x00ff, 0x0044),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0,
> 0x, 0x32103210),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1,
> 0x, 0x32103210), @@ -3461,7 +3461,7 @@ static const struct
> soc15_reg_golden golden_settings_gc_10_3_7[] = {
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x,
> 0x0280),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x,
> 0x0080),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG,
> 0x0c1807ff, 0x0041),
> - SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL,
> 0x1ff1, 0x0500),
> + SOC15_REG_GOLDEN_VALUE(GC, 0,
> mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1,
> +0x0500),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER,
> 0x00ff, 0x00e4),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0,
> 0x, 0x32103210),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1,
> 0x, 0x32103210),
> --
> 2.25.1
RE: [PATCH] drm/amdgpu: enable TMZ option for onwards asic
[AMD Official Use Only]
Reviewed-by: Aaron Liu
--
Best Regards
Aaron Liu
> -Original Message-
> From: Liang, Prike
> Sent: Friday, February 18, 2022 10:08 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Liu, Aaron
> ; Huang, Ray ; Liang, Prike
>
> Subject: [PATCH] drm/amdgpu: enable TMZ option for onwards asic
>
> The TMZ is disabled by default and enable TMZ option for the IP discovery
> based asic will help on the TMZ function verification.
>
> Signed-off-by: Prike Liang
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> index 956cc994ca7d..2cbb8c432168 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> @@ -581,6 +581,7 @@ void amdgpu_gmc_tmz_set(struct amdgpu_device
> *adev)
> case CHIP_NAVI12:
> case CHIP_VANGOGH:
> case CHIP_YELLOW_CARP:
> + case CHIP_IP_DISCOVERY:
> /* Don't enable it by default yet.
>*/
> if (amdgpu_tmz < 1) {
> --
> 2.17.1
RE: [PATCH] drm/amdgpu: enable TMZ option for onwards asic
[AMD Official Use Only]
":" is expected behind "case CHIP_IP_DISCOVERY"
--
Best Regards
Aaron Liu
> -Original Message-
> From: amd-gfx On Behalf Of Prike
> Liang
> Sent: Friday, February 18, 2022 9:37 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Liang, Prike
> ; Huang, Ray
> Subject: [PATCH] drm/amdgpu: enable TMZ option for onwards asic
>
> The TMZ is disabled by default and enable TMZ option for the IP discovery
> based asic will help on the TMZ function verification.
>
> Signed-off-by: Prike Liang
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> index 956cc994ca7d..d2dd526a4c80 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> @@ -581,6 +581,7 @@ void amdgpu_gmc_tmz_set(struct amdgpu_device
> *adev)
> case CHIP_NAVI12:
> case CHIP_VANGOGH:
> case CHIP_YELLOW_CARP:
> + case CHIP_IP_DISCOVERY
> /* Don't enable it by default yet.
>*/
> if (amdgpu_tmz < 1) {
> --
> 2.17.1
RE: [PATCH] drm/amd/pm: correct the sequence of sending gpu reset msg
[AMD Official Use Only]
Yifan,
Please remove Change-Id.
With this fixed, Acked-by: Aaron Liu
--
Best Regards
Aaron Liu
> -Original Message-
> From: amd-gfx On Behalf Of Yifan
> Zhang
> Sent: Monday, February 14, 2022 12:12 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Zhang, Yifan
> ; Liu, Aaron
> Subject: [PATCH] drm/amd/pm: correct the sequence of sending gpu reset
> msg
>
> the 2nd parameter should be smu msg type rather than asic msg index.
>
> Signed-off-by: Yifan Zhang
> Change-Id: I0a65fac53b06c053ce193580d68cf586e77d2c2d
> ---
> drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c | 9 ++---
> 1 file changed, 2 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
> index e90387a84cbb..e2d099409123 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
> @@ -262,14 +262,9 @@ static int yellow_carp_post_smu_init(struct
> smu_context *smu)
>
> static int yellow_carp_mode_reset(struct smu_context *smu, int type) {
> - int ret = 0, index = 0;
> -
> - index = smu_cmn_to_asic_specific_index(smu,
> CMN2ASIC_MAPPING_MSG,
> - SMU_MSG_GfxDeviceDriverReset);
> - if (index < 0)
> - return index == -EACCES ? 0 : index;
> + int ret = 0;
>
> - ret = smu_cmn_send_smc_msg_with_param(smu, (uint16_t)index,
> type, NULL);
> + ret = smu_cmn_send_smc_msg_with_param(smu,
> +SMU_MSG_GfxDeviceDriverReset, type, NULL);
> if (ret)
> dev_err(smu->adev->dev, "Failed to mode reset!\n");
>
> --
> 2.25.1
RE: [PATCH] drm/amdgpu: move GTT allocation from gmc_sw_init to gmc_hw_init
[Public]
Guchun.
Thanks your reminder. I need to modify again.
--
Best Regards
Aaron Liu
> -Original Message-
> From: Chen, Guchun
> Sent: Thursday, January 27, 2022 3:10 PM
> To: Liu, Aaron ; amd-gfx@lists.freedesktop.org
> Cc: Ji, Ruili ; Kim, Jonathan ;
> Kuehling, Felix ; Liu, Aaron
> ; Huang, Ray ; Deucher,
> Alexander
> Subject: RE: [PATCH] drm/amdgpu: move GTT allocation from gmc_sw_init
> to gmc_hw_init
>
> [Public]
>
> This will create sdma_access_bo only for ASIC with gmc v10? Original
> creation occurs in amdgpu_ttm_init, it's not limited to ASICs with gmc v10.
>
> Regards,
> Guchun
>
> -Original Message-
> From: amd-gfx On Behalf Of
> Aaron Liu
> Sent: Thursday, January 27, 2022 3:04 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Ji, Ruili ; Kim, Jonathan ;
> Kuehling, Felix ; Liu, Aaron
> ; Huang, Ray ; Deucher,
> Alexander
> Subject: [PATCH] drm/amdgpu: move GTT allocation from gmc_sw_init to
> gmc_hw_init
>
> The below patch causes system hang for harvested ASICs.
> d015e9861e55 drm/amdgpu: improve debug VRAM access performance
> using sdma
>
> The root cause is that GTT buffer should be allocated after GC SA harvest
> programming completed.
>
> For harvested AISC, the GC SA harvest process(see utcl2_harvest) is
> programmed in gmc_v10_0_hw_init function. This is a hardware
> programming.
> Therefore should be located in hw init. Hence need to move GTT allocation
> from gmc_v10_0_sw_init to gmc_v10_0_hw_init.
>
> Signed-off-by: Aaron Liu
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 8
> drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 9 +
> 2 files changed, 9 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index 3d8a20956b74..7ce0478b2908 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -1823,12 +1823,6 @@ int amdgpu_ttm_init(struct amdgpu_device
> *adev)
> return r;
> }
>
> - if (amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE,
> - AMDGPU_GEM_DOMAIN_GTT,
> - >mman.sdma_access_bo, NULL,
> - >mman.sdma_access_ptr))
> - DRM_WARN("Debug VRAM access will use slowpath MM
> access\n");
> -
> return 0;
> }
>
> @@ -1850,8 +1844,6 @@ void amdgpu_ttm_fini(struct amdgpu_device
> *adev)
> if (adev->mman.stolen_reserved_size)
> amdgpu_bo_free_kernel(
> >mman.stolen_reserved_memory,
> NULL, NULL);
> - amdgpu_bo_free_kernel(>mman.sdma_access_bo, NULL,
> - >mman.sdma_access_ptr);
> amdgpu_ttm_fw_reserve_vram_fini(adev);
>
> if (drm_dev_enter(adev_to_drm(adev), )) { diff --git
> a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> index 73ab0eebe4e2..c560bdc2a93c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> @@ -1062,6 +1062,12 @@ static int gmc_v10_0_hw_init(void *handle)
> if (adev->umc.funcs && adev->umc.funcs->init_registers)
> adev->umc.funcs->init_registers(adev);
>
> + if (amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE,
> + AMDGPU_GEM_DOMAIN_GTT,
> + >mman.sdma_access_bo, NULL,
> + >mman.sdma_access_ptr))
> + DRM_WARN("Debug VRAM access will use slowpath MM
> access\n");
> +
> return 0;
> }
>
> @@ -1082,6 +1088,9 @@ static int gmc_v10_0_hw_fini(void *handle) {
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> + amdgpu_bo_free_kernel(>mman.sdma_access_bo, NULL,
> + >mman.sdma_access_ptr);
> +
> gmc_v10_0_gart_disable(adev);
>
> if (amdgpu_sriov_vf(adev)) {
> --
> 2.25.1
RE: [PATCH] drm/amd/display: Fix unused variable warning
[AMD Official Use Only] Reviewed-by: Aaron Liu -- Best Regards Aaron Liu > -Original Message- > From: Huang, Tim > Sent: Thursday, January 27, 2022 11:34 AM > To: amd-gfx@lists.freedesktop.org > Cc: Deucher, Alexander ; Huang, Ray > ; Liu, Aaron ; Huang, Tim > > Subject: [PATCH] drm/amd/display: Fix unused variable warning > > [Why] > It will build failed with unused variable 'dc' with '-Werror=unused- > variable'enabled when CONFIG_DRM_AMD_DC_DCN is not defined. > > Signed-off-by: Tim Huang > --- > drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > index 1057f976bec7..8f53c9f6b267 100644 > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > @@ -1027,7 +1027,6 @@ static int dm_dmub_hw_init(struct > amdgpu_device *adev) > const unsigned char *fw_inst_const, *fw_bss_data; > uint32_t i, fw_inst_const_size, fw_bss_data_size; > bool has_hw_support; > - struct dc *dc = adev->dm.dc; > > if (!dmub_srv) > /* DMUB isn't supported on the ASIC. */ @@ -1123,7 +1122,7 > @@ static int dm_dmub_hw_init(struct amdgpu_device *adev) > case IP_VERSION(3, 1, 3): /* Only for this asic hw internal rev B0 */ > hw_params.dpia_supported = true; > #if defined(CONFIG_DRM_AMD_DC_DCN) > - hw_params.disable_dpia = dc- > >debug.dpia_debug.bits.disable_dpia; > + hw_params.disable_dpia = > +adev->dm.dc->debug.dpia_debug.bits.disable_dpia; > #endif > break; > default: > -- > 2.25.1
RE: [PATCH 3/3] drm/amd/display: convert to DCE IP version checking
[AMD Official Use Only]
Tim，
Please remove TAB in the beginning of an empty line and the SPACE in the end of
a line.
With this fixed, series is:
Reviewed-by: Aaron Liu aaron@amd.com<mailto:aaron@amd.com>
--
Best Regards
Aaron Liu
> -Original Message-
> From: Huang, Tim
> Sent: Monday, January 24, 2022 11:21 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Huang, Ray
> ; Liu, Aaron ; Huang, Tim
>
> Subject: [PATCH 3/3] drm/amd/display: convert to DCE IP version checking
>
> Use IP versions rather than asic_type to differentiate IP version specific
> features.
>
> Signed-off-by: Tim Huang mailto:xiaohu.hu...@amd.com>>
> ---
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 +---
> 1 file changed, 5 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 87299e62fe12..c967e1e344e4 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -1119,19 +1119,17 @@ static int dm_dmub_hw_init(struct
> amdgpu_device *adev)
> for (i = 0; i < fb_info->num_fb; ++i)
> hw_params.fb[i] = _info->fb[i];
>
> -switch (adev->asic_type) {
> -case CHIP_YELLOW_CARP:
> -if (dc->ctx->asic_id.hw_internal_rev != YELLOW_CARP_A0) {
> -hw_params.dpia_supported = true;
> + switch (adev->ip_versions[DCE_HWIP][0]) {
> + case IP_VERSION(3, 1, 3): /* Only for this asic hw internal rev B0 */
> + hw_params.dpia_supported = true;
> #if defined(CONFIG_DRM_AMD_DC_DCN)
> -hw_params.disable_dpia = dc-
> >debug.dpia_debug.bits.disable_dpia;
> + hw_params.disable_dpia = dc-
> >debug.dpia_debug.bits.disable_dpia;
> #endif
> -}
> break;
> default:
> break;
> }
> -
> +
> status = dmub_srv_hw_init(dmub_srv, _params);
> if (status != DMUB_STATUS_OK) {
> DRM_ERROR("Error initializing DMUB HW: %d\n", status);
> --
> 2.25.1
RE: [PATCH 1/5] drm/amdgpu: set APU flag based on IP discovery table
[AMD Official Use Only]
Reviewed-by: Aaron Liu
--
Best Regards
Aaron Liu
> -Original Message-
> From: amd-gfx On Behalf Of Alex
> Deucher
> Sent: Saturday, January 22, 2022 4:22 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander
> Subject: [PATCH 1/5] drm/amdgpu: set APU flag based on IP discovery table
>
> Use the IP versions to set the APU flag when necessary.
>
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 13 +
> 1 file changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> index e6a26b554254..ddbe13c9e4c7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> @@ -1253,6 +1253,19 @@ int amdgpu_discovery_set_ip_blocks(struct
> amdgpu_device *adev)
> return -EINVAL;
> }
>
> + switch (adev->ip_versions[GC_HWIP][0]) {
> + case IP_VERSION(9, 1, 0):
> + case IP_VERSION(9, 2, 2):
> + case IP_VERSION(9, 3, 0):
> + case IP_VERSION(10, 1, 3):
> + case IP_VERSION(10, 3, 1):
> + case IP_VERSION(10, 3, 3):
> + adev->flags |= AMD_IS_APU;
> + break;
> + default:
> + break;
> + }
> +
> if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(4, 8, 0))
> adev->gmc.xgmi.supported = true;
>
> --
> 2.34.1
RE: [PATCH] drm/amdgpu: update RLC_PG_DELAY_3 Value to 200us for yellow carp
[AMD Official Use Only]
Ray,
That ROCR issue is caused by CGCG(NOT CGPG).
With this patch applied, the rocr issue still exists.
--
Best Regards
Aaron Liu
> -Original Message-
> From: Huang, Ray
> Sent: Tuesday, November 2, 2021 5:19 PM
> To: Liu, Aaron
> Cc: amd-gfx@lists.freedesktop.org; Deucher, Alexander
>
> Subject: Re: [PATCH] drm/amdgpu: update RLC_PG_DELAY_3 Value to 200us
> for yellow carp
>
> On Tue, Nov 02, 2021 at 04:51:18PM +0800, Liu, Aaron wrote:
> > For yellow carp, the desired CGPG hysteresis value is 0x4E20.
> >
> > Signed-off-by: Aaron Liu
> > ---
> > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 5 +
> > 1 file changed, 1 insertion(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > index 90a834dc4008..b53b36f5ae92 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > @@ -8316,11 +8316,8 @@ static void gfx_v10_cntl_power_gating(struct
> amdgpu_device *adev, bool enable)
> > if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
> > switch (adev->ip_versions[GC_HWIP][0]) {
> > case IP_VERSION(10, 3, 1):
> > - data = 0x4E20 &
> RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
> > - WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
> > - break;
> > case IP_VERSION(10, 3, 3):
> > - data = 0x1388 &
> RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
> > + data = 0x4E20 &
> RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
>
> Acked-by: Huang Rui
>
> Is this patch able to fix the cgpg issue in ROCr test?
>
> Thanks,
> Ray
RE: [PATCH] drm/amdgpu/pm: drop pp_power_profile_mode support for APUs
[AMD Official Use Only]
Sorry, Mario.
Please don't upstream.
We need to discuss whether to drop pp_power_profile_mode support for RN/VGH.
--
Best Regards
Aaron Liu
> -Original Message-
> From: amd-gfx On Behalf Of Liu,
> Aaron
> Sent: Friday, October 29, 2021 10:03 AM
> To: Limonciello, Mario ; amd-
> g...@lists.freedesktop.org
> Cc: Limonciello, Mario
> Subject: RE: [PATCH] drm/amdgpu/pm: drop pp_power_profile_mode
> support for APUs
>
> [AMD Official Use Only]
>
> Reviewed-by: Aaron Liu
>
> --
> Best Regards
> Aaron Liu
>
> > -Original Message-
> > From: amd-gfx On Behalf Of
> > Mario Limonciello
> > Sent: Thursday, October 28, 2021 11:54 PM
> > To: amd-gfx@lists.freedesktop.org
> > Cc: Limonciello, Mario
> > Subject: [PATCH] drm/amdgpu/pm: drop pp_power_profile_mode support
> for
> > APUs
> >
> > Although this has been plumbed for Renoir, Green Sardine, Van Gogh,
> > and Yellow Carp the functionality in the SMU doesn't do anything for
> these APUs.
> > Drop the associated code with them.
> >
> > Signed-off-by: Mario Limonciello
> > ---
> > .../gpu/drm/amd/pm/inc/smu_v13_0_1_ppsmc.h| 4 +-
> > .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 86 --
> > .../gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 87 ---
> > .../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c | 87
> > ---
> > 4 files changed, 2 insertions(+), 262 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1_ppsmc.h
> > b/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1_ppsmc.h
> > index 1d3447991d0c..23d24173bc5d 100644
> > --- a/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1_ppsmc.h
> > +++ b/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1_ppsmc.h
> > @@ -51,7 +51,7 @@
> > #define PPSMC_MSG_PowerUpVcn0x07 ///< Power up VCN;
> > VCN is power gated by default
> > #define PPSMC_MSG_SetHardMinVcn 0x08 ///< For wireless
> > display
> > #define PPSMC_MSG_SetSoftMinGfxclk 0x09 ///< Set SoftMin for
> > GFXCLK, argument is frequency in MHz
> > -#define PPSMC_MSG_ActiveProcessNotify 0x0A ///< Set active work
> > load type
> > +#define PPSMC_MSG_SPARE00x0A ///< Spare
> > #define PPSMC_MSG_ForcePowerDownGfx 0x0B ///< Force power
> > down GFX, i.e. enter GFXOFF
> > #define PPSMC_MSG_PrepareMp1ForUnload 0x0C ///< Prepare
> > PMFW for GFX driver unload
> > #define PPSMC_MSG_SetDriverDramAddrHigh 0x0D ///< Set high 32
> > bits of DRAM address for Driver table transfer @@ -63,7 +63,7 @@
> > #define PPSMC_MSG_SetHardMinSocclkByFreq0x13 ///< Set hard min
> > for SOC CLK
> > #define PPSMC_MSG_SetSoftMinFclk0x14 ///< Set hard min for
> > FCLK
> > #define PPSMC_MSG_SetSoftMinVcn 0x15 ///< Set soft min for
> > VCN clocks (VCLK and DCLK)
> > -#define PPSMC_MSG_SPARE00x16 ///< Spared
> > +#define PPSMC_MSG_SPARE10x16 ///< Spare
> > #define PPSMC_MSG_GetGfxclkFrequency0x17 ///< Get GFX clock
> > frequency
> > #define PPSMC_MSG_GetFclkFrequency 0x18 ///< Get FCLK
> > frequency
> > #define PPSMC_MSG_AllowGfxOff 0x19 ///< Inform PMFW of
> > allowing GFXOFF entry
> > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> > b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> > index 421f38e8dada..2451d990d577 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> > @@ -72,7 +72,6 @@ static struct cmn2asic_msg_mapping
> > vangogh_message_map[SMU_MSG_MAX_COUNT] = {
> > MSG_MAP(RlcPowerNotify, PPSMC_MSG_RlcPowerNotify,
> > 0),
> > MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn,
> > 0),
> > MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxclk,
> > 0),
> > - MSG_MAP(ActiveProcessNotify,
> > PPSMC_MSG_ActiveProcessNotify, 0),
> > MSG_MAP(SetHardMinIspiclkByFreq,
> > PPSMC_MSG_SetHardMinIspiclkByFreq, 0),
> > MSG_MAP(SetHardMinIspxclkByFreq,
> > PPSMC_MSG_SetHardMinIspxclkByFreq, 0),
> > MSG_MAP(SetDriverDramAddrHigh,
> > PPSMC_MSG_SetDriverDramAddrHigh,0),
> > @@ -182,14 +181,6 @@ static struct cmn2asic_mapping
> > vangogh_table_map[SMU_TABLE_COUNT] = {
> > TAB_
RE: [PATCH] drm/amdgpu/pm: drop pp_power_profile_mode support for APUs
[AMD Official Use Only]
Reviewed-by: Aaron Liu
--
Best Regards
Aaron Liu
> -Original Message-
> From: amd-gfx On Behalf Of
> Mario Limonciello
> Sent: Thursday, October 28, 2021 11:54 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Limonciello, Mario
> Subject: [PATCH] drm/amdgpu/pm: drop pp_power_profile_mode support
> for APUs
>
> Although this has been plumbed for Renoir, Green Sardine, Van Gogh, and
> Yellow Carp the functionality in the SMU doesn't do anything for these APUs.
> Drop the associated code with them.
>
> Signed-off-by: Mario Limonciello
> ---
> .../gpu/drm/amd/pm/inc/smu_v13_0_1_ppsmc.h| 4 +-
> .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 86 --
> .../gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 87 ---
> .../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c | 87 ---
> 4 files changed, 2 insertions(+), 262 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1_ppsmc.h
> b/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1_ppsmc.h
> index 1d3447991d0c..23d24173bc5d 100644
> --- a/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1_ppsmc.h
> +++ b/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1_ppsmc.h
> @@ -51,7 +51,7 @@
> #define PPSMC_MSG_PowerUpVcn0x07 ///< Power up VCN;
> VCN is power gated by default
> #define PPSMC_MSG_SetHardMinVcn 0x08 ///< For wireless
> display
> #define PPSMC_MSG_SetSoftMinGfxclk 0x09 ///< Set SoftMin for
> GFXCLK, argument is frequency in MHz
> -#define PPSMC_MSG_ActiveProcessNotify 0x0A ///< Set active work
> load type
> +#define PPSMC_MSG_SPARE00x0A ///< Spare
> #define PPSMC_MSG_ForcePowerDownGfx 0x0B ///< Force power
> down GFX, i.e. enter GFXOFF
> #define PPSMC_MSG_PrepareMp1ForUnload 0x0C ///< Prepare
> PMFW for GFX driver unload
> #define PPSMC_MSG_SetDriverDramAddrHigh 0x0D ///< Set high 32
> bits of DRAM address for Driver table transfer
> @@ -63,7 +63,7 @@
> #define PPSMC_MSG_SetHardMinSocclkByFreq0x13 ///< Set hard min
> for SOC CLK
> #define PPSMC_MSG_SetSoftMinFclk0x14 ///< Set hard min for
> FCLK
> #define PPSMC_MSG_SetSoftMinVcn 0x15 ///< Set soft min for
> VCN clocks (VCLK and DCLK)
> -#define PPSMC_MSG_SPARE00x16 ///< Spared
> +#define PPSMC_MSG_SPARE10x16 ///< Spare
> #define PPSMC_MSG_GetGfxclkFrequency0x17 ///< Get GFX clock
> frequency
> #define PPSMC_MSG_GetFclkFrequency 0x18 ///< Get FCLK
> frequency
> #define PPSMC_MSG_AllowGfxOff 0x19 ///< Inform PMFW of
> allowing GFXOFF entry
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> index 421f38e8dada..2451d990d577 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> @@ -72,7 +72,6 @@ static struct cmn2asic_msg_mapping
> vangogh_message_map[SMU_MSG_MAX_COUNT] = {
> MSG_MAP(RlcPowerNotify, PPSMC_MSG_RlcPowerNotify,
> 0),
> MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn,
> 0),
> MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxclk,
> 0),
> - MSG_MAP(ActiveProcessNotify,
> PPSMC_MSG_ActiveProcessNotify,0),
> MSG_MAP(SetHardMinIspiclkByFreq,
> PPSMC_MSG_SetHardMinIspiclkByFreq,0),
> MSG_MAP(SetHardMinIspxclkByFreq,
> PPSMC_MSG_SetHardMinIspxclkByFreq,0),
> MSG_MAP(SetDriverDramAddrHigh,
> PPSMC_MSG_SetDriverDramAddrHigh, 0),
> @@ -182,14 +181,6 @@ static struct cmn2asic_mapping
> vangogh_table_map[SMU_TABLE_COUNT] = {
> TAB_MAP_VALID(DPMCLOCKS),
> };
>
> -static struct cmn2asic_mapping
> vangogh_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
> - WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,
> WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
> - WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,
> WORKLOAD_PPLIB_VIDEO_BIT),
> - WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,
> WORKLOAD_PPLIB_VR_BIT),
> - WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,
> WORKLOAD_PPLIB_COMPUTE_BIT),
> - WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,
> WORKLOAD_PPLIB_CUSTOM_BIT),
> -};
> -
> static const uint8_t vangogh_throttler_map[] = {
> [THROTTLER_STATUS_BIT_SPL] = (SMU_THROTTLER_SPL_BIT),
> [THROTTLER_STATUS_BIT_FPPT] = (SMU_THROTTLER_FPPT_BIT),
> @@ -1010,80 +1001,6 @@ static int vangogh_get_dpm_ultimate_freq(struct
> smu_context *smu,
> return ret;
> }
>
> -static int vangogh_get_power_profile_mode(struct smu_context *smu,
> -char *buf)
> -{
> - static const char *profile_name[] = {
> - "BOOTUP_DEFAULT",
> - "3D_FULL_SCREEN",
> -
RE: [PATCH] drm/amdgpu/display: add yellow carp B0 with rest of driver
[AMD Official Use Only]
Reviewed-by: Aaron Liu
--
Best Regards
Aaron Liu
> -Original Message-
> From: amd-gfx On Behalf Of Alex
> Deucher
> Sent: Wednesday, October 20, 2021 9:53 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander
> Subject: [PATCH] drm/amdgpu/display: add yellow carp B0 with rest of
> driver
>
> Fix revision id.
>
> Fixes: 626cbb641f1052 ("drm/amdgpu: support B0 external revision id
> for yellow carp")
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/display/include/dal_asic_id.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
> b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
> index a9974f12f7fb..e4a2dfacab4c 100644
> --- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
> +++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
> @@ -228,7 +228,7 @@ enum {
> #define FAMILY_YELLOW_CARP 146
>
> #define YELLOW_CARP_A0 0x01
> -#define YELLOW_CARP_B0 0x1A
> +#define YELLOW_CARP_B0 0x20
> #define YELLOW_CARP_UNKNOWN 0xFF
>
> #ifndef ASICREV_IS_YELLOW_CARP
> --
> 2.31.1
RE: [PATCH] drm/amd/display: Fix white screen page fault for gpuvm
[AMD Official Use Only]
Verified on Yellow Carp.
Acked-by: Aaron Liu
--
Best Regards
Aaron Liu
> -Original Message-
> From: Kazlauskas, Nicholas
> Sent: Tuesday, September 14, 2021 3:26 AM
> To: Alex Deucher
> Cc: amd-gfx list ; Liu, Aaron
>
> Subject: Re: [PATCH] drm/amd/display: Fix white screen page fault for
> gpuvm
>
> On 2021-09-13 3:13 p.m., Alex Deucher wrote:
> > Acked-by: Alex Deucher
> >
> > Can you add a fixes: tag?
> >
> > Alex
>
> Sure, I think the relevant patch is:
>
> Fixes: 64b1d0e8d50 ("drm/amd/display: Add DCN3.1 HWSEQ")
>
> Regards,
> Nicholas Kazlauskas
>
> >
> > On Mon, Sep 13, 2021 at 3:11 PM Nicholas Kazlauskas
> > wrote:
> >>
> >> [Why]
> >> The "base_addr_is_mc_addr" field was added for dcn3.1 support but
> >> pa_config was never updated to set it to false.
> >>
> >> Uninitialized memory causes it to be set to true which results in
> >> address mistranslation and white screen.
> >>
> >> [How]
> >> Use memset to ensure all fields are initialized to 0 by default.
> >>
> >> Cc: Aaron Liu
> >> Signed-off-by: Nicholas Kazlauskas
> >> ---
> >> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++
> >> 1 file changed, 2 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> >> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> >> index 53363728dbb..b0426bb3f2e 100644
> >> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> >> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> >> @@ -1125,6 +1125,8 @@ static void
> mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_
> >> uint32_t agp_base, agp_bot, agp_top;
> >> PHYSICAL_ADDRESS_LOC page_table_start, page_table_end,
> >> page_table_base;
> >>
> >> + memset(pa_config, 0, sizeof(*pa_config));
> >> +
> >> logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start)
> >> >>
> 18;
> >> pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
> >>
> >> --
> >> 2.25.1
> >>
RE: [PATCH] drm/amd/pm: update smu v13.0.1 firmware header
[AMD Official Use Only]
Reviewed-by: Aaron Liu
--
Best Regards
Aaron Liu
> -Original Message-
> From: Hou, Xiaomeng (Matthew)
> Sent: Tuesday, August 3, 2021 11:16 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Aaron ; Deucher, Alexander
> ; Huang, Ray ; Hou,
> Xiaomeng (Matthew)
> Subject: [PATCH] drm/amd/pm: update smu v13.0.1 firmware header
>
> Update smu v13.0.1 firmware header for yellow carp.
>
> Signed-off-by: Xiaomeng Hou
> ---
> drivers/gpu/drm/amd/pm/inc/smu_v13_0_1_pmfw.h | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1_pmfw.h
> b/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1_pmfw.h
> index 5627de734246..c5e26d619bf0 100644
> --- a/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1_pmfw.h
> +++ b/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1_pmfw.h
> @@ -111,7 +111,9 @@ typedef struct {
>uint32_t InWhisperMode: 1;
>uint32_t spare0 : 1;
>uint32_t ZstateStatus : 4;
> - uint32_t spare1 :12;
> + uint32_t spare1 : 4;
> + uint32_t DstateFun: 4;
> + uint32_t DstateDev: 4;
>// MP1_EXT_SCRATCH2
>uint32_t P2JobHandler :24;
>uint32_t RsmuPmiP2FinishedCnt : 8;
> --
> 2.17.1
RE: [PATCH] drm/amd/display: update header file name
[AMD Official Use Only] Reviewed-by: Aaron Liu -- Best Regards Aaron Liu > -Original Message- > From: Hou, Xiaomeng (Matthew) > Sent: Wednesday, July 7, 2021 5:05 PM > To: amd-gfx@lists.freedesktop.org > Cc: Liu, Aaron ; Kazlauskas, Nicholas > ; Hou, Xiaomeng (Matthew) > > Subject: [PATCH] drm/amd/display: update header file name > > Update the register header file name. > > Signed-off-by: Xiaomeng Hou > --- > drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c > b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c > index beea961749e1..8c2b77eb9459 100644 > --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c > +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c > @@ -31,8 +31,8 @@ > #include "dcn31_smu.h" > > #include "yellow_carp_offset.h" > -#include "mp/mp_13_0_1_offset.h" > -#include "mp/mp_13_0_1_sh_mask.h" > +#include "mp/mp_13_0_2_offset.h" > +#include "mp/mp_13_0_2_sh_mask.h" > > #define REG(reg_name) \ > (MP0_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + > reg ## reg_name) > -- > 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH] drm/amdgpu: move apu flags initialization to the start of device init
Reviewed-by: Aaron Liu
--
Best Regards
Aaron Liu
> -Original Message-
> From: Huang, Ray
> Sent: Tuesday, June 22, 2021 5:41 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Zhang, Hawking
> ; Zhou1, Tao ; Yu, Lang
> ; Gong, Curry ; Liu, Aaron
> ; Huang, Ray
> Subject: [PATCH] drm/amdgpu: move apu flags initialization to the start of
> device init
>
> In some asics, we need to adjust the behavior according to the apu flags at
> very early stage.
>
> Signed-off-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 36
> ++
> drivers/gpu/drm/amd/amdgpu/nv.c| 1 -
> drivers/gpu/drm/amd/amdgpu/soc15.c | 10 +-
> 3 files changed, 37 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 3f51b142fc83..e6702d136a6d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -1359,6 +1359,38 @@ static void
> amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev)
> adev->pm.smu_prv_buffer_size = 0;
> }
>
> +static int amdgpu_device_init_apu_flags(struct amdgpu_device *adev) {
> + if (!(adev->flags & AMD_IS_APU) ||
> + adev->asic_type < CHIP_RAVEN)
> + return 0;
> +
> + switch (adev->asic_type) {
> + case CHIP_RAVEN:
> + if (adev->pdev->device == 0x15dd)
> + adev->apu_flags |= AMD_APU_IS_RAVEN;
> + if (adev->pdev->device == 0x15d8)
> + adev->apu_flags |= AMD_APU_IS_PICASSO;
> + break;
> + case CHIP_RENOIR:
> + if ((adev->pdev->device == 0x1636) ||
> + (adev->pdev->device == 0x164c))
> + adev->apu_flags |= AMD_APU_IS_RENOIR;
> + else
> + adev->apu_flags |= AMD_APU_IS_GREEN_SARDINE;
> + break;
> + case CHIP_VANGOGH:
> + adev->apu_flags |= AMD_APU_IS_VANGOGH;
> + break;
> + case CHIP_YELLOW_CARP:
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> /**
> * amdgpu_device_check_arguments - validate module params
> *
> @@ -3358,6 +3390,10 @@ int amdgpu_device_init(struct amdgpu_device
> *adev,
> mutex_init(>psp.mutex);
> mutex_init(>notifier_lock);
>
> + r = amdgpu_device_init_apu_flags(adev);
> + if (r)
> + return r;
> +
> r = amdgpu_device_check_arguments(adev);
> if (r)
> return r;
> diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c
> b/drivers/gpu/drm/amd/amdgpu/nv.c index 455d0425787c..1470488a18e3
> 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
> @@ -1275,7 +1275,6 @@ static int nv_common_early_init(void *handle)
> break;
>
> case CHIP_VANGOGH:
> - adev->apu_flags |= AMD_APU_IS_VANGOGH;
> adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
> AMD_CG_SUPPORT_GFX_MGLS |
> AMD_CG_SUPPORT_GFX_CP_LS |
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
> b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index de85577c9cfd..b02436401d46 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -1360,10 +1360,7 @@ static int soc15_common_early_init(void *handle)
> break;
> case CHIP_RAVEN:
> adev->asic_funcs = _asic_funcs;
> - if (adev->pdev->device == 0x15dd)
> - adev->apu_flags |= AMD_APU_IS_RAVEN;
> - if (adev->pdev->device == 0x15d8)
> - adev->apu_flags |= AMD_APU_IS_PICASSO;
> +
> if (adev->rev_id >= 0x8)
> adev->apu_flags |= AMD_APU_IS_RAVEN2;
>
> @@ -1455,11 +1452,6 @@ static int soc15_common_early_init(void *handle)
> break;
> case CHIP_RENOIR:
> adev->asic_funcs = _asic_funcs;
> - if ((adev->pdev->device == 0x1636) ||
> - (adev->pdev->device == 0x164c))
> - adev->apu_flags |= AMD_APU_IS_RENOIR;
> - else
> - adev->apu_flags |= AMD_APU_IS_GREEN_SARDINE;
>
> if (adev->apu_flags & AMD_APU_IS_RENOIR)
> adev->external_rev_id = adev->rev_id + 0x91;
> --
> 2.25.1
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RE: [PATCH] drm/amdgpu: update mmhub mgcg for mmhub_v2_3
[AMD Official Use Only - Internal Distribution Only]
This patch has been Verfied on Van Gogh.
--
Best Regards
Aaron Liu
> -Original Message-
> From: Huang, Ray
> Sent: Wednesday, January 20, 2021 10:06 AM
> To: Liu, Aaron
> Cc: amd-gfx@lists.freedesktop.org; Deucher, Alexander
>
> Subject: Re: [PATCH] drm/amdgpu: update mmhub mgcg for
> mmhub_v2_3
>
> On Wed, Jan 20, 2021 at 09:57:32AM +0800, Liu, Aaron wrote:
> > Starting from vangogh, the ATCL2 and DAGB0 registers relative to
> > mgcg/ls has changed.
> >
> > For MGCG:
> > Replace mmMM_ATC_L2_MISC_CG with mmMM_ATC_L2_CGTT_CLK_CTRL.
> >
> > For MGLS:
> > Replace mmMM_ATC_L2_MISC_CG with mmMM_ATC_L2_CGTT_CLK_CTRL.
> > Add DAGB0_(WR/RD)_CGTT_CLK_CTRL registers.
> >
> > Signed-off-by: Aaron Liu
>
> Could you double verify it on vangogh as well?
>
> After that, patch is
>
> Acked-by: Huang Rui
>
> > ---
> > drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c | 84
> > ++---
> > 1 file changed, 61 insertions(+), 23 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
> > b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
> > index 92f02883daa3..8f2edba5bc9e 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
> > @@ -492,12 +492,11 @@
> > mmhub_v2_3_update_medium_grain_clock_gating(struct amdgpu_device
> *adev, {
> > uint32_t def, data, def1, data1;
> >
> > - def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);
> > + def = data = RREG32_SOC15(MMHUB, 0,
> mmMM_ATC_L2_CGTT_CLK_CTRL);
> > def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
> >
> > if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
> > - data |= MM_ATC_L2_MISC_CG__ENABLE_MASK;
> > -
> > + data &=
> ~MM_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK;
> > data1 &=
> ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
> >DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
> >DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
> @@ -506,8
> > +505,7 @@ mmhub_v2_3_update_medium_grain_clock_gating(struct
> amdgpu_device *adev,
> >DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
> >
> > } else {
> > - data &= ~MM_ATC_L2_MISC_CG__ENABLE_MASK;
> > -
> > + data |=
> MM_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK;
> > data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
> > DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
> > DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
> @@ -517,7 +515,7 @@
> > mmhub_v2_3_update_medium_grain_clock_gating(struct amdgpu_device
> *adev,
> > }
> >
> > if (def != data)
> > - WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data);
> > + WREG32_SOC15(MMHUB, 0,
> mmMM_ATC_L2_CGTT_CLK_CTRL, data);
> > if (def1 != data1)
> > WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2,
> data1); } @@ -526,17
> > +524,44 @@ static void
> > mmhub_v2_3_update_medium_grain_light_sleep(struct amdgpu_device
> *adev,
> >bool enable)
> > {
> > - uint32_t def, data;
> > -
> > - def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);
> > -
> > - if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
> > - data |= MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
> > - else
> > - data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
> > + uint32_t def, data, def1, data1, def2, data2;
> > +
> > + def = data = RREG32_SOC15(MMHUB, 0,
> mmMM_ATC_L2_CGTT_CLK_CTRL);
> > + def1 = data1 = RREG32_SOC15(MMHUB, 0,
> mmDAGB0_WR_CGTT_CLK_CTRL);
> > + def2 = data2 = RREG32_SOC15(MMHUB, 0,
> mmDAGB0_RD_CGTT_CLK_CTRL);
> > +
> > + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) {
> > + data &=
> ~MM_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK;
> > + data1
> &= !(DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK |
> > +
> DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK |
> > +
> DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK |
> > +
> DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK |
> > +
> DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK);
> > + data2 &= !(DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK
> |
> > +
>
Recall: [PATCH 6/8] drm/amd/pm: add yellow_carp_ppt implementation(V3)
Liu, Aaron would like to recall the message, "[PATCH 6/8] drm/amd/pm: add yellow_carp_ppt implementation(V3)". ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Recall: [PATCH 5/8] drm/amd/pm: add smu13 ip support for moment(V3)
Liu, Aaron would like to recall the message, "[PATCH 5/8] drm/amd/pm: add smu13 ip support for moment(V3)". ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH] drm/amdgpu: allow TMZ on vangogh
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Aaron Liu
--
Best Regards
Aaron Liu
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Friday, October 30, 2020 4:32 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH] drm/amdgpu: allow TMZ on vangogh
Uses the same pathes as navi.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index fa799600a58f..1449489cbe78 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -393,6 +393,7 @@ void amdgpu_gmc_tmz_set(struct amdgpu_device *adev)
case CHIP_NAVI10:
case CHIP_NAVI14:
case CHIP_NAVI12:
+ case CHIP_VANGOGH:
/* Don't enable it by default yet.
*/
if (amdgpu_tmz < 1) {
--
2.25.4
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RE: [PATCH 1/2] drm:amdgpu: check before setting hw priority
[AMD Public Use]
Series is:
Tested-by: Aaron Liu
--
Best Regards
Aaron Liu
-Original Message-
From: Das, Nirmoy
Sent: Wednesday, October 14, 2020 9:53 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Koenig, Christian
; Chen, Guchun ; Liu, Aaron
; Das, Nirmoy
Subject: [PATCH 1/2] drm:amdgpu: check before setting hw priority
Check validity of drm_gpu_scheduler before setting hw priority.
Also fix a minor indentation issue.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index a03398c87344..c8da0978d4f6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -504,9 +504,9 @@ struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx
*ctx, }
static void amdgpu_ctx_set_entity_priority(struct amdgpu_ctx *ctx,
- struct amdgpu_ctx_entity *aentity,
- int hw_ip,
- enum drm_sched_priority priority)
+ struct amdgpu_ctx_entity *aentity,
+ int hw_ip,
+ enum drm_sched_priority priority)
{
struct amdgpu_device *adev = ctx->adev;
unsigned int hw_prio;
@@ -523,6 +523,9 @@ static void amdgpu_ctx_set_entity_priority(struct
amdgpu_ctx *ctx,
hw_prio = array_index_nospec(hw_prio, AMDGPU_RING_PRIO_MAX);
scheds = adev->gpu_sched[hw_ip][hw_prio].sched;
num_scheds = adev->gpu_sched[hw_ip][hw_prio].num_scheds;
+ if (!scheds || !num_scheds)
+ return;
+
drm_sched_entity_modify_sched(>entity, scheds,
num_scheds);
}
--
2.28.0
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RE: [PATCH] Revert "drm/scheduler: improve job distribution with multiple queues"
[AMD Official Use Only - Approved for External Use]
Acked-by: Aaron Liu
--
Best Regards
Aaron Liu
-Original Message-
From: Zhu, Changfeng
Sent: Friday, October 9, 2020 2:17 PM
To: amd-gfx@lists.freedesktop.org; Liu, Aaron
Cc: Zhu, Changfeng
Subject: [PATCH] Revert "drm/scheduler: improve job distribution with multiple
queues"
From: changzhu
From: Changfeng
It needs to revert this patch to avoid amdgpu_test compute hang problem on
picasso/raven1
Change-Id: I5c298bb0c6cd64c67de712db551d15974c41493e
Signed-off-by: Changfeng
---
drivers/gpu/drm/scheduler/sched_entity.c | 2 +-
drivers/gpu/drm/scheduler/sched_main.c | 14 ++
include/drm/gpu_scheduler.h | 6 +++---
3 files changed, 10 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/scheduler/sched_entity.c
b/drivers/gpu/drm/scheduler/sched_entity.c
index 146380118962..c803e14eed91 100644
--- a/drivers/gpu/drm/scheduler/sched_entity.c
+++ b/drivers/gpu/drm/scheduler/sched_entity.c
@@ -486,7 +486,7 @@ void drm_sched_entity_push_job(struct drm_sched_job
*sched_job,
bool first;
trace_drm_sched_job(sched_job, entity);
- atomic_inc(>rq->sched->score);
+ atomic_inc(>rq->sched->num_jobs);
WRITE_ONCE(entity->last_user, current->group_leader);
first = spsc_queue_push(>job_queue, _job->queue_node);
diff --git a/drivers/gpu/drm/scheduler/sched_main.c
b/drivers/gpu/drm/scheduler/sched_main.c
index 9a0d77a68018..851443a19ee0 100644
--- a/drivers/gpu/drm/scheduler/sched_main.c
+++ b/drivers/gpu/drm/scheduler/sched_main.c
@@ -92,7 +92,6 @@ void drm_sched_rq_add_entity(struct drm_sched_rq *rq,
if (!list_empty(>list))
return;
spin_lock(>lock);
- atomic_inc(>sched->score);
list_add_tail(>list, >entities);
spin_unlock(>lock);
}
@@ -111,7 +110,6 @@ void drm_sched_rq_remove_entity(struct drm_sched_rq *rq,
if (list_empty(>list))
return;
spin_lock(>lock);
- atomic_dec(>sched->score);
list_del_init(>list);
if (rq->current_entity == entity)
rq->current_entity = NULL;
@@ -649,7 +647,7 @@ static void drm_sched_process_job(struct dma_fence *f,
struct dma_fence_cb *cb)
struct drm_gpu_scheduler *sched = s_fence->sched;
atomic_dec(>hw_rq_count);
- atomic_dec(>score);
+ atomic_dec(>num_jobs);
trace_drm_sched_process_job(s_fence);
@@ -714,7 +712,7 @@ drm_sched_pick_best(struct drm_gpu_scheduler **sched_list,
{
struct drm_gpu_scheduler *sched, *picked_sched = NULL;
int i;
- unsigned int min_score = UINT_MAX, num_score;
+ unsigned int min_jobs = UINT_MAX, num_jobs;
for (i = 0; i < num_sched_list; ++i) {
sched = sched_list[i];
@@ -725,9 +723,9 @@ drm_sched_pick_best(struct drm_gpu_scheduler **sched_list,
continue;
}
- num_score = atomic_read(>score);
- if (num_score < min_score) {
- min_score = num_score;
+ num_jobs = atomic_read(>num_jobs);
+ if (num_jobs < min_jobs) {
+ min_jobs = num_jobs;
picked_sched = sched;
}
}
@@ -861,7 +859,7 @@ int drm_sched_init(struct drm_gpu_scheduler *sched,
spin_lock_init(>job_list_lock);
atomic_set(>hw_rq_count, 0);
INIT_DELAYED_WORK(>work_tdr, drm_sched_job_timedout);
- atomic_set(>score, 0);
+ atomic_set(>num_jobs, 0);
atomic64_set(>job_id_count, 0);
/* Each scheduler will run on a seperate kernel thread */ diff --git
a/include/drm/gpu_scheduler.h b/include/drm/gpu_scheduler.h index
92436553fd6a..a33590e62108 100644
--- a/include/drm/gpu_scheduler.h
+++ b/include/drm/gpu_scheduler.h
@@ -264,7 +264,7 @@ struct drm_sched_backend_ops {
* @job_list_lock: lock to protect the ring_mirror_list.
* @hang_limit: once the hangs by a job crosses this limit then it is marked
* guilty and it will be considered for scheduling further.
- * @score: score to help loadbalancer pick a idle sched
+ * @num_jobs: the number of jobs in queue in the scheduler
* @ready: marks if the underlying HW is ready to work
* @free_guilty: A hit to time out handler to free the guilty job.
*
@@ -285,8 +285,8 @@ struct drm_gpu_scheduler {
struct list_headring_mirror_list;
spinlock_t job_list_lock;
int hang_limit;
- atomic_tscore;
- boolready;
+ atomic_tnum_jobs;
+ boolready;
boolfree_guilty;
};
--
2.17.1
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RE: [PATCH] drm/amdgpu: check ring type for secure IBs
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Aaron Liu
--
Best Regards
Aaron Liu
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Friday, April 24, 2020 4:47 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH] drm/amdgpu: check ring type for secure IBs
We don't support secure operation on compute rings at the moment so reject them.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index ec2c5e164cd3..b91853fd66d3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -161,6 +161,12 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned
num_ibs,
return -EINVAL;
}
+ if ((ib->flags & AMDGPU_IB_FLAGS_SECURE) &&
+ (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)) {
+ dev_err(adev->dev, "secure submissions not supported on compute
rings\n");
+ return -EINVAL;
+ }
+
alloc_size = ring->funcs->emit_frame_size + num_ibs *
ring->funcs->emit_ib_size;
--
2.25.3
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RE: [PATCH] drm/amdgpu: fix the gfx hang while use per-ib secure flag
[AMD Official Use Only - Internal Distribution Only]
Reviewed: Aaron Liu
-Original Message-
From: Huang, Ray
Sent: Tuesday, February 25, 2020 9:58 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Koenig, Christian
; Liu, Aaron ; Tuikov, Luben
; Pelloux-prayer, Pierre-eric
; Huang, Ray
Subject: [PATCH] drm/amdgpu: fix the gfx hang while use per-ib secure flag
Since 6643ba1 frame control packets are only issued in presence of secure IB(s).
This causes hangs on some hardware (eg: Raven1). This patch restores the
unconditionnal frame control packets issuing, that's to keep the per-IB logic
regarding the secure flag.
Fixes: 6643ba1 drm/amdgpu: Move to a per-IB secure flag (TMZ)
Reported-by: Pierre-Eric Pelloux-Prayer
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 41 +++-
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 5 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 15 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 13 +-
4 files changed, 43 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index 4b2342d..9713a7d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -131,7 +131,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned
num_ibs,
uint64_t fence_ctx;
uint32_t status = 0, alloc_size;
unsigned fence_flags = 0;
- bool secure;
+ int secure = -1;
unsigned i;
int r = 0;
@@ -216,7 +216,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned
num_ibs,
amdgpu_ring_emit_cntxcntl(ring, status);
}
- secure = false;
for (i = 0; i < num_ibs; ++i) {
ib = [i];
@@ -228,27 +227,37 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned
num_ibs,
!amdgpu_sriov_vf(adev)) /* for SRIOV preemption, Preamble
CE ib must be inserted anyway */
continue;
- /* If this IB is TMZ, add frame TMZ start packet,
-* else, turn off TMZ.
-*/
- if (ib->flags & AMDGPU_IB_FLAGS_SECURE &&
ring->funcs->emit_tmz) {
- if (!secure) {
- secure = true;
- amdgpu_ring_emit_tmz(ring, true);
+ if (job && ring->funcs->emit_frame_cntl) {
+ if (secure == -1) {
+ if (ib->flags & AMDGPU_IB_FLAGS_SECURE) {
+ secure = 1;
+ amdgpu_ring_emit_frame_cntl(ring, true,
true);
+ } else {
+ secure = 0;
+ amdgpu_ring_emit_frame_cntl(ring, true,
false);
+ }
+ } else {
+ if (secure == 1 &&
+ !(ib->flags & AMDGPU_IB_FLAGS_SECURE)) {
+ secure = 0;
+ amdgpu_ring_emit_frame_cntl(ring,
false, true);
+ amdgpu_ring_emit_frame_cntl(ring, true,
false);
+ } else if (secure == 0 &&
+ ib->flags & AMDGPU_IB_FLAGS_SECURE) {
+ secure = 1;
+ amdgpu_ring_emit_frame_cntl(ring,
false, false);
+ amdgpu_ring_emit_frame_cntl(ring, true,
true);
+ }
}
- } else if (secure) {
- secure = false;
- amdgpu_ring_emit_tmz(ring, false);
}
amdgpu_ring_emit_ib(ring, job, ib, status);
status &= ~AMDGPU_HAVE_CTX_SWITCH;
}
- if (secure) {
- secure = false;
- amdgpu_ring_emit_tmz(ring, false);
- }
+ if (job && ring->funcs->emit_frame_cntl)
+ amdgpu_ring_emit_frame_cntl(ring, false,
+ (secure == 1) ? true : false);
#ifdef CONFIG_X86_64
if (!(adev->flags & AMD_IS_APU))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 24caff0..4d019d6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -166,7 +166,8 @@ struct amdgpu_ring_funcs {
void (*emit_reg_write_reg_wait)(struct amdgpu_ring *ring,
uint32_t reg0, uint32_t reg1,
uint32_t ref, uint32_t m
RE: [PATCH] drm/amdgpu: remove the alignment placeholder for secure buffer
Reviewed-by: Aaron Liu
BR,
Aaron Liu
> -Original Message-
> From: amd-gfx On Behalf Of
> Huang Rui
> Sent: Friday, January 17, 2020 3:48 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Huang, Ray
> ; Koenig, Christian
> Subject: [PATCH] drm/amdgpu: remove the alignment placeholder for secure
> buffer
>
> The alignment should match the page size for secure buffer, so we didn't
> configure it anymore.
>
> Signed-off-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 4
> 1 file changed, 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> index f39012e..41d49a0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> @@ -261,10 +261,6 @@ int amdgpu_gem_create_ioctl(struct drm_device
> *dev, void *data,
> resv = vm->root.base.bo->tbo.base.resv;
> }
>
> - if (flags & AMDGPU_GEM_CREATE_ENCRYPTED) {
> - /* XXX: pad out alignment to meet TMZ requirements */
> - }
> -
> r = amdgpu_gem_object_create(adev, size, args->in.alignment,
>(u32)(0x & args->in.domains),
>flags, ttm_bo_type_device, resv, );
> --
> 2.7.4
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.f
> reedesktop.org%2Fmailman%2Flistinfo%2Famd-
> gfxdata=02%7C01%7Caaron.liu%40amd.com%7Cfe128e2299c943be48
> 9d08d79b21a418%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C6
> 37148441147752302sdata=HRtRCe7OUhBK4ScG%2BplLUJiK%2Bn8wU1
> BXxb28r5t2bWk%3Dreserved=0
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RE: [PATCH 2/2] drm/amdgpu: enable S/G display for renoir
> -Original Message-
> From: Deucher, Alexander
> Sent: Wednesday, January 8, 2020 11:05 AM
> To: Liu, Aaron ; Alex Deucher
> ; amd-gfx@lists.freedesktop.org
> Subject: RE: [PATCH 2/2] drm/amdgpu: enable S/G display for renoir
>
> [AMD Official Use Only - Internal Distribution Only]
>
> > -Original Message-
> > From: Liu, Aaron
> > Sent: Tuesday, January 7, 2020 9:48 PM
> > To: Alex Deucher ; amd-
> > g...@lists.freedesktop.org
> > Cc: Deucher, Alexander
> > Subject: RE: [PATCH 2/2] drm/amdgpu: enable S/G display for renoir
> >
> > Reviewed & Tested-by: Aaron Liu
> >
>
> Did you test with limited vram? E.g, set the carve out to 32 or 64 MB so the
> driver actually uses gart for display?
>
Hi Alex,
If I lower the UMA size to 64M.(UMA default is 512M)
For Renoir and with [PATCH 2/2], white screen appears and ubuntu desktop cannot
boot up successfully.
For Raven, no matter with or without [PATCH 1/2], the system can bootup
normally.
> Thanks,
>
> Alex
>
> > BR,
> > Aaron Liu
> >
> > > -Original Message-
> > > From: amd-gfx On Behalf Of
> > > Alex Deucher
> > > Sent: Wednesday, January 8, 2020 5:13 AM
> > > To: amd-gfx@lists.freedesktop.org
> > > Cc: Deucher, Alexander
> > > Subject: [PATCH 2/2] drm/amdgpu: enable S/G display for renoir
> > >
> > > Everything is in place so go ahead and enable this for renoir.
> > >
> > > Signed-off-by: Alex Deucher
> > > ---
> > >
> > > I don't have a renoir board handy. Can someone test this?
> > >
> > > drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 1 +
> > > drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
> > > 2 files changed, 2 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> > > b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> > > index 6d520a3eec40..318605ca9bc3 100644
> > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> > > @@ -519,6 +519,7 @@ uint32_t
> > amdgpu_display_supported_domains(struct
> > > amdgpu_device *adev,
> > > switch (adev->asic_type) {
> > > case CHIP_CARRIZO:
> > > case CHIP_STONEY:
> > > + case CHIP_RENOIR:
> > > domain |= AMDGPU_GEM_DOMAIN_GTT;
> > > break;
> > > case CHIP_RAVEN:
> > > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > > index 05118c8860f9..3be7ab0ce9e3 100644
> > > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > > @@ -909,6 +909,7 @@ static int amdgpu_dm_init(struct amdgpu_device
> > > *adev)
> > > switch (adev->asic_type) {
> > > case CHIP_CARRIZO:
> > > case CHIP_STONEY:
> > > + case CHIP_RENOIR:
> > > init_data.flags.gpu_vm_support = true;
> > > break;
> > > case CHIP_RAVEN:
> > > --
> > > 2.24.1
> > >
> > > ___
> > > amd-gfx mailing list
> > > amd-gfx@lists.freedesktop.org
> > > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fli
> > > st
> > > s.f
> > > reedesktop.org%2Fmailman%2Flistinfo%2Famd-
> > >
> >
> gfxdata=02%7C01%7Caaron.liu%40amd.com%7Cd9cdd08e60a942e97c
> > >
> 6a08d793b67ea1%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C6
> > >
> >
> 37140284454500549sdata=TGuS5qqX8siW1sxWUZtQggnk4P2RPjxUiLk
> > > dvS1Fcog%3Dreserved=0
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RE: [PATCH 2/2] drm/amdgpu: enable S/G display for renoir
Reviewed & Tested-by: Aaron Liu
BR,
Aaron Liu
> -Original Message-
> From: amd-gfx On Behalf Of Alex
> Deucher
> Sent: Wednesday, January 8, 2020 5:13 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander
> Subject: [PATCH 2/2] drm/amdgpu: enable S/G display for renoir
>
> Everything is in place so go ahead and enable this for renoir.
>
> Signed-off-by: Alex Deucher
> ---
>
> I don't have a renoir board handy. Can someone test this?
>
> drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 1 +
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
> 2 files changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> index 6d520a3eec40..318605ca9bc3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> @@ -519,6 +519,7 @@ uint32_t amdgpu_display_supported_domains(struct
> amdgpu_device *adev,
> switch (adev->asic_type) {
> case CHIP_CARRIZO:
> case CHIP_STONEY:
> + case CHIP_RENOIR:
> domain |= AMDGPU_GEM_DOMAIN_GTT;
> break;
> case CHIP_RAVEN:
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 05118c8860f9..3be7ab0ce9e3 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -909,6 +909,7 @@ static int amdgpu_dm_init(struct amdgpu_device
> *adev)
> switch (adev->asic_type) {
> case CHIP_CARRIZO:
> case CHIP_STONEY:
> + case CHIP_RENOIR:
> init_data.flags.gpu_vm_support = true;
> break;
> case CHIP_RAVEN:
> --
> 2.24.1
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.f
> reedesktop.org%2Fmailman%2Flistinfo%2Famd-
> gfxdata=02%7C01%7Caaron.liu%40amd.com%7Cd9cdd08e60a942e97c
> 6a08d793b67ea1%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C6
> 37140284454500549sdata=TGuS5qqX8siW1sxWUZtQggnk4P2RPjxUiLk
> dvS1Fcog%3Dreserved=0
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RE: [PATCH] drm/amdgpu: implement TMZ accessor (v2)
> -Original Message-
> From: amd-gfx On Behalf Of
> Luben Tuikov
> Sent: Thursday, November 21, 2019 9:33 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Tuikov, Luben
> ; Koenig, Christian
> Subject: [PATCH] drm/amdgpu: implement TMZ accessor (v2)
>
> Implement an accessor of adev->tmz.enabled. Let not code around access it
> as "if (adev->tmz.enabled)"
> as the organization may change. Instead...
>
> Recruit "bool amdgpu_is_tmz(adev)" to return exactly this Boolean value.
> That is, this function is now an accessor of an already initialized and set
> adev
> and adev->tmz.
>
> Add "void amdgpu_tmz_set(adev)" to check and set
> adev->tmz.* at initialization time. After which
> one uses "bool amdgpu_is_tmz(adev)" to query whether adev supports TMZ.
>
> Also, remove circular header file include.
>
> v2: Remove amdgpu_tmz.[ch] as requested.
>
> Signed-off-by: Luben Tuikov
> ---
> drivers/gpu/drm/amd/amdgpu/Makefile| 2 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu.h| 6 ++-
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c| 23 ++
> drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h| 9
> drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.c| 52 --
> drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.h| 39
> 7 files changed, 39 insertions(+), 95 deletions(-) delete mode 100644
> drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.c
> delete mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.h
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
> b/drivers/gpu/drm/amd/amdgpu/Makefile
> index 83ee1c676e3a..7ae3b22c5628 100644
> --- a/drivers/gpu/drm/amd/amdgpu/Makefile
> +++ b/drivers/gpu/drm/amd/amdgpu/Makefile
> @@ -55,7 +55,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
> amdgpu_vf_error.o amdgpu_sched.o amdgpu_debugfs.o
> amdgpu_ids.o \
> amdgpu_gmc.o amdgpu_mmhub.o amdgpu_xgmi.o amdgpu_csa.o
> amdgpu_ras.o amdgpu_vm_cpu.o \
> amdgpu_vm_sdma.o amdgpu_discovery.o amdgpu_ras_eeprom.o
> amdgpu_nbio.o \
> - amdgpu_umc.o smu_v11_0_i2c.o amdgpu_tmz.o
> + amdgpu_umc.o smu_v11_0_i2c.o
>
> amdgpu-$(CONFIG_PERF_EVENTS) += amdgpu_pmu.o
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index d120fe58ebea..805e12ef13ea 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -90,7 +90,6 @@
> #include "amdgpu_mes.h"
> #include "amdgpu_umc.h"
> #include "amdgpu_mmhub.h"
> -#include "amdgpu_tmz.h"
>
> #define MAX_GPU_INSTANCE 16
>
> @@ -1266,5 +1265,10 @@ _name##_show(struct device *dev,
> \
> \
> static struct device_attribute pmu_attr_##_name = __ATTR_RO(_name)
>
> +static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) {
> + return adev->tmz.enabled;
> +}
> +
> #endif
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index b1408c5e4640..56836054e6a8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -64,7 +64,6 @@
> #include "amdgpu_xgmi.h"
> #include "amdgpu_ras.h"
> #include "amdgpu_pmu.h"
> -#include "amdgpu_tmz.h"
>
> #include
>
> @@ -1073,7 +1072,7 @@ static int amdgpu_device_check_arguments(struct
> amdgpu_device *adev)
>
> adev->firmware.load_type = amdgpu_ucode_get_load_type(adev,
> amdgpu_fw_load_type);
>
> - adev->tmz.enabled = amdgpu_is_tmz(adev);
> + amdgpu_tmz_set(adev);
>
> return ret;
> }
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> index a12f33c0f5df..a0245d8b2f37 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> @@ -333,3 +333,26 @@ void amdgpu_gmc_ras_fini(struct amdgpu_device
> *adev)
> amdgpu_mmhub_ras_fini(adev);
> amdgpu_xgmi_ras_fini(adev);
> }
> +
> +/**
> + * amdgpu_tmz_set -- check and set if a device supports TMZ
> + * @adev: amdgpu_device pointer
> + *
> + * Check and set if an the device @adev supports Trusted Memory
> + * Zones (TMZ).
> + */
> +void amdgpu_tmz_set(struct amdgpu_device *adev) {
> + if (!amdgpu_tmz)
> + return;
> +
> + if (adev->asic_type < CHIP_RAVEN ||
> + adev->asic_type == CHIP_ARCTURUS) {
> + dev_warn(adev->dev, "Trusted Memory Zone (TMZ) feature
> not supported\n");
> + return;
> + }
> +
> + adev->tmz.enabled = true;
> +
> + dev_info(adev->dev, "Trusted Memory Zone (TMZ) feature
> supported and
> +enabled\n"); }
Hi Luben,
TMZ is just a specific feature and I think this is a nice change that moving
amdgpu_tmz to amdgpu_gmc.h.
Another thing, you can rename amdgpu_tmz_set to amdgpu_gmc_tmz_set in
amdgpu_gmc.h/ amdgpu_gmc.c
In amdgpu_gmc.c, all functions are prefixed with
RE: [PATCH 5/5] drm/amdgpu: enable TMZ bit in FRAME_CONTROL for gfx10
BR,
Aaron Liu
> -Original Message-
> From: Tuikov, Luben
> Sent: Wednesday, November 20, 2019 7:52 AM
> To: Liu, Aaron ; amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Huang, Ray
> ; Koenig, Christian
> Subject: Re: [PATCH 5/5] drm/amdgpu: enable TMZ bit in FRAME_CONTROL
> for gfx10
>
> On 2019-11-18 12:18 a.m., Aaron Liu wrote:
> > This patch enables TMZ bit in FRAME_CONTROL for gfx10.
> >
> > Signed-off-by: Aaron Liu
> > ---
> > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > index d6e11ee..8dce067 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > @@ -4588,7 +4588,7 @@ static void gfx_v10_0_ring_emit_cntxcntl(struct
> amdgpu_ring *ring,
> > gfx_v10_0_ring_emit_ce_meta(ring,
> > flags & AMDGPU_IB_PREEMPTED ? true :
> false);
> >
> > - gfx_v10_0_ring_emit_tmz(ring, true, false);
> > + gfx_v10_0_ring_emit_tmz(ring, true, trusted);
> >
>
> Do you mean here "true" (the opposite of "false") as opposed to "trusted"?
>
Here need to consider both non-TMZ and TMZ. Trusted value is decided by
cs.in.flags in
amdgpu_cs_submit* from libdrm.
> Regards,
> Luben
>
> > dw2 |= 0x8000; /* set load_enable otherwise this package is just
> NOPs */
> > if (flags & AMDGPU_HAVE_CTX_SWITCH) {
> >
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RE: [PATCH 1/5] drm/amdgpu: expand sdma copy_buffer interface with tmz parameter
BR,
Aaron Liu
> -Original Message-
> From: Tuikov, Luben
> Sent: Wednesday, November 20, 2019 7:12 AM
> To: Liu, Aaron ; amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Huang, Ray
> ; Koenig, Christian
> Subject: Re: [PATCH 1/5] drm/amdgpu: expand sdma copy_buffer interface
> with tmz parameter
>
> I wonder if we really do need yet another function argument, thus increasing
> the argument list, or if the "tmz" boolean can/is already a property of the
> job/command/ib/etc., and if it can indeed be had from the latter entity...?
>
Hi Luben,
In fact, I also thought about it. Compared to add this argument to other
entities, perhaps it
is more clearly and simply. Another reason is that TMZ is a relatively
independent property.
> Regards,
> Luben
>
> On 2019-11-18 12:18 a.m., Aaron Liu wrote:
> > This patch expands sdma copy_buffer interface with tmz parameter.
> >
> > Signed-off-by: Aaron Liu
> > Reviewed-by: Christian König
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h | 5 +++--
> > drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 4 ++--
> > drivers/gpu/drm/amd/amdgpu/cik_sdma.c| 3 ++-
> > drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 3 ++-
> > drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 3 ++-
> > drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 3 ++-
> > drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 3 ++-
> > drivers/gpu/drm/amd/amdgpu/si_dma.c | 3 ++-
> > 8 files changed, 17 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
> > index 761ff8b..b313465 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
> > @@ -79,7 +79,8 @@ struct amdgpu_buffer_funcs {
> > /* dst addr in bytes */
> > uint64_t dst_offset,
> > /* number of byte to transfer */
> > -uint32_t byte_count);
> > +uint32_t byte_count,
> > +bool tmz);
> >
> > /* maximum bytes in a single operation */
> > uint32_tfill_max_bytes;
> > @@ -97,7 +98,7 @@ struct amdgpu_buffer_funcs {
> > uint32_t byte_count);
> > };
> >
> > -#define amdgpu_emit_copy_buffer(adev, ib, s, d, b)
> > (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
> > +#define amdgpu_emit_copy_buffer(adev, ib, s, d, b, t)
> > +(adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b),
> > +(t))
> > #define amdgpu_emit_fill_buffer(adev, ib, s, d, b)
> > (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
> >
> > struct amdgpu_sdma_instance *
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> > index 339088d..c08c15e 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> > @@ -2022,7 +2022,7 @@ static int amdgpu_map_buffer(struct
> ttm_buffer_object *bo,
> > dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
> > dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
> > amdgpu_emit_copy_buffer(adev, >ibs[0], src_addr,
> > - dst_addr, num_bytes);
> > + dst_addr, num_bytes, false);
> >
> > amdgpu_ring_pad_ib(ring, >ibs[0]);
> > WARN_ON(job->ibs[0].length_dw > num_dw); @@ -2093,7 +2093,7
> @@ int
> > amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
> > uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
> >
> > amdgpu_emit_copy_buffer(adev, >ibs[0], src_offset,
> > - dst_offset, cur_size_in_bytes);
> > + dst_offset, cur_size_in_bytes, false);
> >
> > src_offset += cur_size_in_bytes;
> > dst_offset += cur_size_in_bytes;
> > diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> > b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> > index c45304f..82cdb8f 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> > @@ -1313,7 +1313,8 @@ static void cik_sdma_set_irq_funcs(struct
> > amdgpu_device *adev) static void cik_sdma_emit_copy_buffer(struct
> amdgpu_ib *ib,
> > uint64_t src_offset,
> > uint64_t dst_offs
RE: [PATCH] drm/amd/powerplay: add missing header file declaration
Acked-by: Aaron Liu
BR,
Aaron Liu
> -Original Message-
> From: Quan, Evan
> Sent: Tuesday, November 19, 2019 11:57 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Aaron ; Quan, Evan
> Subject: [PATCH] drm/amd/powerplay: add missing header file declaration
>
> This can fix the compile errors below:
> drivers/gpu/drm/amd/amdgpu/../powerplay/smu_v11_0.c: In function
> ‘smu_v11_0_baco_set_state’:
> drivers/gpu/drm/amd/amdgpu/../powerplay/smu_v11_0.c:1674:27: error:
> implicit declaration of function ‘amdgpu_ras_get_context’ [-Werror=implicit-
> function-declaration]
> struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
>^
> drivers/gpu/drm/amd/amdgpu/../powerplay/smu_v11_0.c:1674:27: warning:
> initialization makes pointer from integer without a cast [-Wint-conversion]
> drivers/gpu/drm/amd/amdgpu/../powerplay/smu_v11_0.c:1692:19: error:
> dereferencing pointer to incomplete type ‘struct amdgpu_ras’
>if (!ras || !ras->supported) {
>
> Change-Id: I1242e64e82715774b8e2931530749782b9107e32
> Signed-off-by: Evan Quan
> ---
> drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> index 8b1c4164a1f6..f677743cb511 100644
> --- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> +++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> @@ -37,6 +37,7 @@
> #include "soc15_common.h"
> #include "atom.h"
> #include "amd_pcie.h"
> +#include "amdgpu_ras.h"
>
> #include "asic_reg/thm/thm_11_0_2_offset.h"
> #include "asic_reg/thm/thm_11_0_2_sh_mask.h"
> --
> 2.24.0
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RE: [PATCH 01/12] amdgpu: add UAPI for creating encrypted buffers
Thanks for reviews.
As Christian's suggestion, I added drm_version checking, for the older driver,
security test suites are disabled.
I create a remote branch for libdrm: remotes/origin/aaliu/for-tmz-support
BR,
Aaron Liu
From: Olsak, Marek
Sent: Saturday, November 16, 2019 3:53 AM
To: Koenig, Christian ; Deucher, Alexander
Cc: Christian König ; Liu, Aaron
; amd-gfx@lists.freedesktop.org; Huang, Ray
; Tuikov, Luben ; Liu, Leo
Subject: Re: [PATCH 01/12] amdgpu: add UAPI for creating encrypted buffers
The way this is upstreamed is that you submit the kernel and userspace patches
for review at the same time. When they see the userspace patches, the kernel
patches will be accepted. When the kernel patches land in the Dave's or Linus's
tree, the userspace patches can be pushed.
Marek
From: Olsak, Marek mailto:marek.ol...@amd.com>>
Sent: November 15, 2019 14:34
To: Koenig, Christian
mailto:christian.koe...@amd.com>>; Deucher, Alexander
mailto:alexander.deuc...@amd.com>>
Cc: Christian König
mailto:ckoenig.leichtzumer...@gmail.com>>;
Liu, Aaron mailto:aaron@amd.com>>;
amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org>
mailto:amd-gfx@lists.freedesktop.org>>; Huang,
Ray mailto:ray.hu...@amd.com>>; Tuikov, Luben
mailto:luben.tui...@amd.com>>; Liu, Leo
mailto:leo@amd.com>>
Subject: Re: [PATCH 01/12] amdgpu: add UAPI for creating encrypted buffers
In the kernel tree, you need to do "make headers_install". Then copy
amdgpu_drm.h from ./usr/ to the libdrm tree and discard parts that we can't
upstream (freesync).
Marek
From: Koenig, Christian
mailto:christian.koe...@amd.com>>
Sent: November 15, 2019 10:08
To: Deucher, Alexander
mailto:alexander.deuc...@amd.com>>
Cc: Christian König
mailto:ckoenig.leichtzumer...@gmail.com>>;
Liu, Aaron mailto:aaron@amd.com>>;
amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org>
mailto:amd-gfx@lists.freedesktop.org>>; Olsak,
Marek mailto:marek.ol...@amd.com>>; Huang, Ray
mailto:ray.hu...@amd.com>>; Tuikov, Luben
mailto:luben.tui...@amd.com>>; Liu, Leo
mailto:leo@amd.com>>
Subject: Re: [PATCH 01/12] amdgpu: add UAPI for creating encrypted buffers
I know, that's the usual chicken and egg problem with updating libdrm.
But we should update the file with the kernel version and not pick all changes
line by line.
Christian.
Am 15.11.2019 15:49 schrieb "Deucher, Alexander"
mailto:alexander.deuc...@amd.com>>:
We can't land the kernel side until we have real userspace (e.g., Mesa) that
uses the TMZ interfaces. The unit tests are not enough.
Alex
____
From: Christian König
mailto:ckoenig.leichtzumer...@gmail.com>>
Sent: Friday, November 15, 2019 7:56 AM
To: Liu, Aaron mailto:aaron@amd.com>>;
amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org>
mailto:amd-gfx@lists.freedesktop.org>>
Cc: Olsak, Marek mailto:marek.ol...@amd.com>>; Huang, Ray
mailto:ray.hu...@amd.com>>; Tuikov, Luben
mailto:luben.tui...@amd.com>>; Deucher, Alexander
mailto:alexander.deuc...@amd.com>>; Liu, Leo
mailto:leo@amd.com>>; Koenig, Christian
mailto:christian.koe...@amd.com>>
Subject: Re: [PATCH 01/12] amdgpu: add UAPI for creating encrypted buffers
Am 15.11.19 um 04:34 schrieb Aaron Liu:
> From: Huang Rui mailto:ray.hu...@amd.com>>
>
> To align the kernel uapi change from Alex:
>
> "Add a flag to the GEM_CREATE ioctl to create encrypted buffers. Buffers with
> this flag set will be created with the TMZ bit set in the PTEs or engines
> accessing them. This is required in order to properly access the data from the
> engines."
>
> We will use GEM_CREATE_ENCRYPTED flag for secure buffer allocation.
>
> Signed-off-by: Huang Rui mailto:ray.hu...@amd.com>>
> Reviewed-by: Alex Deucher
> mailto:alexander.deuc...@amd.com>>
Please read up on how amdpu_drm.h is updated. The change must first land
upstream and then the file is synced up somehow semi-automatic.
Christian.
> ---
> include/drm/amdgpu_drm.h | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
> index 5c28aa7..1a95e37 100644
> --- a/include/drm/amdgpu_drm.h
> +++ b/include/drm/amdgpu_drm.h
> @@ -141,6 +141,11 @@ extern "C" {
>* releasing the memory
>*/
> #define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9)
> +/* Flag that BO will be encrypted and that the TMZ bit should be
> + * set in the PTEs when mapping this buffer via GPUVM or
> + * accessing it with various hw blocks
> + */
> +#define AMDGPU_GEM_CREATE_ENCRYPTED (1 << 10)
>
> /* Hybrid specific */
> /* Flag that the memory allocation should be from top of domain */
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RE: [PATCH 07/12] amdgpu: using IB flags for TMZ or non-TMZ
BR,
Aaron Liu
> -Original Message-
> From: Koenig, Christian
> Sent: Friday, November 15, 2019 8:50 PM
> To: Huang, Ray ; Liu, Aaron
> Cc: amd-gfx@lists.freedesktop.org; Deucher, Alexander
> ; Olsak, Marek ;
> Liu, Leo ; Tuikov, Luben
> Subject: Re: [PATCH 07/12] amdgpu: using IB flags for TMZ or non-TMZ
>
> Am 15.11.19 um 10:32 schrieb Huang Rui:
> > On Fri, Nov 15, 2019 at 11:34:50AM +0800, Liu, Aaron wrote:
> >> In kernel, cs->in.flags is used for TMZ. Hence libdrm should transfer
> >> the flag to kernel.
> >>
> >> Signed-off-by: Aaron Liu
> >> ---
> >> amdgpu/amdgpu.h| 4 +++-
> >> amdgpu/amdgpu_cs.c | 4
> >> 2 files changed, 7 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h index
> f45f9f7..aee3f3d
> >> 100644
> >> --- a/amdgpu/amdgpu.h
> >> +++ b/amdgpu/amdgpu.h
> >> @@ -342,7 +342,9 @@ struct amdgpu_cs_fence_info {
> >>* \sa amdgpu_cs_submit()
> >> */
> >> struct amdgpu_cs_request {
> >> - /** Specify flags with additional information */
> >> + /** Specify flags with additional information
> >> + * 0-normal, 1-tmz
> >> + */
> >>uint64_t flags;
> >>
> >>/** Specify HW IP block type to which to send the IB. */ diff
> >> --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c index
> >> 437c4a4..6f70771 100644
> >> --- a/amdgpu/amdgpu_cs.c
> >> +++ b/amdgpu/amdgpu_cs.c
> >> @@ -254,6 +254,10 @@ static int
> amdgpu_cs_submit_one(amdgpu_context_handle context,
> >>memset(, 0, sizeof(cs));
> >>cs.in.chunks = (uint64_t)(uintptr_t)chunk_array;
> >>cs.in.ctx_id = context->id;
> >> + /* in kernel, _pad is used as flags
> >> + * #define AMDGPU_CS_FLAGS_SECURE (1 << 0)
> >> + */
> >> + cs.in._pad = (uint32_t)ibs_request->flags;
> > _pad is not good here. Because it's used to pass the flags to input param.
> >
> > It's better to rename "_pad" in drm_amdgpu_cs_in as "flags" here.
>
> Actually I don't think we need that stuff altogether, please sync up with
> Marek on this.
>
> As far asI know the whole amdgpu_cs_submit interface was deprecated in
> favor of the new amdgpu_cs_submit_raw() interface.
Christian, Marek,
In addition to syncobj_command_submission_helper uses amdgpu_cs_submit_raw,
the other test suites still use older interface(amdgpu_cs_submit). We'd better
to
reorganize the relevant codes. This does not make much sense to only modify one
call.
> Regards,
> Christian.
>
> >
> > Thanks,
> > Ray
> >
> >>if (ibs_request->resources)
> >>cs.in.bo_list_handle = ibs_request->resources->handle;
> >>cs.in.num_chunks = ibs_request->number_of_ibs;
> >> --
> >> 2.7.4
> >>
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[PATCH 00/12] Initial TMZ support for libdrm and amdgpu_test
These series of patches are to initial TMZ support for libdrm and amdgpu_test. They are based on amd-staging-hybrid-master20190125 branch. So far, gfx/sdma TMZ tests are passed on Raven. Please review them. Thanks, Aaron Aaron Liu (6): amdgpu: using IB flags for TMZ or non-TMZ tests/amdgpu: expand secure param for exec_cs_helper tests/amdgpu: add atomic_mem cp_packet to verify the secure buffer tests/amdgpu: add test to submit a gfx command with secure context tests/amdgpu: add atomic dma command to verify the secure buffer tests/amdgpu: add test to submit a sdma command with secure context Huang Rui (6): amdgpu: add UAPI for creating encrypted buffers tests/amdgpu: add security test suite (v2) tests/amdgpu: add secure buffer allocation test for system memory tests/amdgpu: add secure buffer allocation test for invisible VRAM tests/amdgpu: expand write linear helper for security (v3) tests/amdgpu: add device handle as input param for exec_cs_helper and write_linear_helper (v4) amdgpu/amdgpu.h | 4 +- amdgpu/amdgpu_cs.c| 4 ++ include/drm/amdgpu_drm.h | 5 ++ tests/amdgpu/amdgpu_test.c| 7 ++ tests/amdgpu/amdgpu_test.h| 27 +++ tests/amdgpu/basic_tests.c| 161 -- tests/amdgpu/meson.build | 2 +- tests/amdgpu/security_tests.c | 134 +++ 8 files changed, 322 insertions(+), 22 deletions(-) create mode 100644 tests/amdgpu/security_tests.c BR, Aaron Liu ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH] drm/amd/powerplay: modify the parameters of SMU_MSG_PowerUpVcn to 0
Reviewed-by: Aaron Liu
BR,
Aaron Liu
> -Original Message-
> From: amd-gfx On Behalf Of chen
> gong
> Sent: Thursday, October 24, 2019 4:59 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Gong, Curry
> Subject: [PATCH] drm/amd/powerplay: modify the parameters of
> SMU_MSG_PowerUpVcn to 0
>
> The parameters what SMU_MSG_PowerUpVcn need is 0, not 1
>
> Signed-off-by: chen gong
> ---
> drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> index 45c5f54..4a97519 100644
> --- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> @@ -282,7 +282,7 @@ static int renoir_dpm_set_uvd_enable(struct
> smu_context *smu, bool enable)
> if (enable) {
> /* vcn dpm on is a prerequisite for vcn power gate messages
> */
> if (smu_feature_is_enabled(smu,
> SMU_FEATURE_VCN_PG_BIT)) {
> - ret = smu_send_smc_msg_with_param(smu,
> SMU_MSG_PowerUpVcn, 1);
> + ret = smu_send_smc_msg_with_param(smu,
> SMU_MSG_PowerUpVcn, 0);
> if (ret)
> return ret;
> }
> --
> 2.7.4
>
> ___
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> amd-gfx@lists.freedesktop.org
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RE: [PATCH] drm/amdgpu: Fix SDMA hang when performing VKexample test
Reviewed-by: Aaron Liu
BR,
Aaron Liu
> -Original Message-
> From: amd-gfx On Behalf Of chen
> gong
> Sent: Wednesday, October 23, 2019 2:51 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Gong, Curry
> Subject: [PATCH] drm/amdgpu: Fix SDMA hang when performing VKexample
> test
>
> VKexample test hang during Occlusion/SDMA/Varia runs.
> Clear XNACK_WATERMK in reg SDMA0_UTCL1_WATERMK to fix this issue.
>
> Signed-off-by: chen gong
> ---
> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> index 63a3792..45bd538 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> @@ -254,6 +254,7 @@ static const struct soc15_reg_golden
> golden_settings_sdma_4_3[] = {
> SOC15_REG_GOLDEN_VALUE(SDMA0, 0,
> mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfff7, 0x00403000),
> SOC15_REG_GOLDEN_VALUE(SDMA0, 0,
> mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfff7, 0x00403000),
> SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE,
> 0x03ff, 0x03c0),
> + SOC15_REG_GOLDEN_VALUE(SDMA0, 0,
> mmSDMA0_UTCL1_WATERMK, 0xfc00, 0x)
> };
>
> static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev,
> --
> 2.7.4
>
> ___
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[PATCH] Revert "drm/amdgpu: disable stutter mode for renoir"
This reverts commit c512e6fdfd2da917b5b6792902e7224f58a77f94. Since SBIOS WCD9925N, NMI printing disappeared. Hence enable stutter mode. Signed-off-by: Aaron Liu --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index bdab3f7..9d8d7e8 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2466,8 +2466,6 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY) dm->dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true; - if (adev->asic_type == CHIP_RENOIR) - dm->dc->debug.disable_stutter = true; return 0; fail: -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH 1/2] drm/amd/powerplay: Add mode2 mode for GPU RESET
Reviewed-by: Aaron Liu BR, Aaron Liu > -Original Message- > From: Gong, Curry > Sent: Tuesday, September 24, 2019 10:27 AM > To: Liu, Aaron ; amd-gfx@lists.freedesktop.org > Subject: RE: [PATCH 1/2] drm/amd/powerplay: Add mode2 mode for GPU > RESET > > Hi Aaron: > > Help to review again. > > -----Original Message- > From: Liu, Aaron > Sent: Monday, September 23, 2019 2:41 PM > To: Gong, Curry ; amd-gfx@lists.freedesktop.org > Cc: Gong, Curry > Subject: RE: [PATCH 1/2] drm/amd/powerplay: Add mode2 mode for GPU > RESET > > Hi curry, > > 1. You can separate the patch into 2 patches, one is workaround in > smu_suspend and another is the implementation of mode2_reset. > 2. hwmgr.h is used for amdgpu_powerplay instead of amdgpu_smu. You can > define it directly in amdgpu_smu.h > > BR, > Aaron Liu > > > -Original Message- > > From: amd-gfx On Behalf Of > > chen gong > > Sent: Monday, September 23, 2019 2:14 PM > > To: amd-gfx@lists.freedesktop.org > > Cc: Gong, Curry > > Subject: [PATCH 1/2] drm/amd/powerplay: Add mode2 mode for GPU > RESET > > > > Changes to function "smu_suspend" in amdgpu_smu.c is a workaround. > > > > We should get real information about if baco is enabled or not, while > > we always consider APU SMU feature as enabled in current code. > > > > I know APU do not support baco mode for GPU reset, so I use "adev- > >flags" > > to skip function "smu_feature_is_enabled". > > > > Signed-off-by: chen gong > > --- > > drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 5 - > > drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3 +++ > > drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 6 ++ > > 3 files changed, 13 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c > > b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c > > index 90fa444..e51d727 100644 > > --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c > > +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c > > @@ -1363,7 +1363,10 @@ static int smu_suspend(void *handle) > > int ret; > > struct amdgpu_device *adev = (struct amdgpu_device *)handle; > > struct smu_context *smu = >smu; > > - bool baco_feature_is_enabled = smu_feature_is_enabled(smu, > > SMU_FEATURE_BACO_BIT); > > + bool baco_feature_is_enabled = false; > > + > > + if (!(adev->flags & AMD_IS_APU)) > > + baco_feature_is_enabled = smu_feature_is_enabled(smu, > > +SMU_FEATURE_BACO_BIT); > > > > ret = smu_system_features_control(smu, false); > > if (ret) > > diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h > > b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h > > index 45da21d..35e8b0c 100644 > > --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h > > +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h > > @@ -537,6 +537,7 @@ struct smu_funcs > > enum smu_baco_state (*baco_get_state)(struct smu_context *smu); > > int (*baco_set_state)(struct smu_context *smu, enum > smu_baco_state > > state); > > int (*baco_reset)(struct smu_context *smu); > > +int (*mode2_reset)(struct smu_context *smu); > > int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum > > smu_clk_type clk_type, uint32_t *min, uint32_t *max); }; > > > > @@ -760,6 +761,8 @@ struct smu_funcs > > ((smu)->funcs->baco_get_state? (smu)->funcs- > > >baco_get_state((smu), (state)) : 0) #define smu_baco_reset(smu) \ > > ((smu)->funcs->baco_reset? (smu)->funcs->baco_reset((smu)) : 0) > > +#define smu_mode2_reset(smu) \ > > +((smu)->funcs->mode2_reset? (smu)->funcs->mode2_reset((smu)) : 0) > > #define smu_asic_set_performance_level(smu, level) \ > > ((smu)->ppt_funcs->set_performance_level? (smu)->ppt_funcs- > > >set_performance_level((smu), (level)) : -EINVAL); #define > > smu_dump_pptable(smu) \ diff --git > > a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c > > b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c > > index 24274c9..f762a98 100644 > > --- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c > > +++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c > > @@ -30,6 +30,7 @@ > > #include "soc15_common.h" > > #include "atom.h" > > #include "renoir_ppt.h" > > +#include "hwmgr.h" > > > > #include "asic_reg/mp/mp_12_0_0_offset.h" > > #include "asic_reg/mp/mp_12_0_0_sh_m
RE: [PATCH 1/2] drm/amd/powerplay: Add mode2 mode for GPU RESET
Hi curry,
1. You can separate the patch into 2 patches, one is workaround in smu_suspend
and another is the implementation of mode2_reset.
2. hwmgr.h is used for amdgpu_powerplay instead of amdgpu_smu. You can define
it directly in amdgpu_smu.h
BR,
Aaron Liu
> -Original Message-
> From: amd-gfx On Behalf Of chen
> gong
> Sent: Monday, September 23, 2019 2:14 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Gong, Curry
> Subject: [PATCH 1/2] drm/amd/powerplay: Add mode2 mode for GPU RESET
>
> Changes to function "smu_suspend" in amdgpu_smu.c is a workaround.
>
> We should get real information about if baco is enabled or not, while we
> always consider APU SMU feature as enabled in current code.
>
> I know APU do not support baco mode for GPU reset, so I use "adev->flags"
> to skip function "smu_feature_is_enabled".
>
> Signed-off-by: chen gong
> ---
> drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 5 -
> drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3 +++
> drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 6 ++
> 3 files changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index 90fa444..e51d727 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -1363,7 +1363,10 @@ static int smu_suspend(void *handle)
> int ret;
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> struct smu_context *smu = >smu;
> - bool baco_feature_is_enabled = smu_feature_is_enabled(smu,
> SMU_FEATURE_BACO_BIT);
> + bool baco_feature_is_enabled = false;
> +
> + if (!(adev->flags & AMD_IS_APU))
> + baco_feature_is_enabled = smu_feature_is_enabled(smu,
> +SMU_FEATURE_BACO_BIT);
>
> ret = smu_system_features_control(smu, false);
> if (ret)
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> index 45da21d..35e8b0c 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> @@ -537,6 +537,7 @@ struct smu_funcs
> enum smu_baco_state (*baco_get_state)(struct smu_context *smu);
> int (*baco_set_state)(struct smu_context *smu, enum
> smu_baco_state state);
> int (*baco_reset)(struct smu_context *smu);
> +int (*mode2_reset)(struct smu_context *smu);
> int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum
> smu_clk_type clk_type, uint32_t *min, uint32_t *max); };
>
> @@ -760,6 +761,8 @@ struct smu_funcs
> ((smu)->funcs->baco_get_state? (smu)->funcs-
> >baco_get_state((smu), (state)) : 0) #define smu_baco_reset(smu) \
> ((smu)->funcs->baco_reset? (smu)->funcs->baco_reset((smu)) : 0)
> +#define smu_mode2_reset(smu) \
> +((smu)->funcs->mode2_reset? (smu)->funcs->mode2_reset((smu)) : 0)
> #define smu_asic_set_performance_level(smu, level) \
> ((smu)->ppt_funcs->set_performance_level? (smu)->ppt_funcs-
> >set_performance_level((smu), (level)) : -EINVAL); #define
> smu_dump_pptable(smu) \ diff --git
> a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
> b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
> index 24274c9..f762a98 100644
> --- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
> +++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
> @@ -30,6 +30,7 @@
> #include "soc15_common.h"
> #include "atom.h"
> #include "renoir_ppt.h"
> +#include "hwmgr.h"
>
> #include "asic_reg/mp/mp_12_0_0_offset.h"
> #include "asic_reg/mp/mp_12_0_0_sh_mask.h"
> @@ -380,6 +381,10 @@ static int
> smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum
> smu_clk
> return ret;
> }
>
> +static int smu_v12_0_mode2_reset(struct smu_context *smu){
> + return smu_v12_0_send_msg_with_param(smu,
> +SMU_MSG_GfxDeviceDriverReset, SMU_ASIC_RESET_MODE_2); }
> +
> static const struct smu_funcs smu_v12_0_funcs = {
> .check_fw_status = smu_v12_0_check_fw_status,
> .check_fw_version = smu_v12_0_check_fw_version, @@ -394,6
> +399,7 @@ static const struct smu_funcs smu_v12_0_funcs = {
> .fini_smc_tables = smu_v12_0_fini_smc_tables,
> .populate_smc_tables = smu_v12_0_populate_smc_tables,
> .get_dpm_ultimate_freq = smu_v12_0_get_dpm_ultimate_freq,
> + .mode2_reset = smu_v12_0_mode2_reset,
> };
>
> void smu_v12_0_set_smu_funcs(struct smu_context *smu)
> --
> 2.7.4
>
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RE: [PATCH 2/2] drm/amdgpu: Use mode2 mode to perform GPU RESET for Renoir
Reviewed-by: Aaron Liu
BR,
Aaron Liu
> -Original Message-
> From: amd-gfx On Behalf Of chen
> gong
> Sent: Monday, September 23, 2019 2:14 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Gong, Curry
> Subject: [PATCH 2/2] drm/amdgpu: Use mode2 mode to perform GPU RESET
> for Renoir
>
> Signed-off-by: chen gong
> ---
> drivers/gpu/drm/amd/amdgpu/soc15.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
> b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index 58818761..0f639df9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -514,6 +514,8 @@ static int soc15_asic_baco_reset(struct
> amdgpu_device *adev)
>
> static int soc15_mode2_reset(struct amdgpu_device *adev) {
> + if (is_support_sw_smu(adev))
> + return smu_mode2_reset(>smu);
> if (!adev->powerplay.pp_funcs ||
> !adev->powerplay.pp_funcs->asic_reset_mode_2)
> return -ENOENT;
> @@ -528,6 +530,7 @@ soc15_asic_reset_method(struct amdgpu_device
> *adev)
>
> switch (adev->asic_type) {
> case CHIP_RAVEN:
> + case CHIP_RENOIR:
> return AMD_RESET_METHOD_MODE2;
> case CHIP_VEGA10:
> case CHIP_VEGA12:
> --
> 2.7.4
>
> ___
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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[PATCH] drm/amdgpu: remove program of lbpw for renoir
These is no LBPW on Renoir. So removing program of lbpw for renoir.
Signed-off-by: Aaron Liu
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index b75ef89..fe21ef8 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1646,7 +1646,6 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
switch (adev->asic_type) {
case CHIP_RAVEN:
- case CHIP_RENOIR:
gfx_v9_0_init_lbpw(adev);
break;
case CHIP_VEGA20:
@@ -3013,7 +3012,6 @@ static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
switch (adev->asic_type) {
case CHIP_RAVEN:
- case CHIP_RENOIR:
if (amdgpu_lbpw == 0)
gfx_v9_0_enable_lbpw(adev, false);
else
--
2.7.4
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RE: [PATCH] drm/amdkfd: fix the missed asic name while inited renoir_device_info
Reviewed & Tested-by: Aaron Liu
BR,
Aaron Liu
> -Original Message-
> From: Huang, Ray
> Sent: Tuesday, September 10, 2019 7:17 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Kuehling, Felix ; Liu, Aaron
> ; Huang, Ray
> Subject: [PATCH] drm/amdkfd: fix the missed asic name while inited
> renoir_device_info
>
> This patch fixes null pointer issue below, I missed to init the asic renior
> name
> while I rebase the patches.
>
> [ 106.004250] BUG: kernel NULL pointer dereference, address:
> [ 106.004254] #PF: supervisor read access in kernel
> mode [ 106.004256] #PF: error_code(0x) - not-present page
> [ 106.004257] PGD 0 P4D 0 [ 106.004261] Oops: [#1] SMP NOPTI
> [ 106.004264] CPU: 3 PID: 1422 Comm: modprobe Not tainted 5.2.0-rc1-
> custom #1 [ 106.004266] Hardware name: AMD Celadon-RN/Celadon-RN,
> BIOS
> WCD9814N_Weekly_19_08_1 08/14/2019
> [ 106.004272] RIP: 0010:strncpy+0x12/0x30 [ 106.004274] Code: c1 c0 11
> 48 c1 c6 15 48 31 d0 48 c1 c2 20 31 c2 89 d0 31 f0
> 41 5c 5d c3 55 48 85 d2 48 89 f8 48 89 e5 74 1e 48 01 fa 48 89 f9 <44> 0f b6
> 06
> 41 80 f8 01 44 88 01 48 83 de ff 48 83 c1 01 48 39 d1 [ 106.004278] RSP:
> 0018:c092c1fd37a8 EFLAGS: 00010286 [ 106.004281] RAX:
> 9e943466a28c RBX: 36ed RCX: 9e943466a28c
> [ 106.004283] RDX: 9e943466a2ac RSI: RDI:
> 9e943466a28c [ 106.004285] RBP: c092c1fd37a8 R08:
> 9e943d10 R09: 0228 [ 106.004287] R10:
> 9e94418dc5a8 R11: 9e944746c0d0 R12:
> [ 106.004289] R13: 9e943fa1ec00 R14: 9e943466a200 R15:
> 9e943466a200 [ 106.004291] FS: 7f7a022c5540()
> GS:9e9447ac()
> knlGS:
> [ 106.004294] CS: 0010 DS: ES: CR0: 80050033
> [ 106.004296] CR2: CR3: 0001ff0b CR4:
> 00340ee0 [ 106.004298] Call Trace:
> [ 106.004382] kfd_topology_add_device+0x150/0x610 [amdgpu]
> [ 106.004445] kgd2kfd_device_init+0x2e0/0x4f0 [amdgpu] [ 106.004509]
> amdgpu_amdkfd_device_init+0x14c/0x1b0 [amdgpu]
>
> Signed-off-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdkfd/kfd_device.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> index a2fe0cb..f329b82 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> @@ -353,6 +353,7 @@ static const struct kfd_device_info
> arcturus_device_info = {
>
> static const struct kfd_device_info renoir_device_info = {
> .asic_family = CHIP_RENOIR,
> + .asic_name = "renoir",
> .max_pasid_bits = 16,
> .max_no_of_hqd = 24,
> .doorbell_size = 8,
> --
> 2.7.4
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RE: [PATCH] drm/amd/display: Add stereo mux and dig programming calls for dcn21
Acked-by: Aaron Liu
BR,
Aaron Liu
> -Original Message-
> From: amd-gfx On Behalf Of
> roman...@amd.com
> Sent: Thursday, September 5, 2019 5:43 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Wentland, Harry ; Liu, Aaron
> ; Li, Roman ; Huang, Ray
> ; Deucher, Alexander
> ; Lakha, Bhawanpreet
>
> Subject: [PATCH] drm/amd/display: Add stereo mux and dig programming
> calls for dcn21
>
> From: Roman Li
>
> [Why]
> The earlier patch "Hook up calls to do stereo mux and dig programming..."
> doesn't include update for dcn21.
>
> [How]
> Align dcn21 gpio settings with updated stereo control interface.
>
> Signed-off-by: Roman Li
> ---
> .../amd/display/dc/gpio/dcn21/hw_factory_dcn21.c | 38
> --
> .../amd/display/dc/gpio/dcn21/hw_translate_dcn21.c | 3 +-
> 2 files changed, 36 insertions(+), 5 deletions(-)
>
> diff --git
> a/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c
> b/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c
> index 34485d9..8572678 100644
> --- a/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c
> +++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c
> @@ -35,12 +35,10 @@
>
> #include "hw_factory_dcn21.h"
>
> -
> #include "dcn/dcn_2_1_0_offset.h"
> #include "dcn/dcn_2_1_0_sh_mask.h"
> #include "renoir_ip_offset.h"
>
> -
> #include "reg_helper.h"
> #include "../hpd_regs.h"
> /* begin *
> @@ -136,6 +134,39 @@ static const struct ddc_sh_mask ddc_mask[] = {
> DDC_MASK_SH_LIST_DCN2(_MASK, 6)
> };
>
> +#include "../generic_regs.h"
> +
> +/* set field name */
> +#define SF_GENERIC(reg_name, field_name, post_fix)\
> + .field_name = reg_name ## __ ## field_name ## post_fix
> +
> +#define generic_regs(id) \
> +{\
> + GENERIC_REG_LIST(id)\
> +}
> +
> +static const struct generic_registers generic_regs[] = {
> + generic_regs(A),
> +};
> +
> +static const struct generic_sh_mask generic_shift[] = {
> + GENERIC_MASK_SH_LIST(__SHIFT, A),
> +};
> +
> +static const struct generic_sh_mask generic_mask[] = {
> + GENERIC_MASK_SH_LIST(_MASK, A),
> +};
> +
> +static void define_generic_registers(struct hw_gpio_pin *pin, uint32_t
> +en) {
> + struct hw_generic *generic = HW_GENERIC_FROM_BASE(pin);
> +
> + generic->regs = _regs[en];
> + generic->shifts = _shift[en];
> + generic->masks = _mask[en];
> + generic->base.regs = _regs[en].gpio; }
> +
> static void define_ddc_registers(
> struct hw_gpio_pin *pin,
> uint32_t en)
> @@ -181,7 +212,8 @@ static const struct hw_factory_funcs funcs = {
> .get_hpd_pin = dal_hw_hpd_get_pin,
> .get_generic_pin = dal_hw_generic_get_pin,
> .define_hpd_registers = define_hpd_registers,
> - .define_ddc_registers = define_ddc_registers
> + .define_ddc_registers = define_ddc_registers,
> + .define_generic_registers = define_generic_registers
> };
> /*
> * dal_hw_factory_dcn10_init
> diff --git
> a/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
> b/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
> index ad7c437..fbb58fb 100644
> --- a/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
> +++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
> @@ -58,7 +58,6 @@
> #define SF_HPD(reg_name, field_name, post_fix)\
> .field_name = reg_name ## __ ## field_name ## post_fix
>
> -
> /* macros to expend register list macro defined in HW object header file
> * end */
>
> @@ -71,7 +70,7 @@ static bool offset_to_id( {
> switch (offset) {
> /* GENERIC */
> - case REG(DC_GENERICA):
> + case REG(DC_GPIO_GENERIC_A):
> *id = GPIO_ID_GENERIC;
> switch (mask) {
> case DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK:
> --
> 2.7.4
>
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[PATCH] drm/amdgpu: disable stutter mode for renoir
With stutter mode enabled, NMI prints frequently. Disable stutter mode for renoir. Signed-off-by: Aaron Liu --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 708d595..8e2af2e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2539,6 +2539,8 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY) dm->dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true; + if (adev->asic_type == CHIP_RENOIR) + dm->dc->debug.disable_stutter = true; return 0; fail: -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 2/2] drm/amd/display: update renoir_ip_offset.h
This patch updates MP1_BASE in renoir_ip_offset.h
Signed-off-by: Aaron Liu
---
drivers/gpu/drm/amd/include/renoir_ip_offset.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/include/renoir_ip_offset.h
b/drivers/gpu/drm/amd/include/renoir_ip_offset.h
index 554714c..094648c 100644
--- a/drivers/gpu/drm/amd/include/renoir_ip_offset.h
+++ b/drivers/gpu/drm/amd/include/renoir_ip_offset.h
@@ -155,7 +155,7 @@ static const struct IP_BASE MP0_BASE ={ { { { 0x00016000,
0x0243FC00, 0x00DC
{ { 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE MP1_BASE ={ { { { 0x00016200, 0x02400400,
0x00E8, 0x00EC, 0x00F0 } },
+static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0x02400400,
0x00E8, 0x00EC, 0x00F0 } },
{ { 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0 } },
--
2.7.4
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[PATCH 1/2] drm/amd/display: bypass stereo programming
From: Roman Li
hack to avoid crash on renoir
should be resolved after upcoming gpio refactoring promotion
Signed-off-by: Roman Li
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 5b9dd16..ee2186c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2844,6 +2844,12 @@ static void dcn10_setup_stereo(struct pipe_ctx
*pipe_ctx, struct dc *dc)
{
struct crtc_stereo_flags flags = { 0 };
struct dc_stream_state *stream = pipe_ctx->stream;
+#ifdef CONFIG_DRM_AMD_DC_DCN2_1
+/* TODO: remove after gpio refactor gets promoted
+*otherwise it causing crash on Renoir
+*/
+ return;
+#endif
dcn10_config_stereo_parameters(stream, );
--
2.7.4
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RE: [PATCH xf86-video-amdgpu] Fix hang when entering into dpms-off mode
> -Original Message- > From: Michel Dänzer > Sent: Friday, March 01, 2019 4:43 PM > To: Liu, Aaron > Cc: amd-gfx@lists.freedesktop.org > Subject: Re: [PATCH xf86-video-amdgpu] Fix hang when entering into dpms- > off mode > > On 2019-03-01 7:37 a.m., Liu, Aaron wrote: > > @Michel Dänzer, > > > > I have reviewed your patch and verified it passed. > > Thanks Aaron, so I assume I can add > > Reviewed-by: Aaron Liu > Tested-by: Aaron Liu > > ? Sure > > > > I couldn't merge this merge request to your master manually. > > Don't worry, I'll merge it via the GitLab merge request UI. > > > -- > Earthling Michel Dänzer | https://www.amd.com > Libre software enthusiast | Mesa and X developer ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH xf86-video-amdgpu] Fix hang when entering into dpms-off mode
@Michel Dänzer, I have reviewed your patch and verified it passed. I couldn't merge this merge request to your master manually. The log is below: aaliu@lnx-aaliu:~/work/brahma/xf86-video-amdgpu-gitlab$ git push origin master Username for 'https://gitlab.freedesktop.org': aaliu Password for 'https://aa...@gitlab.freedesktop.org': remote: HTTP Basic: Access denied remote: You must use a personal access token with 'api' scope for Git over HTTP. remote: You can generate one at https://gitlab.freedesktop.org/profile/personal_access_tokens fatal: Authentication failed for 'https://gitlab.freedesktop.org/xorg/driver/xf86-video-amdgpu.git/' BR, Aaron Liu > -Original Message- > From: Michel Dänzer > Sent: Friday, March 01, 2019 12:36 AM > To: Liu, Aaron > Cc: amd-gfx@lists.freedesktop.org > Subject: Re: [PATCH xf86-video-amdgpu] Fix hang when entering into dpms- > off mode > > On 2019-02-28 1:05 p.m., Michel Dänzer wrote: > > On 2019-02-28 3:52 a.m., Aaron Liu wrote: > >> > >> @@ -900,7 +900,12 @@ CARD32 > amdgpu_dri2_deferred_event(OsTimerPtr timer, CARD32 now, pointer data) > >>delta_seq = delta_t * drmmode_crtc->dpms_last_fps; > >>delta_seq /= 100; > >>frame = (CARD64) drmmode_crtc->dpms_last_seq + delta_seq; > >> - if (event_info->drm_queue_seq) > >> + /* > >> + * If CRTC is in DPMS off state, it can't use vblank_handler. > >> + * Because drmmode_wait_vblank is not excuted in such as > >> + * amdgpu_dri2_schedule_swap/amdgpu_dri2_schedule_wait_msc. > >> + */ > >> + if (event_info->drm_queue_seq && amdgpu_crtc_is_enabled(crtc)) > >>drmmode_crtc->drmmode->event_context. > >>vblank_handler(pAMDGPUEnt->fd, frame, drm_now / > 100, > >> drm_now % 100, > >> > > > > This isn't a good solution I'm afraid, as it'll leave the struct > > amdgpu_drm_queue_entry memory associated with > > event_info->drm_queue_seq linked into the amdgpu_drm_queue list, > which > > would gradually slow down processing of that list. > > > > > > I think I know what the issue is, I'll work on a fix in the afternoon. > > Please test > https://gitlab.freedesktop.org/xorg/driver/xf86-video- > amdgpu/merge_requests/29 > . > > > -- > Earthling Michel Dänzer | https://www.amd.com > Libre software enthusiast | Mesa and X developer ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [[PATCH v2]drm/amdgpu/psp: ignore psp response status] drm/amdgpu/psp: ignore psp response status
Yes, thanks. I have modified the typo mistake of "response". BR, Aaron Liu > -Original Message- > From: Paul Menzel > Sent: Tuesday, January 15, 2019 7:07 PM > To: Liu, Aaron > Cc: amd-gfx@lists.freedesktop.org > Subject: Re: [[PATCH v2]drm/amdgpu/psp: ignore psp reponse status] > drm/amdgpu/psp: ignore psp reponse status > > Dear Aaron, > > > On 01/15/19 07:30, Liu, Aaron wrote: > > > The psp code only support ucode loading at the beginning, but forgot > > to remove the checking when more and more PSP command get into PSP. > > I didn’t know that, and missed that your patch is not only about > microcode loading. > > > So some old PSP FW maybe have problem but PSP driver didn’t find it > > out. If reverting the patch, we also can’t find out wrong PSP FW and > > have big problem when support new PSP command. > > Understood. > > > The temporary solution is: do not return error if response is invalid > > but add warning message to notify, it will not block old FW and get > > attention if new PSP FW have some issue. > There is still a small typo in *response* in the summary. > > > Kind regards, > > Paul ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [[PATCH v2]drm/amdgpu/psp: ignore psp reponse status] drm/amdgpu/psp: ignore psp reponse status
Hi Paul,
The psp code only support ucode loading at the beginning, but forgot to remove
the checking when more and more PSP command get into PSP.
So some old PSP FW maybe have problem but PSP driver didn’t find it out.
If reverting the patch, we also can’t find out wrong PSP FW and have big
problem when support new PSP command.
The temporary solution is: do not return error if response is invalid but add
warning message to notify, it will not block old FW and get attention if new
PSP FW have some issue.
BR,
Aaron Liu
> -Original Message-
> From: Paul Menzel
> Sent: Monday, January 14, 2019 9:24 PM
> To: Liu, Aaron
> Cc: amd-gfx@lists.freedesktop.org
> Subject: Re: [[PATCH v2]drm/amdgpu/psp: ignore psp reponse status]
> drm/amdgpu/psp: ignore psp reponse status
>
> Dear Aaron,
>
>
> Am 14.01.19 um 09:47 schrieb Aaron Liu:
> > In some cases, psp response status is not 0 even there is no problem
> > while the command is submitted. Some version of PSP FW doesn't write 0
> > to that field.
> > So here we would like to only print a warning instead of an error
> > during psp initialization to avoid breaking hw_init and it doesn't
> > return -EINVAL.
> >
> > Change-Id: I680679983f972b6969f4949f1faafaf17fe996a6
> > Signed-off-by: Aaron Liu
> > Reviewed-by: Huang Rui
> > Reviewed-by: Xiangliang Yu
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 13 +
> > 1 file changed, 9 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> > index 53c2d60..f26d8fa 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> > @@ -140,14 +140,19 @@ psp_cmd_submit_buf(struct psp_context *psp,
> > while (*((unsigned int *)psp->fence_buf) != index)
> > msleep(1);
> >
> > - /* the status field must be 0 after psp command completion */
> > + /* In some cases, psp response status is not 0 even there is no
> > +* problem while the command is submitted. Some version of PSP
> FW
> > +* doesn't write 0 to that field.
> > +* So here we would like to only print a warning instead of an error
> > +* during psp initialization to avoid breaking hw_init and it doesn't
> > +* return -EINVAL.
> > +*/
> > if (psp->cmd_buf_mem->resp.status) {
> > if (ucode)
> > - DRM_ERROR("failed to load ucode id (%d) ",
> > + DRM_WARN("failed to load ucode id (%d) ",
> > ucode->ucode_id);
> > - DRM_ERROR("psp command failed and response status is
> (%d)\n",
> > + DRM_WARN("psp command failed and response status is
> (%d)\n",
> > psp->cmd_buf_mem->resp.status);
> > - return -EINVAL;
> > }
> >
> > /* get xGMI session id from response buffer */
>
> Please describe, why this error can be ignored, and the rest of the function
> be executed. Won’t that introduce other problems?
>
> How can real error situations be determined now?
>
> Also, please extend the commit messages, that this only affects microcode
> update loading (if I understand this correctly).
>
>
> Kind regards,
>
> Paul
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