Re: [RFC PATCH 10/12] drm/amd/display: Use ARCH_HAS_KERNEL_FPU_SUPPORT

2023-12-13 Thread Timothy Pearson 



- Original Message -
> From: "Samuel Holland" 
> To: "Michael Ellerman" 
> Cc: "linux-kernel" , "amd-gfx" 
> , "linux-arch"
> , "linux-arm-kernel" 
> , loonga...@lists.linux.dev,
> "linuxppc-dev" , "x86" , 
> linux-ri...@lists.infradead.org, "Christoph
> Hellwig" , "Timothy Pearson" 
> 
> Sent: Wednesday, December 13, 2023 7:03:20 PM
> Subject: Re: [RFC PATCH 10/12] drm/amd/display: Use 
> ARCH_HAS_KERNEL_FPU_SUPPORT

> On 2023-12-11 6:23 AM, Michael Ellerman wrote:
>> Hi Samuel,
>> 
>> Thanks for trying to clean all this up.
>> 
>> One problem below.
>> 
>> Samuel Holland  writes:
>>> Now that all previously-supported architectures select
>>> ARCH_HAS_KERNEL_FPU_SUPPORT, this code can depend on that symbol instead
>>> of the existing list of architectures. It can also take advantage of the
>>> common kernel-mode FPU API and method of adjusting CFLAGS.
>>>
>>> Signed-off-by: Samuel Holland 
>> ...
>>> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c
>>> b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c
>>> index 4ae4720535a5..b64f917174ca 100644
>>> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c
>>> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c
>>> @@ -87,20 +78,9 @@ void dc_fpu_begin(const char *function_name, const int 
>>> line)
>>> WARN_ON_ONCE(!in_task());
>>> preempt_disable();
>>> depth = __this_cpu_inc_return(fpu_recursion_depth);
>>> -
>>> if (depth == 1) {
>>> -#if defined(CONFIG_X86) || defined(CONFIG_LOONGARCH)
>>> +   BUG_ON(!kernel_fpu_available());
>>> kernel_fpu_begin();
>>> -#elif defined(CONFIG_PPC64)
>>> -   if (cpu_has_feature(CPU_FTR_VSX_COMP))
>>> -   enable_kernel_vsx();
>>> -   else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP))
>>> -   enable_kernel_altivec();
>>  
>> Note altivec.
>> 
>>> -   else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE))
>>> -   enable_kernel_fp();
>>> -#elif defined(CONFIG_ARM64)
>>> -   kernel_neon_begin();
>>> -#endif
>>> }
>>>  
>>> TRACE_DCN_FPU(true, function_name, line, depth);
>>> diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile
>>> b/drivers/gpu/drm/amd/display/dc/dml/Makefile
>>> index ea7d60f9a9b4..5aad0f572ba3 100644
>>> --- a/drivers/gpu/drm/amd/display/dc/dml/Makefile
>>> +++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile
>>> @@ -25,40 +25,8 @@
>>>  # It provides the general basic services required by other DAL
>>>  # subcomponents.
>>>  
>>> -ifdef CONFIG_X86
>>> -dml_ccflags-$(CONFIG_CC_IS_GCC) := -mhard-float
>>> -dml_ccflags := $(dml_ccflags-y) -msse
>>> -endif
>>> -
>>> -ifdef CONFIG_PPC64
>>> -dml_ccflags := -mhard-float -maltivec
>>> -endif
>> 
>> And altivec is enabled in the flags there.
>> 
>> That doesn't match your implementation for powerpc in patch 7, which
>> only deals with float.
>> 
>> I suspect the AMD driver actually doesn't need altivec enabled, but I
>> don't know that for sure. It compiles without it, but I don't have a GPU
>> to actually test. I've added Timothy on Cc who added the support for
>> powerpc to the driver originally, hopefully he has a test system.

If you would like me to test I'm happy to do so, but I am travelling until 
Friday so would need to wait until then.

Thanks!

Re: [PATCH] drm/amdgpu: Re-enable DCN for 64-bit powerpc

2022-07-25 Thread Timothy Pearson 



- Original Message -
> From: "Linus Torvalds" 
> To: "Michael Ellerman" 
> Cc: "linuxppc-dev" , "Alex Deucher" 
> , "amd-gfx"
> , li...@roeck-us.net, "linux-kernel" 
> , "Dan Horák"
> , "Timothy Pearson" 
> Sent: Monday, July 25, 2022 2:19:57 PM
> Subject: Re: [PATCH] drm/amdgpu: Re-enable DCN for 64-bit powerpc

> On Mon, Jul 25, 2022 at 5:39 AM Michael Ellerman  wrote:
>>
>> Further digging shows that the build failures only occur with compilers
>> that default to 64-bit long double.
> 
> Where the heck do we have 'long double' things anywhere in the kernel?
> 
> I tried to grep for it, and failed miserably. I found some constants
> that would qualify, but they were in the v4l colorspaces-details.rst
> doc file.
> 
> Strange.

We don't, at least not that I can see.  The affected code uses standard doubles.

What I'm wondering is if the compiler is getting confused between standard and 
long doubles when they are both the same bit length...

[PATCH 2/3] amdgpu: Enable initial DCN support on POWER

2019-12-07 Thread Timothy Pearson 
DCN requires floating point support to operate.  Add the appropriate
x86/ppc64 guards and FPU / AltiVec / VSX context switches to DCN.

Note that the current DC20 code doesn't contain all required FPU
wrappers on x86 or POWER, so this patch is insufficient to fully
enable DC20 on POWER.

Signed-off-by: Timothy Pearson 
---
 drivers/gpu/drm/amd/display/Kconfig   |  8 ++---
 drivers/gpu/drm/amd/display/dc/calcs/Makefile |  9 ++
 .../gpu/drm/amd/display/dc/calcs/dcn_calcs.c  |  1 +
 drivers/gpu/drm/amd/display/dc/dcn20/Makefile |  8 +
 .../drm/amd/display/dc/dcn20/dcn20_resource.c |  1 +
 drivers/gpu/drm/amd/display/dc/dcn21/Makefile |  8 +
 .../drm/amd/display/dc/dcn21/dcn21_resource.c |  1 +
 drivers/gpu/drm/amd/display/dc/dml/Makefile   |  9 ++
 drivers/gpu/drm/amd/display/dc/dsc/Makefile   |  8 +
 drivers/gpu/drm/amd/display/dc/os_types.h | 29 +++
 10 files changed, 78 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/Kconfig 
b/drivers/gpu/drm/amd/display/Kconfig
index 313183b80032..c73a63f3e245 100644
--- a/drivers/gpu/drm/amd/display/Kconfig
+++ b/drivers/gpu/drm/amd/display/Kconfig
@@ -6,7 +6,7 @@ config DRM_AMD_DC
bool "AMD DC - Enable new display engine"
default y
select SND_HDA_COMPONENT if SND_HDA_CORE
-   select DRM_AMD_DC_DCN1_0 if X86 && !(KCOV_INSTRUMENT_ALL && 
KCOV_ENABLE_COMPARISONS)
+   select DRM_AMD_DC_DCN1_0 if (X86 || PPC64) && !(KCOV_INSTRUMENT_ALL && 
KCOV_ENABLE_COMPARISONS)
help
  Choose this option if you want to use the new display engine
  support for AMDGPU. This adds required support for Vega and
@@ -20,7 +20,7 @@ config DRM_AMD_DC_DCN1_0
 config DRM_AMD_DC_DCN2_0
bool "DCN 2.0 family"
default y
-   depends on DRM_AMD_DC && X86
+   depends on DRM_AMD_DC && (X86 || PPC64)
depends on DRM_AMD_DC_DCN1_0
help
  Choose this option if you want to have
@@ -28,7 +28,7 @@ config DRM_AMD_DC_DCN2_0
 
 config DRM_AMD_DC_DCN2_1
bool "DCN 2.1 family"
-   depends on DRM_AMD_DC && X86
+   depends on DRM_AMD_DC && (X86 || PPC64)
depends on DRM_AMD_DC_DCN2_0
help
  Choose this option if you want to have
@@ -37,7 +37,7 @@ config DRM_AMD_DC_DCN2_1
 config DRM_AMD_DC_DSC_SUPPORT
bool "DSC support"
default y
-   depends on DRM_AMD_DC && X86
+   depends on DRM_AMD_DC && (X86 || PPC64)
depends on DRM_AMD_DC_DCN1_0
depends on DRM_AMD_DC_DCN2_0
help
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/Makefile 
b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
index 26c6d735cdc7..429ac95b5dc6 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
@@ -1,5 +1,6 @@
 #
 # Copyright 2017 Advanced Micro Devices, Inc.
+# Copyright 2019 Raptor Engineering, LLC
 #
 # Permission is hereby granted, free of charge, to any person obtaining a
 # copy of this software and associated documentation files (the "Software"),
@@ -24,7 +25,13 @@
 # It calculates Bandwidth and Watermarks values for HW programming
 #
 
+ifdef CONFIG_X86_64
 calcs_ccflags := -mhard-float -msse
+endif
+
+ifdef CONFIG_PPC64
+calcs_ccflags := -mhard-float -maltivec
+endif
 
 ifdef CONFIG_CC_IS_GCC
 ifeq ($(call cc-ifversion, -lt, 0701, y), y)
@@ -32,6 +39,7 @@ IS_OLD_GCC = 1
 endif
 endif
 
+ifdef CONFIG_X86_64
 ifdef IS_OLD_GCC
 # Stack alignment mismatch, proceed with caution.
 # GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
@@ -40,6 +48,7 @@ calcs_ccflags += -mpreferred-stack-boundary=4
 else
 calcs_ccflags += -msse2
 endif
+endif
 
 CFLAGS_$(AMDDALPATH)/dc/calcs/dcn_calcs.o := $(calcs_ccflags)
 CFLAGS_$(AMDDALPATH)/dc/calcs/dcn_calc_auto.o := $(calcs_ccflags)
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index cd5471263248..e34ff2f4a3de 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -1,5 +1,6 @@
 /*
  * Copyright 2017 Advanced Micro Devices, Inc.
+ * Copyright 2019 Raptor Engineering, LLC
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile 
b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
index 63f3bddba7da..6a872b7a58bd 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
@@ -10,7 +10,13 @@ ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
 DCN20 += dcn20_dsc.o
 endif
 
+ifdef CONFIG_X86_64
 CFLAGS_$(AMDDALPATH)/dc/dcn20/dcn20_resource.o := -mhard-float -msse
+endif
+
+ifdef CONFIG_PPC64
+CFLAGS_$(AMDDALPATH)/dc

[PATCH 3/3] amdgpu: Wrap FPU dependent functions in dc20

2019-12-07 Thread Timothy Pearson 
dc20 containes several FPU-dependent functions without proper FPU
kernel mode enable/disable wrappers.  Add the required wrappers
for both x86 and POWER.

This enables Navi DC20 support for POWER systems.

Signed-off-by: Timothy Pearson 
---
 .../gpu/drm/amd/display/dc/dcn20/dcn20_resource.c  | 14 --
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 254973751732..95303b77bfd6 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -2917,14 +2917,19 @@ static bool dcn20_validate_bandwidth_internal(struct dc 
*dc, struct dc_state *co
 bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
bool fast_validate)
 {
+   DC_FP_START()
+
bool voltage_supported = false;
bool full_pstate_supported = false;
bool dummy_pstate_supported = false;
double p_state_latency_us = 
context->bw_ctx.dml.soc.dram_clock_change_latency_us;
 
-   if (fast_validate)
-   return dcn20_validate_bandwidth_internal(dc, context, true);
+   if (fast_validate) {
+   voltage_supported = dcn20_validate_bandwidth_internal(dc, 
context, true);
 
+   DC_FP_END()
+   return voltage_supported;
+   }
 
// Best case, we support full UCLK switch latency
voltage_supported = dcn20_validate_bandwidth_internal(dc, context, 
false);
@@ -2953,6 +2958,7 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct 
dc_state *context,
 restore_dml_state:
context->bw_ctx.dml.soc.dram_clock_change_latency_us = 
p_state_latency_us;
 
+   DC_FP_END()
return voltage_supported;
 }
 
@@ -3472,6 +3478,8 @@ static bool construct(
enum dml_project dml_project_version =
get_dml_project_version(ctx->asic_id.hw_internal_rev);
 
+   DC_FP_START()
+
ctx->dc_bios->regs = _regs;
pool->base.funcs = _res_pool_funcs;
 
@@ -3760,10 +3768,12 @@ static bool construct(
 
dc->cap_funcs = cap_funcs;
 
+   DC_FP_END()
return true;
 
 create_fail:
 
+   DC_FP_END()
destruct(pool);
 
return false;
-- 
2.20.1
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[PATCH 1/3] amdgpu: Prepare DCN floating point macros for generic

2019-12-07 Thread Timothy Pearson 
 arch support

Introduce DC_FP_START()/DC_FP_END() macros to help enable floating
point kernel mode support across various architectures.

Signed-off-by: Timothy Pearson 
---
 .../gpu/drm/amd/display/dc/calcs/dcn_calcs.c  | 24 +--
 .../drm/amd/display/dc/dcn20/dcn20_resource.c |  4 ++--
 .../drm/amd/display/dc/dcn21/dcn21_resource.c |  4 ++--
 drivers/gpu/drm/amd/display/dc/os_types.h |  3 +++
 4 files changed, 19 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index 9b2cb57bf2ba..cd5471263248 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -626,7 +626,7 @@ static bool dcn_bw_apply_registry_override(struct dc *dc)
 {
bool updated = false;
 
-   kernel_fpu_begin();
+   DC_FP_START();
if ((int)(dc->dcn_soc->sr_exit_time * 1000) != dc->debug.sr_exit_time_ns
&& dc->debug.sr_exit_time_ns) {
updated = true;
@@ -662,7 +662,7 @@ static bool dcn_bw_apply_registry_override(struct dc *dc)
dc->dcn_soc->dram_clock_change_latency =
dc->debug.dram_clock_change_latency_ns / 1000.0;
}
-   kernel_fpu_end();
+   DC_FP_END();
 
return updated;
 }
@@ -742,7 +742,7 @@ bool dcn_validate_bandwidth(
dcn_bw_sync_calcs_and_dml(dc);
 
memset(v, 0, sizeof(*v));
-   kernel_fpu_begin();
+   DC_FP_START();
 
v->sr_exit_time = dc->dcn_soc->sr_exit_time;
v->sr_enter_plus_exit_time = dc->dcn_soc->sr_enter_plus_exit_time;
@@ -1275,7 +1275,7 @@ bool dcn_validate_bandwidth(
bw_limit = dc->dcn_soc->percent_disp_bw_limit * 
v->fabric_and_dram_bandwidth_vmax0p9;
bw_limit_pass = (v->total_data_read_bandwidth / 1000.0) < bw_limit;
 
-   kernel_fpu_end();
+   DC_FP_END();
 
PERFORMANCE_TRACE_END();
BW_VAL_TRACE_FINISH();
@@ -1443,7 +1443,7 @@ void dcn_bw_update_from_pplib(struct dc *dc)
res = dm_pp_get_clock_levels_by_type_with_voltage(
ctx, DM_PP_CLOCK_TYPE_FCLK, );
 
-   kernel_fpu_begin();
+   DC_FP_START();
 
if (res)
res = verify_clock_values();
@@ -1463,12 +1463,12 @@ void dcn_bw_update_from_pplib(struct dc *dc)
} else
BREAK_TO_DEBUGGER();
 
-   kernel_fpu_end();
+   DC_FP_END();
 
res = dm_pp_get_clock_levels_by_type_with_voltage(
ctx, DM_PP_CLOCK_TYPE_DCFCLK, );
 
-   kernel_fpu_begin();
+   DC_FP_START();
 
if (res)
res = verify_clock_values();
@@ -1481,7 +1481,7 @@ void dcn_bw_update_from_pplib(struct dc *dc)
} else
BREAK_TO_DEBUGGER();
 
-   kernel_fpu_end();
+   DC_FP_END();
 }
 
 void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc)
@@ -1496,11 +1496,11 @@ void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc)
if (!pp || !pp->set_wm_ranges)
return;
 
-   kernel_fpu_begin();
+   DC_FP_START();
min_fclk_khz = dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 * 
100 / 32;
min_dcfclk_khz = dc->dcn_soc->dcfclkv_min0p65 * 1000;
socclk_khz = dc->dcn_soc->socclk * 1000;
-   kernel_fpu_end();
+   DC_FP_END();
 
/* Now notify PPLib/SMU about which Watermarks sets they should select
 * depending on DPM state they are in. And update BW MGR GFX Engine and
@@ -1551,7 +1551,7 @@ void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc)
 
 void dcn_bw_sync_calcs_and_dml(struct dc *dc)
 {
-   kernel_fpu_begin();
+   DC_FP_START();
DC_LOG_BANDWIDTH_CALCS("sr_exit_time: %f ns\n"
"sr_enter_plus_exit_time: %f ns\n"
"urgent_latency: %f ns\n"
@@ -1740,5 +1740,5 @@ void dcn_bw_sync_calcs_and_dml(struct dc *dc)
dc->dml.ip.bug_forcing_LC_req_same_size_fixed =

dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed == 
dcn_bw_yes;
dc->dml.ip.dcfclk_cstate_latency = dc->dcn_ip->dcfclk_cstate_latency;
-   kernel_fpu_end();
+   DC_FP_END();
 }
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 09793336d84f..74ad6f09c1d4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -3243,7 +3243,7 @@ void dcn20_update_bounding_box(struct dc *dc, struct 
_vcs_dpi_soc_bounding_box_s
 
 void dcn20_patch_bounding_box(struct dc *dc, struct 
_vcs_dpi_soc_bounding_box_st *bb)
 {
-   kernel_fpu_begin();
+   DC_FP_START();
if ((int)(bb->sr_exit_time_us * 1000) != 
dc->bb_overrides.sr_exit_time

Re: amdgpu: Enable full DCN support on POWER

2019-12-06 Thread Timothy Pearson 


- Original Message -
> From: "Michel Dänzer" 
> To: "Timothy Pearson" , "Harry Wentland" 
> 
> Cc: "Zhan Liu" , "amd-gfx" 
> Sent: Friday, December 6, 2019 10:12:42 AM
> Subject: Re: amdgpu: Enable full DCN support on POWER

> On 2019-12-06 12:34 a.m., Timothy Pearson wrote:
>>> From: "Harry Wentland"  On 2019-12-05 6:02 p.m.,
>>> Liu, Zhan wrote:
>>>>> From: amd-gfx  On Behalf
>>>>> Of Timothy Pearson
>>>>> 
>>>>> diff --git a/drivers/gpu/drm/amd/display/dc/Makefile
>>>>> b/drivers/gpu/drm/amd/display/dc/Makefile index
>>>>> a160512a2f04..3e026a969386 100644 ---
>>>>> a/drivers/gpu/drm/amd/display/dc/Makefile +++
>>>>> b/drivers/gpu/drm/amd/display/dc/Makefile @@ -1,5 +1,6 @@ # #
>>>>> Copyright 2017 Advanced Micro Devices, Inc. +# Copyright 2019
>>>>> Raptor Engineering, LLC
>>>> 
>>>> NAK.
>>>> 
>>>> IANAL, but I don't think you can add your company's name by
>>>> modifying part of the code. The copyright notice shows the
>>>> authors of the original work.
>>>> 
>>>> When modifying the code, you are required to agree with that
>>>> copyright notice. That's the purpose of that copyright notice
>>>> piece.
> 
> Where did you get that from? Adding a copyright line like this to files
> containing code to which one holds the copyright is standard practice.
> 
> 
>>> I always thought these copyright notices are nearly meaningless.
>>> 
>>> That said, this patch doesn't have any change in this file. I
>>> don't think it warrants an additional copyright notice.
>>> 
>>> Harry
>> 
>> Agreed -- looks like that snuck in with the other changes.  I can
>> back this one out, however in general regardless of the notice having
>> any actual legal meaning (the GIT commit history has the actual legal
>> teeth from what I understand as it establishes shared ownership), our
>> general policy per recommendations is to add the copyright line.  It
>> helps anyone looking at the file know at a glance that there is more
>> than one corporate author, and therefore e.g. the only terms it can
>> be used on without a complex multi-party license renegotiation is (in
>> this case) the GPL v2.
> 
> Did you read the licence under the copyright line you added? :)

Nope, I didn't, at least not right before sending that reply -- I didn't have a 
copy of the file up on that device , and was wildly guessing based on the 
overall kernel distribution license.

> Or are you saying that your patch is intended to be available under the
> GPL only? I'm afraid that would be a problem.

No, there's no problem here with the existing license.  Updated version of the 
patch with a few technical issues fixed should be coming later today / tomorrow 
(depending on how quickly I can get an ACK/NACK on functionality from the 
person that has access to the Navi card).

> 
> --
> Earthling Michel Dänzer   |   https://redhat.com
> Libre software enthusiast | Mesa and X developer
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Re: amdgpu: Enable full DCN support on POWER

2019-12-05 Thread Timothy Pearson 


- Original Message -
> From: "Harry Wentland" 
> To: "Liu, Zhan" , "Timothy Pearson" 
> , "amd-gfx"
> 
> Sent: Thursday, December 5, 2019 5:19:22 PM
> Subject: Re: amdgpu: Enable full DCN support on POWER

> On 2019-12-05 6:02 p.m., Liu, Zhan wrote:
>> 
>> 
>>> -Original Message-
>>> From: amd-gfx  On Behalf Of
>>> Timothy Pearson
>>> Sent: 2019/December/05, Thursday 4:58 PM
>>> To: amd-gfx 
>>> Subject: [PATCH] [RFC v2] amdgpu: Enable full DCN support on POWER
>>>
>>> DCN requires floating point support to operate.  Add the appropriate
>>> x86/ppc64 guards and FPU / AltiVec / VSX context switches to DCN.
>>>
>>> Signed-off-by: Timothy Pearson 
>>> ---
>>>  drivers/gpu/drm/amd/display/Kconfig   |   8 +-
>>>  drivers/gpu/drm/amd/display/dc/Makefile   |   1 +
>>>  drivers/gpu/drm/amd/display/dc/calcs/Makefile |   8 +
>>>  .../gpu/drm/amd/display/dc/calcs/dcn_calcs.c  | 157 ++
>>>  drivers/gpu/drm/amd/display/dc/dcn20/Makefile |   8 +
>>>  .../drm/amd/display/dc/dcn20/dcn20_resource.c |  27 +++
>>>  drivers/gpu/drm/amd/display/dc/dcn21/Makefile |   8 +
>>>  .../drm/amd/display/dc/dcn21/dcn21_resource.c |  27 +++
>>>  drivers/gpu/drm/amd/display/dc/dml/Makefile   |   9 +
>>>  drivers/gpu/drm/amd/display/dc/dsc/Makefile   |   8 +
>>>  drivers/gpu/drm/amd/display/dc/os_types.h |   6 +
>>>  11 files changed, 263 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/display/Kconfig
>>> b/drivers/gpu/drm/amd/display/Kconfig
>>> index 313183b80032..c73a63f3e245 100644
>>> --- a/drivers/gpu/drm/amd/display/Kconfig
>>> +++ b/drivers/gpu/drm/amd/display/Kconfig
>>> @@ -6,7 +6,7 @@ config DRM_AMD_DC
>>> bool "AMD DC - Enable new display engine"
>>> default y
>>> select SND_HDA_COMPONENT if SND_HDA_CORE
>>> -   select DRM_AMD_DC_DCN1_0 if X86 && !(KCOV_INSTRUMENT_ALL
>>> && KCOV_ENABLE_COMPARISONS)
>>> +   select DRM_AMD_DC_DCN1_0 if (X86 || PPC64)
>>> && !(KCOV_INSTRUMENT_ALL &&
>>> +KCOV_ENABLE_COMPARISONS)
>>> help
>>>   Choose this option if you want to use the new display engine
>>>   support for AMDGPU. This adds required support for Vega and @@
>>> -20,7 +20,7 @@ config DRM_AMD_DC_DCN1_0  config
>>> DRM_AMD_DC_DCN2_0
>>> bool "DCN 2.0 family"
>>> default y
>>> -   depends on DRM_AMD_DC && X86
>>> +   depends on DRM_AMD_DC && (X86 || PPC64)
>>> depends on DRM_AMD_DC_DCN1_0
>>> help
>>>   Choose this option if you want to have @@ -28,7 +28,7 @@ config
>>> DRM_AMD_DC_DCN2_0
>>>
>>>  config DRM_AMD_DC_DCN2_1
>>> bool "DCN 2.1 family"
>>> -   depends on DRM_AMD_DC && X86
>>> +   depends on DRM_AMD_DC && (X86 || PPC64)
>>> depends on DRM_AMD_DC_DCN2_0
>>> help
>>>   Choose this option if you want to have @@ -37,7 +37,7 @@ config
>>> DRM_AMD_DC_DCN2_1  config DRM_AMD_DC_DSC_SUPPORT
>>> bool "DSC support"
>>> default y
>>> -   depends on DRM_AMD_DC && X86
>>> +   depends on DRM_AMD_DC && (X86 || PPC64)
>>> depends on DRM_AMD_DC_DCN1_0
>>> depends on DRM_AMD_DC_DCN2_0
>>> help
>>> diff --git a/drivers/gpu/drm/amd/display/dc/Makefile
>>> b/drivers/gpu/drm/amd/display/dc/Makefile
>>> index a160512a2f04..3e026a969386 100644
>>> --- a/drivers/gpu/drm/amd/display/dc/Makefile
>>> +++ b/drivers/gpu/drm/amd/display/dc/Makefile
>>> @@ -1,5 +1,6 @@
>>>  #
>>>  # Copyright 2017 Advanced Micro Devices, Inc.
>>> +# Copyright 2019 Raptor Engineering, LLC
>> 
>> NAK.
>> 
>> IANAL, but I don't think you can add your company's name by modifying part of
>> the code. The copyright notice shows the authors of the original work.
>> 
>> When modifying the code, you are required to agree with that copyright 
>> notice.
>> That's the purpose of that copyright notice piece.
>> 
> 
> I always thought these copyright notices are nearly meaningless.
> 
> That said, this patch doesn't have any change in this file. I don't
> think it warrants an additional copyright notice.
> 
> Harry

Agreed -- looks like that snuck in with the other changes.  I can back th

[PATCH] [RFC v2] amdgpu: Enable full DCN support on POWER

2019-12-05 Thread Timothy Pearson 
DCN requires floating point support to operate.  Add the appropriate
x86/ppc64 guards and FPU / AltiVec / VSX context switches to DCN.

Signed-off-by: Timothy Pearson 
---
 drivers/gpu/drm/amd/display/Kconfig   |   8 +-
 drivers/gpu/drm/amd/display/dc/Makefile   |   1 +
 drivers/gpu/drm/amd/display/dc/calcs/Makefile |   8 +
 .../gpu/drm/amd/display/dc/calcs/dcn_calcs.c  | 157 ++
 drivers/gpu/drm/amd/display/dc/dcn20/Makefile |   8 +
 .../drm/amd/display/dc/dcn20/dcn20_resource.c |  27 +++
 drivers/gpu/drm/amd/display/dc/dcn21/Makefile |   8 +
 .../drm/amd/display/dc/dcn21/dcn21_resource.c |  27 +++
 drivers/gpu/drm/amd/display/dc/dml/Makefile   |   9 +
 drivers/gpu/drm/amd/display/dc/dsc/Makefile   |   8 +
 drivers/gpu/drm/amd/display/dc/os_types.h |   6 +
 11 files changed, 263 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/Kconfig 
b/drivers/gpu/drm/amd/display/Kconfig
index 313183b80032..c73a63f3e245 100644
--- a/drivers/gpu/drm/amd/display/Kconfig
+++ b/drivers/gpu/drm/amd/display/Kconfig
@@ -6,7 +6,7 @@ config DRM_AMD_DC
bool "AMD DC - Enable new display engine"
default y
select SND_HDA_COMPONENT if SND_HDA_CORE
-   select DRM_AMD_DC_DCN1_0 if X86 && !(KCOV_INSTRUMENT_ALL && 
KCOV_ENABLE_COMPARISONS)
+   select DRM_AMD_DC_DCN1_0 if (X86 || PPC64) && !(KCOV_INSTRUMENT_ALL && 
KCOV_ENABLE_COMPARISONS)
help
  Choose this option if you want to use the new display engine
  support for AMDGPU. This adds required support for Vega and
@@ -20,7 +20,7 @@ config DRM_AMD_DC_DCN1_0
 config DRM_AMD_DC_DCN2_0
bool "DCN 2.0 family"
default y
-   depends on DRM_AMD_DC && X86
+   depends on DRM_AMD_DC && (X86 || PPC64)
depends on DRM_AMD_DC_DCN1_0
help
  Choose this option if you want to have
@@ -28,7 +28,7 @@ config DRM_AMD_DC_DCN2_0
 
 config DRM_AMD_DC_DCN2_1
bool "DCN 2.1 family"
-   depends on DRM_AMD_DC && X86
+   depends on DRM_AMD_DC && (X86 || PPC64)
depends on DRM_AMD_DC_DCN2_0
help
  Choose this option if you want to have
@@ -37,7 +37,7 @@ config DRM_AMD_DC_DCN2_1
 config DRM_AMD_DC_DSC_SUPPORT
bool "DSC support"
default y
-   depends on DRM_AMD_DC && X86
+   depends on DRM_AMD_DC && (X86 || PPC64)
depends on DRM_AMD_DC_DCN1_0
depends on DRM_AMD_DC_DCN2_0
help
diff --git a/drivers/gpu/drm/amd/display/dc/Makefile 
b/drivers/gpu/drm/amd/display/dc/Makefile
index a160512a2f04..3e026a969386 100644
--- a/drivers/gpu/drm/amd/display/dc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/Makefile
@@ -1,5 +1,6 @@
 #
 # Copyright 2017 Advanced Micro Devices, Inc.
+# Copyright 2019 Raptor Engineering, LLC
 #
 # Permission is hereby granted, free of charge, to any person obtaining a
 # copy of this software and associated documentation files (the "Software"),
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/Makefile 
b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
index 26c6d735cdc7..20c88aff930a 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
@@ -24,7 +24,13 @@
 # It calculates Bandwidth and Watermarks values for HW programming
 #
 
+ifdef CONFIG_X86_64
 calcs_ccflags := -mhard-float -msse
+endif
+
+ifdef CONFIG_PPC64
+calcs_ccflags := -mhard-float -maltivec
+endif
 
 ifdef CONFIG_CC_IS_GCC
 ifeq ($(call cc-ifversion, -lt, 0701, y), y)
@@ -32,6 +38,7 @@ IS_OLD_GCC = 1
 endif
 endif
 
+ifdef CONFIG_X86_64
 ifdef IS_OLD_GCC
 # Stack alignment mismatch, proceed with caution.
 # GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
@@ -40,6 +47,7 @@ calcs_ccflags += -mpreferred-stack-boundary=4
 else
 calcs_ccflags += -msse2
 endif
+endif
 
 CFLAGS_$(AMDDALPATH)/dc/calcs/dcn_calcs.o := $(calcs_ccflags)
 CFLAGS_$(AMDDALPATH)/dc/calcs/dcn_calc_auto.o := $(calcs_ccflags)
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index 9b2cb57bf2ba..236e852ea60b 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -1,5 +1,6 @@
 /*
  * Copyright 2017 Advanced Micro Devices, Inc.
+ * Copyright 2019 Raptor Engineering, LLC
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -626,7 +627,20 @@ static bool dcn_bw_apply_registry_override(struct dc *dc)
 {
bool updated = false;
 
+#if defined(CONFIG_X86_64)
kernel_fpu_begin();
+#elif defined(CONFIG_PPC64)
+   if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
+   preempt_disable();
+   enable_kernel_vsx();
+   } else if (cpu_has_f

Re: [PATCH] [RFC] amdgpu: Enable full DCN support on POWER

2019-12-05 Thread Timothy Pearson 
Sent this a bit too early, still running through checks.  Watch for a V2 
shortly.

- Original Message -
> From: "Timothy Pearson" 
> To: "amd-gfx" 
> Sent: Thursday, December 5, 2019 3:39:24 PM
> Subject: [PATCH] [RFC] amdgpu: Enable full DCN support on POWER

> DCN requires floating point support to operate.  Add the appropriate
> x86/ppc64 guards and FPU / AltiVec / VSX context switches to DCN.
> 
> Signed-off-by: Timothy Pearson 
> ---
> drivers/gpu/drm/amd/display/Kconfig   |   8 +-
> drivers/gpu/drm/amd/display/dc/Makefile   |   1 +
> drivers/gpu/drm/amd/display/dc/calcs/Makefile |   4 +
> .../gpu/drm/amd/display/dc/calcs/dcn_calcs.c  | 157 ++
> drivers/gpu/drm/amd/display/dc/dcn20/Makefile |   4 +
> .../drm/amd/display/dc/dcn20/dcn20_resource.c |  27 +++
> drivers/gpu/drm/amd/display/dc/dcn21/Makefile |   4 +
> .../drm/amd/display/dc/dcn21/dcn21_resource.c |  27 +++
> drivers/gpu/drm/amd/display/dc/dml/Makefile   |   5 +
> drivers/gpu/drm/amd/display/dc/dsc/Makefile   |   4 +
> drivers/gpu/drm/amd/display/dc/os_types.h |   6 +
> 11 files changed, 243 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/Kconfig
> b/drivers/gpu/drm/amd/display/Kconfig
> index 313183b80032..c73a63f3e245 100644
> --- a/drivers/gpu/drm/amd/display/Kconfig
> +++ b/drivers/gpu/drm/amd/display/Kconfig
> @@ -6,7 +6,7 @@ config DRM_AMD_DC
>   bool "AMD DC - Enable new display engine"
>   default y
>   select SND_HDA_COMPONENT if SND_HDA_CORE
> - select DRM_AMD_DC_DCN1_0 if X86 && !(KCOV_INSTRUMENT_ALL &&
> KCOV_ENABLE_COMPARISONS)
> + select DRM_AMD_DC_DCN1_0 if (X86 || PPC64) && !(KCOV_INSTRUMENT_ALL &&
> KCOV_ENABLE_COMPARISONS)
>   help
> Choose this option if you want to use the new display engine
> support for AMDGPU. This adds required support for Vega and
> @@ -20,7 +20,7 @@ config DRM_AMD_DC_DCN1_0
> config DRM_AMD_DC_DCN2_0
>   bool "DCN 2.0 family"
>   default y
> - depends on DRM_AMD_DC && X86
> + depends on DRM_AMD_DC && (X86 || PPC64)
>   depends on DRM_AMD_DC_DCN1_0
>   help
> Choose this option if you want to have
> @@ -28,7 +28,7 @@ config DRM_AMD_DC_DCN2_0
> 
> config DRM_AMD_DC_DCN2_1
>   bool "DCN 2.1 family"
> - depends on DRM_AMD_DC && X86
> + depends on DRM_AMD_DC && (X86 || PPC64)
>   depends on DRM_AMD_DC_DCN2_0
>   help
> Choose this option if you want to have
> @@ -37,7 +37,7 @@ config DRM_AMD_DC_DCN2_1
> config DRM_AMD_DC_DSC_SUPPORT
>   bool "DSC support"
>   default y
> - depends on DRM_AMD_DC && X86
> + depends on DRM_AMD_DC && (X86 || PPC64)
>   depends on DRM_AMD_DC_DCN1_0
>   depends on DRM_AMD_DC_DCN2_0
>   help
> diff --git a/drivers/gpu/drm/amd/display/dc/Makefile
> b/drivers/gpu/drm/amd/display/dc/Makefile
> index a160512a2f04..3e026a969386 100644
> --- a/drivers/gpu/drm/amd/display/dc/Makefile
> +++ b/drivers/gpu/drm/amd/display/dc/Makefile
> @@ -1,5 +1,6 @@
> #
> # Copyright 2017 Advanced Micro Devices, Inc.
> +# Copyright 2019 Raptor Engineering, LLC
> #
> # Permission is hereby granted, free of charge, to any person obtaining a
> # copy of this software and associated documentation files (the "Software"),
> diff --git a/drivers/gpu/drm/amd/display/dc/calcs/Makefile
> b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
> index 26c6d735cdc7..0d46c37d6c95 100644
> --- a/drivers/gpu/drm/amd/display/dc/calcs/Makefile
> +++ b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
> @@ -24,7 +24,9 @@
> # It calculates Bandwidth and Watermarks values for HW programming
> #
> 
> +ifdef CONFIG_X86_64
> calcs_ccflags := -mhard-float -msse
> +endif
> 
> ifdef CONFIG_CC_IS_GCC
> ifeq ($(call cc-ifversion, -lt, 0701, y), y)
> @@ -32,6 +34,7 @@ IS_OLD_GCC = 1
> endif
> endif
> 
> +ifdef CONFIG_X86_64
> ifdef IS_OLD_GCC
> # Stack alignment mismatch, proceed with caution.
> # GCC < 7.1 cannot compile code using `double` and 
> -mpreferred-stack-boundary=3
> @@ -40,6 +43,7 @@ calcs_ccflags += -mpreferred-stack-boundary=4
> else
> calcs_ccflags += -msse2
> endif
> +endif
> 
> CFLAGS_$(AMDDALPATH)/dc/calcs/dcn_calcs.o := $(calcs_ccflags)
> CFLAGS_$(AMDDALPATH)/dc/calcs/dcn_calc_auto.o := $(calcs_ccflags)
> diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
> b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
> index 9b2cb57bf2ba..5c913b585ac4 100644
> --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
> +++ b/drivers/gpu/drm/a

[PATCH] [RFC] amdgpu: Enable full DCN support on POWER

2019-12-05 Thread Timothy Pearson 
DCN requires floating point support to operate.  Add the appropriate
x86/ppc64 guards and FPU / AltiVec / VSX context switches to DCN.

Signed-off-by: Timothy Pearson 
---
 drivers/gpu/drm/amd/display/Kconfig   |   8 +-
 drivers/gpu/drm/amd/display/dc/Makefile   |   1 +
 drivers/gpu/drm/amd/display/dc/calcs/Makefile |   4 +
 .../gpu/drm/amd/display/dc/calcs/dcn_calcs.c  | 157 ++
 drivers/gpu/drm/amd/display/dc/dcn20/Makefile |   4 +
 .../drm/amd/display/dc/dcn20/dcn20_resource.c |  27 +++
 drivers/gpu/drm/amd/display/dc/dcn21/Makefile |   4 +
 .../drm/amd/display/dc/dcn21/dcn21_resource.c |  27 +++
 drivers/gpu/drm/amd/display/dc/dml/Makefile   |   5 +
 drivers/gpu/drm/amd/display/dc/dsc/Makefile   |   4 +
 drivers/gpu/drm/amd/display/dc/os_types.h |   6 +
 11 files changed, 243 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/Kconfig 
b/drivers/gpu/drm/amd/display/Kconfig
index 313183b80032..c73a63f3e245 100644
--- a/drivers/gpu/drm/amd/display/Kconfig
+++ b/drivers/gpu/drm/amd/display/Kconfig
@@ -6,7 +6,7 @@ config DRM_AMD_DC
bool "AMD DC - Enable new display engine"
default y
select SND_HDA_COMPONENT if SND_HDA_CORE
-   select DRM_AMD_DC_DCN1_0 if X86 && !(KCOV_INSTRUMENT_ALL && 
KCOV_ENABLE_COMPARISONS)
+   select DRM_AMD_DC_DCN1_0 if (X86 || PPC64) && !(KCOV_INSTRUMENT_ALL && 
KCOV_ENABLE_COMPARISONS)
help
  Choose this option if you want to use the new display engine
  support for AMDGPU. This adds required support for Vega and
@@ -20,7 +20,7 @@ config DRM_AMD_DC_DCN1_0
 config DRM_AMD_DC_DCN2_0
bool "DCN 2.0 family"
default y
-   depends on DRM_AMD_DC && X86
+   depends on DRM_AMD_DC && (X86 || PPC64)
depends on DRM_AMD_DC_DCN1_0
help
  Choose this option if you want to have
@@ -28,7 +28,7 @@ config DRM_AMD_DC_DCN2_0
 
 config DRM_AMD_DC_DCN2_1
bool "DCN 2.1 family"
-   depends on DRM_AMD_DC && X86
+   depends on DRM_AMD_DC && (X86 || PPC64)
depends on DRM_AMD_DC_DCN2_0
help
  Choose this option if you want to have
@@ -37,7 +37,7 @@ config DRM_AMD_DC_DCN2_1
 config DRM_AMD_DC_DSC_SUPPORT
bool "DSC support"
default y
-   depends on DRM_AMD_DC && X86
+   depends on DRM_AMD_DC && (X86 || PPC64)
depends on DRM_AMD_DC_DCN1_0
depends on DRM_AMD_DC_DCN2_0
help
diff --git a/drivers/gpu/drm/amd/display/dc/Makefile 
b/drivers/gpu/drm/amd/display/dc/Makefile
index a160512a2f04..3e026a969386 100644
--- a/drivers/gpu/drm/amd/display/dc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/Makefile
@@ -1,5 +1,6 @@
 #
 # Copyright 2017 Advanced Micro Devices, Inc.
+# Copyright 2019 Raptor Engineering, LLC
 #
 # Permission is hereby granted, free of charge, to any person obtaining a
 # copy of this software and associated documentation files (the "Software"),
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/Makefile 
b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
index 26c6d735cdc7..0d46c37d6c95 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
@@ -24,7 +24,9 @@
 # It calculates Bandwidth and Watermarks values for HW programming
 #
 
+ifdef CONFIG_X86_64
 calcs_ccflags := -mhard-float -msse
+endif
 
 ifdef CONFIG_CC_IS_GCC
 ifeq ($(call cc-ifversion, -lt, 0701, y), y)
@@ -32,6 +34,7 @@ IS_OLD_GCC = 1
 endif
 endif
 
+ifdef CONFIG_X86_64
 ifdef IS_OLD_GCC
 # Stack alignment mismatch, proceed with caution.
 # GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
@@ -40,6 +43,7 @@ calcs_ccflags += -mpreferred-stack-boundary=4
 else
 calcs_ccflags += -msse2
 endif
+endif
 
 CFLAGS_$(AMDDALPATH)/dc/calcs/dcn_calcs.o := $(calcs_ccflags)
 CFLAGS_$(AMDDALPATH)/dc/calcs/dcn_calc_auto.o := $(calcs_ccflags)
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index 9b2cb57bf2ba..5c913b585ac4 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -1,5 +1,6 @@
 /*
  * Copyright 2017 Advanced Micro Devices, Inc.
+ * Copyright 2019 Raptor Engineering, LLC
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -626,7 +627,20 @@ static bool dcn_bw_apply_registry_override(struct dc *dc)
 {
bool updated = false;
 
+#if defined(CONFIG_X86_64)
kernel_fpu_begin();
+#elif defined(CONFIG_PPC32) || defined(CONFIG_PPC64)
+   if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
+   preempt_disable();
+   enable_kernel_vsx();
+   } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
+   preempt_disa

Re: [PATCH 1/1] amdgpu: Enable KFD on POWER systems

2019-11-25 Thread Timothy Pearson 


- Original Message -
> From: "Felix Kuehling" 
> To: "Timothy Pearson" 
> Cc: "amd-gfx" 
> Sent: Monday, November 25, 2019 3:34:20 PM
> Subject: Re: [PATCH 1/1] amdgpu: Enable KFD on POWER systems

> On 2019-11-25 4:06 p.m., Timothy Pearson wrote:
>>
>> - Original Message -
>>> From: "Felix Kuehling" 
>>> To: "Timothy Pearson" , "amd-gfx"
>>> 
>>> Sent: Monday, November 25, 2019 11:07:31 AM
>>> Subject: Re: [PATCH 1/1] amdgpu: Enable KFD on POWER systems
>>> Hi Timothy,
>>>
>>> Thank you for the patch and for confirming that it works. We did some
>>> experimental work on Power8 a few years ago. I see that Talos II is Power9.
>>>
>>> At the time we were working on Power8 we had to add some #ifdef
>>> CONFIG_ACPI guards around some ACPI-specific code in KFD. Do you know to
>>> what extent ACPI is available and working on the Power architecture?
>>>
>>> Another problem we ran into with Power, is the physical address map.
>>> System memory can be a physical addresses outside the range accessible
>>> by the GPU. Vega has 44-bit physical addressing. Older Polaris GPUs only
>>> have 40-bits. Did you run into any such problems? Do you need an IOMMU
>>> to make system memory accessible to the GPU?
>>>
>>> Regards,
>>>    Felix
>> Yes, we are POWER9.  It looks like the ACPI guards are no longer required; as
>> you have surmised, POWER does not use ACPI (the equivalent is OPAL, which is 
>> a
>> different interface entirely).  What were the APCI calls used for?  There may
>> be OPAL equivalents that could be added in to replace them and provide 
>> similar
>> functionality.
> 
> There are some ACPI calls (e.g. acpi_get_table) in kfd_crat.c for
> getting a CRAT table from ACPI. This is only useful for AMD APUs, which
> are x86_64. We don't need this for discrete GPUs because on non-APU
> systems there is no CRAT table and we build our own. If you can compile
> the code without problems on Power and with CONFIG_ACPI not defined,
> then I guess this is no longer an issue.

Sounds reasonable -- yes, it compiles without issue so I think we're good to go.

> 
>> Kernel 5.4 enables a > 32-bit and <=64-bit bypass mode for POWER.  This is 
>> one
>> reason we came back and revisited the KFD/ROCm functionality on POWER; as it
>> turns out, after fixing up the userspace tools KFD is indeed functional on
>> POWER with 5.4-rc8 and above.  My understanding is that the POWER IOMMU is 
>> used
>> as a lightweight translation layer between the 64-bit host and the 40/44-bit
>> GPU.
>>
>> I'm working on getting a Debian PPA set up for POWER to make the userspace 
>> tools
>> easier to obtain for testing, but progress is slow due to lack of Debian 
>> source
>> packages.  Probably the easiest way to replicate / test this with HIP is to 
>> use
>> the AOMP repository with my modifications; pull requests are already in place
>> on Github for most of the userspace tooling updates.
>>
>> Thank you!
> Thanks,
>   Felix
> 
> 
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 1/1] amdgpu: Enable KFD on POWER systems

2019-11-25 Thread Timothy Pearson 


- Original Message -
> From: "Felix Kuehling" 
> To: "Timothy Pearson" , "amd-gfx" 
> 
> Sent: Monday, November 25, 2019 11:07:31 AM
> Subject: Re: [PATCH 1/1] amdgpu: Enable KFD on POWER systems

> Hi Timothy,
> 
> Thank you for the patch and for confirming that it works. We did some
> experimental work on Power8 a few years ago. I see that Talos II is Power9.
> 
> At the time we were working on Power8 we had to add some #ifdef
> CONFIG_ACPI guards around some ACPI-specific code in KFD. Do you know to
> what extent ACPI is available and working on the Power architecture?
> 
> Another problem we ran into with Power, is the physical address map.
> System memory can be a physical addresses outside the range accessible
> by the GPU. Vega has 44-bit physical addressing. Older Polaris GPUs only
> have 40-bits. Did you run into any such problems? Do you need an IOMMU
> to make system memory accessible to the GPU?
> 
> Regards,
>   Felix

Yes, we are POWER9.  It looks like the ACPI guards are no longer required; as 
you have surmised, POWER does not use ACPI (the equivalent is OPAL, which is a 
different interface entirely).  What were the APCI calls used for?  There may 
be OPAL equivalents that could be added in to replace them and provide similar 
functionality.

Kernel 5.4 enables a > 32-bit and <=64-bit bypass mode for POWER.  This is one 
reason we came back and revisited the KFD/ROCm functionality on POWER; as it 
turns out, after fixing up the userspace tools KFD is indeed functional on 
POWER with 5.4-rc8 and above.  My understanding is that the POWER IOMMU is used 
as a lightweight translation layer between the 64-bit host and the 40/44-bit 
GPU.

I'm working on getting a Debian PPA set up for POWER to make the userspace 
tools easier to obtain for testing, but progress is slow due to lack of Debian 
source packages.  Probably the easiest way to replicate / test this with HIP is 
to use the AOMP repository with my modifications; pull requests are already in 
place on Github for most of the userspace tooling updates.

Thank you!
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Re: [PATCH 1/1] amdgpu: Enable KFD on POWER systems

2019-11-24 Thread Timothy Pearson 
Sorry for the spam -- I had thought I was signed up for this list but 
apparently was not, and resent a couple times.

- Original Message -
> From: "Timothy Pearson" 
> To: "amd-gfx" 
> Sent: Sunday, November 24, 2019 1:10:52 PM
> Subject: [PATCH 1/1] amdgpu: Enable KFD on POWER systems

> KFD has been verified to function on POWER systems (Talos II / Vega 64).
> It should be available as a kernel configuration option on these systems.
> ---
> drivers/gpu/drm/amd/amdkfd/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdkfd/Kconfig
> b/drivers/gpu/drm/amd/amdkfd/Kconfig
> index a1a35d4d594b..ba0e68057a89 100644
> --- a/drivers/gpu/drm/amd/amdkfd/Kconfig
> +++ b/drivers/gpu/drm/amd/amdkfd/Kconfig
> @@ -5,7 +5,7 @@
> 
> config HSA_AMD
>   bool "HSA kernel driver for AMD GPU devices"
> - depends on DRM_AMDGPU && (X86_64 || ARM64)
> + depends on DRM_AMDGPU && (X86_64 || ARM64 || PPC64)
>   imply AMD_IOMMU_V2 if X86_64
>   select MMU_NOTIFIER
>   help
> --
> 2.20.1
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[PATCH 1/1] amdgpu: Enable KFD on POWER systems

2019-11-24 Thread Timothy Pearson 
KFD has been verified to function on POWER systems (Talos II / Vega 64).
It should be available as a kernel configuration option on these systems.
---
 drivers/gpu/drm/amd/amdkfd/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/Kconfig 
b/drivers/gpu/drm/amd/amdkfd/Kconfig
index a1a35d4d594b..ba0e68057a89 100644
--- a/drivers/gpu/drm/amd/amdkfd/Kconfig
+++ b/drivers/gpu/drm/amd/amdkfd/Kconfig
@@ -5,7 +5,7 @@
 
 config HSA_AMD
bool "HSA kernel driver for AMD GPU devices"
-   depends on DRM_AMDGPU && (X86_64 || ARM64)
+   depends on DRM_AMDGPU && (X86_64 || ARM64 || PPC64)
imply AMD_IOMMU_V2 if X86_64
select MMU_NOTIFIER
help
-- 
2.20.1

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[PATCH 1/1] amdgpu: Enable KFD on POWER systems

2019-11-24 Thread Timothy Pearson 
KFD has been verified to function on POWER systems (Talos II / Vega 64).
It should be available as a kernel configuration option on these systems.
---
 drivers/gpu/drm/amd/amdkfd/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/Kconfig 
b/drivers/gpu/drm/amd/amdkfd/Kconfig
index a1a35d4d594b..ba0e68057a89 100644
--- a/drivers/gpu/drm/amd/amdkfd/Kconfig
+++ b/drivers/gpu/drm/amd/amdkfd/Kconfig
@@ -5,7 +5,7 @@
 
 config HSA_AMD
bool "HSA kernel driver for AMD GPU devices"
-   depends on DRM_AMDGPU && (X86_64 || ARM64)
+   depends on DRM_AMDGPU && (X86_64 || ARM64 || PPC64)
imply AMD_IOMMU_V2 if X86_64
select MMU_NOTIFIER
help
-- 
2.20.1
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[PATCH 1/1] amdgpu: Enable KFD on POWER systems

2019-11-24 Thread Timothy Pearson 
KFD has been verified to function on POWER systems (Talos II / Vega 64).
It should be available as a kernel configuration option on these systems.

Signed-off-by: Timothy Pearson 
---
 drivers/gpu/drm/amd/amdkfd/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/Kconfig 
b/drivers/gpu/drm/amd/amdkfd/Kconfig
index a1a35d4d594b..ba0e68057a89 100644
--- a/drivers/gpu/drm/amd/amdkfd/Kconfig
+++ b/drivers/gpu/drm/amd/amdkfd/Kconfig
@@ -5,7 +5,7 @@
 
 config HSA_AMD
bool "HSA kernel driver for AMD GPU devices"
-   depends on DRM_AMDGPU && (X86_64 || ARM64)
+   depends on DRM_AMDGPU && (X86_64 || ARM64 || PPC64)
imply AMD_IOMMU_V2 if X86_64
select MMU_NOTIFIER
help
-- 
2.20.1
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Re: [PATCH] Increase AMDGPU_MAX_UVD_INSTANCES to 3

2018-06-25 Thread Timothy Pearson 
n 06/25/2018 09:46 AM, James Zhu wrote:
> 
> 
> On 2018-06-23 08:02 PM, Timothy Pearson wrote:
>> amdgpu_fence_driver_start_ring() attempts to access
>> UVD instance 2 during setup, while the existing UVD
>> instance count only allows instances 0 and 1.
>>
>> Increase AMDGPU_MAX_UVD_INSTANCES by one to avoid the
>> invalid array access.
>>
>> Caught by UBSAN.
> Hi Timothy,
> 
> From design of view, it is not right to just change
> AMDGPU_MAX_UVD_INSTANCES to 3.
> 
> Could you tell me some detail of UBSAN test and attach the dmesg also?

Definitely, was looking for some feedback from anyone knowing more about
the internals of the UVD system.

What's happening is that "ring->me" in amdgpu_fence_driver_start_ring()
(drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:379) is set to a value of
"2".  The overall dmesg is otherwise uninteresting, but I can try to
grab the UBSAN output if needed.

-- 
Timothy Pearson
Raptor Engineering
+1 (415) 727-8645 (direct line)
+1 (512) 690-0200 (switchboard)
https://www.raptorengineering.com
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[PATCH] Increase AMDGPU_MAX_UVD_INSTANCES to 3

2018-06-25 Thread Timothy Pearson 

amdgpu_fence_driver_start_ring() attempts to access
UVD instance 2 during setup, while the existing UVD
instance count only allows instances 0 and 1.

Increase AMDGPU_MAX_UVD_INSTANCES by one to avoid the
invalid array access.

Caught by UBSAN.

Signed-off-by: Timothy Pearson 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
index 8b23a1b00c76..4a47cb570af7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
@@ -31,7 +31,7 @@
 #define AMDGPU_UVD_SESSION_SIZE(50*1024)
 #define AMDGPU_UVD_FIRMWARE_OFFSET 256
 
-#define AMDGPU_MAX_UVD_INSTANCES   2
+#define AMDGPU_MAX_UVD_INSTANCES   3
 
 #define AMDGPU_UVD_FIRMWARE_SIZE(adev)\
(AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(((const struct 
common_firmware_header *)(adev)->uvd.fw->data)->ucode_size_bytes) + \
-- 
2.17.1
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[PATCH 1/1] Fix undefined behaviour from signed integer overflow

2018-06-25 Thread Timothy Pearson 

Caught by UBSAN

Signed-off-by: Timothy Pearson 
---
 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
index d644a9bb9078..a9c386fd9493 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
@@ -98,7 +98,7 @@ int smu7_copy_bytes_to_smc(struct pp_hwmgr *hwmgr, uint32_t 
smc_start_address,
 
while (byte_count >= 4) {
/* Bytes are written into the SMC addres space with the MSB first. */
-   data = src[0] * 0x100 + src[1] * 0x1 + src[2] * 0x100 + 
src[3];
+   data = src[0] * 0x100U + src[1] * 0x1U + src[2] * 
0x100U + src[3];
 
result = smu7_set_smc_sram_address(hwmgr, addr, limit);
 
-- 
2.17.1

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