[PATCH v2 6/7] drm/amdgpu: add VCN sensor value for SMU 13.0.5
This will add VCN sensor value for SMU 13.0.5. Signed-off-by: Xiaojian Du --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c index 0dce672ac1b9..218f209c3775 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c @@ -286,7 +286,7 @@ static int smu_v13_0_5_get_smu_metrics_data(struct smu_context *smu, *value = metrics->GfxActivity / 100; break; case METRICS_AVERAGE_VCNACTIVITY: - *value = metrics->UvdActivity; + *value = metrics->UvdActivity / 100; break; case METRICS_CURR_SOCKETPOWER: *value = (metrics->CurrentSocketPower << 8) / 1000; @@ -332,6 +332,12 @@ static int smu_v13_0_5_read_sensor(struct smu_context *smu, (uint32_t *)data); *size = 4; break; + case AMDGPU_PP_SENSOR_VCN_LOAD: + ret = smu_v13_0_5_get_smu_metrics_data(smu, + METRICS_AVERAGE_VCNACTIVITY, + (uint32_t *)data); + *size = 4; + break; case AMDGPU_PP_SENSOR_GPU_INPUT_POWER: ret = smu_v13_0_5_get_smu_metrics_data(smu, METRICS_CURR_SOCKETPOWER, -- 2.34.1
[PATCH v2 7/7] drm/amdgpu: add VCN sensor value for SMU 14.0.0
This will add VCN sensor value for SMU 14.0.0. Signed-off-by: Xiaojian Du --- drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c index 47fdbae4adfc..1d6630d20402 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c @@ -352,6 +352,12 @@ static int smu_v14_0_0_read_sensor(struct smu_context *smu, (uint32_t *)data); *size = 4; break; + case AMDGPU_PP_SENSOR_VCN_LOAD: + ret = smu_v14_0_0_get_smu_metrics_data(smu, + METRICS_AVERAGE_VCNACTIVITY, + (uint32_t *)data); + *size = 4; + break; case AMDGPU_PP_SENSOR_GPU_AVG_POWER: ret = smu_v14_0_0_get_smu_metrics_data(smu, METRICS_AVERAGE_SOCKETPOWER, -- 2.34.1
[PATCH v2 5/7] drm/amdgpu: add VCN sensor value for yellow carp
This will add VCN sensor value for yellow carp. Signed-off-by: Xiaojian Du --- drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c index 2d1736234b4a..d8bcf765a803 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c @@ -363,7 +363,7 @@ static int yellow_carp_get_smu_metrics_data(struct smu_context *smu, *value = metrics->GfxActivity / 100; break; case METRICS_AVERAGE_VCNACTIVITY: - *value = metrics->UvdActivity; + *value = metrics->UvdActivity / 100; break; case METRICS_CURR_SOCKETPOWER: *value = (metrics->CurrentSocketPower << 8) / 1000; @@ -423,6 +423,12 @@ static int yellow_carp_read_sensor(struct smu_context *smu, (uint32_t *)data); *size = 4; break; + case AMDGPU_PP_SENSOR_VCN_LOAD: + ret = yellow_carp_get_smu_metrics_data(smu, + METRICS_AVERAGE_VCNACTIVITY, + (uint32_t *)data); + *size = 4; + break; case AMDGPU_PP_SENSOR_GPU_INPUT_POWER: ret = yellow_carp_get_smu_metrics_data(smu, METRICS_CURR_SOCKETPOWER, -- 2.34.1
[PATCH v2 2/7] drm/amdgpu: add VCN sensor value for SMU 13.0.4
This will add VCN sensor value for SMU 13.0.4. Signed-off-by: Xiaojian Du --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c index bb98156b2fa1..e8119918ef6b 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c @@ -318,7 +318,7 @@ static int smu_v13_0_4_get_smu_metrics_data(struct smu_context *smu, *value = metrics->GfxActivity / 100; break; case METRICS_AVERAGE_VCNACTIVITY: - *value = metrics->UvdActivity; + *value = metrics->UvdActivity / 100; break; case METRICS_AVERAGE_SOCKETPOWER: *value = (metrics->AverageSocketPower << 8) / 1000; @@ -572,6 +572,12 @@ static int smu_v13_0_4_read_sensor(struct smu_context *smu, (uint32_t *)data); *size = 4; break; + case AMDGPU_PP_SENSOR_VCN_LOAD: + ret = smu_v13_0_4_get_smu_metrics_data(smu, + METRICS_AVERAGE_VCNACTIVITY, + (uint32_t *)data); + *size = 4; + break; case AMDGPU_PP_SENSOR_GPU_AVG_POWER: ret = smu_v13_0_4_get_smu_metrics_data(smu, METRICS_AVERAGE_SOCKETPOWER, -- 2.34.1
[PATCH v2 4/7] drm/amdgpu: add VCN sensor value for Vangogh
This will drm/amdgpu: add VCN sensor value for Vangogh. Signed-off-by: Xiaojian Du --- drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c index 2ff6deedef95..29295941aca9 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c @@ -301,7 +301,7 @@ static int vangogh_get_legacy_smu_metrics_data(struct smu_context *smu, *value = metrics->GfxActivity / 100; break; case METRICS_AVERAGE_VCNACTIVITY: - *value = metrics->UvdActivity; + *value = metrics->UvdActivity / 100; break; case METRICS_AVERAGE_SOCKETPOWER: *value = (metrics->CurrentSocketPower << 8) / @@ -1507,6 +1507,12 @@ static int vangogh_read_sensor(struct smu_context *smu, (uint32_t *)data); *size = 4; break; + case AMDGPU_PP_SENSOR_VCN_LOAD: + ret = vangogh_common_get_smu_metrics_data(smu, + METRICS_AVERAGE_VCNACTIVITY, + (uint32_t *)data); + *size = 4; + break; case AMDGPU_PP_SENSOR_GPU_AVG_POWER: ret = vangogh_common_get_smu_metrics_data(smu, METRICS_AVERAGE_SOCKETPOWER, -- 2.34.1
[PATCH v2 1/7] drm/amdgpu: add the sensor value of VCN activity
This will add the sensor value of VCN activity for some ASICs.
Signed-off-by: Xiaojian Du
---
.../gpu/drm/amd/include/kgd_pp_interface.h| 1 +
drivers/gpu/drm/amd/pm/amdgpu_pm.c| 37 +++
2 files changed, 38 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index 36a5ad8c00c5..8a180592e123 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -150,6 +150,7 @@ enum amd_pp_sensors {
AMDGPU_PP_SENSOR_VCN_POWER_STATE,
AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK,
AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK,
+ AMDGPU_PP_SENSOR_VCN_LOAD,
};
enum amd_pp_task {
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 2cd995b0ceba..99cb2c6e8a4b 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -1581,6 +1581,30 @@ static ssize_t amdgpu_get_mem_busy_percent(struct device
*dev,
return sysfs_emit(buf, "%d\n", value);
}
+/**
+ * DOC: vcn_busy_percent
+ *
+ * The amdgpu driver provides a sysfs API for reading how busy the VCN
+ * is as a percentage. The file vcn_busy_percent is used for this.
+ * The SMU firmware computes a percentage of load based on the
+ * aggregate activity level in the IP cores.
+ */
+static ssize_t amdgpu_get_vcn_busy_percent(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct drm_device *ddev = dev_get_drvdata(dev);
+ struct amdgpu_device *adev = drm_to_adev(ddev);
+ unsigned int value;
+ int r;
+
+ r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_VCN_LOAD,
);
+ if (r)
+ return r;
+
+ return sysfs_emit(buf, "%d\n", value);
+}
+
/**
* DOC: pcie_bw
*
@@ -2121,6 +2145,7 @@ static struct amdgpu_device_attr amdgpu_device_attrs[] = {
AMDGPU_DEVICE_ATTR_RW(pp_od_clk_voltage,
ATTR_FLAG_BASIC),
AMDGPU_DEVICE_ATTR_RO(gpu_busy_percent,
ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
AMDGPU_DEVICE_ATTR_RO(mem_busy_percent,
ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
+ AMDGPU_DEVICE_ATTR_RO(vcn_busy_percent,
ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
AMDGPU_DEVICE_ATTR_RO(pcie_bw,
ATTR_FLAG_BASIC),
AMDGPU_DEVICE_ATTR_RW(pp_features,
ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
AMDGPU_DEVICE_ATTR_RO(unique_id,
ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
@@ -2170,6 +2195,15 @@ static int default_attr_update(struct amdgpu_device
*adev, struct amdgpu_device_
} else if (DEVICE_ATTR_IS(mem_busy_percent)) {
if (adev->flags & AMD_IS_APU || gc_ver == IP_VERSION(9, 0, 1))
*states = ATTR_STATE_UNSUPPORTED;
+ } else if (DEVICE_ATTR_IS(vcn_busy_percent)) {
+ if (!(gc_ver == IP_VERSION(10, 3, 1) ||
+ gc_ver == IP_VERSION(10, 3, 3) ||
+ gc_ver == IP_VERSION(10, 3, 6) ||
+ gc_ver == IP_VERSION(10, 3, 7) ||
+ gc_ver == IP_VERSION(11, 0, 1) ||
+ gc_ver == IP_VERSION(11, 0, 4) ||
+ gc_ver == IP_VERSION(11, 5, 0)))
+ *states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(pcie_bw)) {
/* PCIe Perf counters won't work on APU nodes */
if (adev->flags & AMD_IS_APU)
@@ -4365,6 +4399,9 @@ static int amdgpu_debugfs_pm_info_pp(struct seq_file *m,
struct amdgpu_device *a
/* MEM Load */
if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD, (void
*), ))
seq_printf(m, "MEM Load: %u %%\n", value);
+ /* VCN Load */
+ if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_LOAD, (void
*), ))
+ seq_printf(m, "VCN Load: %u %%\n", value);
seq_printf(m, "\n");
--
2.34.1
[PATCH v2 3/7] drm/admgpu: add vclk and dclk sysfs node for some ASICs
This will add vclk and dclk sysfs node for some ASICs.
Signed-off-by: Xiaojian Du
---
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 99cb2c6e8a4b..09069758567d 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -2235,9 +2235,15 @@ static int default_attr_update(struct amdgpu_device
*adev, struct amdgpu_device_
*states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(pp_dpm_vclk)) {
if (!(gc_ver == IP_VERSION(10, 3, 1) ||
+ gc_ver == IP_VERSION(10, 3, 3) ||
+ gc_ver == IP_VERSION(10, 3, 6) ||
+ gc_ver == IP_VERSION(10, 3, 7) ||
gc_ver == IP_VERSION(10, 3, 0) ||
gc_ver == IP_VERSION(10, 1, 2) ||
gc_ver == IP_VERSION(11, 0, 0) ||
+ gc_ver == IP_VERSION(11, 0, 1) ||
+ gc_ver == IP_VERSION(11, 0, 4) ||
+ gc_ver == IP_VERSION(11, 5, 0) ||
gc_ver == IP_VERSION(11, 0, 2) ||
gc_ver == IP_VERSION(11, 0, 3) ||
gc_ver == IP_VERSION(9, 4, 3)))
@@ -2250,9 +2256,15 @@ static int default_attr_update(struct amdgpu_device
*adev, struct amdgpu_device_
*states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(pp_dpm_dclk)) {
if (!(gc_ver == IP_VERSION(10, 3, 1) ||
+ gc_ver == IP_VERSION(10, 3, 3) ||
+ gc_ver == IP_VERSION(10, 3, 6) ||
+ gc_ver == IP_VERSION(10, 3, 7) ||
gc_ver == IP_VERSION(10, 3, 0) ||
gc_ver == IP_VERSION(10, 1, 2) ||
gc_ver == IP_VERSION(11, 0, 0) ||
+ gc_ver == IP_VERSION(11, 0, 1) ||
+ gc_ver == IP_VERSION(11, 0, 4) ||
+ gc_ver == IP_VERSION(11, 5, 0) ||
gc_ver == IP_VERSION(11, 0, 2) ||
gc_ver == IP_VERSION(11, 0, 3) ||
gc_ver == IP_VERSION(9, 4, 3)))
--
2.34.1
[PATCH 2/2] drm/amdgpu: add VCN sensor value for SMU 13.0.4
This will add VCN sensor value for SMU 13.0.4. Signed-off-by: Xiaojian Du --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c index bb98156b2fa1..e8119918ef6b 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c @@ -318,7 +318,7 @@ static int smu_v13_0_4_get_smu_metrics_data(struct smu_context *smu, *value = metrics->GfxActivity / 100; break; case METRICS_AVERAGE_VCNACTIVITY: - *value = metrics->UvdActivity; + *value = metrics->UvdActivity / 100; break; case METRICS_AVERAGE_SOCKETPOWER: *value = (metrics->AverageSocketPower << 8) / 1000; @@ -572,6 +572,12 @@ static int smu_v13_0_4_read_sensor(struct smu_context *smu, (uint32_t *)data); *size = 4; break; + case AMDGPU_PP_SENSOR_VCN_LOAD: + ret = smu_v13_0_4_get_smu_metrics_data(smu, + METRICS_AVERAGE_VCNACTIVITY, + (uint32_t *)data); + *size = 4; + break; case AMDGPU_PP_SENSOR_GPU_AVG_POWER: ret = smu_v13_0_4_get_smu_metrics_data(smu, METRICS_AVERAGE_SOCKETPOWER, -- 2.34.1
[PATCH 1/2] drm/amdgpu: add the sensor value of VCN activity
This will add the sensor value of VCN activity.
Signed-off-by: Xiaojian Du
---
.../gpu/drm/amd/include/kgd_pp_interface.h| 1 +
drivers/gpu/drm/amd/pm/amdgpu_pm.c| 28 +++
2 files changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index 36a5ad8c00c5..8a180592e123 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -150,6 +150,7 @@ enum amd_pp_sensors {
AMDGPU_PP_SENSOR_VCN_POWER_STATE,
AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK,
AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK,
+ AMDGPU_PP_SENSOR_VCN_LOAD,
};
enum amd_pp_task {
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 2cd995b0ceba..602dfa37ab64 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -1581,6 +1581,30 @@ static ssize_t amdgpu_get_mem_busy_percent(struct device
*dev,
return sysfs_emit(buf, "%d\n", value);
}
+/**
+ * DOC: vcn_busy_percent
+ *
+ * The amdgpu driver provides a sysfs API for reading how busy the VCN
+ * is as a percentage. The file vcn_busy_percent is used for this.
+ * The SMU firmware computes a percentage of load based on the
+ * aggregate activity level in the IP cores.
+ */
+static ssize_t amdgpu_get_vcn_busy_percent(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct drm_device *ddev = dev_get_drvdata(dev);
+ struct amdgpu_device *adev = drm_to_adev(ddev);
+ unsigned int value;
+ int r;
+
+ r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_VCN_LOAD,
);
+ if (r)
+ return r;
+
+ return sysfs_emit(buf, "%d\n", value);
+}
+
/**
* DOC: pcie_bw
*
@@ -2121,6 +2145,7 @@ static struct amdgpu_device_attr amdgpu_device_attrs[] = {
AMDGPU_DEVICE_ATTR_RW(pp_od_clk_voltage,
ATTR_FLAG_BASIC),
AMDGPU_DEVICE_ATTR_RO(gpu_busy_percent,
ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
AMDGPU_DEVICE_ATTR_RO(mem_busy_percent,
ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
+ AMDGPU_DEVICE_ATTR_RO(vcn_busy_percent,
ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
AMDGPU_DEVICE_ATTR_RO(pcie_bw,
ATTR_FLAG_BASIC),
AMDGPU_DEVICE_ATTR_RW(pp_features,
ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
AMDGPU_DEVICE_ATTR_RO(unique_id,
ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
@@ -4365,6 +4390,9 @@ static int amdgpu_debugfs_pm_info_pp(struct seq_file *m,
struct amdgpu_device *a
/* MEM Load */
if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD, (void
*), ))
seq_printf(m, "MEM Load: %u %%\n", value);
+ /* VCN Load */
+ if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_LOAD, (void
*), ))
+ seq_printf(m, "VCN Load: %u %%\n", value);
seq_printf(m, "\n");
--
2.34.1
[PATCH 5/5] drm/amdgpu: enable support for psp 13.0.4 block
This patch will enable support for psp 13.0.4 blcok.
Signed-off-by: Xiaojian Du
---
drivers/gpu/drm/amd/amdgpu/Makefile | 3 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 4 +++-
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 13 +
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 1 +
4 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
b/drivers/gpu/drm/amd/amdgpu/Makefile
index c7d0cd15b5ef..5a283d12f8e1 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -115,7 +115,8 @@ amdgpu-y += \
psp_v11_0.o \
psp_v11_0_8.o \
psp_v12_0.o \
- psp_v13_0.o
+ psp_v13_0.o \
+ psp_v13_0_4.o
# add DCE block
amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 242d1847c4aa..95d34590cad1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -1630,12 +1630,14 @@ static int amdgpu_discovery_set_psp_ip_blocks(struct
amdgpu_device *adev)
case IP_VERSION(13, 0, 1):
case IP_VERSION(13, 0, 2):
case IP_VERSION(13, 0, 3):
- case IP_VERSION(13, 0, 4):
case IP_VERSION(13, 0, 5):
case IP_VERSION(13, 0, 7):
case IP_VERSION(13, 0, 8):
amdgpu_device_ip_block_add(adev, _v13_0_ip_block);
break;
+ case IP_VERSION(13, 0, 4):
+ amdgpu_device_ip_block_add(adev, _v13_0_4_ip_block);
+ break;
default:
dev_err(adev->dev,
"Failed to add psp ip block(MP0_HWIP:0x%x)\n",
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 3ee363bfbac2..bf41374e3ea0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -37,6 +37,7 @@
#include "psp_v11_0_8.h"
#include "psp_v12_0.h"
#include "psp_v13_0.h"
+#include "psp_v13_0_4.h"
#include "amdgpu_ras.h"
#include "amdgpu_securedisplay.h"
@@ -151,6 +152,10 @@ static int psp_early_init(void *handle)
psp_v13_0_set_psp_funcs(psp);
psp->autoload_supported = true;
break;
+ case IP_VERSION(13, 0, 4):
+ psp_v13_0_4_set_psp_funcs(psp);
+ psp->autoload_supported = true;
+ break;
default:
return -EINVAL;
}
@@ -3692,3 +3697,11 @@ const struct amdgpu_ip_block_version psp_v13_0_ip_block
= {
.rev = 0,
.funcs = _ip_funcs,
};
+
+const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = {
+ .type = AMD_IP_BLOCK_TYPE_PSP,
+ .major = 13,
+ .minor = 0,
+ .rev = 4,
+ .funcs = _ip_funcs,
+};
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index 180634616b0f..c32b74bd970f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -439,6 +439,7 @@ extern const struct amdgpu_ip_block_version
psp_v11_0_ip_block;
extern const struct amdgpu_ip_block_version psp_v11_0_8_ip_block;
extern const struct amdgpu_ip_block_version psp_v12_0_ip_block;
extern const struct amdgpu_ip_block_version psp_v13_0_ip_block;
+extern const struct amdgpu_ip_block_version psp_v13_0_4_ip_block;
extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
uint32_t field_val, uint32_t mask, bool check_changed);
--
2.25.1
[PATCH 4/5] drm/amdgpu: add files for PSP 13.0.4
This patch will add files for PSP 13.0.4.
Signed-off-by: Xiaojian Du
---
drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.c | 387 +++
drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.h | 30 ++
2 files changed, 417 insertions(+)
create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.h
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.c
b/drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.c
new file mode 100644
index ..321089dfa7db
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.c
@@ -0,0 +1,387 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include "amdgpu.h"
+#include "amdgpu_psp.h"
+#include "amdgpu_ucode.h"
+#include "soc15_common.h"
+#include "psp_v13_0_4.h"
+
+#include "mp/mp_13_0_4_offset.h"
+#include "mp/mp_13_0_4_sh_mask.h"
+
+MODULE_FIRMWARE("amdgpu/psp_13_0_4_toc.bin");
+MODULE_FIRMWARE("amdgpu/psp_13_0_4_ta.bin");
+
+static int psp_v13_0_4_init_microcode(struct psp_context *psp)
+{
+ struct amdgpu_device *adev = psp->adev;
+ const char *chip_name;
+ char ucode_prefix[30];
+ int err = 0;
+
+ switch (adev->ip_versions[MP0_HWIP][0]) {
+ case IP_VERSION(13, 0, 4):
+ amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix,
sizeof(ucode_prefix));
+ chip_name = ucode_prefix;
+ break;
+ default:
+ BUG();
+ }
+
+ switch (adev->ip_versions[MP0_HWIP][0]) {
+ case IP_VERSION(13, 0, 4):
+ err = psp_init_toc_microcode(psp, chip_name);
+ if (err)
+ return err;
+ err = psp_init_ta_microcode(psp, chip_name);
+ if (err)
+ return err;
+ break;
+ default:
+ BUG();
+ }
+
+ return 0;
+}
+
+static bool psp_v13_0_4_is_sos_alive(struct psp_context *psp)
+{
+ struct amdgpu_device *adev = psp->adev;
+ uint32_t sol_reg;
+
+ sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
+
+ return sol_reg != 0x0;
+}
+
+static int psp_v13_0_4_wait_for_bootloader(struct psp_context *psp)
+{
+ struct amdgpu_device *adev = psp->adev;
+
+ int ret;
+ int retry_loop;
+
+ for (retry_loop = 0; retry_loop < 10; retry_loop++) {
+ /* Wait for bootloader to signify that is
+ ready having bit 31 of C2PMSG_35 set to 1 */
+ ret = psp_wait_for(psp,
+ SOC15_REG_OFFSET(MP0, 0,
regMP0_SMN_C2PMSG_35),
+ 0x8000,
+ 0x8000,
+ false);
+
+ if (ret == 0)
+ return 0;
+ }
+
+ return ret;
+}
+
+static int psp_v13_0_4_bootloader_load_component(struct psp_context*psp,
+ struct psp_bin_desc
*bin_desc,
+ enum psp_bootloader_cmd bl_cmd)
+{
+ int ret;
+ uint32_t psp_gfxdrv_command_reg = 0;
+ struct amdgpu_device *adev = psp->adev;
+
+ /* Check tOS sign of life register to confirm sys driver and sOS
+* are already been loaded.
+*/
+ if (psp_v13_0_4_is_sos_alive(psp))
+ return 0;
+
+ ret = psp_v13_0_4_wait_for_bootloader(psp);
+ if (ret)
+ return ret;
+
+ memset(psp->fw_pri_buf, 0, PSP_1_MEG);
+
+ /* Copy PSP KDB binary to memory */
+ memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes);
+
+ /* Provide the PSP KDB to bootloader */
+ WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
+
[PATCH 1/5] drm/amdgpu: send msg to IMU for the front-door loading
This patch will make SMU send msg to IMU for the front-door loading, it is
required by some ASICs.
Signed-off-by: Yifan Zhang
Signed-off-by: Xiaojian Du
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 6d9b3c6af164..79c01fa4b875 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -1360,6 +1360,14 @@ static int smu_hw_init(void *handle)
return ret;
}
+ if (smu->ppt_funcs->set_gfx_power_up_by_imu) {
+ ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu);
+ if (ret) {
+ dev_err(adev->dev, "Failed to Enable gfx imu!\n");
+ return ret;
+ }
+ }
+
if (smu->is_apu) {
smu_dpm_set_vcn_enable(smu, true);
smu_dpm_set_jpeg_enable(smu, true);
--
2.25.1
[PATCH 3/5] drm/amdgpu: add header files for MP 13.0.4
This patch will add header files for MP 13.0.4. Signed-off-by: Xiaojian Du --- .../include/asic_reg/mp/mp_13_0_4_offset.h| 402 .../include/asic_reg/mp/mp_13_0_4_sh_mask.h | 595 ++ 2 files changed, 997 insertions(+) create mode 100644 drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_4_offset.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_4_sh_mask.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_4_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_4_offset.h new file mode 100644 index ..82312ecc0216 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_4_offset.h @@ -0,0 +1,402 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * + */ +#ifndef _mp_13_0_4_OFFSET_HEADER +#define _mp_13_0_4_OFFSET_HEADER + + + +// addressBlock: mp_SmuMp0_SmnDec +// base address: 0x0 +#define regMP0_SMN_C2PMSG_32 0x0060 +#define regMP0_SMN_C2PMSG_32_BASE_IDX 1 +#define regMP0_SMN_C2PMSG_33 0x0061 +#define regMP0_SMN_C2PMSG_33_BASE_IDX 1 +#define regMP0_SMN_C2PMSG_34 0x0062 +#define regMP0_SMN_C2PMSG_34_BASE_IDX 1 +#define regMP0_SMN_C2PMSG_35 0x0063 +#define regMP0_SMN_C2PMSG_35_BASE_IDX 1 +#define regMP0_SMN_C2PMSG_36 0x0064 +#define regMP0_SMN_C2PMSG_36_BASE_IDX 1 +#define regMP0_SMN_C2PMSG_37 0x0065 +#define regMP0_SMN_C2PMSG_37_BASE_IDX 1 +#define regMP0_SMN_C2PMSG_38 0x0066 +#define regMP0_SMN_C2PMSG_38_BASE_IDX 1 +#define regMP0_SMN_C2PMSG_39 0x0067 +#define regMP0_SMN_C2PMSG_39_BASE_IDX 1 +#define regMP0_SMN_C2PMSG_40 0x0068 +#define regMP0_SMN_C2PMSG_40_BASE_IDX 1 +#define regMP0_SMN_C2PMSG_41 0x0069 +#define regMP0_SMN_C2PMSG_41_BASE_IDX 1 +#define regMP0_SMN_C2PMSG_42 0x006a +#define regMP0_SMN_C2PMSG_42_BASE_IDX 1 +#define regMP0_SMN_C2PMSG_43 0x006b +#define regMP0_SMN_C2PMSG_43_BASE_IDX 1 +#define regMP0_SMN_C2PMSG_44 0x006c +#define regMP0_SMN_C2PMSG_44_BASE_IDX 1 +#define regMP0_SMN_C2PMSG_45
[PATCH 2/5] drm/amdgpu: correct RLC_RLCS_BOOTLOAD_STATUS offset and index
This patch corrects RLC_RLCS_BOOTLOAD_STATUS offset and index for
GC 11.0.1.
Signed-off-by: Yifan Zhang
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 0d8193b30fc5..6fd71cb10e54 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -56,6 +56,8 @@
#define regCGTT_WD_CLK_CTRL0x5086
#define regCGTT_WD_CLK_CTRL_BASE_IDX 1
+#define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1 0x4e7e
+#define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1_BASE_IDX 1
MODULE_FIRMWARE("amdgpu/gc_11_0_0_pfp.bin");
MODULE_FIRMWARE("amdgpu/gc_11_0_0_me.bin");
@@ -2765,7 +2767,13 @@ static int
gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
for (i = 0; i < adev->usec_timeout; i++) {
cp_status = RREG32_SOC15(GC, 0, regCP_STAT);
- bootload_status = RREG32_SOC15(GC, 0,
regRLC_RLCS_BOOTLOAD_STATUS);
+
+ if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 1))
+ bootload_status = RREG32_SOC15(GC, 0,
+ regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1);
+ else
+ bootload_status = RREG32_SOC15(GC, 0,
regRLC_RLCS_BOOTLOAD_STATUS);
+
if ((cp_status == 0) &&
(REG_GET_FIELD(bootload_status,
RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
--
2.25.1
[PATCH] drm/admgpu: fix the page fault caused by uninitialized variables
This patch will fix the page fault caused by uninitialized variables.
Signed-off-by: Xiaojian Du
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index c65d82301bca..09780a0f874a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -828,9 +828,9 @@ void amdgpu_gmc_get_reserved_allocation(struct
amdgpu_device *adev)
int amdgpu_gmc_vram_checking(struct amdgpu_device *adev)
{
- struct amdgpu_bo *vram_bo;
- uint64_t vram_gpu;
- void *vram_ptr;
+ struct amdgpu_bo *vram_bo = NULL;
+ uint64_t vram_gpu = 0;
+ void *vram_ptr = NULL;
int ret, size = 0x10;
uint8_t cptr[10];
--
2.17.1
[PATCH] drm/amdgpu: modify a pair of functions for the pcie port wreg/rreg
This patch will modify a pair of functions for pcie port wreg/rreg.
AMD GPU have had an independent NBIO block from SOC15 arch.
If the dirver wants to read/write the address space of the pcie devices,
it has to go through the NBIO block.
This patch will move the pcie port wreg/rreg functions to
"amdgpu_device.c", so that to make the functions can be used on the
future GPU ASICs.
Signed-off-by: Xiaojian Du
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 4 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 33 +
drivers/gpu/drm/amd/amdgpu/nv.c| 34 ++
3 files changed, 39 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index b2da840f4718..691d7868d64d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1421,6 +1421,10 @@ void amdgpu_device_invalidate_hdp(struct amdgpu_device
*adev,
struct amdgpu_ring *ring);
void amdgpu_device_halt(struct amdgpu_device *adev);
+u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev,
+ u32 reg);
+void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev,
+ u32 reg, u32 v);
/* atpx handler */
#if defined(CONFIG_VGA_SWITCHEROO)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index ff4cf0e2a01f..10f2b7cbb49d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -6023,3 +6023,36 @@ void amdgpu_device_halt(struct amdgpu_device *adev)
pci_disable_device(pdev);
pci_wait_for_pending_transaction(pdev);
}
+
+u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev,
+ u32 reg)
+{
+ unsigned long flags, address, data;
+ u32 r;
+
+ address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
+ data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
+
+ spin_lock_irqsave(>pcie_idx_lock, flags);
+ WREG32(address, reg * 4);
+ (void)RREG32(address);
+ r = RREG32(data);
+ spin_unlock_irqrestore(>pcie_idx_lock, flags);
+ return r;
+}
+
+void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev,
+ u32 reg, u32 v)
+{
+ unsigned long flags, address, data;
+
+ address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
+ data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
+
+ spin_lock_irqsave(>pcie_idx_lock, flags);
+ WREG32(address, reg * 4);
+ (void)RREG32(address);
+ WREG32(data, v);
+ (void)RREG32(data);
+ spin_unlock_irqrestore(>pcie_idx_lock, flags);
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index e52d1114501c..17480c1eeae8 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -256,21 +256,6 @@ static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32
reg)
return amdgpu_device_indirect_rreg64(adev, address, data, reg);
}
-static u32 nv_pcie_port_rreg(struct amdgpu_device *adev, u32 reg)
-{
- unsigned long flags, address, data;
- u32 r;
- address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
- data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
-
- spin_lock_irqsave(>pcie_idx_lock, flags);
- WREG32(address, reg * 4);
- (void)RREG32(address);
- r = RREG32(data);
- spin_unlock_irqrestore(>pcie_idx_lock, flags);
- return r;
-}
-
static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
{
unsigned long address, data;
@@ -281,21 +266,6 @@ static void nv_pcie_wreg64(struct amdgpu_device *adev, u32
reg, u64 v)
amdgpu_device_indirect_wreg64(adev, address, data, reg, v);
}
-static void nv_pcie_port_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
-{
- unsigned long flags, address, data;
-
- address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
- data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
-
- spin_lock_irqsave(>pcie_idx_lock, flags);
- WREG32(address, reg * 4);
- (void)RREG32(address);
- WREG32(data, v);
- (void)RREG32(data);
- spin_unlock_irqrestore(>pcie_idx_lock, flags);
-}
-
static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg)
{
unsigned long flags, address, data;
@@ -709,8 +679,8 @@ static int nv_common_early_init(void *handle)
adev->pcie_wreg = _pcie_wreg;
adev->pcie_rreg64 = _pcie_rreg64;
adev->pcie_wreg64 = _pcie_wreg64;
- adev->pciep_rreg = _pcie_port_rreg;
- adev->pciep_wreg = _pcie_port_wreg;
+ adev->pciep_rreg = amdgpu_device_pcie_port_rreg;
+ adev->pciep_wreg = amdgpu_device_pcie_port_w
[Patch v3] drm/amdgpu: add vram check function for GMC
This will add vram check function for GMC block.
It will write pattern data to the vram and then read back from the vram,
so that to verify the work status of vram.
This patch will cover gmc v6/7/8/9/10.
Signed-off-by: Xiaojian Du
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 46 +
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 1 +
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 5 +++
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 5 ++-
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 5 ++-
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 5 ++-
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 7 +++-
7 files changed, 70 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index 83f26bca7dac..96cabf3ed29e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -833,3 +833,49 @@ void amdgpu_gmc_get_reserved_allocation(struct
amdgpu_device *adev)
break;
}
}
+
+int amdgpu_gmc_vram_checking(struct amdgpu_device *adev)
+{
+ struct amdgpu_bo*vram_bo;
+ uint64_tvram_gpu;
+ void*vram_ptr;
+
+ int ret, size = 0x10;
+ uint8_t cptr[10];
+
+ ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE,
+ AMDGPU_GEM_DOMAIN_VRAM,
+ _bo,
+ _gpu,
+ _ptr);
+ if (ret)
+ return ret;
+
+ memset(vram_ptr, 0x86, size);
+ memset(cptr, 0x86, 10);
+
+ /**
+ * Check the start, the mid, and the end of the memory if the content of
+ * each byte is the pattern "0x86". If yes, we suppose the vram bo is
+ * workable.
+ *
+ * Note: If check the each byte of whole 1M bo, it will cost too many
+ * seconds, so here, we just pick up three parts for emulation.
+ */
+ ret = memcmp(vram_ptr, cptr, 10);
+ if (ret)
+ return ret;
+
+ ret = memcmp(vram_ptr + (size / 2), cptr, 10);
+ if (ret)
+ return ret;
+
+ ret = memcmp(vram_ptr + size - 10, cptr, 10);
+ if (ret)
+ return ret;
+
+ amdgpu_bo_free_kernel(_bo, _gpu,
+ _ptr);
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
index 82ec665b366c..f06af61378ef 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
@@ -343,4 +343,5 @@ void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev);
uint64_t amdgpu_gmc_vram_mc2pa(struct amdgpu_device *adev, uint64_t mc_addr);
uint64_t amdgpu_gmc_vram_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo);
uint64_t amdgpu_gmc_vram_cpu_pa(struct amdgpu_device *adev, struct amdgpu_bo
*bo);
+int amdgpu_gmc_vram_checking(struct amdgpu_device *adev);
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index 3915ba837596..41b11c1f8db0 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -1048,6 +1048,11 @@ static int gmc_v10_0_hw_init(void *handle)
if (r)
return r;
+ if (amdgpu_emu_mode == 1) {
+ r = amdgpu_gmc_vram_checking(adev);
+ if (r)
+ return r;
+ }
if (adev->umc.funcs && adev->umc.funcs->init_registers)
adev->umc.funcs->init_registers(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index 0fe714f54cca..dec5539fe779 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -923,7 +923,10 @@ static int gmc_v6_0_hw_init(void *handle)
if (r)
return r;
- return r;
+ if (amdgpu_emu_mode == 1)
+ return amdgpu_gmc_vram_checking(adev);
+ else
+ return r;
}
static int gmc_v6_0_hw_fini(void *handle)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 0a50fdaced7e..b249aa9b3724 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -1112,7 +1112,10 @@ static int gmc_v7_0_hw_init(void *handle)
if (r)
return r;
- return r;
+ if (amdgpu_emu_mode == 1)
+ return amdgpu_gmc_vram_checking(adev);
+ else
+ return r;
}
static int gmc_v7_0_hw_fini(void *handle)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 9a3fc0926903..78ce7828b348 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -1241,7 +1241,10 @@ static int gmc_v8_0_hw_init(void *handle)
if (r)
return r;
- return r;
[Patch v2] drm/amdgpu: add vram check function for GMC
This will add vram check function for GMC, it will cover gmc v6/7/8/9/10
Signed-off-by: Xiaojian Du
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 46 +
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 1 +
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 4 +++
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 6 +++-
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 6 +++-
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 6 +++-
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 8 -
7 files changed, 73 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index 83f26bca7dac..96cabf3ed29e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -833,3 +833,49 @@ void amdgpu_gmc_get_reserved_allocation(struct
amdgpu_device *adev)
break;
}
}
+
+int amdgpu_gmc_vram_checking(struct amdgpu_device *adev)
+{
+ struct amdgpu_bo*vram_bo;
+ uint64_tvram_gpu;
+ void*vram_ptr;
+
+ int ret, size = 0x10;
+ uint8_t cptr[10];
+
+ ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE,
+ AMDGPU_GEM_DOMAIN_VRAM,
+ _bo,
+ _gpu,
+ _ptr);
+ if (ret)
+ return ret;
+
+ memset(vram_ptr, 0x86, size);
+ memset(cptr, 0x86, 10);
+
+ /**
+ * Check the start, the mid, and the end of the memory if the content of
+ * each byte is the pattern "0x86". If yes, we suppose the vram bo is
+ * workable.
+ *
+ * Note: If check the each byte of whole 1M bo, it will cost too many
+ * seconds, so here, we just pick up three parts for emulation.
+ */
+ ret = memcmp(vram_ptr, cptr, 10);
+ if (ret)
+ return ret;
+
+ ret = memcmp(vram_ptr + (size / 2), cptr, 10);
+ if (ret)
+ return ret;
+
+ ret = memcmp(vram_ptr + size - 10, cptr, 10);
+ if (ret)
+ return ret;
+
+ amdgpu_bo_free_kernel(_bo, _gpu,
+ _ptr);
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
index 82ec665b366c..f06af61378ef 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
@@ -343,4 +343,5 @@ void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev);
uint64_t amdgpu_gmc_vram_mc2pa(struct amdgpu_device *adev, uint64_t mc_addr);
uint64_t amdgpu_gmc_vram_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo);
uint64_t amdgpu_gmc_vram_cpu_pa(struct amdgpu_device *adev, struct amdgpu_bo
*bo);
+int amdgpu_gmc_vram_checking(struct amdgpu_device *adev);
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index 3915ba837596..5e407c88c8d0 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -1048,6 +1048,10 @@ static int gmc_v10_0_hw_init(void *handle)
if (r)
return r;
+ r = amdgpu_gmc_vram_checking(adev);
+ if (r)
+ return r;
+
if (adev->umc.funcs && adev->umc.funcs->init_registers)
adev->umc.funcs->init_registers(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index 0fe714f54cca..17770c1017ba 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -923,7 +923,11 @@ static int gmc_v6_0_hw_init(void *handle)
if (r)
return r;
- return r;
+ r = amdgpu_gmc_vram_checking(adev);
+ if (r)
+ return r;
+
+ return 0;
}
static int gmc_v6_0_hw_fini(void *handle)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 0a50fdaced7e..fa43905ae61f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -1112,7 +1112,11 @@ static int gmc_v7_0_hw_init(void *handle)
if (r)
return r;
- return r;
+ r = amdgpu_gmc_vram_checking(adev);
+ if (r)
+ return r;
+
+ return 0;
}
static int gmc_v7_0_hw_fini(void *handle)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 9a3fc0926903..6c94a9712a3a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -1241,7 +1241,11 @@ static int gmc_v8_0_hw_init(void *handle)
if (r)
return r;
- return r;
+ r = amdgpu_gmc_vram_checking(adev);
+ if (r)
+ return r;
+
+ return 0;
}
static int gmc_v8_0_hw_fini(void *handle)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index
[PATCH 2/2] drm/amdgpu: add vram check function for GMC
This will add vram check function for GMC, it will cover gmc v8/9/10
Signed-off-by: Xiaojian Du
Reviewed-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 42 +
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 1 +
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 4 +++
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 6 +++-
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 8 -
5 files changed, 59 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index 83f26bca7dac..dbc0de89d7e4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -833,3 +833,45 @@ void amdgpu_gmc_get_reserved_allocation(struct
amdgpu_device *adev)
break;
}
}
+
+int amdgpu_gmc_vram_checking(struct amdgpu_device *adev)
+{
+ int ret, size = 0x10;
+ uint8_t cptr[10];
+
+ ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE,
+ AMDGPU_GEM_DOMAIN_VRAM,
+ >vram_bo,
+ >vram_gpu,
+ >vram_ptr);
+ if (ret)
+ return ret;
+
+ memset(adev->vram_ptr, 0x86, size);
+ memset(cptr, 0x86, 10);
+
+ /**
+ * Check the start, the mid, and the end of the memory if the content of
+ * each byte is the pattern "0x86". If yes, we suppose the vram bo is
+ * workable.
+ *
+ * Note: If check the each byte of whole 1M bo, it will cost too many
+ * seconds, so here, we just pick up three parts for emulation.
+ */
+ ret = memcmp(adev->vram_ptr, cptr, 10);
+ if (ret)
+ return ret;
+
+ ret = memcmp(adev->vram_ptr + (size / 2), cptr, 10);
+ if (ret)
+ return ret;
+
+ ret = memcmp(adev->vram_ptr + size - 10, cptr, 10);
+ if (ret)
+ return ret;
+
+ amdgpu_bo_free_kernel(>vram_bo, >vram_gpu,
+ >vram_ptr);
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
index 82ec665b366c..f06af61378ef 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
@@ -343,4 +343,5 @@ void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev);
uint64_t amdgpu_gmc_vram_mc2pa(struct amdgpu_device *adev, uint64_t mc_addr);
uint64_t amdgpu_gmc_vram_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo);
uint64_t amdgpu_gmc_vram_cpu_pa(struct amdgpu_device *adev, struct amdgpu_bo
*bo);
+int amdgpu_gmc_vram_checking(struct amdgpu_device *adev);
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index 3915ba837596..5e407c88c8d0 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -1048,6 +1048,10 @@ static int gmc_v10_0_hw_init(void *handle)
if (r)
return r;
+ r = amdgpu_gmc_vram_checking(adev);
+ if (r)
+ return r;
+
if (adev->umc.funcs && adev->umc.funcs->init_registers)
adev->umc.funcs->init_registers(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 9a3fc0926903..6c94a9712a3a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -1241,7 +1241,11 @@ static int gmc_v8_0_hw_init(void *handle)
if (r)
return r;
- return r;
+ r = amdgpu_gmc_vram_checking(adev);
+ if (r)
+ return r;
+
+ return 0;
}
static int gmc_v8_0_hw_fini(void *handle)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index ce7d438eeabe..1ea18b4ff63f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -1771,8 +1771,14 @@ static int gmc_v9_0_hw_init(void *handle)
adev->umc.funcs->init_registers(adev);
r = gmc_v9_0_gart_enable(adev);
+ if (r)
+ return r;
- return r;
+ r = amdgpu_gmc_vram_checking(adev);
+ if (r)
+ return r;
+
+ return 0;
}
/**
--
2.25.1
[PATCH 1/2] drm/admgpu: add data struct for vram check
This patch is to add data struct for vram check.
Signed-off-by: Xiaojian Du
Reviewed-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 64cd80d050eb..13196e50a98a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -928,6 +928,11 @@ struct amdgpu_device {
uint32_tbios_scratch_reg_offset;
uint32_tbios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
+ /* vram check */
+ struct amdgpu_bo*vram_bo;
+ uint64_tvram_gpu;
+ void*vram_ptr;
+
/* Direct GMA */
struct amdgpu_direct_gmadirect_gma;
/* SSG */
--
2.25.1
[PATCH] drm/amdgpu: update the golden setting for vangogh
This patch is to update the golden setting for vangogh. Signed-off-by: Xiaojian Du --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 705fa3027199..9144836798c5 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -3383,6 +3383,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] = SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffbf, 0x0020), SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0x, 0x00070103), SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x17ff, 0x1000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x0001, 0x00010020), SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7, 0x0103), SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x, 0x0040), SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x0fff, 0x00ff), -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amd/pm: retain the fine grain tuning parameters after resume
This patch is to retain the fine grain tuning parameters after resume for
legacy APU, it will cover Raven/Raven2/Picasso.
Signed-off-by: Xiaojian Du
---
.../amd/pm/powerplay/hwmgr/hardwaremanager.c | 3 ++-
.../drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c | 21 +++
2 files changed, 23 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/hardwaremanager.c
b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/hardwaremanager.c
index 25b5831a15cd..370deae7b054 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/hardwaremanager.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/hardwaremanager.c
@@ -82,7 +82,8 @@ int phm_enable_dynamic_state_management(struct pp_hwmgr
*hwmgr)
/* Skip for suspend/resume case */
if (!hwmgr->pp_one_vf && smum_is_dpm_running(hwmgr)
- && !amdgpu_passthrough(adev) && adev->in_suspend) {
+ && !amdgpu_passthrough(adev) && adev->in_suspend
+ && !adev->apu_flags) {
pr_info("dpm has been enabled\n");
return 0;
}
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
index f5fe540cd536..8f71f6a4bb49 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
@@ -377,6 +377,27 @@ static int smu10_enable_gfx_off(struct pp_hwmgr *hwmgr)
static int smu10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
{
+ struct amdgpu_device *adev = hwmgr->adev;
+ struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
+ int ret = -EINVAL;
+
+ if (adev->in_suspend) {
+ pr_info("restore the fine grain parameters\n");
+
+ ret = smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetHardMinGfxClk,
+ smu10_data->gfx_actual_soft_min_freq,
+ NULL);
+ if (ret)
+ return ret;
+ ret = smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetSoftMaxGfxClk,
+ smu10_data->gfx_actual_soft_max_freq,
+ NULL);
+ if (ret)
+ return ret;
+ }
+
return 0;
}
--
2.25.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amd/pm: revise two names of sensor values for vangogh
This patch is to revise two names of sensor values for vangogh.
New smu metrics table is supported by new pmfw
(from version 4.63.36.00 ), it includes two parts, one part is
the current smu metrics table data and the other part is the
average smu metrics table data. The hwmon will read the current gfxclk
and mclk from the current smu metrics table data.
Signed-off-by: Xiaojian Du
---
drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index 35904315c1f9..77f532a49e37 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -270,7 +270,7 @@ static int vangogh_get_legacy_smu_metrics_data(struct
smu_context *smu,
}
switch (member) {
- case METRICS_AVERAGE_GFXCLK:
+ case METRICS_CURR_GFXCLK:
*value = metrics->GfxclkFrequency;
break;
case METRICS_AVERAGE_SOCCLK:
@@ -282,7 +282,7 @@ static int vangogh_get_legacy_smu_metrics_data(struct
smu_context *smu,
case METRICS_AVERAGE_DCLK:
*value = metrics->DclkFrequency;
break;
- case METRICS_AVERAGE_UCLK:
+ case METRICS_CURR_UCLK:
*value = metrics->MemclkFrequency;
break;
case METRICS_AVERAGE_GFXACTIVITY:
@@ -345,7 +345,7 @@ static int vangogh_get_smu_metrics_data(struct smu_context
*smu,
}
switch (member) {
- case METRICS_AVERAGE_GFXCLK:
+ case METRICS_CURR_GFXCLK:
*value = metrics->Current.GfxclkFrequency;
break;
case METRICS_AVERAGE_SOCCLK:
@@ -357,7 +357,7 @@ static int vangogh_get_smu_metrics_data(struct smu_context
*smu,
case METRICS_AVERAGE_DCLK:
*value = metrics->Current.DclkFrequency;
break;
- case METRICS_AVERAGE_UCLK:
+ case METRICS_CURR_UCLK:
*value = metrics->Current.MemclkFrequency;
break;
case METRICS_AVERAGE_GFXACTIVITY:
@@ -1529,14 +1529,14 @@ static int vangogh_read_sensor(struct smu_context *smu,
break;
case AMDGPU_PP_SENSOR_GFX_MCLK:
ret = vangogh_common_get_smu_metrics_data(smu,
- METRICS_AVERAGE_UCLK,
+ METRICS_CURR_UCLK,
(uint32_t *)data);
*(uint32_t *)data *= 100;
*size = 4;
break;
case AMDGPU_PP_SENSOR_GFX_SCLK:
ret = vangogh_common_get_smu_metrics_data(smu,
- METRICS_AVERAGE_GFXCLK,
+ METRICS_CURR_GFXCLK,
(uint32_t *)data);
*(uint32_t *)data *= 100;
*size = 4;
--
2.25.1
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[PATCH] drm/amd/pm: remove the "set" function of pp_dpm_mclk for vangogh
This patch is to remove the "set" function of pp_dpm_mclk for vangogh.
For vangogh, mclk bonds with fclk, they will lock each other
on the same perfomance level. But according to the smu message from pmfw,
only fclk is allowed to set value manually, so remove the unnecessary
code of "set" function for mclk.
Signed-off-by: Xiaojian Du
---
drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index 61ff9a663b21..35904315c1f9 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -1092,7 +1092,6 @@ static int vangogh_set_soft_freq_limited_range(struct
smu_context *smu,
return ret;
break;
case SMU_FCLK:
- case SMU_MCLK:
ret = smu_cmn_send_smc_msg_with_param(smu,
SMU_MSG_SetHardMinFclkByFreq,
min, NULL);
@@ -1180,7 +1179,6 @@ static int vangogh_force_clk_levels(struct smu_context
*smu,
if (ret)
return ret;
break;
- case SMU_MCLK:
case SMU_FCLK:
ret = vangogh_get_dpm_clk_limited(smu,
clk_type,
soft_min_level, _freq);
@@ -1267,7 +1265,6 @@ static int vangogh_force_dpm_limit_value(struct
smu_context *smu, bool highest)
SMU_SOCCLK,
SMU_VCLK,
SMU_DCLK,
- SMU_MCLK,
SMU_FCLK,
};
@@ -1296,7 +1293,6 @@ static int vangogh_unforce_dpm_levels(struct smu_context
*smu)
enum smu_clk_type clk_type;
uint32_tfeature;
} clk_feature_map[] = {
- {SMU_MCLK, SMU_FEATURE_DPM_FCLK_BIT},
{SMU_FCLK, SMU_FEATURE_DPM_FCLK_BIT},
{SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT},
{SMU_VCLK, SMU_FEATURE_VCN_DPM_BIT},
@@ -1428,7 +1424,6 @@ static int vangogh_set_performance_level(struct
smu_context *smu,
if (ret)
return ret;
- vangogh_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask);
vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask);
vangogh_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask);
vangogh_force_clk_levels(smu, SMU_VCLK, 1 << vclk_mask);
@@ -1468,7 +1463,6 @@ static int vangogh_set_performance_level(struct
smu_context *smu,
if (ret)
return ret;
- vangogh_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask);
vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask);
break;
case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
--
2.25.1
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[PATCH] drm/amd/pm: add the callback to get vbios bootup values for vangogh
This patch is to add the callback to get vbios bootup values for
vangogh, it will get the bootup values of gfxclk, mclk, socclk and so
on.
Signed-off-by: Xiaojian Du
---
drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 1 +
drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
index 0d137af1a78a..6274cae4a065 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
@@ -561,6 +561,7 @@ int smu_v11_0_get_vbios_bootup_values(struct smu_context
*smu)
smu->smu_table.boot_values.firmware_caps =
v_3_1->firmware_capability;
break;
case 3:
+ case 4:
default:
v_3_3 = (struct atom_firmware_info_v3_3 *)header;
smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index 5aea67637bd8..7bcd35840bf2 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -1894,6 +1894,7 @@ static const struct pptable_funcs vangogh_ppt_funcs = {
.get_ppt_limit = vangogh_get_ppt_limit,
.get_power_limit = vangogh_get_power_limit,
.set_power_limit = vangogh_set_power_limit,
+ .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
};
void vangogh_set_ppt_funcs(struct smu_context *smu)
--
2.25.1
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[PATCH] drm/amdgpu: enable mode-2 gpu reset for vangogh
From: Xiaojian Du
From: Xiaojian Du
This patch is to enable mdoe-2 gpu reset for vangogh.
Signed-off-by: Xiaojian Du
---
drivers/gpu/drm/amd/amdgpu/nv.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 5846eac292c3..a31ef68ee2ab 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -561,10 +561,6 @@ static int nv_asic_reset(struct amdgpu_device *adev)
int ret = 0;
struct smu_context *smu = >smu;
- /* skip reset on vangogh for now */
- if (adev->asic_type == CHIP_VANGOGH)
- return 0;
-
switch (nv_asic_reset_method(adev)) {
case AMD_RESET_METHOD_PCI:
dev_info(adev->dev, "PCI reset\n");
--
2.17.1
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[PATCH] drm/amd/pm: correct the name of one function for vangogh
This patch is to correct the name of one function for vangogh.
This function is used to print the clock levels of all kinds of IP
components.
Signed-off-by: Xiaojian Du
---
drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index 3f815430e67f..2bc55de1812c 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -442,7 +442,7 @@ static int vangogh_get_dpm_clk_limited(struct smu_context
*smu, enum smu_clk_typ
return 0;
}
-static int vangogh_print_fine_grain_clk(struct smu_context *smu,
+static int vangogh_print_clk_levels(struct smu_context *smu,
enum smu_clk_type clk_type, char *buf)
{
DpmClocks_t *clk_table = smu->smu_table.clocks_table;
@@ -1869,7 +1869,7 @@ static const struct pptable_funcs vangogh_ppt_funcs = {
.interrupt_work = smu_v11_0_interrupt_work,
.get_gpu_metrics = vangogh_get_gpu_metrics,
.od_edit_dpm_table = vangogh_od_edit_dpm_table,
- .print_clk_levels = vangogh_print_fine_grain_clk,
+ .print_clk_levels = vangogh_print_clk_levels,
.set_default_dpm_table = vangogh_set_default_dpm_tables,
.set_fine_grain_gfx_freq_parameters =
vangogh_set_fine_grain_gfx_freq_parameters,
.system_features_control = vangogh_system_features_control,
--
2.25.1
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[PATCH] drm/amd/pm: remove some useless code for vangogh
This patch is to remove some useless code for vangogh.
In the earlier code, vangogh can't finish all the sequence of
smu late init. But now vangogh has one stable work state,so
remove the useless code.
Signed-off-by: Xiaojian Du
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index f958b02f9317..30e2a0ac3279 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -612,9 +612,6 @@ static int smu_late_init(void *handle)
return ret;
}
- if (adev->asic_type == CHIP_VANGOGH)
- return 0;
-
ret = smu_set_default_od_settings(smu);
if (ret) {
dev_err(adev->dev, "Failed to setup default OD settings!\n");
--
2.17.1
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[PATCH] drm/amd/pm: fill in the data member of v2 gpu metrics table for vangogh
This patch is to fill in the data member of v2 gpu metrics table for vangogh. Signed-off-by: Xiaojian Du --- drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c index 6d3c556dbe6b..4726cac8d824 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c @@ -1422,14 +1422,17 @@ static ssize_t vangogh_get_gpu_metrics(struct smu_context *smu, gpu_metrics->average_socket_power = metrics.CurrentSocketPower; gpu_metrics->average_cpu_power = metrics.Power[0]; gpu_metrics->average_soc_power = metrics.Power[1]; + gpu_metrics->average_gfx_power = metrics.Power[2]; memcpy(_metrics->average_core_power[0], [0], sizeof(uint16_t) * 8); gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency; gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency; + gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency; gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency; gpu_metrics->average_vclk_frequency = metrics.VclkFrequency; + gpu_metrics->average_dclk_frequency = metrics.DclkFrequency; memcpy(_metrics->current_coreclk[0], [0], -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amd/pm: make the error log more clear for fine grain tuning function
From: Xiaojian Du
From: Xiaojian Du
This patch is to make the error log more clear for fine grian tuning
function, it covers Raven/Raven2/Picasso/Renoir/Vangogh.
The fine grain tuning function uses the sysfs file -- pp_od_clk_voltage,
but only when another sysfs file -- power_dpm_force_performance_level is
switched to "manual" mode, it is allowd to access "pp_od_clk_voltage".
Signed-off-by: Xiaojian Du
---
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c | 2 +-
drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 3 ++-
drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 3 ++-
3 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
index 88322781e447..ed05a30d1139 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
@@ -1487,7 +1487,7 @@ static int smu10_set_fine_grain_clk_vol(struct pp_hwmgr
*hwmgr,
}
if (!smu10_data->fine_grain_enabled) {
- pr_err("Fine grain not started\n");
+ pr_err("pp_od_clk_voltage is not accessible if
power_dpm_force_perfomance_level is not in manual mode!\n");
return -EINVAL;
}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index 6d3c556dbe6b..a847fa66797e 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -1452,7 +1452,8 @@ static int vangogh_od_edit_dpm_table(struct smu_context
*smu, enum PP_OD_DPM_TAB
struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
if (!(smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)) {
- dev_warn(smu->adev->dev, "Fine grain is not enabled!\n");
+ dev_warn(smu->adev->dev,
+ "pp_od_clk_voltage is not accessible if
power_dpm_force_perfomance_level is not in manual mode!\n");
return -EINVAL;
}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
index ab15570305f7..4ce8fb1d5ce9 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
@@ -350,7 +350,8 @@ static int renoir_od_edit_dpm_table(struct smu_context *smu,
struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
if (!(smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)) {
- dev_warn(smu->adev->dev, "Fine grain is not enabled!\n");
+ dev_warn(smu->adev->dev,
+ "pp_od_clk_voltage is not accessible if
power_dpm_force_perfomance_level is not in manual mode!\n");
return -EINVAL;
}
--
2.17.1
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[PATCH 2/2] drm/amd/pm: modify the fine grain tuning function for vangogh
This patch is to modify the fine grain tuning function for vangogh.
It is risky to add two new flags to common smu struct.
So this patch uses the existing old flag to make the two sysfs files
work separately -- "power_dpm_force_performance_level" and
"pp_od_clk_voltage".
Only the power_dpm_force_performance_level is switched to "manual"
mode, the fine grain tuning function will be started.
In other mode, including "high","low","min_sclk","min_mclk",
"standard" and "peak", the fine grain tuning function will be shut down,
and the frequency range of gfx and cpu clock will be restored the
default values.
Signed-off-by: Xiaojian Du
---
drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 3 --
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 2 -
.../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 52 +--
3 files changed, 48 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
index 277559e80961..25ee9f51813b 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
@@ -466,9 +466,6 @@ struct smu_context
uint32_t gfx_actual_hard_min_freq;
uint32_t gfx_actual_soft_max_freq;
- bool fine_grain_enabled;
- bool fine_grain_started;
-
uint32_t cpu_default_soft_min_freq;
uint32_t cpu_default_soft_max_freq;
uint32_t cpu_actual_soft_min_freq;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 976a9105aecc..7fe61ad3ed10 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -419,8 +419,6 @@ static int smu_set_funcs(struct amdgpu_device *adev)
break;
case CHIP_VANGOGH:
vangogh_set_ppt_funcs(smu);
- /* enable the OD by default to allow the fine grain tuning
function */
- smu->od_enabled = true;
break;
default:
return -EINVAL;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index b49044825680..3e32b223d47b 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -438,6 +438,7 @@ static int vangogh_print_fine_grain_clk(struct smu_context
*smu,
{
DpmClocks_t *clk_table = smu->smu_table.clocks_table;
SmuMetrics_t metrics;
+ struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
int i, size = 0, ret = 0;
uint32_t cur_value = 0, value = 0, count = 0;
bool cur_value_match_level = false;
@@ -450,7 +451,7 @@ static int vangogh_print_fine_grain_clk(struct smu_context
*smu,
switch (clk_type) {
case SMU_OD_SCLK:
- if (smu->od_enabled) {
+ if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
size = sprintf(buf, "%s:\n", "OD_SCLK");
size += sprintf(buf + size, "0: %10uMhz\n",
(smu->gfx_actual_hard_min_freq > 0) ?
smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
@@ -459,7 +460,7 @@ static int vangogh_print_fine_grain_clk(struct smu_context
*smu,
}
break;
case SMU_OD_CCLK:
- if (smu->od_enabled) {
+ if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
size = sprintf(buf, "CCLK_RANGE in Core%d:\n",
smu->cpu_core_id_select);
size += sprintf(buf + size, "0: %10uMhz\n",
(smu->cpu_actual_soft_min_freq > 0) ?
smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq);
@@ -468,7 +469,7 @@ static int vangogh_print_fine_grain_clk(struct smu_context
*smu,
}
break;
case SMU_OD_RANGE:
- if (smu->od_enabled) {
+ if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
size = sprintf(buf, "%s:\n", "OD_RANGE");
size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
smu->gfx_default_hard_min_freq,
smu->gfx_default_soft_max_freq);
@@ -1127,15 +1128,39 @@ static int vangogh_set_performance_level(struct
smu_context *smu,
switch (level) {
case AMD_DPM_FORCED_LEVEL_HIGH:
+ smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
+ smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
+
+ smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
+ smu->cpu_actual_soft_max_freq = smu-
[PATCH 1/2] drm/amd/pm: modify the fine grain tuning function for Renoir
This patch is to modify the fine grain tuning function for Renoir.
The fine grain tuning function uses the sysfs node -- pp_od_clk_voltage
to config gfxclk. Meanwhile, another sysfs
node -- power_dpm_force_perfomance_level also affects the gfx clk.
It will cause confusion when these two sysfs nodes works
together.
This patch uses the existing flag to make these two sysfs nodes works
separately. Only when power_dpm_force_perfomance_level is changed
to "manual" mode, the fine grain function will be started.
In other profile modes, including "auto", "high", "low", "profile_peak",
"profile_standard", "profile_min_sclk", "profile_min_mclk",
the fine grain tuning function will be shut down and the frequency range
of gfx will be restored the default value.
Signed-off-by: Xiaojian Du
---
drivers/gpu/drm/amd/pm/amdgpu_pm.c| 2 +-
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 4
.../gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 20 +--
3 files changed, 6 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index ecd72d896b49..80d6298912aa 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -2221,7 +2221,7 @@ static int default_attr_update(struct amdgpu_device
*adev, struct amdgpu_device_
} else if (DEVICE_ATTR_IS(pp_od_clk_voltage)) {
*states = ATTR_STATE_UNSUPPORTED;
if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
- (is_support_sw_smu(adev) && adev->smu.fine_grain_enabled) ||
+ (is_support_sw_smu(adev) && adev->smu.is_apu) ||
(!is_support_sw_smu(adev) && hwmgr->od_enabled))
*states = ATTR_STATE_SUPPORTED;
} else if (DEVICE_ATTR_IS(mem_busy_percent)) {
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index e94d1b4551b4..976a9105aecc 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -416,10 +416,6 @@ static int smu_set_funcs(struct amdgpu_device *adev)
break;
case CHIP_RENOIR:
renoir_set_ppt_funcs(smu);
- /* enable the fine grain tuning function by default */
- smu->fine_grain_enabled = true;
- /* close the fine grain tuning function by default */
- smu->fine_grain_started = false;
break;
case CHIP_VANGOGH:
vangogh_set_ppt_funcs(smu);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
index f33f5141cbe1..6c8a8ccd2f84 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
@@ -349,17 +349,13 @@ static int renoir_od_edit_dpm_table(struct smu_context
*smu,
long input[], uint32_t
size)
{
int ret = 0;
+ struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
- if (!smu->fine_grain_enabled) {
+ if (!(smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)) {
dev_warn(smu->adev->dev, "Fine grain is not enabled!\n");
return -EINVAL;
}
- if (!smu->fine_grain_started) {
- dev_warn(smu->adev->dev, "Fine grain is enabled but not
started!\n");
- return -EINVAL;
- }
-
switch (type) {
case PP_OD_EDIT_SCLK_VDDC_TABLE:
if (size != 2) {
@@ -482,6 +478,7 @@ static int renoir_print_clk_levels(struct smu_context *smu,
int i, size = 0, ret = 0;
uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0;
SmuMetrics_t metrics;
+ struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
bool cur_value_match_level = false;
memset(, 0, sizeof(metrics));
@@ -492,7 +489,7 @@ static int renoir_print_clk_levels(struct smu_context *smu,
switch (clk_type) {
case SMU_OD_RANGE:
- if (smu->fine_grain_enabled) {
+ if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
ret = smu_cmn_send_smc_msg_with_param(smu,
SMU_MSG_GetMinGfxclkFrequency,
0, );
@@ -507,7 +504,7 @@ static int renoir_print_clk_levels(struct smu_context *smu,
}
break;
case SMU_OD_SCLK:
- if (smu->fine_grain_enabled) {
+ if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
min = (smu->gfx_actual_hard_min_freq > 0) ?
smu->gfx_actual_har
[PATCH] drm/amd/pm: add the workload map for vangogh
From: Xiaojian Du From: Xiaojian Du This patch is to add the workload map for vangogh. Signed-off-by: Xiaojian Du --- drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c index 8737562f990f..7f78a9378f07 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c @@ -1653,5 +1653,6 @@ void vangogh_set_ppt_funcs(struct smu_context *smu) smu->message_map = vangogh_message_map; smu->feature_map = vangogh_feature_mask_map; smu->table_map = vangogh_table_map; + smu->workload_map = vangogh_workload_map; smu->is_apu = true; } -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 2/2] drm/amd/pm: fix one superfluous error for renoir
From: Xiaojian Du From: Xiaojian Du This patch is to fix one superfluous error for renoir. Renoir supports 5 kinds of power profile mode: "FULL SCREEN 3D", "VIDEO", "VR", "COMPUTE" and "CUSTOM". After loading amdgpu driver, the driver will set "BOOTUP_DEFAULT" mode to APU, and it will get one superfluouserror error, which is saying "Unsupported power profile mode 0 on RENOIR", but it will not make any other harmful events, so fix this error. Signed-off-by: Xiaojian Du --- drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c index 1f6a774278b1..f33f5141cbe1 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c @@ -835,6 +835,10 @@ static int renoir_set_power_profile_mode(struct smu_context *smu, long *input, u return -EINVAL; } + if (profile_mode == PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT || + profile_mode == PP_SMC_POWER_PROFILE_POWERSAVING) + return 0; + /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ workload_type = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_WORKLOAD, -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 1/2] drm/amd/pm: support the function to change power profile mode for vangogh
From: Xiaojian Du
From: Xiaojian Du
This patch is to support the function to change power profile mode for
vangogh. Vangogh supports 5 kinds of power profile mode:
"FULL SCREEN 3D", "VIDEO", "VR", "COMPUTE" and "CUSTOM".
Signed-off-by: Xiaojian Du
---
drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index a38433ed3a72..a092b71ff1ec 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -178,6 +178,14 @@ static struct cmn2asic_mapping
vangogh_table_map[SMU_TABLE_COUNT] = {
TAB_MAP_VALID(DPMCLOCKS),
};
+static struct cmn2asic_mapping
vangogh_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
+ WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,
WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
+ WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,
WORKLOAD_PPLIB_VIDEO_BIT),
+ WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,
WORKLOAD_PPLIB_VR_BIT),
+ WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,
WORKLOAD_PPLIB_COMPUTE_BIT),
+ WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,
WORKLOAD_PPLIB_CUSTOM_BIT),
+};
+
static int vangogh_tables_init(struct smu_context *smu)
{
struct smu_table_context *smu_table = >smu_table;
@@ -725,7 +733,8 @@ static int vangogh_get_power_profile_mode(struct
smu_context *smu,
{
static const char *profile_name[] = {
"BOOTUP_DEFAULT",
- "FULL_SCREEN_3D",
+ "3D_FULL_SCREEN",
+ "POWER_SAVING",
"VIDEO",
"VR",
"COMPUTE",
@@ -765,6 +774,10 @@ static int vangogh_set_power_profile_mode(struct
smu_context *smu, long *input,
return -EINVAL;
}
+ if (profile_mode == PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT ||
+ profile_mode == PP_SMC_POWER_PROFILE_POWERSAVING)
+ return 0;
+
/* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
workload_type = smu_cmn_to_asic_specific_index(smu,
CMN2ASIC_MAPPING_WORKLOAD,
--
2.17.1
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[PATCH] drm/amd/pm: correct the sensor value of power for vangogh
This patch is to correct the sensor value of power for vangogh. Signed-off-by: Xiaojian Du --- drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c index 9bccf2ad038c..a33c1e07c5df 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c @@ -252,7 +252,8 @@ static int vangogh_get_smu_metrics_data(struct smu_context *smu, *value = metrics->UvdActivity; break; case METRICS_AVERAGE_SOCKETPOWER: - *value = metrics->CurrentSocketPower; + *value = (metrics->CurrentSocketPower << 8) / + 1000 ; break; case METRICS_TEMPERATURE_EDGE: *value = metrics->GfxTemperature / 100 * -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 2/2] drm/amd/pm: enable the fine grain tuning function for vangogh
This patch is to enale the fine grain tuning function for vangogh. Signed-off-by: Xiaojian Du --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 7b698c5ddad0..1904df5a3e20 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -405,6 +405,8 @@ static int smu_set_funcs(struct amdgpu_device *adev) break; case CHIP_VANGOGH: vangogh_set_ppt_funcs(smu); + /* enable the OD by default to allow the fine grain tuning function */ + smu->od_enabled = true; break; default: return -EINVAL; @@ -474,6 +476,8 @@ static int smu_late_init(void *handle) struct smu_context *smu = >smu; int ret = 0; + smu_set_fine_grain_gfx_freq_parameters(smu); + if (adev->asic_type == CHIP_VANGOGH) return 0; -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 1/2] drm/amd/pm: add the fine grain tuning function for vangogh
This patch is to add the fine grain tuning function for vangogh.
This function uses the pp_od_clk_voltage sysfs file to configure the min
and max value of gfx clock frequency or restore the default value.
Command guide:
echo "s level value" > pp_od_clk_voltage
"s" - set the sclk frequency
"level" - 0 or 1, "0" represents the min value, "1" represents
the max value
"value" - the target value of sclk frequency, it should be
limited in the
safe range.
echo "r" > pp_od_clk_voltage
"r" - reset the sclk frequency, restore the default value
echo "c" > pp_od_clk_voltage
"c" - commit the min and max value of sclk frequency to the system.
only after the commit command, the target values will take
effect.
Example:
1)check the default sclk frequency
$ cat pp_od_clk_voltage
OD_SCLK:
0:200Mhz
1: 1400Mhz
OD_RANGE:
SCLK: 200MHz 1400MHz
2)use "s" -- set command to configure the min or max sclk frequency
$ echo "s 0 600" > pp_od_clk_voltage
$ echo "s 1 1000" > pp_od_clk_voltage
$ echo "c" > pp_od_clk_voltage
$ cat pp_od_clk_voltage
OD_SCLK:
0:600Mhz
1: 1000Mhz
OD_RANGE:
SCLK: 200MHz 1400MHz
3)use "r" -- reset command to restore the min and max sclk frequency
$ echo "r" > pp_od_clk_voltage
& echo "c" > pp_od_clk_voltage
$ cat pp_od_clk_voltage
OD_SCLK:
0:200Mhz
1: 1400Mhz
OD_RANGE:
SCLK: 200MHz 1400MHz
Signed-off-by: Xiaojian Du
---
drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 6 +
.../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c| 2 +
.../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 135 ++
drivers/gpu/drm/amd/pm/swsmu/smu_internal.h | 1 +
4 files changed, 144 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
index ae8ff7b07932..7550757cc059 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
@@ -459,6 +459,11 @@ struct smu_context
unsigned fan_max_rpm;
unsigned manual_fan_speed_rpm;
+
+ uint32_t gfx_default_hard_min_freq;
+ uint32_t gfx_default_soft_max_freq;
+ uint32_t gfx_actual_hard_min_freq;
+ uint32_t gfx_actual_soft_max_freq;
};
struct i2c_adapter;
@@ -577,6 +582,7 @@ struct pptable_funcs {
void (*interrupt_work)(struct smu_context *smu);
int (*gpo_control)(struct smu_context *smu, bool enablement);
int (*gfx_state_change_set)(struct smu_context *smu, uint32_t state);
+ int (*set_fine_grain_gfx_freq_parameters)(struct smu_context *smu);
};
typedef enum {
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
index b880c72c322c..b23311096467 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
@@ -438,11 +438,13 @@ int smu_v11_0_fini_smc_tables(struct smu_context *smu)
kfree(smu_table->overdrive_table);
kfree(smu_table->max_sustainable_clocks);
kfree(smu_table->driver_pptable);
+ kfree(smu_table->clocks_table);
smu_table->gpu_metrics_table = NULL;
smu_table->boot_overdrive_table = NULL;
smu_table->overdrive_table = NULL;
smu_table->max_sustainable_clocks = NULL;
smu_table->driver_pptable = NULL;
+ smu_table->clocks_table = NULL;
kfree(smu_table->hardcode_pptable);
smu_table->hardcode_pptable = NULL;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index cbcbcd8514f0..299ad695f607 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -200,8 +200,14 @@ static int vangogh_tables_init(struct smu_context *smu)
if (!smu_table->watermarks_table)
goto err2_out;
+ smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL);
+ if (!smu_table->clocks_table)
+ goto err3_out;
+
return 0;
+err3_out:
+ kfree(smu_table->clocks_table);
err2_out:
kfree(smu_table->gpu_metrics_table);
err1_out:
@@ -477,6 +483,35 @@ static int vangogh_get_current_clk_freq_by_table(struct
smu_context *smu,
value);
}
+static int vangogh_print_fine_grain_clk(struct smu_context *smu,
+ enum smu_clk_type clk_type, char *buf)
+{
+ int size = 0;
+
+ switch (clk_type) {
+
[PATCH 2/2] drm/amd/pm: update the swSMU headers for vangogh
This patch is to update the swSMU headers for vangogh.
Signed-off-by: Xiaojian Du
Reviewed-by: Huang Rui
Reviewed-by: Evan Quan
---
drivers/gpu/drm/amd/pm/inc/smu11_driver_if_vangogh.h | 6 ++
drivers/gpu/drm/amd/pm/inc/smu_v11_5_pmfw.h | 11 +++
drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h | 11 +--
3 files changed, 22 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_vangogh.h
b/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_vangogh.h
index 8f438c80132e..1c19eae93ff1 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_vangogh.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_vangogh.h
@@ -142,6 +142,12 @@ typedef struct {
uint8_t NumDfPstatesEnabled;
uint8_t NumDpmLevelsEnabled;
+ uint8_t NumDcfclkLevelsEnabled;
+ uint8_t NumDispClkLevelsEnabled; //applies to both dispclk and dppclk
+ uint8_t NumSocClkLevelsEnabled;
+
+ uint8_t IspClkLevelsEnabled; //applies to both ispiclk and ispxclk
+ uint8_t VcnClkLevelsEnabled; //applies to both vclk/dclk
uint8_t spare[2];
} DpmClocks_t;
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_5_pmfw.h
b/drivers/gpu/drm/amd/pm/inc/smu_v11_5_pmfw.h
index 99a406984135..22edd88b8117 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v11_5_pmfw.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_5_pmfw.h
@@ -90,14 +90,16 @@
#define FEATURE_ATHUB_PG_BIT 56
#define FEATURE_ECO_DEEPCSTATE_BIT57
#define FEATURE_CC6_BIT 58
-#define NUM_FEATURES 59
+#define FEATURE_GFX_EDC_BIT 59
+#define NUM_FEATURES 60
typedef struct {
// MP1_EXT_SCRATCH0
uint32_t DpmHandlerID : 8;
uint32_t ActivityMonitorID: 8;
uint32_t DpmTimerID : 8;
- uint32_t spare0 : 8;
+ uint32_t DpmHubID : 4;
+ uint32_t DpmHubTask : 4;
// MP1_EXT_SCRATCH1
uint32_t GfxStatus: 2;
uint32_t GfxoffStatus : 8;
@@ -109,9 +111,10 @@ typedef struct {
uint32_t spare1 : 16;
// MP1_EXT_SCRATCH2
uint32_t P2JobHandler: 32;
- // MP1_EXT_SCRATCH3
-// uint32_t spare2 : 32;
+ // MP1_EXT_SCRATCH3: used for postcodes
+
// MP1_EXT_SCRATCH4:6 are used by Kernel
+ // MP1_EXT_SCRATCH7: used by HW
} FwStatus_t;
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h
b/drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h
index 1ada0eb64663..7e69b3bd311b 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h
@@ -97,9 +97,16 @@
#define PPSMC_MSG_StopDramLogging 0x3F
#define PPSMC_MSG_SetSoftMinCclk 0x40
#define PPSMC_MSG_SetSoftMaxCclk 0x41
-#define PPSMC_Message_Count0x42
+#define PPSMC_MSG_SetDfPstateActiveLevel 0x42
+#define PPSMC_MSG_SetDfPstateSoftMinLevel 0x43
+#define PPSMC_MSG_SetCclkPolicy0x44
+#define PPSMC_MSG_DramLogSetDramAddrHigh 0x45
+#define PPSMC_MSG_DramLogSetDramBufferSize 0x46
+#define PPSMC_MSG_RequestActiveWgp 0x47
+#define PPSMC_MSG_QueryActiveWgp 0x48
+#define PPSMC_Message_Count0x49
-//Argument for PPSMC_MSG_GpuChangeState
+//Argument for PPSMC_MSG_GfxDeviceDriverReset
enum {
MODE1_RESET = 1,
MODE2_RESET = 2
--
2.17.1
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[PATCH 1/2] drm/amd/pm: add the interface to dump smu metrics table for vangogh
This patch is to add the interface to dump smu metrics table for vangogh.
Signed-off-by: Xiaojian Du
Reviewed-by: Huang Rui
Reviewed-by: Evan Quan
---
drivers/gpu/drm/amd/pm/inc/smu_v11_0.h| 2 +
.../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c| 12 +
.../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 52 +++
3 files changed, 66 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
index dc06459af91c..5ad693312187 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
@@ -276,6 +276,8 @@ int smu_v11_0_get_current_pcie_link_speed(struct
smu_context *smu);
void smu_v11_0_init_gpu_metrics_v1_0(struct gpu_metrics_v1_0 *gpu_metrics);
+void smu_v11_0_init_gpu_metrics_v2_0(struct gpu_metrics_v2_0 *gpu_metrics);
+
int smu_v11_0_gfx_ulv_control(struct smu_context *smu,
bool enablement);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
index 6b7d1335b46d..b880c72c322c 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
@@ -1999,6 +1999,18 @@ void smu_v11_0_init_gpu_metrics_v1_0(struct
gpu_metrics_v1_0 *gpu_metrics)
gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
}
+void smu_v11_0_init_gpu_metrics_v2_0(struct gpu_metrics_v2_0 *gpu_metrics)
+{
+ memset(gpu_metrics, 0xFF, sizeof(struct gpu_metrics_v2_0));
+
+ gpu_metrics->common_header.structure_size =
+ sizeof(struct gpu_metrics_v2_0);
+ gpu_metrics->common_header.format_revision = 2;
+ gpu_metrics->common_header.content_revision = 0;
+
+ gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
+}
+
int smu_v11_0_gfx_ulv_control(struct smu_context *smu,
bool enablement)
{
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index 83a1b0a04eb1..cbcbcd8514f0 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -584,6 +584,57 @@ static int vangogh_set_watermarks_table(struct smu_context
*smu,
return 0;
}
+static ssize_t vangogh_get_gpu_metrics(struct smu_context *smu,
+ void **table)
+{
+ struct smu_table_context *smu_table = >smu_table;
+ struct gpu_metrics_v2_0 *gpu_metrics =
+ (struct gpu_metrics_v2_0 *)smu_table->gpu_metrics_table;
+ SmuMetrics_t metrics;
+ int ret = 0;
+
+ ret = smu_cmn_get_metrics_table(smu, , true);
+ if (ret)
+ return ret;
+
+ smu_v11_0_init_gpu_metrics_v2_0(gpu_metrics);
+
+ gpu_metrics->temperature_gfx = metrics.GfxTemperature;
+ gpu_metrics->temperature_soc = metrics.SocTemperature;
+ memcpy(_metrics->temperature_core[0],
+ [0],
+ sizeof(uint16_t) * 8);
+ gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0];
+ gpu_metrics->temperature_l3[1] = metrics.L3Temperature[1];
+
+ gpu_metrics->average_gfx_activity = metrics.GfxActivity;
+ gpu_metrics->average_mm_activity = metrics.UvdActivity;
+
+ gpu_metrics->average_socket_power = metrics.CurrentSocketPower;
+ gpu_metrics->average_cpu_power = metrics.Power[0];
+ gpu_metrics->average_soc_power = metrics.Power[1];
+ memcpy(_metrics->average_core_power[0],
+ [0],
+ sizeof(uint16_t) * 8);
+
+ gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency;
+ gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency;
+ gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency;
+ gpu_metrics->average_vclk_frequency = metrics.VclkFrequency;
+
+ memcpy(_metrics->current_coreclk[0],
+ [0],
+ sizeof(uint16_t) * 8);
+ gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0];
+ gpu_metrics->current_l3clk[1] = metrics.L3Frequency[1];
+
+ gpu_metrics->throttle_status = metrics.ThrottlerStatus;
+
+ *table = (void *)gpu_metrics;
+
+ return sizeof(struct gpu_metrics_v2_0);
+}
+
static const struct pptable_funcs vangogh_ppt_funcs = {
.check_fw_status = smu_v11_0_check_fw_status,
@@ -607,6 +658,7 @@ static const struct pptable_funcs vangogh_ppt_funcs = {
.set_driver_table_location = smu_v11_0_set_driver_table_location,
.disable_all_features_with_exception =
smu_cmn_disable_all_features_with_exception,
.interrupt_work = smu_v11_0_interrupt_work,
+ .get_gpu_metrics = vangogh_get_gpu_metrics,
};
void vangogh_set_ppt_funcs(struct smu_context *smu)
--
2.17.1
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[PATCH] drm/amd/pm: add the reset function of the pp_od_voltage_clk sysfs file for RV/RV2/PCO APU
From: Xiaojian Du
From: Xiaojian Du
This patch is to add the reset function of the pp_od_voltage_clk sysfs
file for Raven/Raven2/Picasso APU.
If the min and max sclk frequence are configured, this function can
be used to restore the default sclk frequence.
Command guide:
echo "r" > pp_od_clk_voltage
r - reset the sclk level
Example:
1) check the default sclk frequence
$ cat pp_od_clk_voltage
OD_SCLK:
0:200Mhz
1: 1400Mhz
OD_RANGE:
SCLK: 200MHz 1400MHz
2) use "s" -- set command to configure the min or max sclk frequence
$ echo "s 0 600" > pp_od_clk_voltage
$ echo "s 1 1000" > pp_od_clk_voltage
$ cat pp_od_clk_voltage
OD_SCLK:
0:600Mhz
1: 1000Mhz
OD_RANGE:
SCLK: 200MHz 1400MHz
3) use "r" -- reset command to restore the default sclk frequence range
$ echo "r" > pp_od_clk_voltage
$ cat pp_od_clk_voltage
OD_SCLK:
0:200Mhz
1: 1400Mhz
OD_RANGE:
SCLK: 200MHz 1400MHz
Signed-off-by: Xiaojian Du
---
.../drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c | 32 ++-
1 file changed, 24 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
index cf60f3992303..bbe7f101acbf 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
@@ -1421,18 +1421,34 @@ static int smu10_set_fine_grain_clk_vol(struct pp_hwmgr
*hwmgr,
return -EINVAL;
}
- if (size != 2) {
- pr_err("Input parameter number not correct\n");
- return -EINVAL;
- }
-
if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) {
- if (input[0] == 0)
+ if (size != 2) {
+ pr_err("Input parameter number not correct\n");
+ return -EINVAL;
+ }
+
+ if (input[0] == 0) {
smu10_set_hard_min_gfxclk_by_freq(hwmgr, input[1]);
- else if (input[0] == 1)
+ } else if (input[0] == 1) {
smu10_set_soft_max_gfxclk_by_freq(hwmgr, input[1]);
- else
+ } else {
return -EINVAL;
+ }
+ } else if (type == PP_OD_RESTORE_DEFAULT_TABLE) {
+ if (size != 0) {
+ pr_err("Input parameter number not correct\n");
+ return -EINVAL;
+ }
+
+ uint32_t min_freq, max_freq = 0;
+
+ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency,
_freq);
+ smu10_set_hard_min_gfxclk_by_freq(hwmgr, min_freq);
+ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency,
_freq);
+ smu10_set_soft_max_gfxclk_by_freq(hwmgr, max_freq);
+
+ } else {
+ return -EINVAL;
}
return 0;
--
2.17.1
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[PATCH 10/10] drm/amd/pm: enable the rest functions of swSMU for vangogh.
This patch is to enable the rest functions of swSMU for vangogh. Signed-off-by: Xiaojian Du Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 1a8a9cf993ce..39990790ed67 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -,9 +,6 @@ static int smu_hw_init(void *handle) smu_set_gfx_cgpg(>smu, true); } - if (adev->asic_type == CHIP_VANGOGH) - return 0; - if (!smu->pm_enabled) return 0; -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 07/10] drm/amd/pm: remove some redundant smu message mapping for vangogh
This patch is to remove some redundant smu message mapping for vangogh.
Signed-off-by: Xiaojian Du
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/inc/smu_types.h | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_types.h
b/drivers/gpu/drm/amd/pm/inc/smu_types.h
index 1e8558da84af..4a6d1381df16 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_types.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_types.h
@@ -302,13 +302,9 @@ enum smu_clk_type {
__SMU_DUMMY_MAP(CCLK_DPM), \
__SMU_DUMMY_MAP(FAN_CONTROLLER), \
__SMU_DUMMY_MAP(VCN_DPM), \
- __SMU_DUMMY_MAP(FCLK_DPM), \
- __SMU_DUMMY_MAP(SOCCLK_DPM), \
- __SMU_DUMMY_MAP(MP0CLK_DPM), \
__SMU_DUMMY_MAP(LCLK_DPM), \
__SMU_DUMMY_MAP(SHUBCLK_DPM),\
__SMU_DUMMY_MAP(DCFCLK_DPM), \
- __SMU_DUMMY_MAP(GFX_DPM), \
__SMU_DUMMY_MAP(DS_DCFCLK), \
__SMU_DUMMY_MAP(S0I2), \
__SMU_DUMMY_MAP(SMU_LOW_POWER), \
--
2.17.1
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[PATCH 08/10] drm/amd/pm: add one new function to get 32 bit feature mask for vangogh
This patch is to add one new function to get 32 bit feature mask for
vangogh.
Signed-off-by: Xiaojian Du
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 55 +++---
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h | 4 ++
2 files changed, 54 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
index 92b2ea4c197b..dc28f22aeb38 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
@@ -346,6 +346,43 @@ int smu_cmn_get_enabled_mask(struct smu_context *smu,
return ret;
}
+int smu_cmn_get_enabled_32_bits_mask(struct smu_context *smu,
+ uint32_t *feature_mask,
+ uint32_t num)
+{
+ uint32_t feature_mask_en_low = 0;
+ uint32_t feature_mask_en_high = 0;
+ struct smu_feature *feature = >smu_feature;
+ int ret = 0;
+
+ if (!feature_mask || num < 2)
+ return -EINVAL;
+
+ if (bitmap_empty(feature->enabled, feature->feature_num)) {
+ ret = smu_cmn_send_smc_msg_with_param(smu,
SMU_MSG_GetEnabledSmuFeatures, 0,
+
_mask_en_low);
+
+ if (ret)
+ return ret;
+
+ ret = smu_cmn_send_smc_msg_with_param(smu,
SMU_MSG_GetEnabledSmuFeatures, 1,
+
_mask_en_high);
+
+ if (ret)
+ return ret;
+
+ feature_mask[0] = feature_mask_en_low;
+ feature_mask[1] = feature_mask_en_high;
+
+ } else {
+ bitmap_copy((unsigned long *)feature_mask, feature->enabled,
+feature->feature_num);
+ }
+
+ return ret;
+
+}
+
int smu_cmn_feature_update_enable_state(struct smu_context *smu,
uint64_t feature_mask,
bool enabled)
@@ -437,11 +474,19 @@ size_t smu_cmn_get_pp_feature_mask(struct smu_context
*smu,
size_t size = 0;
int ret = 0, i;
- ret = smu_cmn_get_enabled_mask(smu,
- feature_mask,
- 2);
- if (ret)
- return 0;
+ if (!smu->is_apu) {
+ ret = smu_cmn_get_enabled_mask(smu,
+ feature_mask,
+ 2);
+ if (ret)
+ return 0;
+ } else {
+ ret = smu_cmn_get_enabled_32_bits_mask(smu,
+ feature_mask,
+ 2);
+ if (ret)
+ return 0;
+ }
size = sprintf(buf + size, "features high: 0x%08x low: 0x%08x\n",
feature_mask[1], feature_mask[0]);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
index ab577be23c15..01e825d83d8d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
@@ -52,6 +52,10 @@ int smu_cmn_get_enabled_mask(struct smu_context *smu,
uint32_t *feature_mask,
uint32_t num);
+int smu_cmn_get_enabled_32_bits_mask(struct smu_context *smu,
+ uint32_t *feature_mask,
+ uint32_t num);
+
int smu_cmn_feature_update_enable_state(struct smu_context *smu,
uint64_t feature_mask,
bool enabled);
--
2.17.1
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[PATCH 06/10] drm/amd/pm: set the initial value of pm info to zero
This patch is to set the initial value of pm info to zero.
The "value64" is ported to the hwmon and debugfs node, it is a uint64 type.
When it is used for NV10/VEGA10/VEGA20, its word size is appropriate,
because NV10/VEGA10/VEGA20 has a 64bit smu feature mask, which is separated to
high 32bit and low 32bit.
But some asic has only 32bit smu feature mask,and this 32bit mask will fill the
low 32bit of "value64".
So if this "value64" is not initialized to zero, the high 32bit will be
filled by a meaningless value, when the whole "value64" is ported to the
"SMC Feature Mask" in the "amdgpu_pm_info" on some specific asic, it
will be a wrong value.
Signed-off-by: Xiaojian Du
Reviewed-by: Huang Rui
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 89632ee88ae2..080af05724ed 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -3464,7 +3464,7 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device
*adev)
{
uint32_t value;
- uint64_t value64;
+ uint64_t value64 = 0;
uint32_t query = 0;
int size;
--
2.17.1
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[PATCH 05/10] drm/amd/pm: update the smu v11.5 driver interface header for vangogh
This patch is to update the smu v11.5 driver interface header for vangogh.
Signed-off-by: Xiaojian Du
Reviewed-by: Huang Rui
Reviewed-by: Alex Deucher
---
.../drm/amd/pm/inc/smu11_driver_if_vangogh.h | 70 +--
drivers/gpu/drm/amd/pm/inc/smu_v11_0.h| 2 +-
2 files changed, 36 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_vangogh.h
b/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_vangogh.h
index 20f8c6f460b8..8f438c80132e 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_vangogh.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_vangogh.h
@@ -100,13 +100,13 @@ typedef struct {
DpmActivityMonitorCoeffExt_t
DpmActivityMonitorCoeff[CUSTOM_DPM_SETTING_COUNT];
} CustomDpmSettings_t;
-#define NUM_DCFCLK_DPM_LEVELS 6
-#define NUM_DISPCLK_DPM_LEVELS 6
-#define NUM_DPPCLK_DPM_LEVELS 6
-#define NUM_SOCCLK_DPM_LEVELS 8
-#define NUM_ISPICLK_DPM_LEVELS 6
-#define NUM_ISPXCLK_DPM_LEVELS 6
-#define NUM_VCN_DPM_LEVELS 8
+#define NUM_DCFCLK_DPM_LEVELS 7
+#define NUM_DISPCLK_DPM_LEVELS 7
+#define NUM_DPPCLK_DPM_LEVELS 7
+#define NUM_SOCCLK_DPM_LEVELS 7
+#define NUM_ISPICLK_DPM_LEVELS 7
+#define NUM_ISPXCLK_DPM_LEVELS 7
+#define NUM_VCN_DPM_LEVELS 5
#define NUM_FCLK_DPM_LEVELS 4
#define NUM_SOC_VOLTAGE_LEVELS 8
@@ -160,30 +160,30 @@ typedef struct {
#define THROTTLER_STATUS_BIT_TDC_CVIP 10
typedef struct {
- uint16_t AverageGfxclkFrequency; //[MHz]
- uint16_t AverageSocclkFrequency; //[MHz]
- uint16_t AverageVclkFrequency; //[MHz]
- uint16_t AverageDclkFrequency; //[MHz]
- uint16_t AverageMemclkFrequency; //[MHz]
+ uint16_t GfxclkFrequency; //[MHz]
+ uint16_t SocclkFrequency; //[MHz]
+ uint16_t VclkFrequency;//[MHz]
+ uint16_t DclkFrequency;//[MHz]
+ uint16_t MemclkFrequency; //[MHz]
uint16_t spare;
- uint16_t AverageGfxActivity; //[centi]
- uint16_t AverageUvdActivity; //[centi]
+ uint16_t GfxActivity; //[centi]
+ uint16_t UvdActivity; //[centi]
- uint16_t Voltage[3]; //[mV] indices: VDDCR_VDD, VDDCR_SOC, VDDCR_GFX
- uint16_t Current[3]; //[mA] indices: VDDCR_VDD, VDDCR_SOC, VDDCR_GFX
- uint16_t Power[3]; //[mW] indices: VDDCR_VDD, VDDCR_SOC, VDDCR_GFX
- uint16_t CurrentSocketPower; //[mW]
+ uint16_t Voltage[3]; //[mV] indices: VDDCR_VDD, VDDCR_SOC,
VDDCR_GFX
+ uint16_t Current[3]; //[mA] indices: VDDCR_VDD, VDDCR_SOC,
VDDCR_GFX
+ uint16_t Power[3]; //[mW] indices: VDDCR_VDD, VDDCR_SOC,
VDDCR_GFX
+ uint16_t CurrentSocketPower; //[mW]
- //3rd party tools in Windows need this info in the case of APUs
- uint16_t CoreFrequency[8]; //[MHz]
- uint16_t CorePower[8]; //[mW]
- uint16_t CoreTemperature[8]; //[centi-Celsius]
- uint16_t L3Frequency[2]; //[MHz]
- uint16_t L3Temperature[2]; //[centi-Celsius]
+ //3rd party tools in Windows need info in the case of APUs
+ uint16_t CoreFrequency[8]; //[MHz]
+ uint16_t CorePower[8]; //[mW]
+ uint16_t CoreTemperature[8]; //[centi-Celsius]
+ uint16_t L3Frequency[2]; //[MHz]
+ uint16_t L3Temperature[2]; //[centi-Celsius]
- uint16_t GfxTemperature; //[centi-Celsius]
- uint16_t SocTemperature; //[centi-Celsius]
+ uint16_t GfxTemperature; //[centi-Celsius]
+ uint16_t SocTemperature; //[centi-Celsius]
uint16_t EdgeTemperature;
uint16_t ThrottlerStatus;
} SmuMetrics_t;
@@ -197,15 +197,15 @@ typedef struct {
#define WORKLOAD_PPLIB_CUSTOM_BIT 5
#define WORKLOAD_PPLIB_COUNT 6
-#define TABLE_BIOS_IF 0// Called by BIOS
-#define TABLE_WATERMARKS 1 // Called by DAL through VBIOS
-#define TABLE_CUSTOM_DPM 2 // Called by Driver
-#define TABLE_SPARE1 3
-#define TABLE_DPMCLOCKS 4// Called by Driver
-#define TABLE_MOMENTARY_PM 5 // Called by Tools
-#define TABLE_MODERN_STDBY 6 // Called by Tools for Modern Standby Log
-#define TABLE_SMU_METRICS 7 // Called by Driver
-#define TABLE_COUNT 8
+#define TABLE_BIOS_IF0 // Called by BIOS
+#define TABLE_WATERMARKS 1 // Called by DAL through VBIOS
+#define TABLE_CUSTOM_DPM 2 // Called by Driver
+#define TABLE_SPARE1 3
+#define TABLE_DPMCLOCKS 4 // Called by Driver
+#define TABLE_SPARE2 5 // Called by Tools
+#define TABLE_MODERN_STDBY 6 // Called by Tools for Modern Standby Log
+#define TABLE_SMU_METRICS7 // Called by Driver
+#define TABLE_COUNT 8
//ISP tile definitions
typedef enum {
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
index b5f0cc7829f0..2efa0dd3719f 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
@@ -32,7 +32,7 @@
#define SMU11_DRIVER_IF_VERSION_NV14 0x36
#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x3A
#define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0x5
-#define SMU11_DRIVER_IF_VERSION_VANGOGH 0x01
+#define SMU11_DRIVER_IF_VERSION_VANGOGH 0x02
[PATCH 03/10] drm/amd/pm: add new smc message mapping for vangogh
This patch is to add new smc message mapping for vangogh. Signed-off-by: Xiaojian Du Reviewed-by: Huang Rui Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/pm/inc/smu_types.h | 24 1 file changed, 24 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/inc/smu_types.h b/drivers/gpu/drm/amd/pm/inc/smu_types.h index c8eee2a427d0..1e8558da84af 100644 --- a/drivers/gpu/drm/amd/pm/inc/smu_types.h +++ b/drivers/gpu/drm/amd/pm/inc/smu_types.h @@ -184,6 +184,30 @@ __SMU_DUMMY_MAP(SetSoftMinSocclkByFreq), \ __SMU_DUMMY_MAP(PowerUpCvip),\ __SMU_DUMMY_MAP(PowerDownCvip), \ + __SMU_DUMMY_MAP(EnableGfxOff), \ + __SMU_DUMMY_MAP(SetSoftMinGfxclk), \ + __SMU_DUMMY_MAP(SetSoftMinFclk), \ + __SMU_DUMMY_MAP(GetThermalLimit),\ + __SMU_DUMMY_MAP(GetCurrentTemperature), \ + __SMU_DUMMY_MAP(GetCurrentPower),\ + __SMU_DUMMY_MAP(GetCurrentVoltage), \ + __SMU_DUMMY_MAP(GetCurrentCurrent), \ + __SMU_DUMMY_MAP(GetAverageCpuActivity), \ + __SMU_DUMMY_MAP(GetAverageGfxActivity), \ + __SMU_DUMMY_MAP(GetAveragePower),\ + __SMU_DUMMY_MAP(GetAverageTemperature), \ + __SMU_DUMMY_MAP(SetAveragePowerTimeConstant),\ + __SMU_DUMMY_MAP(SetAverageActivityTimeConstant), \ + __SMU_DUMMY_MAP(SetAverageTemperatureTimeConstant), \ + __SMU_DUMMY_MAP(SetMitigationEndHysteresis), \ + __SMU_DUMMY_MAP(GetCurrentFreq), \ + __SMU_DUMMY_MAP(SetReducedPptLimit), \ + __SMU_DUMMY_MAP(SetReducedThermalLimit), \ + __SMU_DUMMY_MAP(DramLogSetDramAddr), \ + __SMU_DUMMY_MAP(StartDramLogging), \ + __SMU_DUMMY_MAP(StopDramLogging),\ + __SMU_DUMMY_MAP(SetSoftMinCclk), \ + __SMU_DUMMY_MAP(SetSoftMaxCclk), \ __SMU_DUMMY_MAP(SetGpoFeaturePMask), \ #undef __SMU_DUMMY_MAP -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 01/10] drm/amd/pm: update the smu v11.5 smc header for vangogh
This patch is to update the smu v11.5 smc header for vangogh. Signed-off-by: Xiaojian Du Reviewed-by: Huang Rui Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h | 114 +++ 1 file changed, 68 insertions(+), 46 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h b/drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h index 55c1b151a68d..1ada0eb64663 100644 --- a/drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h +++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h @@ -32,55 +32,77 @@ #define PPSMC_Result_CmdRejectedBusy 0xFC // Message Definitions: -#define PPSMC_MSG_TestMessage 0x1 -#define PPSMC_MSG_GetSmuVersion 0x2 -#define PPSMC_MSG_GetDriverIfVersion 0x3 -#define PPSMC_MSG_EnableGfxOff 0x4 -#define PPSMC_MSG_DisableGfxOff 0x5 -#define PPSMC_MSG_PowerDownIspByTile 0x6 // ISP is power gated by default -#define PPSMC_MSG_PowerUpIspByTile 0x7 -#define PPSMC_MSG_PowerDownVcn 0x8 // VCN is power gated by default -#define PPSMC_MSG_PowerUpVcn 0x9 -#define PPSMC_MSG_spare 0xA -#define PPSMC_MSG_SetHardMinVcn 0xB // For wireless display -#define PPSMC_MSG_SetMinVideoGfxclkFreq0xC //Sets SoftMin for GFXCLK. Arg is in MHz -#define PPSMC_MSG_ActiveProcessNotify 0xD -#define PPSMC_MSG_SetHardMinIspiclkByFreq 0xE -#define PPSMC_MSG_SetHardMinIspxclkByFreq 0xF -#define PPSMC_MSG_SetDriverDramAddrHigh 0x10 -#define PPSMC_MSG_SetDriverDramAddrLow 0x11 -#define PPSMC_MSG_TransferTableSmu2Dram 0x12 -#define PPSMC_MSG_TransferTableDram2Smu 0x13 -#define PPSMC_MSG_GfxDeviceDriverReset 0x14 //mode 2 reset during TDR -#define PPSMC_MSG_GetEnabledSmuFeatures 0x15 -#define PPSMC_MSG_spare1 0x16 -#define PPSMC_MSG_SetHardMinSocclkByFreq 0x17 -#define PPSMC_MSG_SetMinVideoFclkFreq 0x18 -#define PPSMC_MSG_SetSoftMinVcn 0x19 -#define PPSMC_MSG_EnablePostCode 0x1A -#define PPSMC_MSG_GetGfxclkFrequency 0x1B -#define PPSMC_MSG_GetFclkFrequency 0x1C -#define PPSMC_MSG_AllowGfxOff 0x1D -#define PPSMC_MSG_DisallowGfxOff 0x1E -#define PPSMC_MSG_SetSoftMaxGfxClk 0x1F -#define PPSMC_MSG_SetHardMinGfxClk 0x20 -#define PPSMC_MSG_SetSoftMaxSocclkByFreq 0x21 -#define PPSMC_MSG_SetSoftMaxFclkByFreq 0x22 -#define PPSMC_MSG_SetSoftMaxVcn 0x23 -#define PPSMC_MSG_GpuChangeState 0x24 //FIXME AHOLLA - check how to do for VGM -#define PPSMC_MSG_SetPowerLimitPercentage 0x25 -#define PPSMC_MSG_PowerDownJpeg 0x26 -#define PPSMC_MSG_PowerUpJpeg 0x27 -#define PPSMC_MSG_SetHardMinFclkByFreq 0x28 -#define PPSMC_MSG_SetSoftMinSocclkByFreq 0x29 -#define PPSMC_MSG_PowerUpCvip 0x2A -#define PPSMC_MSG_PowerDownCvip 0x2B -#define PPSMC_Message_Count 0x2C +#define PPSMC_MSG_TestMessage 0x1 +#define PPSMC_MSG_GetSmuVersion0x2 +#define PPSMC_MSG_GetDriverIfVersion 0x3 +#define PPSMC_MSG_EnableGfxOff 0x4 +#define PPSMC_MSG_DisableGfxOff0x5 +#define PPSMC_MSG_PowerDownIspByTile 0x6 // ISP is power gated by default +#define PPSMC_MSG_PowerUpIspByTile 0x7 +#define PPSMC_MSG_PowerDownVcn 0x8 // VCN is power gated by default +#define PPSMC_MSG_PowerUpVcn 0x9 +#define PPSMC_MSG_spare0xA +#define PPSMC_MSG_SetHardMinVcn0xB // For wireless display +#define PPSMC_MSG_SetSoftMinGfxclk 0xC //Sets SoftMin for GFXCLK. Arg is in MHz +#define PPSMC_MSG_ActiveProcessNotify 0xD +#define PPSMC_MSG_SetHardMinIspiclkByFreq 0xE +#define PPSMC_MSG_SetHardMinIspxclkByFreq 0xF +#define PPSMC_MSG_SetDriverDramAddrHigh0x10 +#define PPSMC_MSG_SetDriverDramAddrLow 0x11 +#define PPSMC_MSG_TransferTableSmu2Dram0x12 +#define PPSMC_MSG_TransferTableDram2Smu0x13 +#define PPSMC_MSG_GfxDeviceDriverReset 0x14 //mode 2 reset during TDR +#define PPSMC_MSG_GetEnabledSmuFeatures0x15 +#define PPSMC_MSG_spare1 0x16 +#define PPSMC_MSG_SetHardMinSocclkByFreq 0x17 +#define PPSMC_MSG_SetSoftMinFclk 0x18 //Used to be PPSMC_MSG_SetMinVideoFclkFreq +#define PPSMC_MSG_SetSoftMinVcn0x19 +#define PPSMC_MSG_EnablePostCode 0x1A +#define PPSMC_MSG_GetGfxclkFrequency 0x1B +#define PPSMC_MSG_GetFclkFrequency 0x1C +#define PPSMC_MSG_AllowGfxOff 0x1D +#define PPSMC_MSG_DisallowGfxOff 0x1E +#define PPSMC_MSG_SetSoftMaxGfxClk 0x1F +#define PPSMC_MSG_SetHardMinGfxClk 0x20 +#define PPSMC_MSG_SetSoftMaxSocclkByFreq 0x21 +#define PPSMC_MSG_SetSoftMaxFclkByFreq 0x22 +#define PPSMC_MSG_SetSoftMaxVcn0x23 +#define PPSMC_MSG_spare2 0x24
[PATCH 02/10] drm/amd/pm: update the smu v11.5 firmware header for vangogh
This patch is to update the smu v11.5 firmware header for vangogh.
Signed-off-by: Xiaojian Du
Reviewed-by: Huang Rui
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/inc/smu_v11_5_pmfw.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_5_pmfw.h
b/drivers/gpu/drm/amd/pm/inc/smu_v11_5_pmfw.h
index abf13abd3919..99a406984135 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v11_5_pmfw.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_5_pmfw.h
@@ -89,7 +89,7 @@
#define FEATURE_SOC_VOLTAGE_MON_BIT 55
#define FEATURE_ATHUB_PG_BIT 56
#define FEATURE_ECO_DEEPCSTATE_BIT57
-#define FEATURE_CC6 58
+#define FEATURE_CC6_BIT 58
#define NUM_FEATURES 59
typedef struct {
--
2.17.1
___
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 04/10] drm/amd/pm: add UMD Pstate Msg Parameters for vangogh temporarily
This patch is to add UMD Pstate Msg Parameters for vangogh temporarily, the values refer to renoir. Signed-off-by: Xiaojian Du Reviewed-by: Huang Rui Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h index d8696e2274c4..8756766296cd 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h @@ -27,4 +27,9 @@ extern void vangogh_set_ppt_funcs(struct smu_context *smu); +/* UMD PState Vangogh Msg Parameters in MHz */ +#define VANGOGH_UMD_PSTATE_GFXCLK 700 +#define VANGOGH_UMD_PSTATE_SOCCLK 678 +#define VANGOGH_UMD_PSTATE_FCLK 800 + #endif -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 09/10] drm/amd/pm: add some swSMU functions for vangogh.
This patch is to add some swSMU functions for vangogh, to support the
sensor info on "hwmon" and pm info.
Signed-off-by: Xiaojian Du
Reviewed-by: Alex Deucher
---
.../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 411 ++
1 file changed, 338 insertions(+), 73 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index 145712a24b80..83a1b0a04eb1 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -52,53 +52,72 @@
FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \
FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT)| \
FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)| \
- FEATURE_MASK(FEATURE_GFX_DPM_BIT)| \
- FEATURE_MASK(FEATURE_ISP_DPM_BIT)| \
- FEATURE_MASK(FEATURE_A55_DPM_BIT)| \
- FEATURE_MASK(FEATURE_CVIP_DSP_DPM_BIT))
+ FEATURE_MASK(FEATURE_GFX_DPM_BIT))
static struct cmn2asic_msg_mapping vangogh_message_map[SMU_MSG_MAX_COUNT] = {
- MSG_MAP(TestMessage,PPSMC_MSG_TestMessage,
1),
- MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion,
1),
- MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion,
1),
- MSG_MAP(AllowGfxOff,PPSMC_MSG_EnableGfxOff,
1),
- MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisableGfxOff,
1),
- MSG_MAP(PowerDownIspByTile, PPSMC_MSG_PowerDownIspByTile,
1),
- MSG_MAP(PowerUpIspByTile, PPSMC_MSG_PowerUpIspByTile,
1),
- MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn,
1),
- MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn,
1),
- MSG_MAP(Spare, PPSMC_MSG_spare,
1),
- MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn,
1),
- MSG_MAP(SetMinVideoGfxclkFreq,
PPSMC_MSG_SetMinVideoGfxclkFreq,1),
- MSG_MAP(ActiveProcessNotify,PPSMC_MSG_ActiveProcessNotify,
1),
- MSG_MAP(SetHardMinIspiclkByFreq,
PPSMC_MSG_SetHardMinIspiclkByFreq, 1),
- MSG_MAP(SetHardMinIspxclkByFreq,
PPSMC_MSG_SetHardMinIspxclkByFreq, 1),
- MSG_MAP(SetDriverDramAddrHigh,
PPSMC_MSG_SetDriverDramAddrHigh,1),
- MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow,
1),
- MSG_MAP(TransferTableSmu2Dram,
PPSMC_MSG_TransferTableSmu2Dram,1),
- MSG_MAP(TransferTableDram2Smu,
PPSMC_MSG_TransferTableDram2Smu,1),
- MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset,
1),
- MSG_MAP(GetEnabledSmuFeatures,
PPSMC_MSG_GetEnabledSmuFeatures,1),
- MSG_MAP(Spare1, PPSMC_MSG_spare1,
1),
- MSG_MAP(SetHardMinSocclkByFreq,
PPSMC_MSG_SetHardMinSocclkByFreq, 1),
- MSG_MAP(SetMinVideoFclkFreq,PPSMC_MSG_SetMinVideoFclkFreq,
1),
- MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn,
1),
- MSG_MAP(EnablePostCode, PPSMC_MSG_EnablePostCode,
1),
- MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency,
1),
- MSG_MAP(GetFclkFrequency, PPSMC_MSG_GetFclkFrequency,
1),
- MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk,
1),
- MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk,
1),
- MSG_MAP(SetSoftMaxSocclkByFreq,
PPSMC_MSG_SetSoftMaxSocclkByFreq, 1),
- MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq,
1),
- MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn,
1),
- MSG_MAP(GpuChangeState, PPSMC_MSG_GpuChangeState,
1),
- MSG_MAP(SetPowerLimitPercentage,
PPSMC_MSG_SetPowerLimitPercentage, 1),
- MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg,
1),
- MSG_MAP(PowerUpJpeg,PPSMC_MSG_PowerUpJpeg,
1),
- MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq,
1),
- MSG_MAP(SetSoftMinSocclkByFreq,
PPSMC_MSG_SetSoftMinSocclkByFreq, 1),
- MSG_MAP(PowerUpCvip,PPSMC_MSG_PowerUpCvip,
1),
- MSG_MAP(PowerDownCvip, PPSMC_MSG_PowerDownCvip,
1),
+ MSG_MAP(TestMessage,PPSMC_MSG_TestMessage,
0),
+ MSG_MAP(Get
[PATCH] drm/amd/powerplay: add one sysfs file -- "pp_od_clk_voltage" to support the feature to modify gfx engine clock(Mhz units) on Raven/Raven2/Picasso APU.
From: Xiaojian Du
From: Xiaojian Du
This patch is to add one sysfs file -- "pp_od_clk_voltage" for
Raven/Raven2/Picasso APU, which is only used by dGPU like VEGA10.
This sysfs file supports the feature to modify gfx engine clock(Mhz units), it
can
be used to configure the min value and the max value for gfx clock limited in
the
safe range.
Command guide:
echo "s level clock" > pp_od_clk_voltage
s - adjust teh sclk level
level - 0 or 1, "0" represents the min value, "1" represents the max
value
clock - the clock value(Mhz units), like 400, 800 or 1200, the value
must be within the
OD_RANGE limits.
Example:
$ cat pp_od_clk_voltage
OD_SCLK:
0:200Mhz
1: 1400Mhz
OD_RANGE:
SCLK: 200MHz 1400MHz
$ echo "s 0 600" > pp_od_clk_voltage
$ echo "s 1 1000" > pp_od_clk_voltage
$ cat pp_od_clk_voltage
OD_SCLK:
0:600Mhz
1: 1000Mhz
OD_RANGE:
SCLK: 200MHz 1400MHz
Signed-off-by: Xiaojian Du
---
.../gpu/drm/amd/include/kgd_pp_interface.h| 1 +
drivers/gpu/drm/amd/pm/amdgpu_pm.c| 12 +++
drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h | 4 +
drivers/gpu/drm/amd/pm/inc/hwmgr.h| 5 ++
.../gpu/drm/amd/pm/powerplay/amd_powerplay.c | 17 +++-
.../drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c | 79 +++
6 files changed, 117 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index 0aec28fda058..94132c70d7af 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -281,6 +281,7 @@ struct amd_pm_funcs {
int (*get_power_limit)(void *handle, uint32_t *limit, bool
default_limit);
int (*get_power_profile_mode)(void *handle, char *buf);
int (*set_power_profile_mode)(void *handle, long *input, uint32_t size);
+ int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input,
uint32_t size);
int (*odn_edit_dpm_table)(void *handle, uint32_t type, long *input,
uint32_t size);
int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state);
int (*smu_i2c_bus_access)(void *handle, bool acquire);
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index b5d2f30043ad..fe0de00f56e2 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -827,6 +827,18 @@ static ssize_t amdgpu_set_pp_od_clk_voltage(struct device
*dev,
return -EINVAL;
}
} else {
+
+ if (adev->powerplay.pp_funcs->set_fine_grain_clk_vol) {
+ ret = amdgpu_dpm_set_fine_grain_clk_vol(adev, type,
+ parameter,
+ parameter_size);
+ if (ret) {
+ pm_runtime_mark_last_busy(ddev->dev);
+ pm_runtime_put_autosuspend(ddev->dev);
+ return -EINVAL;
+ }
+ }
+
if (adev->powerplay.pp_funcs->odn_edit_dpm_table) {
ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
parameter, parameter_size);
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
index dff4a5f99bb0..f6e0e7d8a007 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
@@ -349,6 +349,10 @@ enum amdgpu_pcie_gen {
((adev)->powerplay.pp_funcs->set_power_profile_mode(\
(adev)->powerplay.pp_handle, parameter, size))
+#define amdgpu_dpm_set_fine_grain_clk_vol(adev, type, parameter, size) \
+ ((adev)->powerplay.pp_funcs->set_fine_grain_clk_vol(\
+ (adev)->powerplay.pp_handle, type, parameter, size))
+
#define amdgpu_dpm_odn_edit_dpm_table(adev, type, parameter, size) \
((adev)->powerplay.pp_funcs->odn_edit_dpm_table(\
(adev)->powerplay.pp_handle, type, parameter, size))
diff --git a/drivers/gpu/drm/amd/pm/inc/hwmgr.h
b/drivers/gpu/drm/amd/pm/inc/hwmgr.h
index 1b3529efc91e..3898a95ec28b 100644
--- a/drivers/gpu/drm/amd/pm/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/pm/inc/hwmgr.h
@@ -340,6 +340,9 @@ struct pp_hwmgr_func {
int (*odn_edit_dpm_table)(struct pp_hwmgr *hwmgr,
enum PP_OD_DPM_TABLE_COMMAND type,
long *input, uint32_t size);
+ int (*set_fine_grain_clk_vol)(struct pp_hwmgr *hwmgr,
+ enum PP_OD_DPM_TABLE_COMMAND type,
+
