Re: [PATCH UMR] Fix off-by-one error for decoding sdma linear write packet
[AMD Official Use Only - Internal Distribution Only]
Sure Tom, here it is.
BR,
Xiaojie
From: StDenis, Tom
Sent: Tuesday, July 14, 2020 10:11 PM
To: Yuan, Xiaojie; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH UMR] Fix off-by-one error for decoding sdma linear write
packet
[AMD Official Use Only - Internal Distribution Only]
Thanks, can you attach the patch to your email instead though so it applies
cleanly?
Cheers,
Tom
From: Yuan, Xiaojie
Sent: Tuesday, July 14, 2020 00:18
To: amd-gfx@lists.freedesktop.org; StDenis, Tom
Cc: Yuan, Xiaojie
Subject: [PATCH UMR] Fix off-by-one error for decoding sdma linear write packet
COUNT in linear write packet represents dword number - 1
Before fix:
navi10.sdma0.ring[ 0] == 0x0002.w. OPCODE: [WRITE], SUB-OPCODE: [0],
LINEAR_WRITE
navi10.sdma0.ring[ 1] == 0x00400a60... |---+ WORD [1]: DST_ADDR_LO:
0x00400a60
navi10.sdma0.ring[ 2] == 0x... |---+ WORD [2]: DST_ADDR_HI:
0x
navi10.sdma0.ring[ 3] == 0x... |---+ WORD [3]: COUNT: 0x
navi10.sdma0.ring[ 4] == 0xdeadbeef...
After fix:
navi10.sdma0.ring[ 0] == 0x0002.w. OPCODE: [WRITE], SUB-OPCODE: [0],
LINEAR_WRITE
navi10.sdma0.ring[ 1] == 0x00400a60... |---+ WORD [1]: DST_ADDR_LOa:
0x00400a60
navi10.sdma0.ring[ 2] == 0x... |---+ WORD [2]: DST_ADDR_HIb:
0x
navi10.sdma0.ring[ 3] == 0x... |---+ WORD [3]: COUNTc: 0x
navi10.sdma0.ring[ 4] == 0xdeadbeef... \---+ WORD [4]: DATA: 0xdeadbeef
Signed-off-by: Xiaojie Yuan
---
src/lib/ring_decode.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/lib/ring_decode.c b/src/lib/ring_decode.c
index c3b5d18..a74229d 100644
--- a/src/lib/ring_decode.c
+++ b/src/lib/ring_decode.c
@@ -1819,7 +1819,7 @@ static void parse_next_sdma_pkt(struct umr_asic *asic,
struct umr_ring_decoder *
case 2: printf("DST_ADDR_HI:
%s0x%08lx%s", YELLOW, (unsigned long)ib, RST);
break;
case 3: printf("COUNT:
%s0x%08lx%s", BLUE, (unsigned long)ib, RST);
- decoder->sdma.n_words
+= ib - 1;
+ decoder->sdma.n_words
+= ib;
break;
default: printf("DATA:
%s0x%08lx%s", BLUE, (unsigned long)ib, RST);
break;
--
2.20.1
From 269c5dba567553ad88ae96d1d3b098c3c331cf35 Mon Sep 17 00:00:00 2001
From: Xiaojie Yuan
Date: Tue, 14 Jul 2020 12:13:04 +0800
Subject: [PATCH] Fix off-by-one error for decoding sdma linear write packet
COUNT in linear write packet represents dword number - 1
Before fix:
navi10.sdma0.ring[ 0] == 0x0002.w. OPCODE: [WRITE], SUB-OPCODE: [0], LINEAR_WRITE
navi10.sdma0.ring[ 1] == 0x00400a60... |---+ WORD [1]: DST_ADDR_LO: 0x00400a60
navi10.sdma0.ring[ 2] == 0x... |---+ WORD [2]: DST_ADDR_HI: 0x
navi10.sdma0.ring[ 3] == 0x... |---+ WORD [3]: COUNT: 0x
navi10.sdma0.ring[ 4] == 0xdeadbeef...
After fix:
navi10.sdma0.ring[ 0] == 0x0002.w. OPCODE: [WRITE], SUB-OPCODE: [0], LINEAR_WRITE
navi10.sdma0.ring[ 1] == 0x00400a60... |---+ WORD [1]: DST_ADDR_LO: 0x00400a60
navi10.sdma0.ring[ 2] == 0x... |---+ WORD [2]: DST_ADDR_HI: 0x
navi10.sdma0.ring[ 3] == 0x... |---+ WORD [3]: COUNT: 0x
navi10.sdma0.ring[ 4] == 0xdeadbeef... \---+ WORD [4]: DATA: 0xdeadbeef
Signed-off-by: Xiaojie Yuan
---
src/lib/ring_decode.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/lib/ring_decode.c b/src/lib/ring_decode.c
index c3b5d18..a74229d 100644
--- a/src/lib/ring_decode.c
+++ b/src/lib/ring_decode.c
@@ -1819,7 +1819,7 @@ static void parse_next_sdma_pkt(struct umr_asic *asic, struct umr_ring_decoder *
case 2: printf("DST_ADDR_HI: %s0x%08lx%s", YELLOW, (unsigned long)ib, RST);
break;
case 3: printf("COUNT: %s0x%08lx%s", BLUE, (unsigned long)ib, RST);
- decoder->sdma.n_words += ib - 1;
+ decoder->sdma.n_words += ib;
break;
default: printf("DATA: %s0x%08lx%s", BLUE, (unsigned long)ib, RST);
break;
--
2.20.1
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Re: [PATCH] drm/amdgpu/sdma5: fix wptr overwritten in ->get_wptr()
[AMD Official Use Only - Internal Distribution Only]
The logic in sdma2.4, sdma3 and sdma4 look fine.
I sent v2 to add fix for sdma5.2 as well.
BR,
Xiaojie
From: Christian König
Sent: Tuesday, July 14, 2020 4:47 PM
To: Yuan, Xiaojie; amd-gfx@lists.freedesktop.org
Cc: Ma, Le
Subject: Re: [PATCH] drm/amdgpu/sdma5: fix wptr overwritten in ->get_wptr()
Am 14.07.20 um 10:09 schrieb Xiaojie Yuan:
> "u64 *wptr" points to the the wptr value in write back buffer and
> "*wptr = (*wptr) >> 2;" results in the value being overwritten each time
> when ->get_wptr() is called.
>
> umr uses /sys/kernel/debug/dri/0/amdgpu_ring_sdma0 to get rptr/wptr and
> decode ring content and it is affected by this issue.
>
> fix and simplify the logic similar as sdma_v4_0_ring_get_wptr().
>
> Suggested-by: Le Ma
> Signed-off-by: Xiaojie Yuan
Nice, catch. I'm wondering how this code ever came to be.
Patch is Reviewed-by: Christian König
Can you please double check that we don't have that nonsense in
sdma_v4_0 or even older as well?
Thanks,
Christian.
> ---
> drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 26 --
> 1 file changed, 8 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> index abb0ab653b10..e2232dd12d8e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> @@ -315,30 +315,20 @@ static uint64_t sdma_v5_0_ring_get_rptr(struct
> amdgpu_ring *ring)
> static uint64_t sdma_v5_0_ring_get_wptr(struct amdgpu_ring *ring)
> {
> struct amdgpu_device *adev = ring->adev;
> - u64 *wptr = NULL;
> - uint64_t local_wptr = 0;
> + u64 wptr;
>
> if (ring->use_doorbell) {
> /* XXX check if swapping is necessary on BE */
> - wptr = ((u64 *)>wb.wb[ring->wptr_offs]);
> - DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", *wptr);
> - *wptr = (*wptr) >> 2;
> - DRM_DEBUG("wptr/doorbell after shift == 0x%016llx\n", *wptr);
> + wptr = READ_ONCE(*((u64 *)>wb.wb[ring->wptr_offs]));
> + DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
> } else {
> - u32 lowbit, highbit;
> -
> - wptr = _wptr;
> - lowbit = RREG32(sdma_v5_0_get_reg_offset(adev, ring->me,
> mmSDMA0_GFX_RB_WPTR)) >> 2;
> - highbit = RREG32(sdma_v5_0_get_reg_offset(adev, ring->me,
> mmSDMA0_GFX_RB_WPTR_HI)) >> 2;
> -
> - DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n",
> - ring->me, highbit, lowbit);
> - *wptr = highbit;
> - *wptr = (*wptr) << 32;
> - *wptr |= lowbit;
> + wptr = RREG32(sdma_v5_0_get_reg_offset(adev, ring->me,
> mmSDMA0_GFX_RB_WPTR_HI));
> + wptr = wptr << 32;
> + wptr |= RREG32(sdma_v5_0_get_reg_offset(adev, ring->me,
> mmSDMA0_GFX_RB_WPTR));
> + DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n",
> ring->me, wptr);
> }
>
> - return *wptr;
> + return wptr >> 2;
> }
>
> /**
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Re: [PATCH] drm/amdgpu: use ARRAY_SIZE() to add amdgpu debugfs files
[AMD Official Use Only - Internal Distribution Only]
Hi Chris,
This was observed when I was trying to add a new debugfs file. Some similar
occurrences using ARRAY_SIZE() are:
- amdgpu_kms.c :: amdgpu_firmware_info_list
- amdgpu_pm.c :: amdgpu_debugfs_pm_info
- amdgpu_ttm.c :: amdgpu_ttm_debugfs_list
- amdgpu_dm_debugfs.c :: amdgpu_dm_debugfs_list
This patch simply unified the usage of amdgpu_debugfs_add_files().
BTW, do you intended to use:
debugfs_create_file() - need to call debugfs_remove() explicitly
or the drm helper
drm_debugfs_create_files() - debugfs files will be removed automatically
If so, we need a separate patch to cleanup them in a batch.
BR,
Xiaojie
From: Christian König
Sent: Monday, July 13, 2020 4:38 PM
To: Yuan, Xiaojie; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: use ARRAY_SIZE() to add amdgpu debugfs files
Am 13.07.20 um 07:59 schrieb Xiaojie Yuan:
> to easily add new debugfs file w/o changing the hardcoded list count.
In general a good idea, but I would rather like to see
amdgpu_debugfs_add_files() completely removed and debugfs_create_file()
used directly instead.
Christian.
>
> Signed-off-by: Xiaojie Yuan
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 6 --
> drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 3 ++-
> drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c| 3 ++-
> 3 files changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
> index b8ce43c28116..58d4c219178a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
> @@ -781,8 +781,10 @@ int amdgpu_debugfs_fence_init(struct amdgpu_device *adev)
> {
> #if defined(CONFIG_DEBUG_FS)
> if (amdgpu_sriov_vf(adev))
> - return amdgpu_debugfs_add_files(adev,
> amdgpu_debugfs_fence_list_sriov, 1);
> - return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list, 2);
> + return amdgpu_debugfs_add_files(adev,
> amdgpu_debugfs_fence_list_sriov,
> +
> ARRAY_SIZE(amdgpu_debugfs_fence_list_sriov));
> + return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list,
> + ARRAY_SIZE(amdgpu_debugfs_fence_list));
> #else
> return 0;
> #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> index 77d988a0033f..8c64d8d6cb82 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> @@ -928,7 +928,8 @@ static const struct drm_info_list
> amdgpu_debugfs_gem_list[] = {
> int amdgpu_debugfs_gem_init(struct amdgpu_device *adev)
> {
> #if defined(CONFIG_DEBUG_FS)
> - return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 1);
> + return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list,
> + ARRAY_SIZE(amdgpu_debugfs_gem_list));
> #endif
> return 0;
> }
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> index 4ffc32b78745..dcd492170598 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> @@ -468,7 +468,8 @@ static const struct drm_info_list
> amdgpu_debugfs_sa_list[] = {
> int amdgpu_debugfs_sa_init(struct amdgpu_device *adev)
> {
> #if defined(CONFIG_DEBUG_FS)
> - return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_sa_list, 1);
> + return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_sa_list,
> + ARRAY_SIZE(amdgpu_debugfs_sa_list));
> #else
> return 0;
> #endif
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Re: [PATCH] drm/amdgpu: add fbdev suspend/resume on gpu reset
[AMD Official Use Only - Internal Distribution Only] Hi Evan, Does this patch also fix the baco failure on Navi14 with display connected? BR, Xiaojie From: amd-gfx on behalf of Evan Quan Sent: Wednesday, March 11, 2020 4:18 PM To: amd-gfx@lists.freedesktop.org Cc: Quan, Evan Subject: [PATCH] drm/amdgpu: add fbdev suspend/resume on gpu reset This can fix the baco reset failure seen on Navi10. And this should be a low risk fix as the same sequence is already used for system suspend/resume. Change-Id: Idb4d02c5fcbbd5b7817195ee04c7af34c346a053 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 572eb6ea8eab..a35c89973614 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -3935,6 +3935,8 @@ static int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive, if (r) goto out; + amdgpu_fbdev_set_suspend(tmp_adev, 0); + /* must succeed. */ amdgpu_ras_resume(tmp_adev); @@ -4108,6 +4110,8 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, */ amdgpu_unregister_gpu_instance(tmp_adev); + amdgpu_fbdev_set_suspend(adev, 1); + /* disable ras on ALL IPs */ if (!(in_ras_intr && !use_baco) && amdgpu_device_ip_need_full_reset(tmp_adev)) -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfxdata=02%7C01%7CXiaojie.Yuan%40amd.com%7C3eace080fd0b4f67337e08d7c594e441%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637195115872403614sdata=%2B%2B3xRFOl2Ho%2BRe9VuzqHtZNoVZ3s%2BxIP7xTv6yG11LA%3Dreserved=0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu/discovery: make the discovery code less chatty
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Xiaojie Yuan
BR,
Xiaojie
From: amd-gfx on behalf of Alex Deucher
Sent: Thursday, February 20, 2020 2:51 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH] drm/amdgpu/discovery: make the discovery code less chatty
Make the IP block base output debug only.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index f95092741c38..27d8ae19a7a4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -307,7 +307,7 @@ int amdgpu_discovery_reg_base_init(struct amdgpu_device
*adev)
for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) {
if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id))
{
- DRM_INFO("set register base offset for
%s\n",
+ DRM_DEBUG("set register base offset for
%s\n",
hw_id_names[le16_to_cpu(ip->hw_id)]);
adev->reg_offset[hw_ip][ip->number_instance] =
ip->base_address;
--
2.24.1
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Re: [PATCH umr v2] fix field names for INDIRECT_BUFFER_CONST/CIK for gfx9/gfx10
[AMD Official Use Only - Internal Distribution Only]
Thanks Tom.
BR,
Xiaojie
From: StDenis, Tom
Sent: Wednesday, February 19, 2020 8:01 PM
To: Yuan, Xiaojie; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH umr v2] fix field names for INDIRECT_BUFFER_CONST/CIK for
gfx9/gfx10
Hmm it doesn't apply on top of the tip of master. I'll just manually
apply it.
Tom
On 2020-02-19 6:56 a.m., Xiaojie Yuan wrote:
> field names for INDIRECT_BUFFER_CONST/CIK of gfx9/gfx10 are the same.
> fields like OFFLOAD_POLLING and VALID are defined in mec's
> INDIRECT_BUFFER packet, so not applicable here.
>
> v2: fix umr_pm4_decode_opcodes.c as well
>
> Signed-off-by: Xiaojie Yuan
> ---
> src/lib/ring_decode.c| 23 +++
> src/lib/umr_pm4_decode_opcodes.c | 20 ++--
> 2 files changed, 13 insertions(+), 30 deletions(-)
>
> diff --git a/src/lib/ring_decode.c b/src/lib/ring_decode.c
> index 250dfd7..fa44f27 100644
> --- a/src/lib/ring_decode.c
> +++ b/src/lib/ring_decode.c
> @@ -617,22 +617,13 @@ static void print_decode_pm4_pkt3(struct umr_asic
> *asic, struct umr_ring_decoder
> case 2: printf("IB_SIZE:%s%lu%s, VMID:
> %s%lu%s", BLUE, BITS(ib, 0, 20), RST, BLUE, BITS(ib, 24, 28), RST);
> decoder->pm4.next_ib_state.ib_size =
> BITS(ib, 0, 20) * 4;
> decoder->pm4.next_ib_state.ib_vmid =
> decoder->next_ib_info.vmid ? decoder->next_ib_info.vmid : BITS(ib, 24, 28);
> - if (decoder->pm4.cur_opcode == 0x33) {
> - if (asic->family >= FAMILY_NV) {
> - printf(", CHAIN:
> %s%u%s, PRE_ENA: %s%u%s, CACHE_POLICY: %s%u%s, PRE_RESUME: %s%u%s PRIV:
> %s%u%s",
> -BLUE,
> (unsigned)BITS(ib, 20, 21), RST,
> -BLUE,
> (unsigned)BITS(ib, 21, 22), RST,
> -BLUE,
> (unsigned)BITS(ib, 28, 30), RST,
> -BLUE,
> (unsigned)BITS(ib, 30, 31), RST,
> -BLUE,
> (unsigned)BITS(ib, 31, 32), RST);
> - } else if (asic->family >=
> FAMILY_AI) {
> - printf(", CHAIN:
> %s%u%s, OFFLOAD_POLLING: %s%u%s, VALID: %s%u%s, CACHE_POLICY: %s%u%s PRIV:
> %s%u%s",
> -BLUE,
> (unsigned)BITS(ib, 20, 21), RST,
> -BLUE,
> (unsigned)BITS(ib, 21, 22), RST,
> -BLUE,
> (unsigned)BITS(ib, 23, 24), RST,
> -BLUE,
> (unsigned)BITS(ib, 28, 30), RST,
> -BLUE,
> (unsigned)BITS(ib, 31, 32), RST);
> - }
> + if (asic->family >= FAMILY_AI) {
> + printf(", CHAIN: %s%u%s,
> PRE_ENA: %s%u%s, CACHE_POLICY: %s%u%s, PRE_RESUME: %s%u%s PRIV: %s%u%s",
> +BLUE,
> (unsigned)BITS(ib, 20, 21), RST,
> +BLUE,
> (unsigned)BITS(ib, 21, 22), RST,
> +BLUE,
> (unsigned)BITS(ib, 28, 30), RST,
> +BLUE,
> (unsigned)BITS(ib, 30, 31), RST,
> +BLUE,
> (unsigned)BITS(ib, 31, 32), RST);
> }
> if (!asic->options.no_follow_ib) {
> if (umr_read_vram(asic,
> decoder->pm4.next_ib_state.ib_vmid,
> diff --git a/src/lib/umr_pm4_decode_opcodes.c
> b/src/lib/umr_pm4_decode_opcodes.c
> index d7c1495..a823ecf 100644
> --- a/src/lib/umr_pm4_decode_opcodes.c
> +++ b/src/lib/umr_pm4_decode_opcodes.c
> @@ -429,20 +429,12 @@ static void decode_pkt3(struct umr_asic *asic, struct
> umr_pm4_stream_decode_ui *
> ui->add_field(ui, ib_addr + 8, ib_vmid, "IB_BASE_HI",
>
Re: [PATCH umr] fix field names for INDIRECT_BUFFER_CONST/CIK for gfx9/gfx10
[AMD Official Use Only - Internal Distribution Only]
Sure, I'll send v2 soon.
BR,
Xiaojie
From: StDenis, Tom
Sent: Wednesday, February 19, 2020 7:51 PM
To: Yuan, Xiaojie; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH umr] fix field names for INDIRECT_BUFFER_CONST/CIK for
gfx9/gfx10
Yup, my bad. We also need to fix the streaming version (line 432 of
src/lib/umr_pm4_decode_opcodes.c). Would you like to incorporate this
into this patch? Otherwise I can do it separately.
Thanks,
Tom
On 2020-02-19 6:26 a.m., Xiaojie Yuan wrote:
> field names for INDIRECT_BUFFER_CONST/CIK of gfx9/gfx10 are the same.
> fields like OFFLOAD_POLLING and VALID are defined in mec's
> INDIRECT_BUFFER packet, so not applicable here.
>
> Signed-off-by: Xiaojie Yuan
> ---
> src/lib/ring_decode.c | 23 +++
> 1 file changed, 7 insertions(+), 16 deletions(-)
>
> diff --git a/src/lib/ring_decode.c b/src/lib/ring_decode.c
> index 250dfd7..fa44f27 100644
> --- a/src/lib/ring_decode.c
> +++ b/src/lib/ring_decode.c
> @@ -617,22 +617,13 @@ static void print_decode_pm4_pkt3(struct umr_asic
> *asic, struct umr_ring_decoder
> case 2: printf("IB_SIZE:%s%lu%s, VMID:
> %s%lu%s", BLUE, BITS(ib, 0, 20), RST, BLUE, BITS(ib, 24, 28), RST);
> decoder->pm4.next_ib_state.ib_size =
> BITS(ib, 0, 20) * 4;
> decoder->pm4.next_ib_state.ib_vmid =
> decoder->next_ib_info.vmid ? decoder->next_ib_info.vmid : BITS(ib, 24, 28);
> - if (decoder->pm4.cur_opcode == 0x33) {
> - if (asic->family >= FAMILY_NV) {
> - printf(", CHAIN:
> %s%u%s, PRE_ENA: %s%u%s, CACHE_POLICY: %s%u%s, PRE_RESUME: %s%u%s PRIV:
> %s%u%s",
> -BLUE,
> (unsigned)BITS(ib, 20, 21), RST,
> -BLUE,
> (unsigned)BITS(ib, 21, 22), RST,
> -BLUE,
> (unsigned)BITS(ib, 28, 30), RST,
> -BLUE,
> (unsigned)BITS(ib, 30, 31), RST,
> -BLUE,
> (unsigned)BITS(ib, 31, 32), RST);
> - } else if (asic->family >=
> FAMILY_AI) {
> - printf(", CHAIN:
> %s%u%s, OFFLOAD_POLLING: %s%u%s, VALID: %s%u%s, CACHE_POLICY: %s%u%s PRIV:
> %s%u%s",
> -BLUE,
> (unsigned)BITS(ib, 20, 21), RST,
> -BLUE,
> (unsigned)BITS(ib, 21, 22), RST,
> -BLUE,
> (unsigned)BITS(ib, 23, 24), RST,
> -BLUE,
> (unsigned)BITS(ib, 28, 30), RST,
> -BLUE,
> (unsigned)BITS(ib, 31, 32), RST);
> - }
> + if (asic->family >= FAMILY_AI) {
> + printf(", CHAIN: %s%u%s,
> PRE_ENA: %s%u%s, CACHE_POLICY: %s%u%s, PRE_RESUME: %s%u%s PRIV: %s%u%s",
> +BLUE,
> (unsigned)BITS(ib, 20, 21), RST,
> +BLUE,
> (unsigned)BITS(ib, 21, 22), RST,
> +BLUE,
> (unsigned)BITS(ib, 28, 30), RST,
> +BLUE,
> (unsigned)BITS(ib, 30, 31), RST,
> +BLUE,
> (unsigned)BITS(ib, 31, 32), RST);
> }
> if (!asic->options.no_follow_ib) {
> if (umr_read_vram(asic,
> decoder->pm4.next_ib_state.ib_vmid,
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Re: [PATCH umr 1/2] rename mmBIF_BX_PF_MM_* for nbio 2.3
Thanks Tom. I'm just publishing this quick fix so that I can continue my
debugging with umr, and your solution sounds more reasonable ; )
BR,
Xiaojie
> On Feb 14, 2020, at 10:55 PM, StDenis, Tom wrote:
>
> Hi,
>
> Thanks for the patch however since the *.i files are machine generate I'd
> rather like to avoid patches like this (since they will need to be
> continually applied).
>
> The ideal solution is to either patch src/lib/read_vram.c or to patch the
> kernel headers. The kernel headers are also likewise machine generated so
> patching umr is probably the best.
>
> I'll do this myself.
>
> I will however apply patch #2 of the series.
>
> Thanks,
>
> Tom
>
>
>> On 2020-02-14 9:50 a.m., Xiaojie Yuan wrote:
>> Fixes following error while dumping gfx ring:
>>
>> [BUG]: reg [mmMM_INDEX] not found on asic [navi10]
>> [BUG]: reg [mmMM_INDEX_HI] not found on asic [navi10]
>> [BUG]: reg [mmMM_DATA] not found on asic [navi10]
>> Cannot read from system memory: Operation not permitted
>> [ERROR]: Accessing system memory returned: -1
>> Cannot read from system memory: Bad address
>> [ERROR]: Accessing system memory returned: -1
>>
>> Signed-off-by: Xiaojie Yuan
>> ---
>> src/lib/ip/nbio230_bits.i | 6 +++---
>> src/lib/ip/nbio230_regs.i | 6 +++---
>> 2 files changed, 6 insertions(+), 6 deletions(-)
>>
>> diff --git a/src/lib/ip/nbio230_bits.i b/src/lib/ip/nbio230_bits.i
>> index 506ccba..fd5bad8 100644
>> --- a/src/lib/ip/nbio230_bits.i
>> +++ b/src/lib/ip/nbio230_bits.i
>> @@ -1,11 +1,11 @@
>> -static struct umr_bitfield mmBIF_BX_PF_MM_INDEX[] = {
>> +static struct umr_bitfield mmMM_INDEX[] = {
>> { "MM_OFFSET", 0, 30, _bitfield_default },
>> { "MM_APER", 31, 31, _bitfield_default },
>> };
>> -static struct umr_bitfield mmBIF_BX_PF_MM_DATA[] = {
>> +static struct umr_bitfield mmMM_DATA[] = {
>> { "MM_DATA", 0, 31, _bitfield_default },
>> };
>> -static struct umr_bitfield mmBIF_BX_PF_MM_INDEX_HI[] = {
>> +static struct umr_bitfield mmMM_INDEX_HI[] = {
>> { "MM_OFFSET_HI", 0, 31, _bitfield_default },
>> };
>> static struct umr_bitfield mmSYSHUB_INDEX_OVLP[] = {
>> diff --git a/src/lib/ip/nbio230_regs.i b/src/lib/ip/nbio230_regs.i
>> index ab57385..27a644b 100644
>> --- a/src/lib/ip/nbio230_regs.i
>> +++ b/src/lib/ip/nbio230_regs.i
>> @@ -1,6 +1,6 @@
>> -{ "mmBIF_BX_PF_MM_INDEX", REG_MMIO, 0x, 0,
>> _BX_PF_MM_INDEX[0],
>> sizeof(mmBIF_BX_PF_MM_INDEX)/sizeof(mmBIF_BX_PF_MM_INDEX[0]), 0, 0 },
>> -{ "mmBIF_BX_PF_MM_DATA", REG_MMIO, 0x0001, 0, _BX_PF_MM_DATA[0],
>> sizeof(mmBIF_BX_PF_MM_DATA)/sizeof(mmBIF_BX_PF_MM_DATA[0]), 0, 0 },
>> -{ "mmBIF_BX_PF_MM_INDEX_HI", REG_MMIO, 0x0006, 0,
>> _BX_PF_MM_INDEX_HI[0],
>> sizeof(mmBIF_BX_PF_MM_INDEX_HI)/sizeof(mmBIF_BX_PF_MM_INDEX_HI[0]), 0, 0 },
>> +{ "mmMM_INDEX", REG_MMIO, 0x, 0, _INDEX[0],
>> sizeof(mmMM_INDEX)/sizeof(mmMM_INDEX[0]), 0, 0 },
>> +{ "mmMM_DATA", REG_MMIO, 0x0001, 0, _DATA[0],
>> sizeof(mmMM_DATA)/sizeof(mmMM_DATA[0]), 0, 0 },
>> +{ "mmMM_INDEX_HI", REG_MMIO, 0x0006, 0, _INDEX_HI[0],
>> sizeof(mmMM_INDEX_HI)/sizeof(mmMM_INDEX_HI[0]), 0, 0 },
>> { "mmSYSHUB_INDEX_OVLP", REG_MMIO, 0x0008, 0, _INDEX_OVLP[0],
>> sizeof(mmSYSHUB_INDEX_OVLP)/sizeof(mmSYSHUB_INDEX_OVLP[0]), 0, 0 },
>> { "mmSYSHUB_DATA_OVLP", REG_MMIO, 0x0009, 0, _DATA_OVLP[0],
>> sizeof(mmSYSHUB_DATA_OVLP)/sizeof(mmSYSHUB_DATA_OVLP[0]), 0, 0 },
>> { "mmPCIE_INDEX", REG_MMIO, 0x000c, 0, _INDEX[0],
>> sizeof(mmPCIE_INDEX)/sizeof(mmPCIE_INDEX[0]), 0, 0 },
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Re: [PATCH 2/2] drm/amdgpu/gfx10: disable gfxoff when reading rlc clock
Series is Reviewed-by: Xiaojie Yuan
BR,
Xiaojie
> On Feb 12, 2020, at 9:53 PM, Alex Deucher wrote:
>
> Otherwise we readback all ones. Fixes rlc counter
> readback while gfxoff is active.
>
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index 4e25b39ac14f..0eff2e7d33fa 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -3924,11 +3924,13 @@ static uint64_t
> gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
> {
>uint64_t clock;
>
> +amdgpu_gfx_off_ctrl(adev, false);
>mutex_lock(>gfx.gpu_clock_mutex);
>WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
>clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
>((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
>mutex_unlock(>gfx.gpu_clock_mutex);
> +amdgpu_gfx_off_ctrl(adev, true);
>return clock;
> }
>
> --
> 2.24.1
>
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Re: [PATCH] drm/amd/powerplay: update smu11_driver_if_navi10.h
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Xiaojie Yuan
BR,
Xiaojie
From: amd-gfx on behalf of Evan Quan
Sent: Monday, February 10, 2020 3:11 PM
To: amd-gfx@lists.freedesktop.org
Cc: Quan, Evan
Subject: [PATCH] drm/amd/powerplay: update smu11_driver_if_navi10.h
To pair the latest SMU firmwares.
Change-Id: I5262c750fa08bc6268b43e3420e110e9ee71ccf6
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h | 3 ++-
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 4 ++--
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h
b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h
index ac0120e384be..4b2da98afcd2 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h
@@ -701,7 +701,8 @@ typedef struct {
// APCC Settings
uint16_t PccThresholdLow;
uint16_t PccThresholdHigh;
- uint32_t PaddingAPCC[6]; //FIXME pending SPEC
+ uint32_t MGpuFanBoostLimitRpm;
+ uint32_t PaddingAPCC[5];
// Temperature Dependent Vmin
uint16_t VDDGFX_TVmin; //Celcius
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index d5314d12628a..acccdf621b4e 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -28,8 +28,8 @@
#define SMU11_DRIVER_IF_VERSION_INV 0x
#define SMU11_DRIVER_IF_VERSION_VG20 0x13
#define SMU11_DRIVER_IF_VERSION_ARCT 0x12
-#define SMU11_DRIVER_IF_VERSION_NV10 0x33
-#define SMU11_DRIVER_IF_VERSION_NV14 0x34
+#define SMU11_DRIVER_IF_VERSION_NV10 0x35
+#define SMU11_DRIVER_IF_VERSION_NV14 0x36
/* MP Apertures */
#define MP0_Public 0x0380
--
2.25.0
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Re: [PATCH 2/2] drm/amdgpu: skip reservation of discovery tmr region in pre-Navi
[AMD Official Use Only - Internal Distribution Only]
Series is Reviewed-by: Xiaojie Yuan
BR,
Xiaojie
From: amd-gfx on behalf of Hawking
Zhang
Sent: Friday, January 17, 2020 2:57 AM
To: amd-gfx@lists.freedesktop.org; Deucher, Alexander; Gao, Likun
Cc: Zhang, Hawking
Subject: [PATCH 2/2] drm/amdgpu: skip reservation of discovery tmr region in
pre-Navi
IP discovery is only supported in Navi series and onwards.
There is no need to reserve a portion of vram as discovery
tmr region for pre-Navi adapters.
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 967f6d0..f21fd8fa 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1822,14 +1822,16 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
* reserve TMR memory at the top of VRAM which holds
* IP Discovery data and is protected by PSP.
*/
- r = amdgpu_bo_create_kernel_at(adev,
+ if (adev->discovery_tmr_size > 0) {
+ r = amdgpu_bo_create_kernel_at(adev,
adev->gmc.real_vram_size - adev->discovery_tmr_size,
adev->discovery_tmr_size,
AMDGPU_GEM_DOMAIN_VRAM,
>discovery_memory,
NULL);
- if (r)
- return r;
+ if (r)
+ return r;
+ }
DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
(unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
--
2.7.4
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Re: [PATCH] drm/scheduler: fix documentation by replacing rq_list with sched_list
[AMD Official Use Only - Internal Distribution Only] Hi Nirmoy, Seems like documentation for struct drm_sched_entity@gpu_scheduler.h need update as well. BR, Xiaojie From: amd-gfx on behalf of Nirmoy Das Sent: Tuesday, January 14, 2020 5:58 PM To: amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander; Ho, Kenny; Das, Nirmoy; Koenig, Christian Subject: [PATCH] drm/scheduler: fix documentation by replacing rq_list with sched_list Signed-off-by: Nirmoy Das --- drivers/gpu/drm/scheduler/sched_entity.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/scheduler/sched_entity.c b/drivers/gpu/drm/scheduler/sched_entity.c index 2e3a058fc239..62bcca855c69 100644 --- a/drivers/gpu/drm/scheduler/sched_entity.c +++ b/drivers/gpu/drm/scheduler/sched_entity.c @@ -45,7 +45,7 @@ * @guilty: atomic_t set to 1 when a job on this queue * is found to be guilty causing a timeout * - * Note: the rq_list should have atleast one element to schedule + * Note: the sched_list should have atleast one element to schedule * the entity * * Returns 0 on success or a negative error code on failure. -- 2.24.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfxdata=02%7C01%7CXiaojie.Yuan%40amd.com%7Cb5b5e9e4c2a34ac6b50308d798d81903%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637145926254946780sdata=ZgkmwrForbuXnPGGHz2UVE67anyILWedAMNlcSA%2BvUw%3Dreserved=0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 2/2] drm/amdgpu: remove memory training p2c buffer reservation(V2)
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Xiaojie Yuan
BR,
Xiaojie
From: Tianci Yin
Sent: Thursday, December 19, 2019 10:44 AM
To: amd-gfx@lists.freedesktop.org
Cc: Tuikov, Luben; Koenig, Christian; Deucher, Alexander; Zhang, Hawking; Xu,
Feifei; Yuan, Xiaojie; Long, Gang; Wang, Kevin(Yang); Yin, Tianci (Rico)
Subject: [PATCH 2/2] drm/amdgpu: remove memory training p2c buffer
reservation(V2)
From: "Tianci.Yin"
IP discovery TMR(occupied the top VRAM with size DISCOVERY_TMR_SIZE)
has been reserved, and the p2c buffer is in the range of this TMR, so
the p2c buffer reservation is unnecessary.
Change-Id: Ib1f2f2b4a1f3869c03ffe22e2836cdbee17ba99f
Reviewed-by: Kevin Wang
Signed-off-by: Tianci.Yin
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 21 ++---
2 files changed, 2 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index 5f8fd3e3535b..3265487b859f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -202,7 +202,6 @@ struct psp_memory_training_context {
/*vram offset of the p2c training data*/
u64 p2c_train_data_offset;
- struct amdgpu_bo *p2c_bo;
/*vram offset of the c2p training data*/
u64 c2p_train_data_offset;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index ec84acdd43a2..60f17e989014 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1681,9 +1681,6 @@ static int amdgpu_ttm_training_reserve_vram_fini(struct
amdgpu_device *adev)
amdgpu_bo_free_kernel(>c2p_bo, NULL, NULL);
ctx->c2p_bo = NULL;
- amdgpu_bo_free_kernel(>p2c_bo, NULL, NULL);
- ctx->p2c_bo = NULL;
-
return 0;
}
@@ -1725,17 +1722,6 @@ static int amdgpu_ttm_training_reserve_vram_init(struct
amdgpu_device *adev)
ctx->p2c_train_data_offset,
ctx->c2p_train_data_offset);
- ret = amdgpu_bo_create_kernel_at(adev,
-ctx->p2c_train_data_offset,
-ctx->train_data_size,
-AMDGPU_GEM_DOMAIN_VRAM,
->p2c_bo,
-NULL);
- if (ret) {
- DRM_ERROR("alloc p2c_bo failed(%d)!\n", ret);
- goto Err_out;
- }
-
ret = amdgpu_bo_create_kernel_at(adev,
ctx->c2p_train_data_offset,
ctx->train_data_size,
@@ -1744,15 +1730,12 @@ static int amdgpu_ttm_training_reserve_vram_init(struct
amdgpu_device *adev)
NULL);
if (ret) {
DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret);
- goto Err_out;
+ amdgpu_ttm_training_reserve_vram_fini(adev);
+ return ret;
}
ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS;
return 0;
-
-Err_out:
- amdgpu_ttm_training_reserve_vram_fini(adev);
- return ret;
}
/**
--
2.17.1
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Re: [PATCH] drm/amd/powerplay: clear VBIOS scratchs on baco exit
Hi Evan,
Just out of curiosity, may I know what issue are you trying to fix?
I used to see vbios post failure (hangs in atombios init table) after baco exit
occasionally on navi.
BR,
Xiaojie
> On Dec 6, 2019, at 11:37 AM, Evan Quan wrote:
>
> This is needed for coming asic init on performing gpu reset.
>
> Change-Id: If3671a24d239e3d288665fadaa2c40c87d5da40b
> Signed-off-by: Evan Quan
> ---
> drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> index 39ec06aee809..ab809df7bc35 100644
> --- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> +++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> @@ -1659,6 +1659,12 @@ int smu_v11_0_baco_set_state(struct smu_context *smu,
> enum smu_baco_state state)
>}
>} else {
>ret = smu_send_smc_msg(smu, SMU_MSG_ExitBaco);
> +if (ret)
> +goto out;
> +
> +WREG32_SOC15(NBIO, 0, mmBIOS_SCRATCH_6, 0);
> +WREG32_SOC15(NBIO, 0, mmBIOS_SCRATCH_7, 0);
> +
>bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
>BIF_DOORBELL_INT_CNTL,
>DOORBELL_INTERRUPT_DISABLE, 0);
> --
> 2.24.0
>
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Re: [PATCH] drm/amdgpu: fix calltrace during kmd unload(v2)
[AMD Official Use Only - Internal Distribution Only]
Tested on navi14 and s3/baco works fine with patch applied.
Reviewed-by: Xiaojie Yuan
BR,
Xiaojie
From: amd-gfx on behalf of Monk Liu
Sent: Thursday, November 28, 2019 2:57 PM
To: amd-gfx@lists.freedesktop.org
Cc: Liu, Monk
Subject: [PATCH] drm/amdgpu: fix calltrace during kmd unload(v2)
kernel would report a warning on double unpin
on the csb BO because we unpin it during hw_fini
but actually we don't need to pin/unpin it during
hw_init/fini since it is created with kernel pinned
v2:
get_csb in init_rlc so hw_init() will make CSIB content
back even after reset or s3.
take care of gfx7/8 as well
v3:
use bo_create_kernel instead of bo_create_reserved for CSB
otherwise the bo_free_kernel() on CSB is not aligned and
would led to its internal reserve pending there forever
Signed-off-by: Monk Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c | 10 +-
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 58 +
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 2 ++
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 40 +--
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 40 +--
5 files changed, 6 insertions(+), 144 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c
index c8793e6..6373bfb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c
@@ -124,13 +124,12 @@ int amdgpu_gfx_rlc_init_sr(struct amdgpu_device *adev,
u32 dws)
*/
int amdgpu_gfx_rlc_init_csb(struct amdgpu_device *adev)
{
- volatile u32 *dst_ptr;
u32 dws;
int r;
/* allocate clear state block */
adev->gfx.rlc.clear_state_size = dws =
adev->gfx.rlc.funcs->get_csb_size(adev);
- r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
+ r = amdgpu_bo_create_kernel(adev, dws * 4, PAGE_SIZE,
AMDGPU_GEM_DOMAIN_VRAM,
>gfx.rlc.clear_state_obj,
>gfx.rlc.clear_state_gpu_addr,
@@ -141,13 +140,6 @@ int amdgpu_gfx_rlc_init_csb(struct amdgpu_device *adev)
return r;
}
- /* set up the cs buffer */
- dst_ptr = adev->gfx.rlc.cs_ptr;
- adev->gfx.rlc.funcs->get_csb_buffer(adev, dst_ptr);
- amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
- amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
- amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
-
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 7372904..7703b25 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -991,39 +991,6 @@ static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
return 0;
}
-static int gfx_v10_0_csb_vram_pin(struct amdgpu_device *adev)
-{
- int r;
-
- r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
- if (unlikely(r != 0))
- return r;
-
- r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj,
- AMDGPU_GEM_DOMAIN_VRAM);
- if (!r)
- adev->gfx.rlc.clear_state_gpu_addr =
- amdgpu_bo_gpu_offset(adev->gfx.rlc.clear_state_obj);
-
- amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
-
- return r;
-}
-
-static void gfx_v10_0_csb_vram_unpin(struct amdgpu_device *adev)
-{
- int r;
-
- if (!adev->gfx.rlc.clear_state_obj)
- return;
-
- r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true);
- if (likely(r == 0)) {
- amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
- amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
- }
-}
-
static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
{
amdgpu_bo_free_kernel(>gfx.mec.hpd_eop_obj, NULL, NULL);
@@ -1785,25 +1752,7 @@ static void gfx_v10_0_enable_gui_idle_interrupt(struct
amdgpu_device *adev,
static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
{
- int r;
-
- if (adev->in_gpu_reset) {
- r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
- if (r)
- return r;
-
- r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj,
- (void **)>gfx.rlc.cs_ptr);
- if (!r) {
- adev->gfx.rlc.funcs->get_csb_buffer(adev,
- adev->gfx.rlc.cs_ptr);
- amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
- }
-
- amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
- if (r)
- return r;
- }
+ adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
/* csib */
WREG32_SOC15(GC, 0,
Re: [PATCH 5/5] drm/amdgpu: fix calltrace during kmd unload
[AMD Official Use Only - Internal Distribution Only]
Hi Monk,
As long as the content of CSIB won't be changed by CP FW in runtime, I have no
objection to 're-initialize after S3 resume'.
I am not quite sure about the actual behavior, let me do an experiment to
confirm that and add Hawking / Jack who adds the original CSIB code for comment.
BTW, note that I recently has a patch to re-initialize CSIB in baco sequence,
please consider to squash it when making your final fix:
commit c8494497feb0050a66128ca626f3883d6f08d783
Author: Xiaojie Yuan
Date: Wed Nov 20 14:02:22 2019 +0800
drm/amdgpu/gfx10: re-init clear state buffer after gpu reset
This patch fixes 2nd baco reset failure with gfxoff enabled on navi1x.
clear state buffer (resides in vram) is corrupted after 1st baco reset,
upon gfxoff exit, CPF gets garbage header in CSIB and hangs.
Signed-off-by: Xiaojie Yuan
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
BR,
Xiaojie
From: Liu, Monk
Sent: Thursday, November 28, 2019 10:53 AM
To: Yuan, Xiaojie; Deucher, Alexander; Koenig, Christian
Cc: amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH 5/5] drm/amdgpu: fix calltrace during kmd unload
Hi Xiaojie
For SRIOV we don't use suspend so I didn't think to that part, thanks for the
remind !
But we still need to fix this call trace issue anyway (our jenkins testing
system consider such call trace as an error )
How about we do " adev->gfx.rlc.funcs->get_csb_buffer(adev, dst_ptr);" in the
hw_init() ? this way
You don't need to evict the CSIB during suspend and the CSIB always will be
re-initialized after S3 resume ?
@Deucher, Alexander @Koenig, Christian what's your opinion ?
_
Monk Liu|GPU Virtualization Team |AMD
-Original Message-----
From: Yuan, Xiaojie
Sent: Tuesday, November 26, 2019 9:10 PM
To: Liu, Monk
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 5/5] drm/amdgpu: fix calltrace during kmd unload
Hi Monk,
hw_fini() is called in suspend code path as well. I'm wondering how csb can be
evicted if it's not unpined before suspend.
BR,
Xiaojie
> On Nov 26, 2019, at 7:50 PM, Monk Liu wrote:
>
> kernel would report a warning on double unpin on the csb BO because we
> unpin it during hw_fini but actually we don't need to pin/unpin it
> during hw_init/fini since it is created with kernel pinned
>
> remove all those useless code for gfx9/10
>
> Signed-off-by: Monk Liu
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c | 1 -
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 38
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 39 -
> 3 files changed, 78 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c
> index c8793e6..289fada 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c
> @@ -145,7 +145,6 @@ int amdgpu_gfx_rlc_init_csb(struct amdgpu_device *adev)
>dst_ptr = adev->gfx.rlc.cs_ptr;
>adev->gfx.rlc.funcs->get_csb_buffer(adev, dst_ptr);
>amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
> -amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
>amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
>
>return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index a56cba9..5ee7467 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -996,39 +996,6 @@ static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
>return 0;
> }
>
> -static int gfx_v10_0_csb_vram_pin(struct amdgpu_device *adev) -{
> -int r;
> -
> -r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
> -if (unlikely(r != 0))
> -return r;
> -
> -r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj,
> -AMDGPU_GEM_DOMAIN_VRAM);
> -if (!r)
> -adev->gfx.rlc.clear_state_gpu_addr =
> -amdgpu_bo_gpu_offset(adev->gfx.rlc.clear_state_obj);
> -
> -amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
> -
> -return r;
> -}
> -
> -static void gfx_v10_0_csb_vram_unpin(struct amdgpu_device *adev) -{
> -int r;
> -
> -if (!adev->gfx.rlc.clear_state_obj)
> -return;
> -
> -r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true);
> -if (likely(r == 0)) {
> -amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
> -amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
> -}
> -}
> -
> static void gfx_v10_0_mec_fini(struct amdgpu_device *adev) {
>amdgpu_bo_free_kernel(>gfx.mec.hpd_e
Re: [PATCH 5/5] drm/amdgpu: fix calltrace during kmd unload
Hi Monk,
hw_fini() is called in suspend code path as well. I'm wondering how csb can be
evicted if it's not unpined before suspend.
BR,
Xiaojie
> On Nov 26, 2019, at 7:50 PM, Monk Liu wrote:
>
> kernel would report a warning on double unpin
> on the csb BO because we unpin it during hw_fini
> but actually we don't need to pin/unpin it during
> hw_init/fini since it is created with kernel pinned
>
> remove all those useless code for gfx9/10
>
> Signed-off-by: Monk Liu
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c | 1 -
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 38
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 39 -
> 3 files changed, 78 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c
> index c8793e6..289fada 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c
> @@ -145,7 +145,6 @@ int amdgpu_gfx_rlc_init_csb(struct amdgpu_device *adev)
>dst_ptr = adev->gfx.rlc.cs_ptr;
>adev->gfx.rlc.funcs->get_csb_buffer(adev, dst_ptr);
>amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
> -amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
>amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
>
>return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index a56cba9..5ee7467 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -996,39 +996,6 @@ static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
>return 0;
> }
>
> -static int gfx_v10_0_csb_vram_pin(struct amdgpu_device *adev)
> -{
> -int r;
> -
> -r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
> -if (unlikely(r != 0))
> -return r;
> -
> -r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj,
> -AMDGPU_GEM_DOMAIN_VRAM);
> -if (!r)
> -adev->gfx.rlc.clear_state_gpu_addr =
> -amdgpu_bo_gpu_offset(adev->gfx.rlc.clear_state_obj);
> -
> -amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
> -
> -return r;
> -}
> -
> -static void gfx_v10_0_csb_vram_unpin(struct amdgpu_device *adev)
> -{
> -int r;
> -
> -if (!adev->gfx.rlc.clear_state_obj)
> -return;
> -
> -r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true);
> -if (likely(r == 0)) {
> -amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
> -amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
> -}
> -}
> -
> static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
> {
>amdgpu_bo_free_kernel(>gfx.mec.hpd_eop_obj, NULL, NULL);
> @@ -3780,10 +3747,6 @@ static int gfx_v10_0_hw_init(void *handle)
>int r;
>struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> -r = gfx_v10_0_csb_vram_pin(adev);
> -if (r)
> -return r;
> -
>if (!amdgpu_emu_mode)
>gfx_v10_0_init_golden_registers(adev);
>
> @@ -3871,7 +3834,6 @@ static int gfx_v10_0_hw_fini(void *handle)
>}
>gfx_v10_0_cp_enable(adev, false);
>gfx_v10_0_enable_gui_idle_interrupt(adev, false);
> -gfx_v10_0_csb_vram_unpin(adev);
>
>return 0;
> }
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 4cc2e50..524a7ba 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -1683,39 +1683,6 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device
> *adev)
>return 0;
> }
>
> -static int gfx_v9_0_csb_vram_pin(struct amdgpu_device *adev)
> -{
> -int r;
> -
> -r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
> -if (unlikely(r != 0))
> -return r;
> -
> -r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj,
> -AMDGPU_GEM_DOMAIN_VRAM);
> -if (!r)
> -adev->gfx.rlc.clear_state_gpu_addr =
> -amdgpu_bo_gpu_offset(adev->gfx.rlc.clear_state_obj);
> -
> -amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
> -
> -return r;
> -}
> -
> -static void gfx_v9_0_csb_vram_unpin(struct amdgpu_device *adev)
> -{
> -int r;
> -
> -if (!adev->gfx.rlc.clear_state_obj)
> -return;
> -
> -r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true);
> -if (likely(r == 0)) {
> -amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
> -amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
> -}
> -}
> -
> static void gfx_v9_0_mec_fini(struct amdgpu_device *adev)
> {
>amdgpu_bo_free_kernel(>gfx.mec.hpd_eop_obj, NULL, NULL);
> @@ -3694,10 +3661,6 @@ static int gfx_v9_0_hw_init(void *handle)
>
>gfx_v9_0_constants_init(adev);
>
> -r = gfx_v9_0_csb_vram_pin(adev);
> -if (r)
> -return r;
> -
>r = adev->gfx.rlc.funcs->resume(adev);
>if (r)
>return r;
> @@ -3779,8 +3742,6 @@ static int gfx_v9_0_hw_fini(void *handle)
>gfx_v9_0_cp_enable(adev, false);
>
Re: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset
Hi Evan, Yes, I know this commit, but the reason for csb corruption is different. The fix you mentioned is for suspend code path when bo is not unpinned at fini time. Then it is not evicted (resides in vram) and corrupts because of vram power down. For gpu reset code path, bos are not evicted, so we need to re-init csb. BR, Xiaojie > On Nov 21, 2019, at 9:28 AM, Quan, Evan wrote: > > Hmm, this seems an old issue which was found on gfx v9. > >drm/amdgpu: pin the csb buffer on hw init v2 > >Without this pin, the csb buffer will be filled with inconsistent >data after S3 resume. And that will causes gfx hang on gfxoff >exit since this csb will be executed then. > >v2: fit amdgpu_bo_pin change(take one less argument) > > Maybe we need to find out a solution suitable for all ASICs. > > Regards, > Evan > -Original Message- > From: amd-gfx On Behalf Of Yuan, > Xiaojie > Sent: Wednesday, November 20, 2019 5:10 PM > To: Zhang, Hawking ; Koenig, Christian > ; amd-gfx@lists.freedesktop.org > Cc: Long, Gang ; Xiao, Jack ; Ma, Le > > Subject: Re: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu > reset > > Got it. > Thanks Hawking and Chris for your attention. > > BR, > Xiaojie > > ________ > From: Zhang, Hawking > Sent: Wednesday, November 20, 2019 5:04 PM > To: Yuan, Xiaojie; Koenig, Christian; amd-gfx@lists.freedesktop.org > Cc: Long, Gang; Xiao, Jack; Ma, Le > Subject: RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu > reset > > I'm okay with the re-initialize and it's more straightforward approach. > > Regards, > Hawking > -Original Message- > From: Yuan, Xiaojie > Sent: 2019年11月20日 17:00 > To: Zhang, Hawking ; Koenig, Christian > ; amd-gfx@lists.freedesktop.org > Cc: Long, Gang ; Xiao, Jack > Subject: Re: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu > reset > > I can try this approach as well. > This csb is similar to the kiq mqd which are allocated in vram and might > corrupt after baco reset. > > BR, > Xiaojie > > > From: Zhang, Hawking > Sent: Wednesday, November 20, 2019 4:54 PM > To: Koenig, Christian; Yuan, Xiaojie; amd-gfx@lists.freedesktop.org > Cc: Long, Gang; Xiao, Jack > Subject: RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu > reset > > I think we should evict the bo and then move it back. > > Regards, > Hawking > > -Original Message- > From: Christian König > Sent: 2019年11月20日 16:47 > To: Zhang, Hawking ; Yuan, Xiaojie > ; amd-gfx@lists.freedesktop.org > Cc: Long, Gang ; Xiao, Jack > Subject: Re: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu > reset > > A baco reset also resets the MC, doesn't it? n this case it would be expected > that the content of VRAM is corrupted. > > Christian. > >> Am 20.11.19 um 09:45 schrieb Zhang, Hawking: >> Or in another word, we are still not clear when the corruption actually >> happens, right? >> >> Regards, >> Hawking >> -Original Message- >> From: amd-gfx On Behalf Of >> Zhang, Hawking >> Sent: 2019年11月20日 16:44 >> To: Yuan, Xiaojie ; >> amd-gfx@lists.freedesktop.org >> Cc: Long, Gang ; Xiao, Jack >> Subject: RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer >> after gpu reset >> >> Just make sure I understand you correctly. So until fw team root cause the >> reason of csb corruption, we keep the workaround in driver, correct? >> >> Regards, >> Hawking >> -Original Message- >> From: Yuan, Xiaojie >> Sent: 2019年11月20日 14:47 >> To: amd-gfx@lists.freedesktop.org >> Cc: Zhang, Hawking ; Xiao, Jack >> ; Long, Gang ; Yuan, Xiaojie >> >> Subject: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after >> gpu reset >> >> This patch fixes 2nd baco reset failure with gfxoff enabled on navi1x. >> >> clear state buffer (resides in vram) is corrupted after 1st baco reset, upon >> gfxoff exit, CPF gets garbage header in CSIB and hangs. >> >> Signed-off-by: Xiaojie Yuan >> --- >> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 43 ++ >> 1 file changed, 37 insertions(+), 6 deletions(-) >> >> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c >> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c >> index 9274bd4b6c68..8e24ea08ca39 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c >> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.
Re: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset
Got it.
Thanks Hawking and Chris for your attention.
BR,
Xiaojie
From: Zhang, Hawking
Sent: Wednesday, November 20, 2019 5:04 PM
To: Yuan, Xiaojie; Koenig, Christian; amd-gfx@lists.freedesktop.org
Cc: Long, Gang; Xiao, Jack; Ma, Le
Subject: RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu
reset
I'm okay with the re-initialize and it's more straightforward approach.
Regards,
Hawking
-Original Message-
From: Yuan, Xiaojie
Sent: 2019年11月20日 17:00
To: Zhang, Hawking ; Koenig, Christian
; amd-gfx@lists.freedesktop.org
Cc: Long, Gang ; Xiao, Jack
Subject: Re: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu
reset
I can try this approach as well.
This csb is similar to the kiq mqd which are allocated in vram and might
corrupt after baco reset.
BR,
Xiaojie
From: Zhang, Hawking
Sent: Wednesday, November 20, 2019 4:54 PM
To: Koenig, Christian; Yuan, Xiaojie; amd-gfx@lists.freedesktop.org
Cc: Long, Gang; Xiao, Jack
Subject: RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu
reset
I think we should evict the bo and then move it back.
Regards,
Hawking
-Original Message-
From: Christian König
Sent: 2019年11月20日 16:47
To: Zhang, Hawking ; Yuan, Xiaojie
; amd-gfx@lists.freedesktop.org
Cc: Long, Gang ; Xiao, Jack
Subject: Re: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu
reset
A baco reset also resets the MC, doesn't it? n this case it would be expected
that the content of VRAM is corrupted.
Christian.
Am 20.11.19 um 09:45 schrieb Zhang, Hawking:
> Or in another word, we are still not clear when the corruption actually
> happens, right?
>
> Regards,
> Hawking
> -Original Message-
> From: amd-gfx On Behalf Of
> Zhang, Hawking
> Sent: 2019年11月20日 16:44
> To: Yuan, Xiaojie ;
> amd-gfx@lists.freedesktop.org
> Cc: Long, Gang ; Xiao, Jack
> Subject: RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer
> after gpu reset
>
> Just make sure I understand you correctly. So until fw team root cause the
> reason of csb corruption, we keep the workaround in driver, correct?
>
> Regards,
> Hawking
> -Original Message-
> From: Yuan, Xiaojie
> Sent: 2019年11月20日 14:47
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhang, Hawking ; Xiao, Jack
> ; Long, Gang ; Yuan, Xiaojie
>
> Subject: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after
> gpu reset
>
> This patch fixes 2nd baco reset failure with gfxoff enabled on navi1x.
>
> clear state buffer (resides in vram) is corrupted after 1st baco reset, upon
> gfxoff exit, CPF gets garbage header in CSIB and hangs.
>
> Signed-off-by: Xiaojie Yuan
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 43 ++
> 1 file changed, 37 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index 9274bd4b6c68..8e24ea08ca39 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -1789,27 +1789,52 @@ static void
> gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
> WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); }
>
> -static void gfx_v10_0_init_csb(struct amdgpu_device *adev)
> +static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
> {
> + int r;
> +
> + if (adev->in_gpu_reset) {
> + r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
> + if (r)
> + return r;
> +
> + r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj,
> +(void **)>gfx.rlc.cs_ptr);
> + if (!r) {
> + adev->gfx.rlc.funcs->get_csb_buffer(adev,
> + adev->gfx.rlc.cs_ptr);
> + amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
> + }
> +
> + amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
> + if (r)
> + return r;
> + }
> +
> /* csib */
> WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
>adev->gfx.rlc.clear_state_gpu_addr >> 32);
> WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
>adev->gfx.rlc.clear_state_gpu_addr & 0xfffc);
> WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH,
> adev->gfx.rlc.clear_state_size);
> +
> + return 0;
> }
>
> -static void gfx_v10_0_init_pg(struct amdgpu_device *adev)
> +static int gfx_v10_0_init_pg(struct amdgpu_device *adev)
> {
> int i;
> + int r;
>
> - gfx_v10_0_init_csb(adev);
> + r = gfx_v10_0_i
Re: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset
I can try this approach as well.
This csb is similar to the kiq mqd which are allocated in vram and might
corrupt after baco reset.
BR,
Xiaojie
From: Zhang, Hawking
Sent: Wednesday, November 20, 2019 4:54 PM
To: Koenig, Christian; Yuan, Xiaojie; amd-gfx@lists.freedesktop.org
Cc: Long, Gang; Xiao, Jack
Subject: RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu
reset
I think we should evict the bo and then move it back.
Regards,
Hawking
-Original Message-
From: Christian König
Sent: 2019年11月20日 16:47
To: Zhang, Hawking ; Yuan, Xiaojie
; amd-gfx@lists.freedesktop.org
Cc: Long, Gang ; Xiao, Jack
Subject: Re: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu
reset
A baco reset also resets the MC, doesn't it? n this case it would be expected
that the content of VRAM is corrupted.
Christian.
Am 20.11.19 um 09:45 schrieb Zhang, Hawking:
> Or in another word, we are still not clear when the corruption actually
> happens, right?
>
> Regards,
> Hawking
> -Original Message-
> From: amd-gfx On Behalf Of
> Zhang, Hawking
> Sent: 2019年11月20日 16:44
> To: Yuan, Xiaojie ;
> amd-gfx@lists.freedesktop.org
> Cc: Long, Gang ; Xiao, Jack
> Subject: RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer
> after gpu reset
>
> Just make sure I understand you correctly. So until fw team root cause the
> reason of csb corruption, we keep the workaround in driver, correct?
>
> Regards,
> Hawking
> -Original Message-
> From: Yuan, Xiaojie
> Sent: 2019年11月20日 14:47
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhang, Hawking ; Xiao, Jack
> ; Long, Gang ; Yuan, Xiaojie
>
> Subject: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after
> gpu reset
>
> This patch fixes 2nd baco reset failure with gfxoff enabled on navi1x.
>
> clear state buffer (resides in vram) is corrupted after 1st baco reset, upon
> gfxoff exit, CPF gets garbage header in CSIB and hangs.
>
> Signed-off-by: Xiaojie Yuan
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 43 ++
> 1 file changed, 37 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index 9274bd4b6c68..8e24ea08ca39 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -1789,27 +1789,52 @@ static void
> gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
> WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); }
>
> -static void gfx_v10_0_init_csb(struct amdgpu_device *adev)
> +static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
> {
> + int r;
> +
> + if (adev->in_gpu_reset) {
> + r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
> + if (r)
> + return r;
> +
> + r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj,
> +(void **)>gfx.rlc.cs_ptr);
> + if (!r) {
> + adev->gfx.rlc.funcs->get_csb_buffer(adev,
> + adev->gfx.rlc.cs_ptr);
> + amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
> + }
> +
> + amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
> + if (r)
> + return r;
> + }
> +
> /* csib */
> WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
>adev->gfx.rlc.clear_state_gpu_addr >> 32);
> WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
>adev->gfx.rlc.clear_state_gpu_addr & 0xfffc);
> WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH,
> adev->gfx.rlc.clear_state_size);
> +
> + return 0;
> }
>
> -static void gfx_v10_0_init_pg(struct amdgpu_device *adev)
> +static int gfx_v10_0_init_pg(struct amdgpu_device *adev)
> {
> int i;
> + int r;
>
> - gfx_v10_0_init_csb(adev);
> + r = gfx_v10_0_init_csb(adev);
> + if (r)
> + return r;
>
> for (i = 0; i < adev->num_vmhubs; i++)
> amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);
>
> /* TODO: init power gating */
> - return;
> + return 0;
> }
>
> void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) @@ -1911,7 +1936,10 @@
> static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
> r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
> if (r)
> return r;
> - gfx_v10_0_init_pg(adev);
> +
> + r = gfx_v10_0_init_pg(adev);
> + if (r)
> +
Re: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset
Hi Hawking,
This is a formal fix I think.
As you suggested, I tried to dump csb in various locations in gpu reset
sequence:
1. after gfx_v10_0_hw_fini() completes - csb still contains correct data
|
v
baco reset
|
v
2. right after gmc resume - csb contains corrupted data
In this small time window, no firmware touches csb and it should prove that
vram lost causes csb corrupt.
BR,
Xiaojie
From: Zhang, Hawking
Sent: Wednesday, November 20, 2019 4:43 PM
To: Yuan, Xiaojie; amd-gfx@lists.freedesktop.org
Cc: Xiao, Jack; Long, Gang
Subject: RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu
reset
Just make sure I understand you correctly. So until fw team root cause the
reason of csb corruption, we keep the workaround in driver, correct?
Regards,
Hawking
-Original Message-
From: Yuan, Xiaojie
Sent: 2019年11月20日 14:47
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Xiao, Jack ;
Long, Gang ; Yuan, Xiaojie
Subject: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset
This patch fixes 2nd baco reset failure with gfxoff enabled on navi1x.
clear state buffer (resides in vram) is corrupted after 1st baco reset, upon
gfxoff exit, CPF gets garbage header in CSIB and hangs.
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 43 ++
1 file changed, 37 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 9274bd4b6c68..8e24ea08ca39 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -1789,27 +1789,52 @@ static void gfx_v10_0_enable_gui_idle_interrupt(struct
amdgpu_device *adev,
WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); }
-static void gfx_v10_0_init_csb(struct amdgpu_device *adev)
+static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
{
+ int r;
+
+ if (adev->in_gpu_reset) {
+ r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
+ if (r)
+ return r;
+
+ r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj,
+ (void **)>gfx.rlc.cs_ptr);
+ if (!r) {
+ adev->gfx.rlc.funcs->get_csb_buffer(adev,
+ adev->gfx.rlc.cs_ptr);
+ amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
+ }
+
+ amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
+ if (r)
+ return r;
+ }
+
/* csib */
WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
adev->gfx.rlc.clear_state_gpu_addr >> 32);
WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
adev->gfx.rlc.clear_state_gpu_addr & 0xfffc);
WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
+
+ return 0;
}
-static void gfx_v10_0_init_pg(struct amdgpu_device *adev)
+static int gfx_v10_0_init_pg(struct amdgpu_device *adev)
{
int i;
+ int r;
- gfx_v10_0_init_csb(adev);
+ r = gfx_v10_0_init_csb(adev);
+ if (r)
+ return r;
for (i = 0; i < adev->num_vmhubs; i++)
amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);
/* TODO: init power gating */
- return;
+ return 0;
}
void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) @@ -1911,7 +1936,10 @@
static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
if (r)
return r;
- gfx_v10_0_init_pg(adev);
+
+ r = gfx_v10_0_init_pg(adev);
+ if (r)
+ return r;
/* enable RLC SRM */
gfx_v10_0_rlc_enable_srm(adev);
@@ -1937,7 +1965,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device
*adev)
return r;
}
- gfx_v10_0_init_pg(adev);
+ r = gfx_v10_0_init_pg(adev);
+ if (r)
+ return r;
+
adev->gfx.rlc.funcs->start(adev);
if (adev->firmware.load_type ==
AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
--
2.20.1
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Re: [PATCH 2/2] drm/amdgpu: disable gfxoff when using register read interface
Hi Chris,
The info ioctl code path seems already covered at libdrm initialization time:
amdgpu_device_initialize()
-> amdgpu_queury_gpu_info_init()
-> amdgpu_read_mm_registers()
-> drmCommandWrite(fd, DRM_AMDGPU_INFO, ...)
BR,
Xiaojie
From: Christian König
Sent: Tuesday, November 19, 2019 12:18 AM
To: Yuan, Xiaojie; Alex Deucher
Cc: Deucher, Alexander; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/2] drm/amdgpu: disable gfxoff when using register read
interface
Hi Xiaojie,
could you add that test to the unit tests we have in libdrm?
Would be rather nice to have,
Christian.
Am 18.11.19 um 15:09 schrieb Yuan, Xiaojie:
> Hi Alex,
>
> I tried on Navi14 with Gfxoff enabled (gfx in 'OFF' state when I run the test
> program) and used a test program to read GRBM_STATUS/CP_STAT/GB_ADDR_CONFIG
> via DRM_IOCTL_AMDGPU_INFO.
>
> All read out values are valid as below (in this read cycle, I saw gfx block
> is first awakened and then powered off again automatically):
>
> drm version: 3.36.0
> grbm_status: 0x3028
> cp_stat: 0x
> gb_addr_config: 0x0043
>
> At least for Navi, reading register when gfxoff seems not a problem...
>
> Test program:
>
> #include
> #include
> #include
> #include
> #include
> #include
> #include
> #include
> #include
> #include
> #include
> #include
>
> int get_reg_val(int fd, int reg_offset, int *val)
> {
> struct drm_amdgpu_info request;
> int r;
>
> memset(, 0, sizeof(request));
> request.return_pointer = (uintptr_t)val;
> request.return_size = sizeof(uint32_t);
> request.query = AMDGPU_INFO_READ_MMR_REG;
> request.read_mmr_reg.dword_offset = reg_offset;
> request.read_mmr_reg.count = 1;
> request.read_mmr_reg.instance = 0x;
> request.read_mmr_reg.flags = 0;
>
> r = ioctl(fd, DRM_IOCTL_AMDGPU_INFO, );
> if (r < 0) {
> perror("failed to read register");
> return -errno;
> }
>
> return 0;
> }
>
> int main(int argc, const char *argv[])
> {
> const char *device = "/dev/dri/card0";
> int fd;
> int r;
> struct drm_version version;
> struct drm_auth auth;
> int cp_stat;
> int grbm_status;
> int gb_addr_config;
>
> fd = open(device, O_RDWR | O_CLOEXEC);
> if (fd < 0) {
> perror("failed to open device\n");
> return -errno;
> }
>
> memset(, 0, sizeof(version));
>
> r = ioctl(fd, DRM_IOCTL_VERSION, );
> if (r < 0) {
> perror("failed to get drm version");
> r = -errno;
> goto close;
> }
>
> printf("drm version: %d.%d.%d\n", version.version_major,
>version.version_minor,
>version.version_patchlevel);
>
> r = get_reg_val(fd, 0x2004, _status);
> if (r < 0)
> goto close;
> printf("grbm_status: 0x%08x\n", grbm_status);
>
> r = get_reg_val(fd, 0x21a0, _stat);
> if (r < 0)
> goto close;
> printf("cp_stat: 0x%08x\n", cp_stat);
>
> r = get_reg_val(fd, 0x263e, _addr_config);
> if (r < 0)
> goto close;
> printf("gb_addr_config: 0x%08x\n", gb_addr_config);
>
> close:
> close(fd);
>
> return r;
> }
>
> BR,
> Xiaojie
>
>
> From: amd-gfx on behalf of Yuan,
> Xiaojie
> Sent: Saturday, November 16, 2019 1:02 AM
> To: Alex Deucher
> Cc: Deucher, Alexander; amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 2/2] drm/amdgpu: disable gfxoff when using register read
> interface
>
> Yes. IIRC, some asics' amdgpu_gfx_ctrl() is implemented as synchronous (upon
> function returns, gfx block is guaranteed to be in power-up state). Anyway,
> let me confirm about that soon.
>
> BR,
> Xiaojie
>
>> On Nov 16, 2019, at 12:52 AM, Alex Deucher wrote:
>>
>>> On Fri, Nov 15, 2019 at 11:46 AM Yuan, Xiaojie wrote:
>>>
>>> Hi Alex,
>>>
>>> IMHO, driver sending Disallow_Gfxoff message to SMU doesn't mean gfx block
>>> will be immediately powered up, so I'm not sure MMIO register access will
>>> be successful within this time w
Re: [PATCH 2/2] drm/amdgpu: disable gfxoff when using register read interface
Acked-by: Xiaojie Yuan
BR,
Xiaojie
From: Alex Deucher
Sent: Tuesday, November 19, 2019 1:24 AM
To: Yuan, Xiaojie
Cc: Deucher, Alexander; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/2] drm/amdgpu: disable gfxoff when using register read
interface
Can I get an RB or AB on the patch from anyone?
Thanks!
Alex
On Mon, Nov 18, 2019 at 9:09 AM Yuan, Xiaojie wrote:
>
> Hi Alex,
>
> I tried on Navi14 with Gfxoff enabled (gfx in 'OFF' state when I run the test
> program) and used a test program to read GRBM_STATUS/CP_STAT/GB_ADDR_CONFIG
> via DRM_IOCTL_AMDGPU_INFO.
>
> All read out values are valid as below (in this read cycle, I saw gfx block
> is first awakened and then powered off again automatically):
>
> drm version: 3.36.0
> grbm_status: 0x3028
> cp_stat: 0x
> gb_addr_config: 0x0043
>
> At least for Navi, reading register when gfxoff seems not a problem...
>
> Test program:
>
> #include
> #include
> #include
> #include
> #include
> #include
> #include
> #include
> #include
> #include
> #include
> #include
>
> int get_reg_val(int fd, int reg_offset, int *val)
> {
> struct drm_amdgpu_info request;
> int r;
>
> memset(, 0, sizeof(request));
> request.return_pointer = (uintptr_t)val;
> request.return_size = sizeof(uint32_t);
> request.query = AMDGPU_INFO_READ_MMR_REG;
> request.read_mmr_reg.dword_offset = reg_offset;
> request.read_mmr_reg.count = 1;
> request.read_mmr_reg.instance = 0x;
> request.read_mmr_reg.flags = 0;
>
> r = ioctl(fd, DRM_IOCTL_AMDGPU_INFO, );
> if (r < 0) {
> perror("failed to read register");
> return -errno;
> }
>
> return 0;
> }
>
> int main(int argc, const char *argv[])
> {
> const char *device = "/dev/dri/card0";
> int fd;
> int r;
> struct drm_version version;
> struct drm_auth auth;
> int cp_stat;
> int grbm_status;
> int gb_addr_config;
>
> fd = open(device, O_RDWR | O_CLOEXEC);
> if (fd < 0) {
> perror("failed to open device\n");
> return -errno;
> }
>
> memset(, 0, sizeof(version));
>
> r = ioctl(fd, DRM_IOCTL_VERSION, );
> if (r < 0) {
> perror("failed to get drm version");
> r = -errno;
> goto close;
> }
>
> printf("drm version: %d.%d.%d\n", version.version_major,
> version.version_minor,
> version.version_patchlevel);
>
> r = get_reg_val(fd, 0x2004, _status);
> if (r < 0)
> goto close;
> printf("grbm_status: 0x%08x\n", grbm_status);
>
> r = get_reg_val(fd, 0x21a0, _stat);
> if (r < 0)
> goto close;
> printf("cp_stat: 0x%08x\n", cp_stat);
>
> r = get_reg_val(fd, 0x263e, _addr_config);
> if (r < 0)
> goto close;
> printf("gb_addr_config: 0x%08x\n", gb_addr_config);
>
> close:
> close(fd);
>
> return r;
> }
>
> BR,
> Xiaojie
>
>
> From: amd-gfx on behalf of Yuan,
> Xiaojie
> Sent: Saturday, November 16, 2019 1:02 AM
> To: Alex Deucher
> Cc: Deucher, Alexander; amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 2/2] drm/amdgpu: disable gfxoff when using register read
> interface
>
> Yes. IIRC, some asics' amdgpu_gfx_ctrl() is implemented as synchronous (upon
> function returns, gfx block is guaranteed to be in power-up state). Anyway,
> let me confirm about that soon.
>
> BR,
> Xiaojie
>
> > On Nov 16, 2019, at 12:52 AM, Alex Deucher wrote:
> >
> >> On Fri, Nov 15, 2019 at 11:46 AM Yuan, Xiaojie
> >> wrote:
> >>
> >> Hi Alex,
> >>
> >> IMHO, driver sending Disallow_Gfxoff message to SMU doesn't mean gfx block
> >> will be immediately powered up, so I'm not sure MMIO register access will
> >> be successful within this time window(maybe GRBM access will be pending
> >> until gfx block is powered up?)
> >>
> >> If you are not in a hurry to commit this fix, I can verify on my Navi
> >> boards next Monday.
> >
> > That would be great. Maybe we can add a delay in that function to
&
Re: [PATCH 2/2] drm/amdgpu: disable gfxoff when using register read interface
Hi Alex,
I tried on Navi14 with Gfxoff enabled (gfx in 'OFF' state when I run the test
program) and used a test program to read GRBM_STATUS/CP_STAT/GB_ADDR_CONFIG via
DRM_IOCTL_AMDGPU_INFO.
All read out values are valid as below (in this read cycle, I saw gfx block is
first awakened and then powered off again automatically):
drm version: 3.36.0
grbm_status: 0x3028
cp_stat: 0x
gb_addr_config: 0x0043
At least for Navi, reading register when gfxoff seems not a problem...
Test program:
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
int get_reg_val(int fd, int reg_offset, int *val)
{
struct drm_amdgpu_info request;
int r;
memset(, 0, sizeof(request));
request.return_pointer = (uintptr_t)val;
request.return_size = sizeof(uint32_t);
request.query = AMDGPU_INFO_READ_MMR_REG;
request.read_mmr_reg.dword_offset = reg_offset;
request.read_mmr_reg.count = 1;
request.read_mmr_reg.instance = 0x;
request.read_mmr_reg.flags = 0;
r = ioctl(fd, DRM_IOCTL_AMDGPU_INFO, );
if (r < 0) {
perror("failed to read register");
return -errno;
}
return 0;
}
int main(int argc, const char *argv[])
{
const char *device = "/dev/dri/card0";
int fd;
int r;
struct drm_version version;
struct drm_auth auth;
int cp_stat;
int grbm_status;
int gb_addr_config;
fd = open(device, O_RDWR | O_CLOEXEC);
if (fd < 0) {
perror("failed to open device\n");
return -errno;
}
memset(, 0, sizeof(version));
r = ioctl(fd, DRM_IOCTL_VERSION, );
if (r < 0) {
perror("failed to get drm version");
r = -errno;
goto close;
}
printf("drm version: %d.%d.%d\n", version.version_major,
version.version_minor,
version.version_patchlevel);
r = get_reg_val(fd, 0x2004, _status);
if (r < 0)
goto close;
printf("grbm_status: 0x%08x\n", grbm_status);
r = get_reg_val(fd, 0x21a0, _stat);
if (r < 0)
goto close;
printf("cp_stat: 0x%08x\n", cp_stat);
r = get_reg_val(fd, 0x263e, _addr_config);
if (r < 0)
goto close;
printf("gb_addr_config: 0x%08x\n", gb_addr_config);
close:
close(fd);
return r;
}
BR,
Xiaojie
From: amd-gfx on behalf of Yuan,
Xiaojie
Sent: Saturday, November 16, 2019 1:02 AM
To: Alex Deucher
Cc: Deucher, Alexander; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/2] drm/amdgpu: disable gfxoff when using register read
interface
Yes. IIRC, some asics' amdgpu_gfx_ctrl() is implemented as synchronous (upon
function returns, gfx block is guaranteed to be in power-up state). Anyway, let
me confirm about that soon.
BR,
Xiaojie
> On Nov 16, 2019, at 12:52 AM, Alex Deucher wrote:
>
>> On Fri, Nov 15, 2019 at 11:46 AM Yuan, Xiaojie wrote:
>>
>> Hi Alex,
>>
>> IMHO, driver sending Disallow_Gfxoff message to SMU doesn't mean gfx block
>> will be immediately powered up, so I'm not sure MMIO register access will be
>> successful within this time window(maybe GRBM access will be pending until
>> gfx block is powered up?)
>>
>> If you are not in a hurry to commit this fix, I can verify on my Navi boards
>> next Monday.
>
> That would be great. Maybe we can add a delay in that function to
> take that into account?
>
> Thanks!
>
> Alex
>
>>
>> BR,
>> Xiaojie
>>
>>> On Nov 15, 2019, at 12:44 AM, Alex Deucher wrote:
>>>
>>> When gfxoff is enabled, accessing gfx registers via MMIO
>>> can lead to a hang.
>>>
>>> Bug: https://bugzilla.kernel.org/show_bug.cgi?id=205497
>>> Signed-off-by: Alex Deucher
>>> ---
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 6 +-
>>> 1 file changed, 5 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>>> index 6ddea7607ad0..5f3b3a705b29 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>>> @@ -659,15 +659,19 @@ static int amdgpu_info_ioctl(struct drm_device *dev,
>>> void *data, struct drm_file
>>> return -ENOMEM;
>>> alloc_size = info->read_mmr_reg.count * sizeof(*regs);
Re: [PATCH] drm/amdgpu: remove experimental flag for Navi14
Reviewed-by: Xiaojie Yuan
BR,
Xiaojie
> On Nov 15, 2019, at 10:51 PM, Alex Deucher wrote:
>
> 5.4 and newer works fine with navi14.
>
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index e1c15721611a..b19157b19fa0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -1013,10 +1013,10 @@ static const struct pci_device_id pciidlist[] = {
>{0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
>{0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
>/* Navi14 */
> -{0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> CHIP_NAVI14|AMD_EXP_HW_SUPPORT},
> -{0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> CHIP_NAVI14|AMD_EXP_HW_SUPPORT},
> -{0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> CHIP_NAVI14|AMD_EXP_HW_SUPPORT},
> -{0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> CHIP_NAVI14|AMD_EXP_HW_SUPPORT},
> +{0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
> +{0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
> +{0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
> +{0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
>
>/* Renoir */
>{0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> CHIP_RENOIR|AMD_IS_APU|AMD_EXP_HW_SUPPORT},
> --
> 2.23.0
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
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Re: [PATCH 2/2] drm/amdgpu: disable gfxoff when using register read interface
Yes. IIRC, some asics' amdgpu_gfx_ctrl() is implemented as synchronous (upon
function returns, gfx block is guaranteed to be in power-up state). Anyway, let
me confirm about that soon.
BR,
Xiaojie
> On Nov 16, 2019, at 12:52 AM, Alex Deucher wrote:
>
>> On Fri, Nov 15, 2019 at 11:46 AM Yuan, Xiaojie wrote:
>>
>> Hi Alex,
>>
>> IMHO, driver sending Disallow_Gfxoff message to SMU doesn't mean gfx block
>> will be immediately powered up, so I'm not sure MMIO register access will be
>> successful within this time window(maybe GRBM access will be pending until
>> gfx block is powered up?)
>>
>> If you are not in a hurry to commit this fix, I can verify on my Navi boards
>> next Monday.
>
> That would be great. Maybe we can add a delay in that function to
> take that into account?
>
> Thanks!
>
> Alex
>
>>
>> BR,
>> Xiaojie
>>
>>> On Nov 15, 2019, at 12:44 AM, Alex Deucher wrote:
>>>
>>> When gfxoff is enabled, accessing gfx registers via MMIO
>>> can lead to a hang.
>>>
>>> Bug: https://bugzilla.kernel.org/show_bug.cgi?id=205497
>>> Signed-off-by: Alex Deucher
>>> ---
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 6 +-
>>> 1 file changed, 5 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>>> index 6ddea7607ad0..5f3b3a705b29 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>>> @@ -659,15 +659,19 @@ static int amdgpu_info_ioctl(struct drm_device *dev,
>>> void *data, struct drm_file
>>> return -ENOMEM;
>>> alloc_size = info->read_mmr_reg.count * sizeof(*regs);
>>>
>>> -for (i = 0; i < info->read_mmr_reg.count; i++)
>>> +amdgpu_gfx_off_ctrl(adev, false);
>>> +for (i = 0; i < info->read_mmr_reg.count; i++) {
>>> if (amdgpu_asic_read_register(adev, se_num, sh_num,
>>> info->read_mmr_reg.dword_offset + i,
>>> [i])) {
>>> DRM_DEBUG_KMS("unallowed offset %#x\n",
>>> info->read_mmr_reg.dword_offset + i);
>>> kfree(regs);
>>> +amdgpu_gfx_off_ctrl(adev, true);
>>> return -EFAULT;
>>> }
>>> +}
>>> +amdgpu_gfx_off_ctrl(adev, true);
>>> n = copy_to_user(out, regs, min(size, alloc_size));
>>> kfree(regs);
>>> return n ? -EFAULT : 0;
>>> --
>>> 2.23.0
>>>
>>> ___
>>> amd-gfx mailing list
>>> amd-gfx@lists.freedesktop.org
>>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
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Re: [PATCH] drm/amdgpu/nv: add asic func for fetching vbios from rom directly
Reviewed-by: Xiaojie Yuan
BR,
Xiaojie
> On Nov 16, 2019, at 12:12 AM, Alex Deucher wrote:
>
> Ping?
>
>> On Wed, Nov 13, 2019 at 2:29 PM Alex Deucher wrote:
>>
>> Needed as a fallback if the vbios can't be fetched by other means.
>>
>> Signed-off-by: Alex Deucher
>> ---
>> drivers/gpu/drm/amd/amdgpu/nv.c | 24 ++--
>> 1 file changed, 22 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c
>> b/drivers/gpu/drm/amd/amdgpu/nv.c
>> index 7283d6198b89..ad04d1d6e9c7 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/nv.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
>> @@ -40,6 +40,7 @@
>> #include "gc/gc_10_1_0_sh_mask.h"
>> #include "hdp/hdp_5_0_0_offset.h"
>> #include "hdp/hdp_5_0_0_sh_mask.h"
>> +#include "smuio/smuio_11_0_0_offset.h"
>>
>> #include "soc15.h"
>> #include "soc15_common.h"
>> @@ -156,8 +157,27 @@ static bool nv_read_disabled_bios(struct amdgpu_device
>> *adev)
>> static bool nv_read_bios_from_rom(struct amdgpu_device *adev,
>> u8 *bios, u32 length_bytes)
>> {
>> - /* TODO: will implement it when SMU header is available */
>> - return false;
>> + u32 *dw_ptr;
>> + u32 i, length_dw;
>> +
>> + if (bios == NULL)
>> + return false;
>> + if (length_bytes == 0)
>> + return false;
>> + /* APU vbios image is part of sbios image */
>> + if (adev->flags & AMD_IS_APU)
>> + return false;
>> +
>> + dw_ptr = (u32 *)bios;
>> + length_dw = ALIGN(length_bytes, 4) / 4;
>> +
>> + /* set rom index to 0 */
>> + WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0);
>> + /* read out the rom data */
>> + for (i = 0; i < length_dw; i++)
>> + dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA));
>> +
>> + return true;
>> }
>>
>> static struct soc15_allowed_register_entry nv_allowed_read_registers[] = {
>> --
>> 2.23.0
>>
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Re: [PATCH 2/2] drm/amdgpu: disable gfxoff when using register read interface
Hi Alex,
IMHO, driver sending Disallow_Gfxoff message to SMU doesn't mean gfx block will
be immediately powered up, so I'm not sure MMIO register access will be
successful within this time window(maybe GRBM access will be pending until gfx
block is powered up?)
If you are not in a hurry to commit this fix, I can verify on my Navi boards
next Monday.
BR,
Xiaojie
> On Nov 15, 2019, at 12:44 AM, Alex Deucher wrote:
>
> When gfxoff is enabled, accessing gfx registers via MMIO
> can lead to a hang.
>
> Bug: https://bugzilla.kernel.org/show_bug.cgi?id=205497
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 6 +-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> index 6ddea7607ad0..5f3b3a705b29 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> @@ -659,15 +659,19 @@ static int amdgpu_info_ioctl(struct drm_device *dev,
> void *data, struct drm_file
>return -ENOMEM;
>alloc_size = info->read_mmr_reg.count * sizeof(*regs);
>
> -for (i = 0; i < info->read_mmr_reg.count; i++)
> +amdgpu_gfx_off_ctrl(adev, false);
> +for (i = 0; i < info->read_mmr_reg.count; i++) {
>if (amdgpu_asic_read_register(adev, se_num, sh_num,
> info->read_mmr_reg.dword_offset + i,
> [i])) {
>DRM_DEBUG_KMS("unallowed offset %#x\n",
> info->read_mmr_reg.dword_offset + i);
>kfree(regs);
> +amdgpu_gfx_off_ctrl(adev, true);
>return -EFAULT;
>}
> +}
> +amdgpu_gfx_off_ctrl(adev, true);
>n = copy_to_user(out, regs, min(size, alloc_size));
>kfree(regs);
>return n ? -EFAULT : 0;
> --
> 2.23.0
>
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Re: [PATCH v2] drm/amdgpu: Need to free discovery memory
Please use 'drm/amdgpu/discovery: ' prefix in commit message to let us easily track all discovery-releated changes. Other than this, patch is Reviewed-by: Xiaojie Yuan BR, Xiaojie From: amd-gfx on behalf of Emily Deng Sent: Monday, November 4, 2019 11:03 AM To: amd-gfx@lists.freedesktop.org Cc: Deng, Emily Subject: [PATCH v2] drm/amdgpu: Need to free discovery memory When unloading driver, need to free discovery memory. Signed-off-by: Emily Deng --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 28b09f6..7cbe6d9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -2106,9 +2106,6 @@ void amdgpu_ttm_late_init(struct amdgpu_device *adev) void *stolen_vga_buf; /* return the VGA stolen memory (if any) back to VRAM */ amdgpu_bo_free_kernel(>stolen_vga_memory, NULL, _vga_buf); - - /* return the IP Discovery TMR memory back to VRAM */ - amdgpu_bo_free_kernel(>discovery_memory, NULL, NULL); } /** @@ -2121,7 +2118,10 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev) amdgpu_ttm_debugfs_fini(adev); amdgpu_ttm_training_reserve_vram_fini(adev); + /* return the IP Discovery TMR memory back to VRAM */ + amdgpu_bo_free_kernel(>discovery_memory, NULL, NULL); amdgpu_ttm_fw_reserve_vram_fini(adev); + if (adev->mman.aper_base_kaddr) iounmap(adev->mman.aper_base_kaddr); adev->mman.aper_base_kaddr = NULL; -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: Need to free discovery memory
Hi Emily,
Thanks for catching this.
I think freeing Discovery TMR bo should be put at amdgpu_ttm_fini() instead of
amdgpu_ttm_late_init() because unlike VGA stolen bo, touching PSP-protected
Discovery TMR bo will cause GPU hang. Therefore, it should be reserved across
the life-cycle of amdgpu driver.
Please kindly send v2 patch with this change.
BR,
Xiaojie
From: amd-gfx on behalf of Emily Deng
Sent: Friday, November 1, 2019 5:07 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deng, Emily
Subject: [PATCH] drm/amdgpu: Need to free discovery memory
When unloading driver, need to free discovery memory.
Signed-off-by: Emily Deng
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 9f2a893..50d6ed2 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -1091,8 +1091,11 @@ static int gmc_v9_0_sw_fini(void *handle)
amdgpu_gem_force_release(adev);
amdgpu_vm_manager_fini(adev);
- if (gmc_v9_0_keep_stolen_memory(adev))
+ if (gmc_v9_0_keep_stolen_memory(adev)) {
amdgpu_bo_free_kernel(>stolen_vga_memory, NULL,
_vga_buf);
+ /* return the IP Discovery TMR memory back to VRAM */
+ amdgpu_bo_free_kernel(>discovery_memory, NULL, NULL);
+ }
amdgpu_gart_table_vram_free(adev);
amdgpu_bo_fini(adev);
--
2.7.4
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[PATCH] drm/amd/powerplay: print the pptable provider
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 7e882999abad..0f7504ae2395 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -368,6 +368,7 @@ int smu_v11_0_setup_pptable(struct smu_context *smu)
version_major = le16_to_cpu(hdr->header.header_version_major);
version_minor = le16_to_cpu(hdr->header.header_version_minor);
if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
+ pr_info("use driver provided pptable %d\n",
smu->smu_table.boot_values.pp_table_id);
switch (version_minor) {
case 0:
ret = smu_v11_0_set_pptable_v2_0(smu, , );
@@ -384,6 +385,7 @@ int smu_v11_0_setup_pptable(struct smu_context *smu)
return ret;
} else {
+ pr_info("use vbios provided pptable\n");
index =
get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
powerplayinfo);
--
2.20.1
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[PATCH] drm/amdgpu/gfx10: fix mqd backup/restore for gfx rings
1. no need to allocate an extra member for 'mqd_backup' array
2. backup/restore mqd to/from the correct 'mqd_backup' array slot
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 2 +-
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 9 +
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 459aa9059542..6d19e7891491 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -225,7 +225,7 @@ struct amdgpu_me {
uint32_tnum_me;
uint32_tnum_pipe_per_me;
uint32_tnum_queue_per_pipe;
- void*mqd_backup[AMDGPU_MAX_GFX_RINGS + 1];
+ void*mqd_backup[AMDGPU_MAX_GFX_RINGS];
/* These are the resources for which amdgpu takes ownership */
DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index ef1975a5323a..2c5dc9b58e23 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3075,6 +3075,7 @@ static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring
*ring)
{
struct amdgpu_device *adev = ring->adev;
struct v10_gfx_mqd *mqd = ring->mqd_ptr;
+ int mqd_idx = ring - >gfx.gfx_ring[0];
if (!adev->in_gpu_reset && !adev->in_suspend) {
memset((void *)mqd, 0, sizeof(*mqd));
@@ -3086,12 +3087,12 @@ static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring
*ring)
#endif
nv_grbm_select(adev, 0, 0, 0, 0);
mutex_unlock(>srbm_mutex);
- if (adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS])
- memcpy(adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS],
mqd, sizeof(*mqd));
+ if (adev->gfx.me.mqd_backup[mqd_idx])
+ memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd,
sizeof(*mqd));
} else if (adev->in_gpu_reset) {
/* reset mqd with the backup copy */
- if (adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS])
- memcpy(mqd,
adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS], sizeof(*mqd));
+ if (adev->gfx.me.mqd_backup[mqd_idx])
+ memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx],
sizeof(*mqd));
/* reset the ring */
ring->wptr = 0;
amdgpu_ring_clear_ring(ring);
--
2.20.1
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[PATCH 2/2] drm/amdgpu/psp11: fix typo in comment
Signed-off-by: Xiaojie Yuan --- drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c index dfe85a1d79a5..4eb5bacb55f7 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c @@ -232,7 +232,7 @@ static int psp_v11_0_bootloader_load_kdb(struct psp_context *psp) /* Copy PSP KDB binary to memory */ memcpy(psp->fw_pri_buf, psp->kdb_start_addr, psp->kdb_bin_size); - /* Provide the sys driver to bootloader */ + /* Provide the PSP KDB to bootloader */ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, (uint32_t)(psp->fw_pri_mc_addr >> 20)); psp_gfxdrv_command_reg = PSP_BL__LOAD_KEY_DATABASE; -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 1/2] drm/amdgpu/psp11: wait for sOS ready for ring creation
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index e8e70b74ea5b..dfe85a1d79a5 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -459,6 +459,14 @@ static int psp_v11_0_ring_create(struct psp_context *psp,
0x8000, 0x8000, false);
} else {
+ /* Wait for sOS ready for ring creation */
+ ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0,
mmMP0_SMN_C2PMSG_64),
+ 0x8000, 0x8000, false);
+ if (ret) {
+ DRM_ERROR("Failed to wait for sOS ready for ring
creation\n");
+ return ret;
+ }
+
/* Write low address of the ring to C2PMSG_69 */
psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
--
2.20.1
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[PATCH] drm/amd/powerplay: print where the pptable comes from
this helps to know whether the pptable is from firmware or vbios
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 9883f0a4471a..809883c21241 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -369,6 +369,9 @@ static int smu_v11_0_setup_pptable(struct smu_context *smu)
version_major = le16_to_cpu(hdr->header.header_version_major);
version_minor = le16_to_cpu(hdr->header.header_version_minor);
if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
+ pr_info("using soft pptable #%d\n",
+ smu->smu_table.boot_values.pp_table_id);
+
switch (version_minor) {
case 0:
ret = smu_v11_0_set_pptable_v2_0(smu, , );
@@ -385,6 +388,8 @@ static int smu_v11_0_setup_pptable(struct smu_context *smu)
return ret;
} else {
+ pr_info("using pptable from vbios\n");
+
index =
get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
powerplayinfo);
--
2.20.1
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Re: [PATCH 2/2] drm/amd/powerplay: re-enable FW_DSTATE feature bit
Hi there,
Could someone give an RB or ACK? This patch has been verified on both navi12
and navi14.
Thanks.
BR,
Xiaojie
From: Deucher, Alexander
Sent: Thursday, October 10, 2019 8:20 PM
To: Feng, Kenneth ; Yuan, Xiaojie ;
amd-gfx@lists.freedesktop.org
Cc: Xiao, Jack ; Wang, Kevin(Yang) ;
Zhang, Hawking ; Quan, Evan
Subject: Re: [PATCH 2/2] drm/amd/powerplay: re-enable FW_DSTATE feature bit
Great. thanks!
Alex
From: Feng, Kenneth
Sent: Thursday, October 10, 2019 3:00 AM
To: Yuan, Xiaojie ; Deucher, Alexander
; amd-gfx@lists.freedesktop.org
Cc: Xiao, Jack ; Wang, Kevin(Yang) ;
Zhang, Hawking ; Quan, Evan
Subject: RE: [PATCH 2/2] drm/amd/powerplay: re-enable FW_DSTATE feature bit
Hi Alex,
This issue was navi10 specific and was found in May, 2019.
It was early after the asic back, then since gfxoff was removed from navi10, we
didn’t really verify which firmware version started to have a fix.
For navi14/navi12, there’s no such issue at all.
Sorry for losing the track of it.
From: Yuan, Xiaojie
Sent: Thursday, October 10, 2019 1:17 AM
To: Deucher, Alexander ;
amd-gfx@lists.freedesktop.org
Cc: Xiao, Jack ; Wang, Kevin(Yang) ;
Zhang, Hawking ; Quan, Evan ; Feng,
Kenneth
Subject: Re: [PATCH 2/2] drm/amd/powerplay: re-enable FW_DSTATE feature bit
Hi Alex,
For now, gfxoff for navi10 is disabled by default, and I also verified on
navi14 with both GFXOFF and FW_DSTATE feature bits toggled on.
Hi Kenneth / Jack,
Could you help to confirm the firmware version?
BR,
Xiaojie
From: Deucher, Alexander
mailto:alexander.deuc...@amd.com>>
Sent: Wednesday, October 9, 2019 9:35 PM
To: Yuan, Xiaojie mailto:xiaojie.y...@amd.com>>;
amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org>
mailto:amd-gfx@lists.freedesktop.org>>
Cc: Xiao, Jack mailto:jack.x...@amd.com>>; Wang, Kevin(Yang)
mailto:kevin1.w...@amd.com>>; Zhang, Hawking
mailto:hawking.zh...@amd.com>>; Quan, Evan
mailto:evan.q...@amd.com>>; Feng, Kenneth
mailto:kenneth.f...@amd.com>>
Subject: Re: [PATCH 2/2] drm/amd/powerplay: re-enable FW_DSTATE feature bit
What version of firmware has the fix? Was it recently fixed? We should check
the version if the old one may be out in the wild.
Alex
From: amd-gfx
mailto:amd-gfx-boun...@lists.freedesktop.org>>
on behalf of Yuan, Xiaojie mailto:xiaojie.y...@amd.com>>
Sent: Wednesday, October 9, 2019 7:08 AM
To: amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org>
mailto:amd-gfx@lists.freedesktop.org>>
Cc: Xiao, Jack mailto:jack.x...@amd.com>>; Wang, Kevin(Yang)
mailto:kevin1.w...@amd.com>>; Zhang, Hawking
mailto:hawking.zh...@amd.com>>; Quan, Evan
mailto:evan.q...@amd.com>>; Feng, Kenneth
mailto:kenneth.f...@amd.com>>; Yuan, Xiaojie
mailto:xiaojie.y...@amd.com>>
Subject: [PATCH 2/2] drm/amd/powerplay: re-enable FW_DSTATE feature bit
SMU firmware has fix the bug, so remove this workaround.
Signed-off-by: Xiaojie Yuan mailto:xiaojie.y...@amd.com>>
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 44152c1f01c7..3628295469c4 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -359,11 +359,8 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
| FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
| FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
- if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
+ if (adev->pm.pp_feature & PP_GFXOFF_MASK)
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
- /* TODO: remove it once fw fix the bug */
- *(uint64_t *)feature_mask &=
~FEATURE_MASK(FEATURE_FW_DSTATE_BIT);
- }
if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
*(uint64_t *)feature_mask |=
FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
--
2.20.1
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[PATCH v2] drm/amdgpu/discovery: reserve discovery data at the top of VRAM
IP Discovery data is TMR fenced by the latest PSP BL,
so we need to reserve this region.
Tested on navi10/12/14 with VBIOS integrated with latest PSP BL.
v2: use DISCOVERY_TMR_SIZE macro as bo size
use amdgpu_bo_create_kernel_at() to allocate bo
Signed-off-by: Xiaojie Yuan
Reviewed-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 17 +
drivers/gpu/drm/amd/include/discovery.h | 1 -
5 files changed, 22 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index be0b2c69c223..6775647f0ba5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -812,6 +812,7 @@ struct amdgpu_device {
uint8_t *bios;
uint32_tbios_size;
struct amdgpu_bo*stolen_vga_memory;
+ struct amdgpu_bo*discovery_memory;
uint32_tbios_scratch_reg_offset;
uint32_tbios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 1481899f86c1..71198c5318e1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -136,7 +136,7 @@ static int amdgpu_discovery_read_binary(struct
amdgpu_device *adev, uint8_t *bin
{
uint32_t *p = (uint32_t *)binary;
uint64_t vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20;
- uint64_t pos = vram_size - BINARY_MAX_SIZE;
+ uint64_t pos = vram_size - DISCOVERY_TMR_SIZE;
unsigned long flags;
while (pos < vram_size) {
@@ -179,7 +179,7 @@ int amdgpu_discovery_init(struct amdgpu_device *adev)
uint16_t checksum;
int r;
- adev->discovery = kzalloc(BINARY_MAX_SIZE, GFP_KERNEL);
+ adev->discovery = kzalloc(DISCOVERY_TMR_SIZE, GFP_KERNEL);
if (!adev->discovery)
return -ENOMEM;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h
index 85b8c4d4d576..5a6693d7d269 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h
@@ -24,6 +24,8 @@
#ifndef __AMDGPU_DISCOVERY__
#define __AMDGPU_DISCOVERY__
+#define DISCOVERY_TMR_SIZE (64 << 10)
+
int amdgpu_discovery_init(struct amdgpu_device *adev);
void amdgpu_discovery_fini(struct amdgpu_device *adev);
int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index edffc883549a..ed7b10e0848d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1955,6 +1955,20 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
NULL, _vga_buf);
if (r)
return r;
+
+ /*
+* reserve one TMR (64K) memory at the top of VRAM which holds
+* IP Discovery data and is protected by PSP.
+*/
+ r = amdgpu_bo_create_kernel_at(adev,
+ adev->gmc.real_vram_size -
DISCOVERY_TMR_SIZE,
+ DISCOVERY_TMR_SIZE,
+ AMDGPU_GEM_DOMAIN_VRAM,
+ >discovery_memory,
+ NULL);
+ if (r)
+ return r;
+
DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
(unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
@@ -2024,6 +2038,9 @@ void amdgpu_ttm_late_init(struct amdgpu_device *adev)
void *stolen_vga_buf;
/* return the VGA stolen memory (if any) back to VRAM */
amdgpu_bo_free_kernel(>stolen_vga_memory, NULL, _vga_buf);
+
+ /* return the IP Discovery TMR memory back to VRAM */
+ amdgpu_bo_free_kernel(>discovery_memory, NULL, NULL);
}
/**
diff --git a/drivers/gpu/drm/amd/include/discovery.h
b/drivers/gpu/drm/amd/include/discovery.h
index 5dcb776548d8..7ec4331e67f2 100644
--- a/drivers/gpu/drm/amd/include/discovery.h
+++ b/drivers/gpu/drm/amd/include/discovery.h
@@ -25,7 +25,6 @@
#define _DISCOVERY_H_
#define PSP_HEADER_SIZE 256
-#define BINARY_MAX_SIZE (64 << 10)
#define BINARY_SIGNATURE0x28211407
#define DISCOVERY_TABLE_SIGNATURE 0x53445049
--
2.20.1
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Re: [PATCH] drm/amdgpu/discovery: reserve discovery data at the top of VRAM
Thanks Alex. I'll try to use the new api and send v2 patch.
BR,
Xiaojie
From: Alex Deucher
Sent: Thursday, October 10, 2019 8:57 PM
To: Yuan, Xiaojie
Cc: amd-gfx@lists.freedesktop.org ; Xiao, Jack
; Zhang, Hawking
Subject: Re: [PATCH] drm/amdgpu/discovery: reserve discovery data at the top of
VRAM
On Thu, Oct 10, 2019 at 8:48 AM Yuan, Xiaojie wrote:
>
> IP Discovery data is TMR fenced by the latest PSP BL,
> so we need to reserve this region.
>
> Signed-off-by: Xiaojie Yuan
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 15 +++
> 2 files changed, 16 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index be0b2c69c223..6775647f0ba5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -812,6 +812,7 @@ struct amdgpu_device {
> uint8_t *bios;
> uint32_tbios_size;
> struct amdgpu_bo*stolen_vga_memory;
> + struct amdgpu_bo*discovery_memory;
> uint32_tbios_scratch_reg_offset;
> uint32_tbios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index edffc883549a..c3d7eb685a23 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -1955,6 +1955,18 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
> NULL, _vga_buf);
> if (r)
> return r;
> +
> + /*
> +* reserve one TMR (64K) memory at the top of VRAM which holds
> +* IP Discovery data and is protected by PSP.
> +*/
> + r = amdgpu_bo_create_kernel(adev, 64 << 10, PAGE_SIZE,
> + AMDGPU_GEM_DOMAIN_VRAM,
> + >discovery_memory,
> + NULL, NULL);
> + if (r)
> + return r;
> +
I think we should use amdgpu_bo_create_kernel_at() for both this and
stolen_vga_memory so that we make sure we end up reserving the right
location since both of these buffers are created by firmware at fixed
locations.
Alex
> DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
> (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
>
> @@ -2024,6 +2036,9 @@ void amdgpu_ttm_late_init(struct amdgpu_device *adev)
> void *stolen_vga_buf;
> /* return the VGA stolen memory (if any) back to VRAM */
> amdgpu_bo_free_kernel(>stolen_vga_memory, NULL,
> _vga_buf);
> +
> + /* return the IP Discovery TMR memory back to VRAM */
> + amdgpu_bo_free_kernel(>discovery_memory, NULL, NULL);
> }
>
> /**
> --
> 2.20.1
>
> ___
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[PATCH] drm/amdgpu/discovery: reserve discovery data at the top of VRAM
IP Discovery data is TMR fenced by the latest PSP BL,
so we need to reserve this region.
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 15 +++
2 files changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index be0b2c69c223..6775647f0ba5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -812,6 +812,7 @@ struct amdgpu_device {
uint8_t *bios;
uint32_tbios_size;
struct amdgpu_bo*stolen_vga_memory;
+ struct amdgpu_bo*discovery_memory;
uint32_tbios_scratch_reg_offset;
uint32_tbios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index edffc883549a..c3d7eb685a23 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1955,6 +1955,18 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
NULL, _vga_buf);
if (r)
return r;
+
+ /*
+* reserve one TMR (64K) memory at the top of VRAM which holds
+* IP Discovery data and is protected by PSP.
+*/
+ r = amdgpu_bo_create_kernel(adev, 64 << 10, PAGE_SIZE,
+ AMDGPU_GEM_DOMAIN_VRAM,
+ >discovery_memory,
+ NULL, NULL);
+ if (r)
+ return r;
+
DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
(unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
@@ -2024,6 +2036,9 @@ void amdgpu_ttm_late_init(struct amdgpu_device *adev)
void *stolen_vga_buf;
/* return the VGA stolen memory (if any) back to VRAM */
amdgpu_bo_free_kernel(>stolen_vga_memory, NULL, _vga_buf);
+
+ /* return the IP Discovery TMR memory back to VRAM */
+ amdgpu_bo_free_kernel(>discovery_memory, NULL, NULL);
}
/**
--
2.20.1
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Re: [PATCH 1/2] drm/amd/powerplay: add more feature bits
Ping ... BR, Xiaojie From: Yuan, Xiaojie Sent: Wednesday, October 9, 2019 7:08 PM To: amd-gfx@lists.freedesktop.org Cc: Zhang, Hawking ; Xiao, Jack ; Feng, Kenneth ; Quan, Evan ; Wang, Kevin(Yang) ; Yuan, Xiaojie Subject: [PATCH 1/2] drm/amd/powerplay: add more feature bits Signed-off-by: Xiaojie Yuan --- drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c index 5a34d01f7f7c..44152c1f01c7 100644 --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c @@ -337,19 +337,22 @@ navi10_get_allowed_feature_mask(struct smu_context *smu, | FEATURE_MASK(FEATURE_PPT_BIT) | FEATURE_MASK(FEATURE_TDC_BIT) | FEATURE_MASK(FEATURE_GFX_EDC_BIT) + | FEATURE_MASK(FEATURE_APCC_PLUS_BIT) | FEATURE_MASK(FEATURE_VR0HOT_BIT) | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT) | FEATURE_MASK(FEATURE_THERMAL_BIT) | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT) | FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT) | FEATURE_MASK(FEATURE_DS_GFXCLK_BIT) + | FEATURE_MASK(FEATURE_DS_LCLK_BIT) | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT) | FEATURE_MASK(FEATURE_FW_DSTATE_BIT) | FEATURE_MASK(FEATURE_BACO_BIT) | FEATURE_MASK(FEATURE_ACDC_BIT) | FEATURE_MASK(FEATURE_GFX_SS_BIT) | FEATURE_MASK(FEATURE_APCC_DFLL_BIT) - | FEATURE_MASK(FEATURE_FW_CTF_BIT); + | FEATURE_MASK(FEATURE_FW_CTF_BIT) + | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT); if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT) -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 2/2] drm/amd/powerplay: re-enable FW_DSTATE feature bit
Hi Alex,
For now, gfxoff for navi10 is disabled by default, and I also verified on
navi14 with both GFXOFF and FW_DSTATE feature bits toggled on.
Hi Kenneth / Jack,
Could you help to confirm the firmware version?
BR,
Xiaojie
From: Deucher, Alexander
Sent: Wednesday, October 9, 2019 9:35 PM
To: Yuan, Xiaojie ; amd-gfx@lists.freedesktop.org
Cc: Xiao, Jack ; Wang, Kevin(Yang) ;
Zhang, Hawking ; Quan, Evan ; Feng,
Kenneth
Subject: Re: [PATCH 2/2] drm/amd/powerplay: re-enable FW_DSTATE feature bit
What version of firmware has the fix? Was it recently fixed? We should check
the version if the old one may be out in the wild.
Alex
From: amd-gfx on behalf of Yuan,
Xiaojie
Sent: Wednesday, October 9, 2019 7:08 AM
To: amd-gfx@lists.freedesktop.org
Cc: Xiao, Jack ; Wang, Kevin(Yang) ;
Zhang, Hawking ; Quan, Evan ; Feng,
Kenneth ; Yuan, Xiaojie
Subject: [PATCH 2/2] drm/amd/powerplay: re-enable FW_DSTATE feature bit
SMU firmware has fix the bug, so remove this workaround.
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 44152c1f01c7..3628295469c4 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -359,11 +359,8 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
| FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
| FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
- if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
+ if (adev->pm.pp_feature & PP_GFXOFF_MASK)
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
- /* TODO: remove it once fw fix the bug */
- *(uint64_t *)feature_mask &=
~FEATURE_MASK(FEATURE_FW_DSTATE_BIT);
- }
if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
*(uint64_t *)feature_mask |=
FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
--
2.20.1
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[PATCH] drm/amdgpu/sdma5: fix mask value of POLL_REGMEM packet for pipe sync
sdma will hang once sequence number to be polled reaches 0x1000_ Signed-off-by: Xiaojie Yuan --- drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c index ad5c3566337c..3460c00f3eaa 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c @@ -1126,7 +1126,7 @@ static void sdma_v5_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) amdgpu_ring_write(ring, addr & 0xfffc); amdgpu_ring_write(ring, upper_32_bits(addr) & 0x); amdgpu_ring_write(ring, seq); /* reference */ - amdgpu_ring_write(ring, 0xfff); /* mask */ + amdgpu_ring_write(ring, 0x); /* mask */ amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ } -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 2/2] drm/amd/powerplay: re-enable FW_DSTATE feature bit
SMU firmware has fix the bug, so remove this workaround.
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 44152c1f01c7..3628295469c4 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -359,11 +359,8 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
| FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
| FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
- if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
+ if (adev->pm.pp_feature & PP_GFXOFF_MASK)
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
- /* TODO: remove it once fw fix the bug */
- *(uint64_t *)feature_mask &=
~FEATURE_MASK(FEATURE_FW_DSTATE_BIT);
- }
if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
--
2.20.1
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[PATCH 1/2] drm/amd/powerplay: add more feature bits
Signed-off-by: Xiaojie Yuan --- drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c index 5a34d01f7f7c..44152c1f01c7 100644 --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c @@ -337,19 +337,22 @@ navi10_get_allowed_feature_mask(struct smu_context *smu, | FEATURE_MASK(FEATURE_PPT_BIT) | FEATURE_MASK(FEATURE_TDC_BIT) | FEATURE_MASK(FEATURE_GFX_EDC_BIT) + | FEATURE_MASK(FEATURE_APCC_PLUS_BIT) | FEATURE_MASK(FEATURE_VR0HOT_BIT) | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT) | FEATURE_MASK(FEATURE_THERMAL_BIT) | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT) | FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT) | FEATURE_MASK(FEATURE_DS_GFXCLK_BIT) + | FEATURE_MASK(FEATURE_DS_LCLK_BIT) | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT) | FEATURE_MASK(FEATURE_FW_DSTATE_BIT) | FEATURE_MASK(FEATURE_BACO_BIT) | FEATURE_MASK(FEATURE_ACDC_BIT) | FEATURE_MASK(FEATURE_GFX_SS_BIT) | FEATURE_MASK(FEATURE_APCC_DFLL_BIT) - | FEATURE_MASK(FEATURE_FW_CTF_BIT); + | FEATURE_MASK(FEATURE_FW_CTF_BIT) + | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT); if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT) -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu/gmc10: apply the 'invalidation from sdma' workaround for navi
Hi Alex / Christian,
When gfxoff is enabled for Navi12, I observed sdma0 hang while launching
desktop. When this workaround is applied, the issue fades away.
That's why I included this workaround for Navi12 as well.
BR,
Xiaojie
From: Koenig, Christian
Sent: Thursday, September 26, 2019 10:20 PM
To: Alex Deucher
Cc: Deucher, Alexander ; Yuan, Xiaojie
; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu/gmc10: apply the 'invalidation from sdma'
workaround for navi
Am 26.09.2019 15:51 schrieb Alex Deucher :
On Thu, Sep 26, 2019 at 9:47 AM Koenig, Christian
wrote:
>
> Am 26.09.19 um 15:40 schrieb Alex Deucher:
> > On Thu, Sep 26, 2019 at 8:29 AM Christian König
> > wrote:
> >> Stop, wait a second guys!
> >>
> >> This will disable the workaround for Navi10 and that is certainly not
> >> correct:
> >>
> >> !(adev->asic_type >= CHIP_NAVI10 && adev->asic_type <= CHIP_NAVI12)
> >>
> > Actually, I think it's correct. When I merged the baco patch, I
> > accidentally dropped the navi checks. E.g.,
> > @@ -245,8 +245,9 @@ static void gmc_v10_0_flush_gpu_tlb(struct
> > amdgpu_device *adev,
> > mutex_lock(>mman.gtt_window_lock);
> >
> > gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB, 0);
> > - if (!adev->mman.buffer_funcs_enabled || !adev->ib_pool_ready ||
> > - adev->asic_type != CHIP_NAVI10) {
> > + if (!adev->mman.buffer_funcs_enabled ||
> > + !adev->ib_pool_ready ||
> > + adev->in_gpu_reset) {
> > gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB, 0);
> > mutex_unlock(>mman.gtt_window_lock);
> > return;
> > I think it should have been
> > adev->asic_type != CHIP_NAVI10 && adev->asic_type != CHIP_NAVI14 &&
> > adev->asic_type != CHIP_NAVI12
>
> My last status is that Navi12 is not supposed to need that workaround,
> that's why we checked Navi10 and later Navi14 separately.
>
> It's possible that I miss-read the !(adev->asic_type >= CHIP_NAVI10 &&
> adev->asic_type <= CHIP_NAVI12) check here, but either way that looks to
> complicated to me.
>
> We should rather mention every affected asic type separately here.
Good point. navi12 should be dropped from the check. How about the following?
I would rather test explicitly for Navi 10 and 14, cause we can't be sure if
there won't be another variant in the future.
Christian.
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index 241a4e57cf4a..280bbd7ca8a0 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -292,7 +292,8 @@ static void gmc_v10_0_flush_gpu_tlb(struct
amdgpu_device *adev, uint32_t vmid,
if (!adev->mman.buffer_funcs_enabled ||
!adev->ib_pool_ready ||
- adev->in_gpu_reset) {
+ adev->in_gpu_reset ||
+ (adev->asic_type == CHIP_NAVI12)) {
gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0);
mutex_unlock(>mman.gtt_window_lock);
return;
Alex
>
> Regards,
> Christian.
>
> >
> > Alex
> >
> >> Christian.
> >>
> >>
> >> Am 26.09.19 um 14:26 schrieb Deucher, Alexander:
> >>
> >> Please add a patch description. With that fixed:
> >> Reviewed-by: Alex Deucher
> >>
> >> From: amd-gfx on behalf of Yuan,
> >> Xiaojie
> >> Sent: Thursday, September 26, 2019 4:09 AM
> >> To: amd-gfx@lists.freedesktop.org
> >> Cc: alexdeuc...@gmail.com
> >> Subject: Re: [PATCH] drm/amdgpu/gmc10: apply the 'invalidation from sdma'
> >> workaround for navi
> >>
> >> Hi Alex,
> >>
> >> This patch is to add the asic_type check which is missing after drm-next
> >> branch rebase.
> >>
> >> BR,
> >> Xiaojie
> >>
> >> From: Yuan, Xiaojie
> >> Sent: Thursday, September 26, 2019 4:08 PM
> >> To: amd-gfx@lists.freedesktop.org
> >> Cc: alexdeuc...@gmail.com ; Yuan, Xiaojie
> >>
> >> Subject: [PATCH] drm/amdgpu/gmc10: apply the 'invalidation from sdma'
> >> workaround for navi
> >>
> >> Fixes: 767acabdac81 ("drm/amd/powerplay: add baco smu reset function for
> >> smu11")
> >> Signed-off-by: Xiaojie Yuan
> >> ---
> >> drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 1 +
Re: [PATCH] drm/amdgpu/gmc10: apply the 'invalidation from sdma' workaround for navi
Hi Alex,
This patch is to add the asic_type check which is missing after drm-next branch
rebase.
BR,
Xiaojie
From: Yuan, Xiaojie
Sent: Thursday, September 26, 2019 4:08 PM
To: amd-gfx@lists.freedesktop.org
Cc: alexdeuc...@gmail.com ; Yuan, Xiaojie
Subject: [PATCH] drm/amdgpu/gmc10: apply the 'invalidation from sdma'
workaround for navi
Fixes: 767acabdac81 ("drm/amd/powerplay: add baco smu reset function for smu11")
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index cb3f61873baa..dc2e68e019eb 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -292,6 +292,7 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device
*adev, uint32_t vmid,
if (!adev->mman.buffer_funcs_enabled ||
!adev->ib_pool_ready ||
+ !(adev->asic_type >= CHIP_NAVI10 && adev->asic_type <= CHIP_NAVI12)
||
adev->in_gpu_reset) {
gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0);
mutex_unlock(>mman.gtt_window_lock);
--
2.20.1
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[PATCH] drm/amdgpu/gmc10: apply the 'invalidation from sdma' workaround for navi
Fixes: 767acabdac81 ("drm/amd/powerplay: add baco smu reset function for smu11")
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index cb3f61873baa..dc2e68e019eb 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -292,6 +292,7 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device
*adev, uint32_t vmid,
if (!adev->mman.buffer_funcs_enabled ||
!adev->ib_pool_ready ||
+ !(adev->asic_type >= CHIP_NAVI10 && adev->asic_type <= CHIP_NAVI12)
||
adev->in_gpu_reset) {
gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0);
mutex_unlock(>mman.gtt_window_lock);
--
2.20.1
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Re: [PATCH 2/2] drm/amdgpu/atomfirmware: simplify the interface to get vram info
Series is Reviewed-by: Xiaojie Yuan
BR,
Xiaojie
From: amd-gfx on behalf of Alex Deucher
Sent: Tuesday, September 24, 2019 4:35 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH 2/2] drm/amdgpu/atomfirmware: simplify the interface to get
vram info
fetch both the vram type and width in one function call. This
avoids having to parse the same data table twice to get the two
pieces of data.
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 34 +
.../gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h | 4 +-
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c| 21 +++-
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 49 ++-
4 files changed, 37 insertions(+), 71 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
index 9feccec2ea5d..19913c39588b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
@@ -169,9 +169,8 @@ static int convert_atom_mem_type_to_vram_type(struct
amdgpu_device *adev,
return vram_type;
}
-static int
-amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
- int *vram_width, int *vram_type)
+int amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
+ int *vram_width, int *vram_type)
{
struct amdgpu_mode_info *mode_info = >mode_info;
int index, i = 0;
@@ -185,7 +184,6 @@ amdgpu_atomfirmware_get_vram_info(struct amdgpu_device
*adev,
u32 mem_channel_width;
u32 module_id;
-
if (adev->flags & AMD_IS_APU)
index =
get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
integratedsysteminfo);
@@ -261,34 +259,6 @@ amdgpu_atomfirmware_get_vram_info(struct amdgpu_device
*adev,
return 0;
}
-/*
- * Return vram width from integrated system info table, if available,
- * or 0 if not.
- */
-int amdgpu_atomfirmware_get_vram_width(struct amdgpu_device *adev)
-{
- int vram_width = 0, vram_type = 0;
- int r = amdgpu_atomfirmware_get_vram_info(adev, _width,
_type);
- if (r)
- return 0;
-
- return vram_width;
-}
-
-/*
- * Return vram type from either integrated system info table
- * or umc info table, if available, or 0 (TYPE_UNKNOWN) if not
- */
-int amdgpu_atomfirmware_get_vram_type(struct amdgpu_device *adev)
-{
- int vram_width = 0, vram_type = 0;
- int r = amdgpu_atomfirmware_get_vram_info(adev, _width,
_type);
- if (r)
- return 0;
-
- return vram_type;
-}
-
/*
* Return true if vbios enabled ecc by default, if umc info table is available
* or false if ecc is not enabled or umc info table is not available
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
index 5ec6f92f353c..82819f03e444 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
@@ -29,8 +29,8 @@
bool amdgpu_atomfirmware_gpu_supports_virtualization(struct amdgpu_device
*adev);
void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev);
int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev);
-int amdgpu_atomfirmware_get_vram_width(struct amdgpu_device *adev);
-int amdgpu_atomfirmware_get_vram_type(struct amdgpu_device *adev);
+int amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
+ int *vram_width, int *vram_type);
int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev);
int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev);
bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index 0a11d78d1fb2..cb3f61873baa 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -539,17 +539,6 @@ static void gmc_v10_0_vram_gtt_location(struct
amdgpu_device *adev,
*/
static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
{
- int chansize, numchan;
-
- if (!amdgpu_emu_mode)
- adev->gmc.vram_width = amdgpu_atomfirmware_get_vram_width(adev);
- else {
- /* hard code vram_width for emulation */
- chansize = 128;
- numchan = 1;
- adev->gmc.vram_width = numchan * chansize;
- }
-
/* Could aper size report 0 ? */
adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
@@ -635,7 +624,7 @@ static unsigned gmc_v10_0_get_vbios_fb_size(struct
amdgpu_device *adev)
static int gmc_v10_0_sw_init(void *handle)
{
- int r;
+ int r, vram_width =
Re: [PATCH] drm/amdgpu/gmc10: apply the 'invalidation from sdma' workaround for navi12
Thanks Evan. Since we currently has only once place to check 'is navi series',
I'd prefer not to put into a macro until we have another place to check that.
Does the change below looks good to you?
- adev->asic_type > CHIP_NAVI14 ||
+ !(adev->asic_type >= CHIP_NAVI10 && adev->asic_type <= CHIP_NAVI12)
||
BR,
Xiaojie
From: Quan, Evan
Sent: Tuesday, September 24, 2019 11:18 AM
To: Yuan, Xiaojie; amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking; Xiao, Jack; Yin, Tianci (Rico)
Subject: RE: [PATCH] drm/amdgpu/gmc10: apply the 'invalidation from sdma'
workaround for navi12
A small nitpick: if this workaround is needed for all NAVi ASICs, can we make a
macro for this?
e.g. #define ASIC_IS_NAVI_SERIES(adev) (adev->asic_type >=
CHIP_NAVI10 && adev->asic_type <= NAVI12)
Then we can use
if (!adev->mman.buffer_funcs_enabled ||
!adev->ib_pool_ready ||
- adev->asic_type > CHIP_NAVI14 ||
+ !ASIC_IS_NAVI_SERIES(adev) ||
adev->in_gpu_reset) {
-Original Message-
From: Yuan, Xiaojie
Sent: Tuesday, September 24, 2019 11:01 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Xiao, Jack ;
Yin, Tianci (Rico) ; Quan, Evan ; Yuan,
Xiaojie
Subject: [PATCH] drm/amdgpu/gmc10: apply the 'invalidation from sdma'
workaround for navi12
when gfxoff is enabled, sdma hangs while entering desktop without this
workaround
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index ed1c3b883f6a..0304ca8fe723 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -291,7 +291,7 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device
*adev, uint32_t vmid,
if (!adev->mman.buffer_funcs_enabled ||
!adev->ib_pool_ready ||
- adev->asic_type > CHIP_NAVI14 ||
+ adev->asic_type > CHIP_NAVI12 ||
adev->in_gpu_reset) {
gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0);
mutex_unlock(>mman.gtt_window_lock);
--
2.20.1
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[PATCH] drm/amdgpu/gmc10: apply the 'invalidation from sdma' workaround for navi12
when gfxoff is enabled, sdma hangs while entering desktop without this
workaround
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index ed1c3b883f6a..0304ca8fe723 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -291,7 +291,7 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device
*adev, uint32_t vmid,
if (!adev->mman.buffer_funcs_enabled ||
!adev->ib_pool_ready ||
- adev->asic_type > CHIP_NAVI14 ||
+ adev->asic_type > CHIP_NAVI12 ||
adev->in_gpu_reset) {
gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0);
mutex_unlock(>mman.gtt_window_lock);
--
2.20.1
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Re: [PATCH 1/2] drm/amdgpu/gmc10: do not apply the 'invalidation from sdma' workaround for navi12
Oops, you are right Evan. I'll send another patch.
It's a little counter-intuitive that asic type id of navi12 is larger than
navi14.
BR,
Xiaojie
From: Quan, Evan
Sent: Tuesday, September 24, 2019 10:09 AM
To: Yuan, Xiaojie; amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking; Xiao, Jack; Feng, Kenneth; Wang, Kevin(Yang)
Subject: RE: [PATCH 1/2] drm/amdgpu/gmc10: do not apply the 'invalidation from
sdma' workaround for navi12
The patch makes me a little confusing.
According to asic type list,
CHIP_NAVI10,/* 25 */
CHIP_NAVI14,/* 26 */
CHIP_NAVI12,/* 27 */
CHIP_LAST,
before the sdma workaround applies only for Navi10 and Navi14(not Navi12).
However, it seems this patch reverse the logics totally. It applies the
workaround only for Navi12.
-Original Message-
From: Yuan, Xiaojie
Sent: Monday, September 23, 2019 9:58 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Xiao, Jack ;
Feng, Kenneth ; Quan, Evan ; Wang,
Kevin(Yang) ; Yuan, Xiaojie
Subject: [PATCH 1/2] drm/amdgpu/gmc10: do not apply the 'invalidation from
sdma' workaround for navi12
when gfxoff is enabled, applying this workaround makes sdma hang while entering
desktop.
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index ed1c3b883f6a..3897e0d28838 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -291,7 +291,8 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device
*adev, uint32_t vmid,
if (!adev->mman.buffer_funcs_enabled ||
!adev->ib_pool_ready ||
- adev->asic_type > CHIP_NAVI14 ||
+ adev->asic_type == CHIP_NAVI10 ||
+ adev->asic_type == CHIP_NAVI14 ||
adev->in_gpu_reset) {
gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0);
mutex_unlock(>mman.gtt_window_lock);
--
2.20.1
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[PATCH 1/2] drm/amdgpu/gmc10: do not apply the 'invalidation from sdma' workaround for navi12
when gfxoff is enabled, applying this workaround makes sdma hang while
entering desktop.
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index ed1c3b883f6a..3897e0d28838 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -291,7 +291,8 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device
*adev, uint32_t vmid,
if (!adev->mman.buffer_funcs_enabled ||
!adev->ib_pool_ready ||
- adev->asic_type > CHIP_NAVI14 ||
+ adev->asic_type == CHIP_NAVI10 ||
+ adev->asic_type == CHIP_NAVI14 ||
adev->in_gpu_reset) {
gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0);
mutex_unlock(>mman.gtt_window_lock);
--
2.20.1
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[PATCH 2/2] drm/amdgpu/gfx10: enable gfxoff for navi12
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 082a0b3298a9..22406f56c818 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -580,7 +580,6 @@ static void gfx_v10_0_check_gfxoff_flag(struct
amdgpu_device *adev)
{
switch (adev->asic_type) {
case CHIP_NAVI10:
- case CHIP_NAVI12:
adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
break;
default:
@@ -4184,6 +4183,7 @@ static int gfx_v10_0_set_powergating_state(void *handle,
bool enable = (state == AMD_PG_STATE_GATE) ? true : false;
switch (adev->asic_type) {
case CHIP_NAVI10:
+ case CHIP_NAVI12:
case CHIP_NAVI14:
if (!enable) {
amdgpu_gfx_off_ctrl(adev, false);
--
2.20.1
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Re: [PATCH] drm/amdgpu: flag navi12 and 14 as experimental for 5.4
Reviewed-by: Xiaojie Yuan
BR,
Xiaojie
> On Sep 18, 2019, at 3:52 AM, Alex Deucher wrote:
>
> We can remove this later as things get closer to launch.
>
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index c68e54a27a2c..5da72ca6f3e1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -1011,15 +1011,15 @@ static const struct pci_device_id pciidlist[] = {
>{0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
>{0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
>/* Navi14 */
> -{0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
> -{0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
> -{0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
> +{0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> CHIP_NAVI14|AMD_EXP_HW_SUPPORT},
> +{0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> CHIP_NAVI14|AMD_EXP_HW_SUPPORT},
> +{0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> CHIP_NAVI14|AMD_EXP_HW_SUPPORT},
>
>/* Renoir */
>{0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> CHIP_RENOIR|AMD_IS_APU|AMD_EXP_HW_SUPPORT},
>
>/* Navi12 */
> -{0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
> +{0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> CHIP_NAVI12|AMD_EXP_HW_SUPPORT},
>
>{0, 0, 0}
> };
> --
> 2.20.1
>
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[PATCH] drm/amdgpu/powerplay: add new mapping for APCC_DFLL feature
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/powerplay/inc/smu_types.h | 1 +
drivers/gpu/drm/amd/powerplay/navi10_ppt.c| 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
index ab8c92a60fc4..12a1de55ce3c 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
@@ -252,6 +252,7 @@ enum smu_clk_type {
__SMU_DUMMY_MAP(TEMP_DEPENDENT_VMIN), \
__SMU_DUMMY_MAP(MMHUB_PG), \
__SMU_DUMMY_MAP(ATHUB_PG), \
+ __SMU_DUMMY_MAP(APCC_DFLL), \
__SMU_DUMMY_MAP(WAFL_CG),
#undef __SMU_DUMMY_MAP
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 16634e657589..5a34d01f7f7c 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -176,6 +176,7 @@ static struct smu_11_0_cmn2aisc_mapping
navi10_feature_mask_map[SMU_FEATURE_COUN
FEA_MAP(TEMP_DEPENDENT_VMIN),
FEA_MAP(MMHUB_PG),
FEA_MAP(ATHUB_PG),
+ FEA_MAP(APCC_DFLL),
};
static struct smu_11_0_cmn2aisc_mapping navi10_table_map[SMU_TABLE_COUNT] = {
--
2.20.1
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[PATCH] drm/amdgpu: get gpu info from ip discovery table
except soc_bounding_box which is not integrated in discovery table yet
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 13bd6a6bd8aa..70e0f24d37a8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1474,6 +1474,9 @@ static int amdgpu_device_parse_gpu_info_fw(struct
amdgpu_device *adev)
(const struct gpu_info_firmware_v1_0
*)(adev->firmware.gpu_info_fw->data +
le32_to_cpu(hdr->header.ucode_array_offset_bytes));
+ if (amdgpu_discovery && adev->asic_type >= CHIP_NAVI10)
+ goto parse_soc_bounding_box;
+
adev->gfx.config.max_shader_engines =
le32_to_cpu(gpu_info_fw->gc_num_se);
adev->gfx.config.max_cu_per_sh =
le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
adev->gfx.config.max_sh_per_se =
le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
@@ -1501,7 +1504,13 @@ static int amdgpu_device_parse_gpu_info_fw(struct
amdgpu_device *adev)
adev->gfx.config.num_packer_per_sc =
le32_to_cpu(gpu_info_fw->num_packer_per_sc);
}
+
+parse_soc_bounding_box:
#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ /*
+* soc bounding box info is not integrated in disocovery table,
+* we always need to parse it from gpu info firmware.
+*/
if (hdr->version_minor == 2) {
const struct gpu_info_firmware_v1_2 *gpu_info_fw =
(const struct gpu_info_firmware_v1_2
*)(adev->firmware.gpu_info_fw->data +
@@ -1618,6 +1627,9 @@ static int amdgpu_device_ip_early_init(struct
amdgpu_device *adev)
if (r)
return r;
+ if (amdgpu_discovery && adev->asic_type >= CHIP_NAVI10)
+ amdgpu_discovery_get_gfx_info(adev);
+
amdgpu_amdkfd_device_probe(adev);
if (amdgpu_sriov_vf(adev)) {
--
2.20.1
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Re: [PATCH] drm/amdgpu: fix null pointer deref in firmware header printing
Thanks Kevin. I've sent out v2 patch. BR, Xiaojie From: Wang, Kevin(Yang) Sent: Thursday, September 5, 2019 6:26 PM To: Yuan, Xiaojie; amd-gfx@lists.freedesktop.org Subject: Re: [PATCH] drm/amdgpu: fix null pointer deref in firmware header printing On 9/5/19 5:41 PM, Yuan, Xiaojie wrote: > When CE's ucode_id(8) is used to get sdma_hdr, we will be accessing an > unallocated amdgpu_firmware_info instance. > > This issue appears on rhel7.7 with gcc 4.8.5. Newer compilers might have > optimized out such 'defined but not referenced' variable. > > [ 1120.798564] BUG: unable to handle kernel NULL pointer dereference at > 000a > [ 1120.806703] IP: [] psp_np_fw_load+0x1e3/0x390 [amdgpu] > [ 1120.813693] PGD 8002603ff067 PUD 271b8d067 PMD 0 > [ 1120.818931] Oops: [#1] SMP > [ 1120.822245] Modules linked in: amdgpu(OE+) amdkcl(OE) amd_iommu_v2 > amdttm(OE) amd_sched(OE) xt_CHECKSUM ipt_MASQUERADE nf_nat_masquerade_ipv4 > tun bridge stp llc devlink ip6t_rpfilter ip6t_REJECT nf_reject_ipv6 > ipt_REJECT nf_reject_ipv4 xt_conntrack ebtable_nat ip6table_nat > nf_conntrack_ipv6 nf_defrag_ipv6 nf_nat_ipv6 ip6table_mangle > ip6table_security ip6table_raw iptable_nat nf_conntrack_ipv4 nf_defrag_ipv4 > nf_nat_ipv4 nf_nat iptable_mangle iptable_security iptable_raw nf_conntrack > libcrc32c ip_set nfnetlink ebtable_filter ebtables ip6table_filter ip6_tables > iptable_filter sunrpc dm_mirror dm_region_hash dm_log dm_mod intel_pmc_core > intel_powerclamp coretemp intel_rapl joydev kvm_intel eeepc_wmi asus_wmi kvm > sparse_keymap iTCO_wdt irqbypass rfkill crc32_pclmul snd_hda_codec_realtek > mxm_wmi ghash_clmulni_intel intel_wmi_thunderbolt iTCO_vendor_support > snd_hda_codec_generic snd_hda_codec_hdmi aesni_intel lrw gf128mul glue_helper > ablk_helper sg cryptd pcspkr snd_hda_intel snd_hda_codec snd_hda_core > snd_hwdep snd_seq snd_seq_device snd_pcm snd_timer snd pinctrl_sunrisepoint > pinctrl_intel soundcore acpi_pad mei_me wmi mei i2c_i801 pcc_cpufreq > ip_tables ext4 mbcache jbd2 sd_mod crc_t10dif crct10dif_generic i915 > i2c_algo_bit iosf_mbi drm_kms_helper e1000e syscopyarea sysfillrect sysimgblt > fb_sys_fops ahci libahci drm ptp libata crct10dif_pclmul crct10dif_common > crc32c_intel serio_raw pps_core drm_panel_orientation_quirks video i2c_hid > [ 1120.954136] CPU: 4 PID: 2426 Comm: modprobe Tainted: G OE > 3.10.0-1062.el7.x86_64 #1 > [ 1120.964390] Hardware name: System manufacturer System Product Name/Z170-A, > BIOS 1302 11/09/2015 > [ 1120.973321] task: 991ef1e3c1c0 ti: 991ee625c000 task.ti: > 991ee625c000 > [ 1120.981020] RIP: 0010:[] [] > psp_np_fw_load+0x1e3/0x390 [amdgpu] > [ 1120.990483] RSP: 0018:991ee625f950 EFLAGS: 00010202 > [ 1120.995935] RAX: 0002 RBX: 991edf6b2d38 RCX: > 991edf6a > [ 1121.003391] RDX: RSI: 991f01d13898 RDI: > c110afb3 > [ 1121.010706] RBP: 991ee625f9b0 R08: R09: > > [ 1121.018029] R10: 04c4 R11: 991ee625f64e R12: > 991edf6b3220 > [ 1121.025353] R13: 991edf6a R14: 0008 R15: > 991edf6b2d30 > [ 1121.032666] FS: 7f97b0c0b740() GS:991f01d0() > knlGS: > [ 1121.041000] CS: 0010 DS: ES: CR0: 80050033 > [ 1121.046880] CR2: 000a CR3: 00025e604000 CR4: > 003607e0 > [ 1121.054239] DR0: DR1: DR2: > > [ 1121.061631] DR3: DR6: fffe0ff0 DR7: > 0400 > [ 1121.068938] Call Trace: > [ 1121.071494] [] psp_hw_init+0x218/0x270 [amdgpu] > [ 1121.077886] [] amdgpu_device_fw_loading+0xe8/0x160 > [amdgpu] > [ 1121.085296] [] ? vega10_ih_irq_init+0x4bc/0x730 [amdgpu] > [ 1121.092534] [] amdgpu_device_init+0x1495/0x1c90 [amdgpu] > [ 1121.099675] [] amdgpu_driver_load_kms+0x8b/0x2f0 > [amdgpu] > [ 1121.106888] [] drm_dev_register+0x12f/0x1d0 [drm] > [ 1121.113419] [] ? pci_enable_device_flags+0xe8/0x140 > [ 1121.120183] [] amdgpu_pci_probe+0xca/0x170 [amdgpu] > [ 1121.126919] [] local_pci_probe+0x4a/0xb0 > [ 1121.132622] [] pci_device_probe+0x109/0x160 > [ 1121.138607] [] driver_probe_device+0xc5/0x3e0 > [ 1121.144766] [] __driver_attach+0x93/0xa0 > [ 1121.150507] [] ? __device_attach+0x50/0x50 > [ 1121.156422] [] bus_for_each_dev+0x75/0xc0 > [ 1121.162213] [] driver_attach+0x1e/0x20 > [ 1121.167771] [] bus_add_driver+0x200/0x2d0 > [ 1121.173590] [] driver_register+0x64/0xf0 > [ 1121.179345] [] __pci_register_driver+0xa5/0xc0 > [ 1121.185593] [] ? 0xc099efff > [ 1121.190914] [] amdgpu_init+0xa4/0xb0 [amdg
[PATCH v2] drm/amdgpu: fix null pointer deref in firmware header printing
v2: declare as (struct common_firmware_header *) type because struct xxx_firmware_header inherits from it When CE's ucode_id(8) is used to get sdma_hdr, we will be accessing an unallocated amdgpu_firmware_info instance. This issue appears on rhel7.7 with gcc 4.8.5. Newer compilers might have optimized out such 'defined but not referenced' variable. [ 1120.798564] BUG: unable to handle kernel NULL pointer dereference at 000a [ 1120.806703] IP: [] psp_np_fw_load+0x1e3/0x390 [amdgpu] [ 1120.813693] PGD 8002603ff067 PUD 271b8d067 PMD 0 [ 1120.818931] Oops: [#1] SMP [ 1120.822245] Modules linked in: amdgpu(OE+) amdkcl(OE) amd_iommu_v2 amdttm(OE) amd_sched(OE) xt_CHECKSUM ipt_MASQUERADE nf_nat_masquerade_ipv4 tun bridge stp llc devlink ip6t_rpfilter ip6t_REJECT nf_reject_ipv6 ipt_REJECT nf_reject_ipv4 xt_conntrack ebtable_nat ip6table_nat nf_conntrack_ipv6 nf_defrag_ipv6 nf_nat_ipv6 ip6table_mangle ip6table_security ip6table_raw iptable_nat nf_conntrack_ipv4 nf_defrag_ipv4 nf_nat_ipv4 nf_nat iptable_mangle iptable_security iptable_raw nf_conntrack libcrc32c ip_set nfnetlink ebtable_filter ebtables ip6table_filter ip6_tables iptable_filter sunrpc dm_mirror dm_region_hash dm_log dm_mod intel_pmc_core intel_powerclamp coretemp intel_rapl joydev kvm_intel eeepc_wmi asus_wmi kvm sparse_keymap iTCO_wdt irqbypass rfkill crc32_pclmul snd_hda_codec_realtek mxm_wmi ghash_clmulni_intel intel_wmi_thunderbolt iTCO_vendor_support snd_hda_codec_generic snd_hda_codec_hdmi aesni_intel lrw gf128mul glue_helper ablk_helper sg cryptd pcspkr snd_hda_intel snd_hda_codec snd_hda_core snd_hwdep snd_seq snd_seq_device snd_pcm snd_timer snd pinctrl_sunrisepoint pinctrl_intel soundcore acpi_pad mei_me wmi mei i2c_i801 pcc_cpufreq ip_tables ext4 mbcache jbd2 sd_mod crc_t10dif crct10dif_generic i915 i2c_algo_bit iosf_mbi drm_kms_helper e1000e syscopyarea sysfillrect sysimgblt fb_sys_fops ahci libahci drm ptp libata crct10dif_pclmul crct10dif_common crc32c_intel serio_raw pps_core drm_panel_orientation_quirks video i2c_hid [ 1120.954136] CPU: 4 PID: 2426 Comm: modprobe Tainted: G OE 3.10.0-1062.el7.x86_64 #1 [ 1120.964390] Hardware name: System manufacturer System Product Name/Z170-A, BIOS 1302 11/09/2015 [ 1120.973321] task: 991ef1e3c1c0 ti: 991ee625c000 task.ti: 991ee625c000 [ 1120.981020] RIP: 0010:[] [] psp_np_fw_load+0x1e3/0x390 [amdgpu] [ 1120.990483] RSP: 0018:991ee625f950 EFLAGS: 00010202 [ 1120.995935] RAX: 0002 RBX: 991edf6b2d38 RCX: 991edf6a [ 1121.003391] RDX: RSI: 991f01d13898 RDI: c110afb3 [ 1121.010706] RBP: 991ee625f9b0 R08: R09: [ 1121.018029] R10: 04c4 R11: 991ee625f64e R12: 991edf6b3220 [ 1121.025353] R13: 991edf6a R14: 0008 R15: 991edf6b2d30 [ 1121.032666] FS: 7f97b0c0b740() GS:991f01d0() knlGS: [ 1121.041000] CS: 0010 DS: ES: CR0: 80050033 [ 1121.046880] CR2: 000a CR3: 00025e604000 CR4: 003607e0 [ 1121.054239] DR0: DR1: DR2: [ 1121.061631] DR3: DR6: fffe0ff0 DR7: 0400 [ 1121.068938] Call Trace: [ 1121.071494] [] psp_hw_init+0x218/0x270 [amdgpu] [ 1121.077886] [] amdgpu_device_fw_loading+0xe8/0x160 [amdgpu] [ 1121.085296] [] ? vega10_ih_irq_init+0x4bc/0x730 [amdgpu] [ 1121.092534] [] amdgpu_device_init+0x1495/0x1c90 [amdgpu] [ 1121.099675] [] amdgpu_driver_load_kms+0x8b/0x2f0 [amdgpu] [ 1121.106888] [] drm_dev_register+0x12f/0x1d0 [drm] [ 1121.113419] [] ? pci_enable_device_flags+0xe8/0x140 [ 1121.120183] [] amdgpu_pci_probe+0xca/0x170 [amdgpu] [ 1121.126919] [] local_pci_probe+0x4a/0xb0 [ 1121.132622] [] pci_device_probe+0x109/0x160 [ 1121.138607] [] driver_probe_device+0xc5/0x3e0 [ 1121.144766] [] __driver_attach+0x93/0xa0 [ 1121.150507] [] ? __device_attach+0x50/0x50 [ 1121.156422] [] bus_for_each_dev+0x75/0xc0 [ 1121.162213] [] driver_attach+0x1e/0x20 [ 1121.167771] [] bus_add_driver+0x200/0x2d0 [ 1121.173590] [] driver_register+0x64/0xf0 [ 1121.179345] [] __pci_register_driver+0xa5/0xc0 [ 1121.185593] [] ? 0xc099efff [ 1121.190914] [] amdgpu_init+0xa4/0xb0 [amdgpu] [ 1121.197101] [] do_one_initcall+0xba/0x240 [ 1121.202901] [] load_module+0x271a/0x2bb0 [ 1121.208598] [] ? ddebug_proc_write+0x100/0x100 [ 1121.214894] [] SyS_init_module+0xef/0x140 [ 1121.220698] [] system_call_fastpath+0x25/0x2a [ 1121.226870] Code: b4 01 60 a2 00 00 31 c0 e8 83 60 33 e4 41 8b 47 08 48 8b 4d d0 48 c7 c7 b3 af 10 c1 48 69 c0 68 07 00 00 48 8b 84 01 60 a2 00 00 <48> 8b 70 08 31 c0 48 89 75 c8 e8 56 60 33 e4 48 8b 4d d0 48 c7 [ 1121.247422] RIP [] psp_np_fw_load+0x1e3/0x390 [amdgpu] [ 1121.254432] RSP [ 1121.258017] CR2: 000a [ 1121.261427] ---[ end trace e98b35387ede75bd ]--- Signed-off-by:
[PATCH] drm/amdgpu: fix null pointer deref in firmware header printing
When CE's ucode_id(8) is used to get sdma_hdr, we will be accessing an
unallocated amdgpu_firmware_info instance.
This issue appears on rhel7.7 with gcc 4.8.5. Newer compilers might have
optimized out such 'defined but not referenced' variable.
[ 1120.798564] BUG: unable to handle kernel NULL pointer dereference at
000a
[ 1120.806703] IP: [] psp_np_fw_load+0x1e3/0x390 [amdgpu]
[ 1120.813693] PGD 8002603ff067 PUD 271b8d067 PMD 0
[ 1120.818931] Oops: [#1] SMP
[ 1120.822245] Modules linked in: amdgpu(OE+) amdkcl(OE) amd_iommu_v2
amdttm(OE) amd_sched(OE) xt_CHECKSUM ipt_MASQUERADE nf_nat_masquerade_ipv4 tun
bridge stp llc devlink ip6t_rpfilter ip6t_REJECT nf_reject_ipv6 ipt_REJECT
nf_reject_ipv4 xt_conntrack ebtable_nat ip6table_nat nf_conntrack_ipv6
nf_defrag_ipv6 nf_nat_ipv6 ip6table_mangle ip6table_security ip6table_raw
iptable_nat nf_conntrack_ipv4 nf_defrag_ipv4 nf_nat_ipv4 nf_nat iptable_mangle
iptable_security iptable_raw nf_conntrack libcrc32c ip_set nfnetlink
ebtable_filter ebtables ip6table_filter ip6_tables iptable_filter sunrpc
dm_mirror dm_region_hash dm_log dm_mod intel_pmc_core intel_powerclamp coretemp
intel_rapl joydev kvm_intel eeepc_wmi asus_wmi kvm sparse_keymap iTCO_wdt
irqbypass rfkill crc32_pclmul snd_hda_codec_realtek mxm_wmi ghash_clmulni_intel
intel_wmi_thunderbolt iTCO_vendor_support snd_hda_codec_generic
snd_hda_codec_hdmi aesni_intel lrw gf128mul glue_helper ablk_helper sg cryptd
pcspkr snd_hda_intel snd_hda_codec snd_hda_core snd_hwdep snd_seq
snd_seq_device snd_pcm snd_timer snd pinctrl_sunrisepoint pinctrl_intel
soundcore acpi_pad mei_me wmi mei i2c_i801 pcc_cpufreq ip_tables ext4 mbcache
jbd2 sd_mod crc_t10dif crct10dif_generic i915 i2c_algo_bit iosf_mbi
drm_kms_helper e1000e syscopyarea sysfillrect sysimgblt fb_sys_fops ahci
libahci drm ptp libata crct10dif_pclmul crct10dif_common crc32c_intel serio_raw
pps_core drm_panel_orientation_quirks video i2c_hid
[ 1120.954136] CPU: 4 PID: 2426 Comm: modprobe Tainted: G OE
3.10.0-1062.el7.x86_64 #1
[ 1120.964390] Hardware name: System manufacturer System Product Name/Z170-A,
BIOS 1302 11/09/2015
[ 1120.973321] task: 991ef1e3c1c0 ti: 991ee625c000 task.ti:
991ee625c000
[ 1120.981020] RIP: 0010:[] []
psp_np_fw_load+0x1e3/0x390 [amdgpu]
[ 1120.990483] RSP: 0018:991ee625f950 EFLAGS: 00010202
[ 1120.995935] RAX: 0002 RBX: 991edf6b2d38 RCX: 991edf6a
[ 1121.003391] RDX: RSI: 991f01d13898 RDI: c110afb3
[ 1121.010706] RBP: 991ee625f9b0 R08: R09:
[ 1121.018029] R10: 04c4 R11: 991ee625f64e R12: 991edf6b3220
[ 1121.025353] R13: 991edf6a R14: 0008 R15: 991edf6b2d30
[ 1121.032666] FS: 7f97b0c0b740() GS:991f01d0()
knlGS:
[ 1121.041000] CS: 0010 DS: ES: CR0: 80050033
[ 1121.046880] CR2: 000a CR3: 00025e604000 CR4: 003607e0
[ 1121.054239] DR0: DR1: DR2:
[ 1121.061631] DR3: DR6: fffe0ff0 DR7: 0400
[ 1121.068938] Call Trace:
[ 1121.071494] [] psp_hw_init+0x218/0x270 [amdgpu]
[ 1121.077886] [] amdgpu_device_fw_loading+0xe8/0x160
[amdgpu]
[ 1121.085296] [] ? vega10_ih_irq_init+0x4bc/0x730 [amdgpu]
[ 1121.092534] [] amdgpu_device_init+0x1495/0x1c90 [amdgpu]
[ 1121.099675] [] amdgpu_driver_load_kms+0x8b/0x2f0 [amdgpu]
[ 1121.106888] [] drm_dev_register+0x12f/0x1d0 [drm]
[ 1121.113419] [] ? pci_enable_device_flags+0xe8/0x140
[ 1121.120183] [] amdgpu_pci_probe+0xca/0x170 [amdgpu]
[ 1121.126919] [] local_pci_probe+0x4a/0xb0
[ 1121.132622] [] pci_device_probe+0x109/0x160
[ 1121.138607] [] driver_probe_device+0xc5/0x3e0
[ 1121.144766] [] __driver_attach+0x93/0xa0
[ 1121.150507] [] ? __device_attach+0x50/0x50
[ 1121.156422] [] bus_for_each_dev+0x75/0xc0
[ 1121.162213] [] driver_attach+0x1e/0x20
[ 1121.167771] [] bus_add_driver+0x200/0x2d0
[ 1121.173590] [] driver_register+0x64/0xf0
[ 1121.179345] [] __pci_register_driver+0xa5/0xc0
[ 1121.185593] [] ? 0xc099efff
[ 1121.190914] [] amdgpu_init+0xa4/0xb0 [amdgpu]
[ 1121.197101] [] do_one_initcall+0xba/0x240
[ 1121.202901] [] load_module+0x271a/0x2bb0
[ 1121.208598] [] ? ddebug_proc_write+0x100/0x100
[ 1121.214894] [] SyS_init_module+0xef/0x140
[ 1121.220698] [] system_call_fastpath+0x25/0x2a
[ 1121.226870] Code: b4 01 60 a2 00 00 31 c0 e8 83 60 33 e4 41 8b 47 08 48 8b
4d d0 48 c7 c7 b3 af 10 c1 48 69 c0 68 07 00 00 48 8b 84 01 60 a2 00 00 <48> 8b
70 08 31 c0 48 89 75 c8 e8 56 60 33 e4 48 8b 4d d0 48 c7
[ 1121.247422] RIP [] psp_np_fw_load+0x1e3/0x390 [amdgpu]
[ 1121.254432] RSP
[ 1121.258017] CR2: 000a
[ 1121.261427] ---[ end trace e98b35387ede75bd ]---
Signed-off-by: Xiaojie Yuan
Fixes: 5206b0e79cfe ("drm/amdgpu: add firmware header printing for psp fw
loading")
---
[PATCH] drm/amd/powerplay: fix 'unusedd variable' compile warning
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 2 --
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 2 --
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 2 --
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 2 --
4 files changed, 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index 6e8eb0f94c8b..1c6732847185 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -1931,7 +1931,5 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
void arcturus_set_ppt_funcs(struct smu_context *smu)
{
- struct smu_table_context *smu_table = >smu_table;
-
smu->ppt_funcs = _ppt_funcs;
}
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index e3add8b59291..16634e657589 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -1630,7 +1630,5 @@ static const struct pptable_funcs navi10_ppt_funcs = {
void navi10_set_ppt_funcs(struct smu_context *smu)
{
- struct smu_table_context *smu_table = >smu_table;
-
smu->ppt_funcs = _ppt_funcs;
}
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index b7fa8b158ff2..a5cf846b50d4 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -257,8 +257,6 @@ static const struct pptable_funcs renoir_ppt_funcs = {
void renoir_set_ppt_funcs(struct smu_context *smu)
{
- struct smu_table_context *smu_table = >smu_table;
-
smu->ppt_funcs = _ppt_funcs;
smu->smc_if_version = SMU12_DRIVER_IF_VERSION;
}
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index 18d1b432f719..929f61891dfa 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -3180,7 +3180,5 @@ static const struct pptable_funcs vega20_ppt_funcs = {
void vega20_set_ppt_funcs(struct smu_context *smu)
{
- struct smu_table_context *smu_table = >smu_table;
-
smu->ppt_funcs = _ppt_funcs;
}
--
2.20.1
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Re: [PATCH] drm/amdgpu/virtual_dce: drop error message in hw_init
Reviewed-by: Xiaojie Yuan
BR,
Xiaojie
> On Aug 28, 2019, at 9:56 PM, Alex Deucher wrote:
>
> No need to add new asic cases. This is a sw display
> implementation, so just drop the error message so when
> we add new asics, all we have to do is add the virtual
> dce IP module.
>
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 11 +--
> 1 file changed, 1 insertion(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
> b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
> index 6dadbed7ce43..fe242cc7c04f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
> @@ -452,17 +452,8 @@ static int dce_virtual_hw_init(void *handle)
> #endif
>/* no DCE */
>break;
> -case CHIP_VEGA10:
> -case CHIP_VEGA12:
> -case CHIP_VEGA20:
> -case CHIP_ARCTURUS:
> -case CHIP_RENOIR:
> -case CHIP_NAVI10:
> -case CHIP_NAVI14:
> -case CHIP_NAVI12:
> -break;
>default:
> -DRM_ERROR("Virtual display unsupported ASIC type: 0x%X\n",
> adev->asic_type);
> +break;
>}
>return 0;
> }
> --
> 2.20.1
>
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[PATCH 2/3] drm/amdgpu: enable athub powergating for navi12
Signed-off-by: Xiaojie Yuan --- drivers/gpu/drm/amd/amdgpu/nv.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index 9eda82d4430e..384f8f512fc4 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -650,7 +650,8 @@ static int nv_common_early_init(void *handle) AMD_CG_SUPPORT_ATHUB_LS | AMD_CG_SUPPORT_VCN_MGCG; adev->pg_flags = AMD_PG_SUPPORT_VCN | - AMD_PG_SUPPORT_VCN_DPG; + AMD_PG_SUPPORT_VCN_DPG | + AMD_PG_SUPPORT_ATHUB; adev->external_rev_id = adev->rev_id + 0xa; break; default: -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 1/3] drm/amdgpu: enable vcn powergating for navi12
Signed-off-by: Xiaojie Yuan --- drivers/gpu/drm/amd/amdgpu/nv.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index a3d99f2ddf6b..9eda82d4430e 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -649,7 +649,8 @@ static int nv_common_early_init(void *handle) AMD_CG_SUPPORT_ATHUB_MGCG | AMD_CG_SUPPORT_ATHUB_LS | AMD_CG_SUPPORT_VCN_MGCG; - adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG; + adev->pg_flags = AMD_PG_SUPPORT_VCN | + AMD_PG_SUPPORT_VCN_DPG; adev->external_rev_id = adev->rev_id + 0xa; break; default: -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 3/3] drm/amd/powerplay: enable jpeg powergating for navi1x
jpeg pg depends on vcn pg
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 2d908afbf525..1970843f225f 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -368,7 +368,8 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN)
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT);
+ *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT)
+ | FEATURE_MASK(FEATURE_JPEG_PG_BIT);
/* disable DPM UCLK and DS SOCCLK on navi10 A0 secure board */
if (is_asic_secure(smu)) {
--
2.20.1
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Re: [PATCH] drm/amdgpu: set adev->num_vmhubs for gmc6,7,8
Reviewed-by: Xiaojie Yuan
BR,
Xiaojie
> On Aug 23, 2019, at 10:45 PM, Alex Deucher wrote:
>
> So that we properly handle them on older asics.
>
> Fixes: 3ff985485b29 ("drm/amdgpu: Export function to flush TLB of specific vm
> hub")
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 2 ++
> drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 2 ++
> drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 2 ++
> 3 files changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> index 564fb1ce292f..3264548e375c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> @@ -839,6 +839,8 @@ static int gmc_v6_0_sw_init(void *handle)
>int dma_bits;
>struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> +adev->num_vmhubs = 1;
> +
>if (adev->flags & AMD_IS_APU) {
>adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
>} else {
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> index 9e6a23304fd7..cc0aa178eb2d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> @@ -959,6 +959,8 @@ static int gmc_v7_0_sw_init(void *handle)
>int dma_bits;
>struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> +adev->num_vmhubs = 1;
> +
>if (adev->flags & AMD_IS_APU) {
>adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
>} else {
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> index f7d6a07ba4e1..88f3a171452f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> @@ -1079,6 +1079,8 @@ static int gmc_v8_0_sw_init(void *handle)
>int dma_bits;
>struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> +adev->num_vmhubs = 1;
> +
>if (adev->flags & AMD_IS_APU) {
>adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
>} else {
> --
> 2.20.1
>
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[PATCH] drm/amdgpu: add dummy read for some GCVM status registers
The GRBM register interface is now capable of bursting 1 cycle per
register wr->wr, wr->rd much faster than previous muticycle per
transaction done interface. This has caused a problem where status
registers requiring HW to update have a 1 cycle delay, due to the
register update having to go through GRBM.
SW may operate on an incorrect value if they write a register and
immediately check the corresponding status register.
Registers requiring HW to clear or set fields may be delayed by 1 cycle.
For example,
1. write VM_INVALIDATE_ENG0_REQ mask = 5a
2. read VM_INVALIDATE_ENG0_ACK till the ack is same as the request mask = 5a
a. HW will reset VM_INVALIDATE_ENG0_ACK = 0 until invalidation is complete
3. write VM_INVALIDATE_ENG0_REQ mask = 5a
4. read VM_INVALIDATE_ENG0_ACK till the ack is same as the request mask = 5a
a. First read of VM_INVALIDATE_ENG0_ACK = 5a instead of 0
b. Second read of VM_INVALIDATE_ENG0_ACK = 0 because
the remote GRBM h/w register takes one extra cycle to be cleared
c. In this case, SW will see a false ACK if they exit on first read
Affected registers (only GC variant) | Recommended Dummy Read
--+
VM_INVALIDATE_ENG*_ACK| VM_INVALIDATE_ENG*_REQ
VM_L2_STATUS | VM_L2_STATUS
VM_L2_PROTECTION_FAULT_STATUS | VM_L2_PROTECTION_FAULT_STATUS
VM_L2_PROTECTION_FAULT_ADDR_HI/LO32 | VM_L2_PROTECTION_FAULT_ADDR_HI/LO32
VM_L2_IH_LOG_BUSY | VM_L2_IH_LOG_BUSY
MC_VM_L2_PERFCOUNTER_HI/LO| MC_VM_L2_PERFCOUNTER_HI/LO
ATC_L2_PERFCOUNTER_HI/LO | ATC_L2_PERFCOUNTER_HI/LO
ATC_L2_PERFCOUNTER2_HI/LO | ATC_L2_PERFCOUNTER2_HI/LO
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 15 +++
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 16
2 files changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index d83d8a6a1fc0..56f76a1f32ee 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -135,6 +135,14 @@ static int gmc_v10_0_process_interrupt(struct
amdgpu_device *adev,
addr |= ((u64)entry->src_data[1] & 0xf) << 44;
if (!amdgpu_sriov_vf(adev)) {
+ /*
+* Issue a dummy read to wait for the status register to
+* be updated to avoid reading an incorrect value due to
+* the new fast GRBM interface.
+*/
+ if (entry->vmid_src == AMDGPU_GFXHUB_0)
+ RREG32(hub->vm_l2_pro_fault_status);
+
status = RREG32(hub->vm_l2_pro_fault_status);
WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
}
@@ -228,6 +236,13 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device
*adev, uint32_t vmid,
WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);
+ /*
+* Issue a dummy read to wait for the ACK register to be cleared
+* to avoid a false ACK due to the new fast GRBM interface.
+*/
+ if (vmhub == AMDGPU_GFXHUB_0)
+ RREG32_NO_KIQ(hub->vm_inv_eng0_req + eng);
+
/* Wait for ACK with a delay.*/
for (i = 0; i < adev->usec_timeout; i++) {
tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 6de17267fc35..17700606f54b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -352,6 +352,14 @@ static int gmc_v9_0_process_interrupt(struct amdgpu_device
*adev,
/* If it's the first fault for this address, process it normally */
if (!amdgpu_sriov_vf(adev)) {
+ /*
+* Issue a dummy read to wait for the status register to
+* be updated to avoid reading an incorrect value due to
+* the new fast GRBM interface.
+*/
+ if (entry->vmid_src == AMDGPU_GFXHUB_0)
+ RREG32(hub->vm_l2_pro_fault_status);
+
status = RREG32(hub->vm_l2_pro_fault_status);
WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
}
@@ -480,6 +488,14 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device
*adev, uint32_t vmid,
spin_lock(>gmc.invalidate_lock);
WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);
+
+ /*
+* Issue a dummy read to wait for the ACK register to be cleared
+* to avoid a false ACK due to the new fast GRBM interface.
+*/
+ if (vmhub == AMDGPU_GFXHUB_0)
+ RREG32_NO_KIQ(hub->vm_inv_eng0_req + eng);
+
for (j = 0; j < adev->usec_timeout; j++) {
tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
if (tmp & (1 << vmid))
--
2.20.1
Re: [PATCH] drm/amdgpu/sdma5: fix number of sdma5 trap irq types for navi1x
Thanks Alex. I've sent out patch v2.
BR,
Xiaojie
> On Aug 21, 2019, at 9:30 PM, Alex Deucher wrote:
>
>> On Wed, Aug 21, 2019 at 9:23 AM Yuan, Xiaojie wrote:
>>
>> navi1x has 2 sdma engines but commit
>> "e7b58d03b678 drm/amdgpu: reorganize sdma v4 code to support more instances"
>> changes the max number of sdma irq types (AMDGPU_SDMA_IRQ_LAST) from 2 to 8
>> which causes amdgpu_irq_gpu_reset_resume_helper() to recover irq of sdma
>> engines with following logic:
>>
>> (enable irq for sdma0) * 1 time
>> (enable irq for sdma1) * 1 time
>> (disable irq for sdma1) * 6 times
>>
>> as a result, after gpu reset, interrupt for sdma1 is lost.
>>
>> for asics with more sdma5 engines, we need to set 'num_types' depending
>> on asic type just like what sdma_v4_0_set_irq_funcs() does.
>>
>> Signed-off-by: Xiaojie Yuan
>> ---
>> drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
>> b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
>> index 41932d8b88c3..32bce3eb5fc2 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
>> @@ -1625,7 +1625,7 @@ static const struct amdgpu_irq_src_funcs
>> sdma_v5_0_illegal_inst_irq_funcs = {
>>
>> static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev)
>> {
>> - adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
>> + adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE2;
>
> It would be more future proof to set the num_types based on the num instances.
>
> Alex
>
>>adev->sdma.trap_irq.funcs = _v5_0_trap_irq_funcs;
>>adev->sdma.illegal_inst_irq.funcs = _v5_0_illegal_inst_irq_funcs;
>> }
>> --
>> 2.20.1
>>
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[PATCH] drm/amdgpu/sdma5: fix number of sdma5 trap irq types for navi1x
v2: set num_types based on num_instances
navi1x has 2 sdma engines but commit
"e7b58d03b678 drm/amdgpu: reorganize sdma v4 code to support more instances"
changes the max number of sdma irq types (AMDGPU_SDMA_IRQ_LAST) from 2 to 8
which causes amdgpu_irq_gpu_reset_resume_helper() to recover irq of sdma
engines with following logic:
(enable irq for sdma0) * 1 time
(enable irq for sdma1) * 1 time
(disable irq for sdma1) * 6 times
as a result, after gpu reset, interrupt for sdma1 is lost.
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
index 41932d8b88c3..89174e778d2f 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
@@ -1625,7 +1625,8 @@ static const struct amdgpu_irq_src_funcs
sdma_v5_0_illegal_inst_irq_funcs = {
static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev)
{
- adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
+ adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
+ adev->sdma.num_instances;
adev->sdma.trap_irq.funcs = _v5_0_trap_irq_funcs;
adev->sdma.illegal_inst_irq.funcs = _v5_0_illegal_inst_irq_funcs;
}
--
2.20.1
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[PATCH] drm/amdgpu/sdma5: fix number of sdma5 trap irq types for navi1x
navi1x has 2 sdma engines but commit
"e7b58d03b678 drm/amdgpu: reorganize sdma v4 code to support more instances"
changes the max number of sdma irq types (AMDGPU_SDMA_IRQ_LAST) from 2 to 8
which causes amdgpu_irq_gpu_reset_resume_helper() to recover irq of sdma
engines with following logic:
(enable irq for sdma0) * 1 time
(enable irq for sdma1) * 1 time
(disable irq for sdma1) * 6 times
as a result, after gpu reset, interrupt for sdma1 is lost.
for asics with more sdma5 engines, we need to set 'num_types' depending
on asic type just like what sdma_v4_0_set_irq_funcs() does.
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
index 41932d8b88c3..32bce3eb5fc2 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
@@ -1625,7 +1625,7 @@ static const struct amdgpu_irq_src_funcs
sdma_v5_0_illegal_inst_irq_funcs = {
static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev)
{
- adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
+ adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE2;
adev->sdma.trap_irq.funcs = _v5_0_trap_irq_funcs;
adev->sdma.illegal_inst_irq.funcs = _v5_0_illegal_inst_irq_funcs;
}
--
2.20.1
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Re: [PATCH] drm/amdgpu: Fix a typo in the include header guard of 'navi12_ip_offset.h'
Reviewed-by: Xiaojie Yuan Xiaojie > On Aug 19, 2019, at 12:00 AM, Christophe JAILLET > wrote: > > '_navi10_ip_offset_HEADER' is already used in 'navi10_ip_offset.h', so use > '_navi12_ip_offset_HEADER' instead here. > > Signed-off-by: Christophe JAILLET > --- > drivers/gpu/drm/amd/include/navi12_ip_offset.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/amd/include/navi12_ip_offset.h > b/drivers/gpu/drm/amd/include/navi12_ip_offset.h > index 229e8fddfcc1..6c2cc6296c06 100644 > --- a/drivers/gpu/drm/amd/include/navi12_ip_offset.h > +++ b/drivers/gpu/drm/amd/include/navi12_ip_offset.h > @@ -18,8 +18,8 @@ > * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN > * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. > */ > -#ifndef _navi10_ip_offset_HEADER > -#define _navi10_ip_offset_HEADER > +#ifndef _navi12_ip_offset_HEADER > +#define _navi12_ip_offset_HEADER > > #define MAX_INSTANCE 7 > #define MAX_SEGMENT5 > -- > 2.20.1 > ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: remove redundant argument for psp_funcs::cmd_submit callback
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 3 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 5 ++---
drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 1 -
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 1 -
drivers/gpu/drm/amd/amdgpu/psp_v12_0.c | 1 -
drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 1 -
6 files changed, 3 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 7715c0da5229..52dbdb4ebe0c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -144,8 +144,7 @@ psp_cmd_submit_buf(struct psp_context *psp,
memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
index = atomic_inc_return(>fence_value);
- ret = psp_cmd_submit(psp, ucode, psp->cmd_buf_mc_addr,
-fence_mc_addr, index);
+ ret = psp_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index);
if (ret) {
atomic_dec(>fence_value);
mutex_unlock(>mutex);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index 0029fa2b2ff9..b73d4aa28fba 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -90,7 +90,6 @@ struct psp_funcs
int (*ring_destroy)(struct psp_context *psp,
enum psp_ring_type ring_type);
int (*cmd_submit)(struct psp_context *psp,
- struct amdgpu_firmware_info *ucode,
uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
int index);
bool (*compare_sram_data)(struct psp_context *psp,
@@ -223,8 +222,8 @@ struct amdgpu_psp_funcs {
#define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type))
#define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type))
#define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type)))
-#define psp_cmd_submit(psp, ucode, cmd_mc, fence_mc, index) \
- (psp)->funcs->cmd_submit((psp), (ucode), (cmd_mc), (fence_mc),
(index))
+#define psp_cmd_submit(psp, cmd_mc, fence_mc, index) \
+ (psp)->funcs->cmd_submit((psp), (cmd_mc), (fence_mc), (index))
#define psp_compare_sram_data(psp, ucode, type) \
(psp)->funcs->compare_sram_data((psp), (ucode), (type))
#define psp_init_microcode(psp) \
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
index 77c2bc344dfc..e5fff6b30137 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
@@ -187,7 +187,6 @@ static int psp_v10_0_ring_destroy(struct psp_context *psp,
}
static int psp_v10_0_cmd_submit(struct psp_context *psp,
- struct amdgpu_firmware_info *ucode,
uint64_t cmd_buf_mc_addr, uint64_t
fence_mc_addr,
int index)
{
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index e3fd91e6a314..7277890838cc 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -496,7 +496,6 @@ static int psp_v11_0_ring_destroy(struct psp_context *psp,
}
static int psp_v11_0_cmd_submit(struct psp_context *psp,
- struct amdgpu_firmware_info *ucode,
uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
int index)
{
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
index f37b8af4b986..fd55baa6ea31 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
@@ -334,7 +334,6 @@ static int psp_v12_0_ring_destroy(struct psp_context *psp,
}
static int psp_v12_0_cmd_submit(struct psp_context *psp,
- struct amdgpu_firmware_info *ucode,
uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
int index)
{
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
index ba327581f301..4a02058682f5 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
@@ -409,7 +409,6 @@ static int psp_v3_1_ring_destroy(struct psp_context *psp,
}
static int psp_v3_1_cmd_submit(struct psp_context *psp,
- struct amdgpu_firmware_info *ucode,
uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
int index)
{
--
2.20.1
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[PATCH 2/2] drm/amdgpu: add firmware header printing for psp fw loading
firmware header information is printed for direct fw loading but not
added for psp fw loading yet
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 54 +
1 file changed, 54 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 4b2d2fd72dc6..7715c0da5229 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -944,6 +944,58 @@ static int psp_get_fw_type(struct amdgpu_firmware_info
*ucode,
return 0;
}
+static void psp_print_fw_hdr(struct psp_context *psp,
+struct amdgpu_firmware_info *ucode)
+{
+ struct amdgpu_device *adev = psp->adev;
+ const struct sdma_firmware_header_v1_0 *sdma_hdr =
+ (const struct sdma_firmware_header_v1_0 *)
+ adev->sdma.instance[ucode->ucode_id -
AMDGPU_UCODE_ID_SDMA0].fw->data;
+ const struct gfx_firmware_header_v1_0 *ce_hdr =
+ (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
+ const struct gfx_firmware_header_v1_0 *pfp_hdr =
+ (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
+ const struct gfx_firmware_header_v1_0 *me_hdr =
+ (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
+ const struct gfx_firmware_header_v1_0 *mec_hdr =
+ (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
+ const struct rlc_firmware_header_v2_0 *rlc_hdr =
+ (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
+ const struct smc_firmware_header_v1_0 *smc_hdr =
+ (const struct smc_firmware_header_v1_0 *)adev->pm.fw->data;
+
+ switch (ucode->ucode_id) {
+ case AMDGPU_UCODE_ID_SDMA0:
+ case AMDGPU_UCODE_ID_SDMA1:
+ case AMDGPU_UCODE_ID_SDMA2:
+ case AMDGPU_UCODE_ID_SDMA3:
+ case AMDGPU_UCODE_ID_SDMA4:
+ case AMDGPU_UCODE_ID_SDMA5:
+ case AMDGPU_UCODE_ID_SDMA6:
+ case AMDGPU_UCODE_ID_SDMA7:
+ amdgpu_ucode_print_sdma_hdr(_hdr->header);
+ break;
+ case AMDGPU_UCODE_ID_CP_CE:
+ amdgpu_ucode_print_gfx_hdr(_hdr->header);
+ break;
+ case AMDGPU_UCODE_ID_CP_PFP:
+ amdgpu_ucode_print_gfx_hdr(_hdr->header);
+ break;
+ case AMDGPU_UCODE_ID_CP_ME:
+ amdgpu_ucode_print_gfx_hdr(_hdr->header);
+ break;
+ case AMDGPU_UCODE_ID_CP_MEC1:
+ amdgpu_ucode_print_gfx_hdr(_hdr->header);
+ break;
+ case AMDGPU_UCODE_ID_RLC_G:
+ amdgpu_ucode_print_rlc_hdr(_hdr->header);
+ break;
+ case AMDGPU_UCODE_ID_SMC:
+ amdgpu_ucode_print_smc_hdr(_hdr->header);
+ break;
+ }
+}
+
static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode,
struct psp_gfx_cmd_resp *cmd)
{
@@ -1028,6 +1080,8 @@ static int psp_np_fw_load(struct psp_context *psp)
ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)
continue;
+ psp_print_fw_hdr(psp, ucode);
+
ret = psp_execute_np_fw_load(psp, ucode);
if (ret)
return ret;
--
2.20.1
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[PATCH 1/2] drm/amdgpu: fix debug level for ppt offset/size
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index 35fd46bdfc53..82f6b413718b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -83,8 +83,8 @@ void amdgpu_ucode_print_smc_hdr(const struct
common_firmware_header *hdr)
const struct smc_firmware_header_v2_0 *v2_hdr =
container_of(v1_hdr, struct smc_firmware_header_v2_0,
v1_0);
- DRM_INFO("ppt_offset_bytes: %u\n",
le32_to_cpu(v2_hdr->ppt_offset_bytes));
- DRM_INFO("ppt_size_bytes: %u\n",
le32_to_cpu(v2_hdr->ppt_size_bytes));
+ DRM_DEBUG("ppt_offset_bytes: %u\n",
le32_to_cpu(v2_hdr->ppt_offset_bytes));
+ DRM_DEBUG("ppt_size_bytes: %u\n",
le32_to_cpu(v2_hdr->ppt_size_bytes));
} else {
DRM_ERROR("Unknown SMC ucode version: %u.%u\n", version_major,
version_minor);
}
--
2.20.1
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[PATCH] drm/amdgpu: remove special autoload handling for navi12
s/r list in rlc firmware is ready, so remove the special autoload handling
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index aaa4cdf8bcae..4b2d2fd72dc6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -1033,8 +1033,7 @@ static int psp_np_fw_load(struct psp_context *psp)
return ret;
/* Start rlc autoload after psp recieved all the gfx firmware */
- if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM
||
- (adev->asic_type == CHIP_NAVI12 && ucode->ucode_id ==
AMDGPU_UCODE_ID_RLC_G)) {
+ if (ucode->ucode_id ==
AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM) {
ret = psp_rlc_autoload(psp);
if (ret) {
DRM_ERROR("Failed to start rlc autoload\n");
--
2.20.1
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[PATCH] drm/amd/powerplay: disable gfxoff for navi12
gfxoff doesn't work on navi12 yet, so disable it for now
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 066ba593af23..d644669e5d93 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -580,6 +580,7 @@ static void gfx_v10_0_check_gfxoff_flag(struct
amdgpu_device *adev)
{
switch (adev->asic_type) {
case CHIP_NAVI10:
+ case CHIP_NAVI12:
adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
break;
default:
--
2.20.1
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[PATCH] drm/amd/powerplay: add smu if version for navi12
Signed-off-by: Xiaojie Yuan --- drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 1 + drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h index 97605e963c2b..eb04d06757d3 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h +++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h @@ -28,6 +28,7 @@ #define SMU11_DRIVER_IF_VERSION_INV 0x #define SMU11_DRIVER_IF_VERSION_VG20 0x13 #define SMU11_DRIVER_IF_VERSION_NV10 0x33 +#define SMU11_DRIVER_IF_VERSION_NV12 0x33 #define SMU11_DRIVER_IF_VERSION_NV14 0x33 /* MP Apertures */ diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c index 91dfae1a2b16..1e766a8a8447 100644 --- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c +++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c @@ -278,6 +278,9 @@ static int smu_v11_0_check_fw_version(struct smu_context *smu) case CHIP_NAVI10: smu->smc_if_version = SMU11_DRIVER_IF_VERSION_NV10; break; + case CHIP_NAVI12: + smu->smc_if_version = SMU11_DRIVER_IF_VERSION_NV12; + break; case CHIP_NAVI14: smu->smc_if_version = SMU11_DRIVER_IF_VERSION_NV14; break; -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: add navi14 PCI ID
Reviewed-by: Xiaojie Yuan
BR,
Xiaojie
From: amd-gfx on behalf of Alex Deucher
Sent: Thursday, August 8, 2019 3:41 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH] drm/amdgpu: add navi14 PCI ID
Add the navi14 PCI device id.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index cf334c465805..79e22c221b77 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -1007,6 +1007,8 @@ static const struct pci_device_id pciidlist[] = {
{0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
{0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
{0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
+ /* Navi14 */
+ {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
{0, 0, 0}
};
--
2.20.1
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[PATCH 04/10] drm/amdgpu: enable sdma clock gating for navi12
enables sdma medium grained clock gating and memory light sleep Signed-off-by: Xiaojie Yuan Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/nv.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index c48b853bedcf..5c8f7b7ab3c5 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -567,7 +567,9 @@ static int nv_common_early_init(void *handle) AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_HDP_MGCG | - AMD_CG_SUPPORT_HDP_LS; + AMD_CG_SUPPORT_HDP_LS | + AMD_CG_SUPPORT_SDMA_MGCG | + AMD_CG_SUPPORT_SDMA_LS; adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG; adev->external_rev_id = adev->rev_id + 0xa; break; -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 05/10] drm/amdgpu/mmhub2: set clock gating for navi12
add navi12 define
Signed-off-by: Xiaojie Yuan
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
index 9d8acb4c2e22..beef51c3746f 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
@@ -421,6 +421,7 @@ int mmhub_v2_0_set_clockgating(struct amdgpu_device *adev,
switch (adev->asic_type) {
case CHIP_NAVI10:
+ case CHIP_NAVI12:
mmhub_v2_0_update_medium_grain_clock_gating(adev,
state == AMD_CG_STATE_GATE ? true : false);
mmhub_v2_0_update_medium_grain_light_sleep(adev,
--
2.20.1
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[PATCH 09/10] drm/amdgpu: enable athub clock gating for navi12
enables athub medium grained clock gating and memory light sleep Signed-off-by: Xiaojie Yuan Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/nv.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index bc529f0a6b5b..302c60b14196 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -572,7 +572,9 @@ static int nv_common_early_init(void *handle) AMD_CG_SUPPORT_SDMA_MGCG | AMD_CG_SUPPORT_SDMA_LS | AMD_CG_SUPPORT_MC_MGCG | - AMD_CG_SUPPORT_MC_LS; + AMD_CG_SUPPORT_MC_LS | + AMD_CG_SUPPORT_ATHUB_MGCG | + AMD_CG_SUPPORT_ATHUB_LS; adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG; adev->external_rev_id = adev->rev_id + 0xa; break; -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 07/10] drm/amdgpu: enable ih clock gating for navi12
enables ih clock gating Signed-off-by: Xiaojie Yuan Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/nv.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index 9b97b2543454..bc529f0a6b5b 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -566,6 +566,7 @@ static int nv_common_early_init(void *handle) AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_RLC_LS | + AMD_CG_SUPPORT_IH_CG | AMD_CG_SUPPORT_HDP_MGCG | AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_SDMA_MGCG | -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 08/10] drm/amdgpu/athub2: set clock gating for navi12
add navi12 define
Signed-off-by: Xiaojie Yuan
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/athub_v2_0.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/athub_v2_0.c
b/drivers/gpu/drm/amd/amdgpu/athub_v2_0.c
index d3d7c2176933..45f262c6c60f 100644
--- a/drivers/gpu/drm/amd/amdgpu/athub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/athub_v2_0.c
@@ -74,6 +74,7 @@ int athub_v2_0_set_clockgating(struct amdgpu_device *adev,
switch (adev->asic_type) {
case CHIP_NAVI10:
+ case CHIP_NAVI12:
athub_v2_0_update_medium_grain_clock_gating(adev,
state == AMD_CG_STATE_GATE ? true : false);
athub_v2_0_update_medium_grain_light_sleep(adev,
--
2.20.1
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[PATCH 03/10] drm/amdgpu/sdma5: set sdma clock gating for navi12
add navi12 define
Signed-off-by: Xiaojie Yuan
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
index 2a9512132520..a54ee320961e 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
@@ -1491,6 +1491,7 @@ static int sdma_v5_0_set_clockgating_state(void *handle,
switch (adev->asic_type) {
case CHIP_NAVI10:
+ case CHIP_NAVI12:
sdma_v5_0_update_medium_grain_clock_gating(adev,
state == AMD_CG_STATE_GATE ? true : false);
sdma_v5_0_update_medium_grain_light_sleep(adev,
--
2.20.1
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[PATCH 02/10] drm/amdgpu: enable hdp clock gating for navi12
enables hdp medium grained clock gating and memory light sleep Signed-off-by: Xiaojie Yuan Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/nv.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index aef7a5b32b34..c48b853bedcf 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -565,7 +565,9 @@ static int nv_common_early_init(void *handle) AMD_CG_SUPPORT_GFX_MGLS | AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CP_LS | - AMD_CG_SUPPORT_GFX_RLC_LS; + AMD_CG_SUPPORT_GFX_RLC_LS | + AMD_CG_SUPPORT_HDP_MGCG | + AMD_CG_SUPPORT_HDP_LS; adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG; adev->external_rev_id = adev->rev_id + 0xa; break; -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 10/10] drm/amdgpu: enable vcn clock gating for navi12
enables vcn medium grained clock gating Signed-off-by: Xiaojie Yuan Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/nv.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index 302c60b14196..a13032fde5f7 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -574,7 +574,8 @@ static int nv_common_early_init(void *handle) AMD_CG_SUPPORT_MC_MGCG | AMD_CG_SUPPORT_MC_LS | AMD_CG_SUPPORT_ATHUB_MGCG | - AMD_CG_SUPPORT_ATHUB_LS; + AMD_CG_SUPPORT_ATHUB_LS | + AMD_CG_SUPPORT_VCN_MGCG; adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG; adev->external_rev_id = adev->rev_id + 0xa; break; -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 06/10] drm/amdgpu: enable mmhub clock gating for navi12
enables mmhub medium grained clock gating and memory light sleep Signed-off-by: Xiaojie Yuan Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/nv.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index 5c8f7b7ab3c5..9b97b2543454 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -569,7 +569,9 @@ static int nv_common_early_init(void *handle) AMD_CG_SUPPORT_HDP_MGCG | AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_SDMA_MGCG | - AMD_CG_SUPPORT_SDMA_LS; + AMD_CG_SUPPORT_SDMA_LS | + AMD_CG_SUPPORT_MC_MGCG | + AMD_CG_SUPPORT_MC_LS; adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG; adev->external_rev_id = adev->rev_id + 0xa; break; -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 01/10] drm/amdgpu: enable gfx clock gatings for navi12
enables following gfx clock gating features: - medium grained clock gating - medium grained light sleep - coarse grained clock gating - cp memory light sleep - rlc memory light sleep CGLS (Coarse Grained Light Sleep) will break s3, so don't enable it. Signed-off-by: Xiaojie Yuan Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/nv.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index 74beace5323c..aef7a5b32b34 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -561,7 +561,11 @@ static int nv_common_early_init(void *handle) adev->external_rev_id = adev->rev_id + 0x1; break; case CHIP_NAVI12: - adev->cg_flags = 0; + adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | + AMD_CG_SUPPORT_GFX_MGLS | + AMD_CG_SUPPORT_GFX_CGCG | + AMD_CG_SUPPORT_GFX_CP_LS | + AMD_CG_SUPPORT_GFX_RLC_LS; adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG; adev->external_rev_id = adev->rev_id + 0xa; break; -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 00/10] Enable clock gating for Navi12
Alex has helped to reviewed these patches in AMD internally. Re-send them to public mail list. Xiaojie Yuan (10): drm/amdgpu: enable gfx clock gatings for navi12 drm/amdgpu: enable hdp clock gating for navi12 drm/amdgpu/sdma5: set sdma clock gating for navi12 drm/amdgpu: enable sdma clock gating for navi12 drm/amdgpu/mmhub2: set clock gating for navi12 drm/amdgpu: enable mmhub clock gating for navi12 drm/amdgpu: enable ih clock gating for navi12 drm/amdgpu/athub2: set clock gating for navi12 drm/amdgpu: enable athub clock gating for navi12 drm/amdgpu: enable vcn clock gating for navi12 drivers/gpu/drm/amd/amdgpu/athub_v2_0.c | 1 + drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 1 + drivers/gpu/drm/amd/amdgpu/nv.c | 16 +++- drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 1 + 4 files changed, 18 insertions(+), 1 deletion(-) -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu/discovery: move common discovery code out of navi1*_reg_base_init()
move amdgpu_discovery_reg_base_init() from navi1*_reg_base_init() to a
common function nv_reg_base_init().
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c | 14 +-
drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c | 14 +-
drivers/gpu/drm/amd/amdgpu/nv.c | 29 ++--
3 files changed, 29 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c
b/drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c
index 55014ce8670a..a56c93620e78 100644
--- a/drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c
+++ b/drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c
@@ -29,20 +29,8 @@
int navi10_reg_base_init(struct amdgpu_device *adev)
{
- int r, i;
+ int i;
- if (amdgpu_discovery) {
- r = amdgpu_discovery_reg_base_init(adev);
- if (r) {
- DRM_WARN("failed to init reg base from ip discovery
table, "
- "fallback to legacy init method\n");
- goto legacy_init;
- }
-
- return 0;
- }
-
-legacy_init:
for (i = 0 ; i < MAX_INSTANCE ; ++i) {
adev->reg_offset[GC_HWIP][i] = (uint32_t
*)(&(GC_BASE.instance[i]));
adev->reg_offset[HDP_HWIP][i] = (uint32_t
*)(&(HDP_BASE.instance[i]));
diff --git a/drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c
b/drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c
index 864668a7f1d2..3b5f0f65e096 100644
--- a/drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c
+++ b/drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c
@@ -29,20 +29,8 @@
int navi14_reg_base_init(struct amdgpu_device *adev)
{
- int r, i;
+ int i;
- if (amdgpu_discovery) {
- r = amdgpu_discovery_reg_base_init(adev);
- if (r) {
- DRM_WARN("failed to init reg base from ip discovery
table, "
- "fallback to legacy init method\n");
- goto legacy_init;
- }
-
- return 0;
- }
-
-legacy_init:
for (i = 0 ; i < MAX_INSTANCE ; ++i) {
adev->reg_offset[GC_HWIP][i] = (uint32_t
*)(&(GC_BASE.instance[i]));
adev->reg_offset[HDP_HWIP][i] = (uint32_t
*)(&(HDP_BASE.instance[i]));
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 9614c65fa292..9e3d8d4a0d86 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -375,9 +375,22 @@ static const struct amdgpu_ip_block_version
nv_common_ip_block =
.funcs = _common_ip_funcs,
};
-int nv_set_ip_blocks(struct amdgpu_device *adev)
+static int nv_reg_base_init(struct amdgpu_device *adev)
{
- /* Set IP register base before any HW register access */
+ int r;
+
+ if (amdgpu_discovery) {
+ r = amdgpu_discovery_reg_base_init(adev);
+ if (r) {
+ DRM_WARN("failed to init reg base from ip discovery
table, "
+ "fallback to legacy init method\n");
+ goto legacy_init;
+ }
+
+ return 0;
+ }
+
+legacy_init:
switch (adev->asic_type) {
case CHIP_NAVI10:
navi10_reg_base_init(adev);
@@ -392,6 +405,18 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
return -EINVAL;
}
+ return 0;
+}
+
+int nv_set_ip_blocks(struct amdgpu_device *adev)
+{
+ int r;
+
+ /* Set IP register base before any HW register access */
+ r = nv_reg_base_init(adev);
+ if (r)
+ return r;
+
adev->nbio_funcs = _v2_3_funcs;
adev->nbio_funcs->detect_hw_virt(adev);
--
2.20.1
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Re: [PATCH] drm/amdgpu/soc15: fix external_rev_id for navi14
Reviewed-by: Xiaojie Yuan BR, Xiaojie From: Tianci Yin Sent: Monday, August 5, 2019 5:35 PM To: amd-gfx@lists.freedesktop.org Cc: Zhang, Hawking; Xiao, Jack; Yuan, Xiaojie; Yin, Tianci (Rico) Subject: [PATCH] drm/amdgpu/soc15: fix external_rev_id for navi14 From: tiancyin fix the hard code external_rev_id. Change-Id: I7b46f7b49b6d0586d1fa282d4961815fb124379b Signed-off-by: tiancyin --- drivers/gpu/drm/amd/amdgpu/nv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index 9bce6a1..2f45bf2 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -546,7 +546,7 @@ static int nv_common_early_init(void *handle) AMD_CG_SUPPORT_BIF_LS; adev->pg_flags = AMD_PG_SUPPORT_VCN | AMD_PG_SUPPORT_VCN_DPG; - adev->external_rev_id = 20; + adev->external_rev_id = adev->rev_id + 20; break; default: /* FIXME: not supported yet */ -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: pin the csb buffer on hw init for gfx v8
Reviewed-by: Xiaojie Yuan
BR,
Xiaojie
> On Aug 5, 2019, at 10:20 AM, Xu, Feifei wrote:
>
> Reviewed-by: Feifei Xu
>
> -Original Message-
> From: amd-gfx On Behalf Of Gao Likun
> Sent: Monday, August 5, 2019 10:07 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Gao, Likun
> ; Paul Gover ; Yuan, Xiaojie
>
> Subject: [PATCH] drm/amdgpu: pin the csb buffer on hw init for gfx v8
>
> From: Likun Gao
>
> Without this pin, the csb buffer will be filled with inconsistent data after
> S3 resume. And that will causes gfx hang on gfxoff exit since this csb will
> be executed then.
>
> Signed-off-by: Likun Gao
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 40 +++
> 1 file changed, 40 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index d290718..98e5aa8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -1317,6 +1317,39 @@ static int gfx_v8_0_rlc_init(struct amdgpu_device
> *adev)
>return 0;
> }
>
> +static int gfx_v8_0_csb_vram_pin(struct amdgpu_device *adev) {
> +int r;
> +
> +r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
> +if (unlikely(r != 0))
> +return r;
> +
> +r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj,
> +AMDGPU_GEM_DOMAIN_VRAM);
> +if (!r)
> +adev->gfx.rlc.clear_state_gpu_addr =
> +amdgpu_bo_gpu_offset(adev->gfx.rlc.clear_state_obj);
> +
> +amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
> +
> +return r;
> +}
> +
> +static void gfx_v8_0_csb_vram_unpin(struct amdgpu_device *adev) {
> +int r;
> +
> +if (!adev->gfx.rlc.clear_state_obj)
> +return;
> +
> +r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true);
> +if (likely(r == 0)) {
> +amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
> +amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
> +}
> +}
> +
> static void gfx_v8_0_mec_fini(struct amdgpu_device *adev) {
>amdgpu_bo_free_kernel(>gfx.mec.hpd_eop_obj, NULL, NULL); @@ -4791,6
> +4824,10 @@ static int gfx_v8_0_hw_init(void *handle)
>gfx_v8_0_init_golden_registers(adev);
>gfx_v8_0_constants_init(adev);
>
> +r = gfx_v8_0_csb_vram_pin(adev);
> +if (r)
> +return r;
> +
>r = adev->gfx.rlc.funcs->resume(adev);
>if (r)
>return r;
> @@ -4907,6 +4944,9 @@ static int gfx_v8_0_hw_fini(void *handle)
>else
>pr_err("rlc is busy, skip halt rlc\n");
>amdgpu_gfx_rlc_exit_safe_mode(adev);
> +
> +gfx_v8_0_csb_vram_unpin(adev);
> +
>return 0;
> }
>
> --
> 2.7.4
>
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Re: [PATCH] drm/amdgpu: remove unpin clear_state_obj for gfx v8
Hi Likun,
Looks like you can pin csb buffer @gfx_v8_0_hw_init() just like what following
patch does for gfx9, so that we can still use the common function
amdgpu_gfx_rlc_init_csb():
commit 137dc4b9060e99a22dce59b42ca71912cf0180f3
Author: Evan Quan
Date: Wed Jul 4 16:21:52 2018 +0800
drm/amdgpu: pin the csb buffer on hw init v2
Without this pin, the csb buffer will be filled with inconsistent
data after S3 resume. And that will causes gfx hang on gfxoff
exit since this csb will be executed then.
v2: fit amdgpu_bo_pin change(take one less argument)
Signed-off-by: Evan Quan
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
BR,
Xiaojie
From: amd-gfx on behalf of likun Gao
Sent: Friday, August 2, 2019 1:22 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander; Gao, Likun; Paul Gover
Subject: [PATCH] drm/amdgpu: remove unpin clear_state_obj for gfx v8
From: Likun Gao
Remove unpin rlc clear_state_obj for gfx v8 when rlc init,
which will make Stoney pm_suspend hang.
Signed-off-by: Likun Gao
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 22 +++---
1 file changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index d290718..0b73c6e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -1292,6 +1292,8 @@ static int gfx_v8_0_cp_jump_table_num(struct
amdgpu_device *adev)
static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
{
+ volatile u32 *dst_ptr;
+ u32 dws;
const struct cs_section_def *cs_data;
int r;
@@ -1300,10 +1302,24 @@ static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
cs_data = adev->gfx.rlc.cs_data;
if (cs_data) {
- /* init clear state block */
- r = amdgpu_gfx_rlc_init_csb(adev);
- if (r)
+ /* clear state block */
+ adev->gfx.rlc.clear_state_size = dws =
adev->gfx.rlc.funcs->get_csb_size(adev);
+ r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
+ AMDGPU_GEM_DOMAIN_VRAM,
+ >gfx.rlc.clear_state_obj,
+
>gfx.rlc.clear_state_gpu_addr,
+ (void **)>gfx.rlc.cs_ptr);
+ if (r) {
+ dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
+ amdgpu_gfx_rlc_fini(adev);
return r;
+ }
+
+ /* set up the cs buffer */
+ dst_ptr = adev->gfx.rlc.cs_ptr;
+ adev->gfx.rlc.funcs->get_csb_buffer(adev, dst_ptr);
+ amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
+ amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
}
if ((adev->asic_type == CHIP_CARRIZO) ||
--
2.7.4
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Re: [PATCH 2/2] drm/amdkfd: enable KFD support for navi14
Reviewed-by: Xiaojie Yuan BR, Xiaojie From: amd-gfx on behalf of Alex Deucher Sent: Saturday, July 27, 2019 3:16 AM To: amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander Subject: [PATCH 2/2] drm/amdkfd: enable KFD support for navi14 Same as navi10. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index f052c70e4659..97f7c5235cc9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -91,6 +91,7 @@ void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev) kfd2kgd = amdgpu_amdkfd_arcturus_get_functions(); break; case CHIP_NAVI10: + case CHIP_NAVI14: kfd2kgd = amdgpu_amdkfd_gfx_10_0_get_functions(); break; default: -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 1/2] drm/amdgpu/gfx10: update golden settings for navi14
Reviewed-by: Xiaojie Yuan BR, Xiaojie From: amd-gfx on behalf of Alex Deucher Sent: Saturday, July 27, 2019 3:16 AM To: amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander Subject: [PATCH 1/2] drm/amdgpu/gfx10: update golden settings for navi14 Updated settings for hw team. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 6162703e20d2..8e7e62492bfb 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -138,7 +138,6 @@ static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x, 0x0490), SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x, 0x003f), SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0x, 0x03860204), - SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x0043), SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0, 0x0500), SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x07ff, 0x01fe), SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x, 0xe4e4e4e4), -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu/psp11: check if prior to navi10 for sram map
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index 87596c69b235..a8b526dbb6c6 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -538,7 +538,7 @@ psp_v11_0_sram_map(struct amdgpu_device *adev,
case AMDGPU_UCODE_ID_RLC_G:
*sram_offset = 0x2000;
- if (adev->asic_type != CHIP_NAVI10) {
+ if (adev->asic_type < CHIP_NAVI10) {
*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0,
mmRLC_GPM_UCODE_ADDR);
*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0,
mmRLC_GPM_UCODE_DATA);
}
@@ -550,7 +550,7 @@ psp_v11_0_sram_map(struct amdgpu_device *adev,
case AMDGPU_UCODE_ID_SDMA0:
*sram_offset = 0x0;
- if (adev->asic_type != CHIP_NAVI10) {
+ if (adev->asic_type < CHIP_NAVI10) {
*sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0,
mmSDMA0_UCODE_ADDR);
*sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0,
mmSDMA0_UCODE_DATA);
}
--
2.20.1
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Re: [PATCH] drm/amdgpu/discovery: fix DCE_HWIP mapping error in hw_id_map array
Reviewed-by: Xiaojie Yuan
BR,
Xiaojie
From: amd-gfx on behalf of Tianci Yin
Sent: Thursday, July 11, 2019 4:00 PM
To: amd-gfx@lists.freedesktop.org
Cc: Xiao, Jack; Yuan, Xiaojie; Yin, Tianci (Rico); Zhang, Hawking
Subject: [PATCH] drm/amdgpu/discovery: fix DCE_HWIP mapping error in hw_id_map
array
From: tiancyin
ID of DCE_HWIP from vbios is DMU_HWID,
mismatch cause null pointer crash in navi10 modprobe.
Change-Id: I3be363cf5248de904b3bdae2f34d3bbe0bbbc07d
Signed-off-by: tiancyin
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index e049ae6..1481899 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -123,7 +123,7 @@ static int hw_id_map[MAX_HWIP] = {
[UVD_HWIP] = UVD_HWID,
[VCE_HWIP] = VCE_HWID,
[DF_HWIP] = DF_HWID,
- [DCE_HWIP] = DCEAZ_HWID,
+ [DCE_HWIP] = DMU_HWID,
[OSSSYS_HWIP] = OSSSYS_HWID,
[SMUIO_HWIP]= SMUIO_HWID,
[PWR_HWIP] = PWR_HWID,
--
2.7.4
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Re: [PATCH 1/2] drm/amdgpu: switch to macro for psp bootloader command
Reviewed-by: Xiaojie Yuan
BR,
Xiaojie
From: amd-gfx on behalf of Hawking
Zhang
Sent: Wednesday, July 10, 2019 11:58 PM
To: amd-gfx@lists.freedesktop.org; Yuan, Xiaojie; Clements, John; Deucher,
Alexander
Cc: Zhang, Hawking
Subject: [PATCH 1/2] drm/amdgpu: switch to macro for psp bootloader command
Change-Id: Ief4c1e5ca01df0a028a784c0faf37544939733a3
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 9 +
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 4 ++--
3 files changed, 13 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index e28cf5e..8ddcec1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -42,6 +42,15 @@ struct psp_context;
struct psp_xgmi_node_info;
struct psp_xgmi_topology_info;
+enum psp_bootloader_cmd {
+ PSP_BL__LOAD_SYSDRV = 0x1,
+ PSP_BL__LOAD_SOSDRV = 0x2,
+ PSP_BL__NO_ECC = 0x4,
+ PSP_BL__PARTIAL_ECC = 0x5,
+ PSP_BL__FULL_ECC= 0x6,
+ PSP_BL__LOAD_KEY_DATABASE = 0x8,
+};
+
enum psp_ring_type
{
PSP_RING_TYPE__INVALID = 0,
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index 1b6c20c..e784091 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -212,7 +212,7 @@ static int psp_v11_0_bootloader_load_sysdrv(struct
psp_context *psp)
/* Provide the sys driver to bootloader */
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
(uint32_t)(psp->fw_pri_mc_addr >> 20));
- psp_gfxdrv_command_reg = 1 << 16;
+ psp_gfxdrv_command_reg = PSP_BL__LOAD_SYSDRV;
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
psp_gfxdrv_command_reg);
@@ -253,7 +253,7 @@ static int psp_v11_0_bootloader_load_sos(struct psp_context
*psp)
/* Provide the PSP secure OS to bootloader */
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
(uint32_t)(psp->fw_pri_mc_addr >> 20));
- psp_gfxdrv_command_reg = 2 << 16;
+ psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
psp_gfxdrv_command_reg);
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
index 3f58277..ec3a056 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
@@ -153,7 +153,7 @@ static int psp_v3_1_bootloader_load_sysdrv(struct
psp_context *psp)
/* Provide the sys driver to bootloader */
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
(uint32_t)(psp->fw_pri_mc_addr >> 20));
- psp_gfxdrv_command_reg = 1 << 16;
+ psp_gfxdrv_command_reg = PSP_BL__LOAD_SYSDRV;
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
psp_gfxdrv_command_reg);
@@ -216,7 +216,7 @@ static int psp_v3_1_bootloader_load_sos(struct psp_context
*psp)
/* Provide the PSP secure OS to bootloader */
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
(uint32_t)(psp->fw_pri_mc_addr >> 20));
- psp_gfxdrv_command_reg = 2 << 16;
+ psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
psp_gfxdrv_command_reg);
--
2.7.4
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Re: [PATCH 2/2] drm/amdgpu: support key database loading for navi10
Reviewed-by: Xiaojie Yuan
BR,
Xiaojie
From: amd-gfx on behalf of Hawking
Zhang
Sent: Wednesday, July 10, 2019 11:58 PM
To: amd-gfx@lists.freedesktop.org; Yuan, Xiaojie; Clements, John; Deucher,
Alexander
Cc: Zhang, Hawking
Subject: [PATCH 2/2] drm/amdgpu: support key database loading for navi10
Starting from navi10, driver should send Key Database Load command
to Bootloader before loading sys_drv and sos
Change-Id: Ib82d21840fb77da2217dd8b8f013177e61d72990
Signed-off-by: John Clements
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 10 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 5
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 6
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 3 ++
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c| 49 ++-
5 files changed, 72 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index ed580e8b..3378cb38 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -770,6 +770,16 @@ static int psp_hw_start(struct psp_context *psp)
int ret;
if (!amdgpu_sriov_vf(adev) || !adev->in_gpu_reset) {
+
+ if (psp->kdb_start_addr &&
+ (psp->funcs->bootloader_load_kdb != NULL)) {
+ ret = psp_bootloader_load_kdb(psp);
+ if (ret) {
+ DRM_ERROR("PSP load kdb failed!\n");
+ return ret;
+ }
+ }
+
ret = psp_bootloader_load_sysdrv(psp);
if (ret) {
DRM_ERROR("PSP load sysdrv failed!\n");
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index 8ddcec1..6f1746b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -82,6 +82,7 @@ enum psp_reg_prog_id {
struct psp_funcs
{
int (*init_microcode)(struct psp_context *psp);
+ int (*bootloader_load_kdb)(struct psp_context *psp);
int (*bootloader_load_sysdrv)(struct psp_context *psp);
int (*bootloader_load_sos)(struct psp_context *psp);
int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type);
@@ -165,9 +166,11 @@ struct psp_context
uint32_tsys_bin_size;
uint32_tsos_bin_size;
uint32_ttoc_bin_size;
+ uint32_tkdb_bin_size;
uint8_t *sys_start_addr;
uint8_t *sos_start_addr;
uint8_t *toc_start_addr;
+ uint8_t *kdb_start_addr;
/* tmr buffer */
struct amdgpu_bo*tmr_bo;
@@ -229,6 +232,8 @@ struct amdgpu_psp_funcs {
(psp)->funcs->compare_sram_data((psp), (ucode), (type))
#define psp_init_microcode(psp) \
((psp)->funcs->init_microcode ?
(psp)->funcs->init_microcode((psp)) : 0)
+#define psp_bootloader_load_kdb(psp) \
+ ((psp)->funcs->bootloader_load_kdb ?
(psp)->funcs->bootloader_load_kdb((psp)) : 0)
#define psp_bootloader_load_sysdrv(psp) \
((psp)->funcs->bootloader_load_sysdrv ?
(psp)->funcs->bootloader_load_sysdrv((psp)) : 0)
#define psp_bootloader_load_sos(psp) \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index bf7e8ba..2042b60 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -262,6 +262,12 @@ void amdgpu_ucode_print_psp_hdr(const struct
common_firmware_header *hdr)
le32_to_cpu(psp_hdr_v1_1->toc_offset_bytes));
DRM_DEBUG("toc_size_bytes: %u\n",
le32_to_cpu(psp_hdr_v1_1->toc_size_bytes));
+ DRM_DEBUG("kdb_header_version: %u\n",
+
le32_to_cpu(psp_hdr_v1_1->kdb_header_version));
+ DRM_DEBUG("kdb_offset_bytes: %u\n",
+ le32_to_cpu(psp_hdr_v1_1->kdb_offset_bytes));
+ DRM_DEBUG("kdb_size_bytes: %u\n",
+ le32_to_cpu(psp_hdr_v1_1->kdb_size_bytes));
}
} else {
DRM_ERROR("Unknown PSP ucode version: %u.%u\n",
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
index f4694445..c1fb6dc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
@@ -85,6 +85,9 @@ struct p
Re: [PATCH 3/3] drm/amdgpu: enable IP discovery by default on navi
Series is Reviewed-by: Xiaojie Yuan
BR,
Xiaojie
> On Jul 9, 2019, at 2:48 AM, Alex Deucher wrote:
>
> Use the IP discovery table rather than hardcoding the
> settings in the driver.
>
> Reviewed-by: Xiaojie Yuan
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index 7941a5368fb5..6f7772eeeb78 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -140,7 +140,7 @@ uint amdgpu_smu_memory_pool_size = 0;
> uint amdgpu_dc_feature_mask = 0;
> int amdgpu_async_gfx_ring = 1;
> int amdgpu_mcbp = 0;
> -int amdgpu_discovery = 0;
> +int amdgpu_discovery = -1;
> int amdgpu_mes = 0;
>
> struct amdgpu_mgpu_info mgpu_info = {
> @@ -592,6 +592,7 @@ module_param_named(mcbp, amdgpu_mcbp, int, 0444);
> /**
> * DOC: discovery (int)
> * Allow driver to discover hardware IP information from IP Discovery table
> at the top of VRAM.
> + * (-1 = auto (default), 0 = disabled, 1 = enabled)
> */
> MODULE_PARM_DESC(discovery,
>"Allow driver to discover hardware IPs from IP Discovery table at the top
> of VRAM");
> --
> 2.20.1
>
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Re: [PATCH 2/2] drm/amdgpu: enable IP discovery by default on navi
and we might need a follow-up patch to check if (amdgpu_discovery && asic_type
>= CHIP_NAVI10) in amdgpu_device.c.
BR,
Xiaojie
From: amd-gfx on behalf of Yuan,
Xiaojie
Sent: Monday, July 8, 2019 11:45 PM
To: Deucher, Alexander; Alex Deucher; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/2] drm/amdgpu: enable IP discovery by default on navi
Got it. Thanks for the explanation.
Patch is Reviewed-by: Xiaojie Yuan
BR,
Xiaojie
From: Deucher, Alexander
Sent: Monday, July 8, 2019 11:38 PM
To: Yuan, Xiaojie; Alex Deucher; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/2] drm/amdgpu: enable IP discovery by default on navi
auto just means do the right thing for each asic. For example, if there is a
new asic program and the discovery tables are not available yet, for that
program, auto means don't use the discovery table. For other programs where
the table is available (e.g., navi10 and 14), then auto means use the table.
Alex
From: Yuan, Xiaojie
Sent: Monday, July 8, 2019 11:31 AM
To: Alex Deucher; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: Re: [PATCH 2/2] drm/amdgpu: enable IP discovery by default on navi
Hi Alex,
I see there are many 'auto' module params for amdgpu, could you please explain
about the historical intention of using value '-1'?
and shall we check 'amdgpu_discovery' against '-1' for all the code paths in
amdgpu_device.c and navi10_reg_init.c?
BR,
Xiaojie
From: amd-gfx on behalf of Alex Deucher
Sent: Wednesday, July 3, 2019 11:13 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH 2/2] drm/amdgpu: enable IP discovery by default on navi
Use the IP discovery table rather than hardcoding the
settings in the driver.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 7941a5368fb5..6f7772eeeb78 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -140,7 +140,7 @@ uint amdgpu_smu_memory_pool_size = 0;
uint amdgpu_dc_feature_mask = 0;
int amdgpu_async_gfx_ring = 1;
int amdgpu_mcbp = 0;
-int amdgpu_discovery = 0;
+int amdgpu_discovery = -1;
int amdgpu_mes = 0;
struct amdgpu_mgpu_info mgpu_info = {
@@ -592,6 +592,7 @@ module_param_named(mcbp, amdgpu_mcbp, int, 0444);
/**
* DOC: discovery (int)
* Allow driver to discover hardware IP information from IP Discovery table at
the top of VRAM.
+ * (-1 = auto (default), 0 = disabled, 1 = enabled)
*/
MODULE_PARM_DESC(discovery,
"Allow driver to discover hardware IPs from IP Discovery table at the
top of VRAM");
--
2.20.1
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