RE: [PATCH] drm/amdgpu: use u32 for buf size in __amdgpu_eeprom_xfer

[Zhang, Hawking]

[AMD Official Use Only - AMD Internal Distribution Only]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: amd-gfx  On Behalf Of Tao Zhou
Sent: Tuesday, May 21, 2024 11:17
To: amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao 
Subject: [PATCH] drm/amdgpu: use u32 for buf size in __amdgpu_eeprom_xfer

And also make sure the the value of msg[1].len should be in the range of u16.

Signed-off-by: Tao Zhou 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.c
index 09a34c7258e2..35fee3e8cde2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.c
@@ -90,7 +90,7 @@
 #define MAKE_I2C_ADDR(_aa) ((0xA << 3) | (((_aa) >> 16) & 0xF))

 static int __amdgpu_eeprom_xfer(struct i2c_adapter *i2c_adap, u32 eeprom_addr,
-   u8 *eeprom_buf, u16 buf_size, bool read)
+   u8 *eeprom_buf, u32 buf_size, bool read)
 {
u8 eeprom_offset_buf[EEPROM_OFFSET_SIZE];
struct i2c_msg msgs[] = {
@@ -133,15 +133,15 @@ static int __amdgpu_eeprom_xfer(struct i2c_adapter 
*i2c_adap, u32 eeprom_addr,
 * cycle begins. This is implied for the
 * "i2c_transfer()" abstraction.
 */
-   len = min(EEPROM_PAGE_SIZE - (eeprom_addr &
- EEPROM_PAGE_MASK),
- (u32)buf_size);
+   len = min(EEPROM_PAGE_SIZE - (eeprom_addr & 
EEPROM_PAGE_MASK),
+   buf_size);
} else {
/* Reading from the EEPROM has no limitation
 * on the number of bytes read from the EEPROM
 * device--they are simply sequenced out.
+* Keep in mind that i2c_msg.len is u16 type.
 */
-   len = buf_size;
+   len = min(U16_MAX, buf_size);
}
msgs[1].len = len;
msgs[1].buf = eeprom_buf;
--
2.34.1

RE: [PATCH] drm/amdgpu: Add CRC16 selection in config

[Zhang, Hawking]

[AMD Official Use Only - AMD Internal Distribution Only]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: Lazar, Lijo 
Sent: Tuesday, May 21, 2024 15:15
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Deucher, Alexander 
; Kuehling, Felix ; 
Kasiviswanathan, Harish ; kernel test robot 

Subject: [PATCH] drm/amdgpu: Add CRC16 selection in config

KFD uses crc16 for gpu_id generation.

Fixes: 6dbc6469ab0b ("drm/amdkfd: Ensure gpu_id is unique")
Reported-by: kernel test robot 
Closes: 
https://lore.kernel.org/oe-kbuild-all/202405211405.tidtwibx-...@intel.com/

Signed-off-by: Lijo Lazar 
---
 drivers/gpu/drm/amd/amdgpu/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/Kconfig 
b/drivers/gpu/drm/amd/amdgpu/Kconfig
index 0cd9d2939407..0051fb1b437f 100644
--- a/drivers/gpu/drm/amd/amdgpu/Kconfig
+++ b/drivers/gpu/drm/amd/amdgpu/Kconfig
@@ -17,6 +17,7 @@ config DRM_AMDGPU
select HWMON
select I2C
select I2C_ALGOBIT
+   select CRC16
select BACKLIGHT_CLASS_DEVICE
select INTERVAL_TREE
select DRM_BUDDY
--
2.25.1

RE: [PATCH] drm/amdgpu/mes12: mes hw_fini fix for mode1 reset

[Zhang, Hawking]

[AMD Official Use Only - AMD Internal Distribution Only]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: Xiao, Jack 
Sent: Tuesday, May 21, 2024 15:36
To: amd-gfx@lists.freedesktop.org; Deucher, Alexander 
; Zhang, Hawking ; Min, Frank 
; Gao, Likun ; Feng, Kenneth 

Cc: Xiao, Jack 
Subject: [PATCH] drm/amdgpu/mes12: mes hw_fini fix for mode1 reset

Port mes11 hw_fini to mes12, fix for mode1 reset.

Signed-off-by: Jack Xiao 
---
 drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c 
b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
index 45b70a4c4ada..f18fdda023c9 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
@@ -1380,11 +1380,12 @@ static int mes_v12_0_kiq_hw_init(struct amdgpu_device 
*adev)

 static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev)  {
-   if (!adev->enable_uni_mes && adev->mes.ring.sched.ready)
+   if (adev->mes.ring.sched.ready) {
mes_v12_0_kiq_dequeue_sched(adev);
+   adev->mes.ring.sched.ready = false;
+   }

-   if (!amdgpu_sriov_vf(adev))
-   mes_v12_0_enable(adev, false);
+   mes_v12_0_enable(adev, false);

return 0;
 }
--
2.41.0

RE: [PATCH] drm/amdgpu: update type of buf size to u32 for eeprom functions

[Zhang, Hawking]

[AMD Official Use Only - AMD Internal Distribution Only]


Hmm... but in __amdgpu_eeprom_xfer, the u32 will still be cut to u16.
__amdgpu_eeprom_xfer(struct i2c_adapter *i2c_adap, u32 eeprom_addr, u8 
*eeprom_buf, u16 buf_size, bool read)

Regards,
Hawking

-Original Message-
From: amd-gfx  On Behalf Of Tao Zhou
Sent: Monday, May 20, 2024 10:46
To: amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao 
Subject: [PATCH] drm/amdgpu: update type of buf size to u32 for eeprom functions

Avoid overflow issue.

Signed-off-by: Tao Zhou mailto:tao.zh...@amd.com>>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.c | 6 +++---  
drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.h | 4 ++--
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.c
index e71768661ca8..09a34c7258e2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.c
@@ -179,7 +179,7 @@ static int __amdgpu_eeprom_xfer(struct i2c_adapter 
*i2c_adap, u32 eeprom_addr,
  * Returns the number of bytes read/written; -errno on error.
  */
 static int amdgpu_eeprom_xfer(struct i2c_adapter *i2c_adap, u32 eeprom_addr,
- u8 *eeprom_buf, u16 buf_size, bool read)
+ u8 *eeprom_buf, u32 buf_size, bool read)
 {
const struct i2c_adapter_quirks *quirks = i2c_adap->quirks;
u16 limit;
@@ -225,7 +225,7 @@ static int amdgpu_eeprom_xfer(struct i2c_adapter *i2c_adap, 
u32 eeprom_addr,

 int amdgpu_eeprom_read(struct i2c_adapter *i2c_adap,
   u32 eeprom_addr, u8 *eeprom_buf,
-  u16 bytes)
+  u32 bytes)
 {
return amdgpu_eeprom_xfer(i2c_adap, eeprom_addr, eeprom_buf, bytes,
  true);
@@ -233,7 +233,7 @@ int amdgpu_eeprom_read(struct i2c_adapter *i2c_adap,

 int amdgpu_eeprom_write(struct i2c_adapter *i2c_adap,
u32 eeprom_addr, u8 *eeprom_buf,
-   u16 bytes)
+   u32 bytes)
 {
return amdgpu_eeprom_xfer(i2c_adap, eeprom_addr, eeprom_buf, bytes,
  false);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.h
index 6935adb2be1f..8083b8253ef4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.h
@@ -28,10 +28,10 @@

 int amdgpu_eeprom_read(struct i2c_adapter *i2c_adap,
   u32 eeprom_addr, u8 *eeprom_buf,
-  u16 bytes);
+  u32 bytes);

 int amdgpu_eeprom_write(struct i2c_adapter *i2c_adap,
u32 eeprom_addr, u8 *eeprom_buf,
-   u16 bytes);
+   u32 bytes);

 #endif
--
2.34.1

RE: [PATCH 2/2] drm/amdgpu: fix documentation errors in gmc v12.0

[Zhang, Hawking]

[AMD Official Use Only - AMD Internal Distribution Only]

Series is

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: amd-gfx  On Behalf Of Alex Deucher
Sent: Wednesday, May 15, 2024 00:44
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander 
Subject: [PATCH 2/2] drm/amdgpu: fix documentation errors in gmc v12.0

Fix up parameter descriptions.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
index 34e751b9b7003..c12c96f5bbaae 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
@@ -282,6 +282,8 @@ static void gmc_v12_0_flush_vm_hub(struct amdgpu_device 
*adev, uint32_t vmid,
  *
  * @adev: amdgpu_device pointer
  * @vmid: vm instance to flush
+ * @vmhub: which hub to flush
+ * @flush_type: the flush type
  *
  * Flush the TLB for the requested page table.
  */
@@ -321,6 +323,9 @@ static void gmc_v12_0_flush_gpu_tlb(struct amdgpu_device 
*adev, uint32_t vmid,
  *
  * @adev: amdgpu_device pointer
  * @pasid: pasid to be flush
+ * @flush_type: the flush type
+ * @all_hub: flush all hubs
+ * @inst: is used to select which instance of KIQ to use for the invalidation
  *
  * Flush the TLB for the requested pasid.
  */
--
2.45.0

RE: [PATCH] drm/amdgpu: fix compiler 'side-effect' check issue for RAS_EVENT_LOG()

[Zhang, Hawking]

[AMD Official Use Only - AMD Internal Distribution Only]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: Wang, Yang(Kevin) 
Sent: Tuesday, May 14, 2024 08:03
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Kamal, Asad 
Subject: [PATCH] drm/amdgpu: fix compiler 'side-effect' check issue for 
RAS_EVENT_LOG()

create a new helper function to avoid compiler 'side-effect'
check about RAS_EVENT_LOG() macro.

Signed-off-by: Yang Wang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 18 ++  
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 13 ++---
 2 files changed, 24 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 1dd13ed3b7b5..c04e6ced1af3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -4504,3 +4504,21 @@ int amdgpu_ras_reserve_page(struct amdgpu_device *adev, 
uint64_t pfn)

return ret;
 }
+
+void amdgpu_ras_event_log_print(struct amdgpu_device *adev, u64 event_id,
+   const char *fmt, ...)
+{
+   struct va_format vaf;
+   va_list args;
+
+   va_start(args, fmt);
+   vaf.fmt = fmt;
+   vaf.va = 
+
+   if (amdgpu_ras_event_id_is_valid(adev, event_id))
+   dev_printk(KERN_INFO, adev->dev, "{%llu}%pV", event_id, );
+   else
+   dev_printk(KERN_INFO, adev->dev, "%pV", );
+
+   va_end(args);
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
index c8980d5f6540..6a8c7b1609df 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
@@ -67,13 +67,8 @@ struct amdgpu_iv_entry;
 /* The high three bits indicates socketid */  #define 
AMDGPU_RAS_GET_FEATURES(val)  ((val) & ~AMDGPU_RAS_FEATURES_SOCKETID_MASK)

-#define RAS_EVENT_LOG(_adev, _id, _fmt, ...)   \
-do {   \
-   if (amdgpu_ras_event_id_is_valid((_adev), (_id)))   
\
-   dev_info((_adev)->dev, "{%llu}" _fmt, (_id), ##__VA_ARGS__);
\
-   else\
-   dev_info((_adev)->dev, _fmt, ##__VA_ARGS__);
\
-} while (0)
+#define RAS_EVENT_LOG(adev, id, fmt, ...)  \
+   amdgpu_ras_event_log_print((adev), (id), (fmt), ##__VA_ARGS__);

 enum amdgpu_ras_block {
AMDGPU_RAS_BLOCK__UMC = 0,
@@ -956,4 +951,8 @@ int amdgpu_ras_put_poison_req(struct amdgpu_device *adev,
enum amdgpu_ras_block block, uint16_t pasid,
pasid_notify pasid_fn, void *data, uint32_t reset);

+__printf(3, 4)
+void amdgpu_ras_event_log_print(struct amdgpu_device *adev, u64 event_id,
+   const char *fmt, ...);
+
 #endif
--
2.34.1

RE: [PATCH 1/8] drm/amdgpu: support imu for gc 12_0_0

[Zhang, Hawking]

[AMD Official Use Only - AMD Internal Distribution Only]

Series is

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: amd-gfx  On Behalf Of Gao, Likun
Sent: Tuesday, May 14, 2024 16:51
To: amd-gfx list 
Subject: [PATCH 1/8] drm/amdgpu: support imu for gc 12_0_0

[AMD Official Use Only - AMD Internal Distribution Only]

[AMD Official Use Only - AMD Internal Distribution Only]

From: Likun Gao 

Support IMU for ASIC with GC 12.0.0
Drop some unused function.

Signed-off-by: Likun Gao 
---
 drivers/gpu/drm/amd/amdgpu/imu_v12_0.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/imu_v12_0.c 
b/drivers/gpu/drm/amd/amdgpu/imu_v12_0.c
index 032ae12b2be2..0c8ef908d112 100644
--- a/drivers/gpu/drm/amd/amdgpu/imu_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/imu_v12_0.c
@@ -32,6 +32,7 @@
 #include "gc/gc_12_0_0_sh_mask.h"
 #include "mmhub/mmhub_4_1_0_offset.h"

+MODULE_FIRMWARE("amdgpu/gc_12_0_0_imu.bin");
 MODULE_FIRMWARE("amdgpu/gc_12_0_1_imu.bin");

 #define TRANSFER_RAM_MASK  0x001c
@@ -367,6 +368,7 @@ static void imu_v12_0_program_rlc_ram(struct amdgpu_device 
*adev)
WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_INDEX, 0x2);

switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
+   case IP_VERSION(12, 0, 0):
case IP_VERSION(12, 0, 1):
if (!r)
program_imu_rlc_ram(adev, data, (const u32)size);
--
2.34.1

RE: [PATCH 3/3] drm/amdgpu: Use NPS ranges from discovery table

[Zhang, Hawking]

[AMD Official Use Only - AMD Internal Distribution Only]

Series is

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: Lazar, Lijo 
Sent: Tuesday, May 14, 2024 16:36
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Deucher, Alexander 
; Koenig, Christian ; Ma, 
Le ; Ma, Le 
Subject: [PATCH 3/3] drm/amdgpu: Use NPS ranges from discovery table

Add GMC API to fetch NPS range information from discovery table. Use NPS range 
information in GMC 9.4.3 SOCs when available, otherwise fallback to software 
method.

Signed-off-by: Lijo Lazar 
Reviewed-by: Le Ma 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 92 +++  
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h |  5 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c   | 76 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h   | 11 +++
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 40 +---
 5 files changed, 212 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 43528ff50e72..afe8d12667f4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -367,6 +367,35 @@ static void amdgpu_discovery_harvest_config_quirk(struct 
amdgpu_device *adev)
}
 }

+static int amdgpu_discovery_verify_npsinfo(struct amdgpu_device *adev,
+  struct binary_header *bhdr)
+{
+   struct table_info *info;
+   uint16_t checksum;
+   uint16_t offset;
+
+   info = >table_list[NPS_INFO];
+   offset = le16_to_cpu(info->offset);
+   checksum = le16_to_cpu(info->checksum);
+
+   struct nps_info_header *nhdr =
+   (struct nps_info_header *)(adev->mman.discovery_bin + offset);
+
+   if (le32_to_cpu(nhdr->table_id) != NPS_INFO_TABLE_ID) {
+   dev_dbg(adev->dev, "invalid ip discovery nps info table id\n");
+   return -EINVAL;
+   }
+
+   if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
+ le32_to_cpu(nhdr->size_bytes),
+ checksum)) {
+   dev_dbg(adev->dev, "invalid nps info data table checksum\n");
+   return -EINVAL;
+   }
+
+   return 0;
+}
+
 static int amdgpu_discovery_init(struct amdgpu_device *adev)  {
struct table_info *info;
@@ -1681,6 +1710,69 @@ static int amdgpu_discovery_get_vcn_info(struct 
amdgpu_device *adev)
return 0;
 }

+union nps_info {
+   struct nps_info_v1_0 v1;
+};
+
+int amdgpu_discovery_get_nps_info(struct amdgpu_device *adev,
+ uint32_t *nps_type,
+ struct amdgpu_gmc_memrange **ranges,
+ int *range_cnt)
+{
+   struct amdgpu_gmc_memrange *mem_ranges;
+   struct binary_header *bhdr;
+   union nps_info *nps_info;
+   u16 offset;
+   int i;
+
+   if (!nps_type || !range_cnt || !ranges)
+   return -EINVAL;
+
+   if (!adev->mman.discovery_bin) {
+   dev_err(adev->dev,
+   "fetch mem range failed, ip discovery uninitialized\n");
+   return -EINVAL;
+   }
+
+   bhdr = (struct binary_header *)adev->mman.discovery_bin;
+   offset = le16_to_cpu(bhdr->table_list[NPS_INFO].offset);
+
+   if (!offset)
+   return -ENOENT;
+
+   /* If verification fails, return as if NPS table doesn't exist */
+   if (amdgpu_discovery_verify_npsinfo(adev, bhdr))
+   return -ENOENT;
+
+   nps_info = (union nps_info *)(adev->mman.discovery_bin + offset);
+
+   switch (le16_to_cpu(nps_info->v1.header.version_major)) {
+   case 1:
+   *nps_type = nps_info->v1.nps_type;
+   *range_cnt = nps_info->v1.count;
+   mem_ranges = kvzalloc(
+   *range_cnt * sizeof(struct amdgpu_gmc_memrange),
+   GFP_KERNEL);
+   for (i = 0; i < *range_cnt; i++) {
+   mem_ranges[i].base_address =
+   nps_info->v1.instance_info[i].base_address;
+   mem_ranges[i].limit_address =
+   nps_info->v1.instance_info[i].limit_address;
+   mem_ranges[i].nid_mask = -1;
+   mem_ranges[i].flags = 0;
+   }
+   *ranges = mem_ranges;
+   break;
+   default:
+   dev_err(adev->dev, "Unhandled NPS info table %d.%d\n",
+   le16_to_cpu(nps_info->v1.header.version_major),
+   le16_to_cpu(nps_info->v1.header.version_minor));
+   return -EINVAL;
+   }
+
+   return 0;
+}
+
 static int amdgpu_di

RE: [PATCH] drm/amdgpu: add debug flag to enable RAS ACA driver.

[Zhang, Hawking]

[AMD Official Use Only - AMD Internal Distribution Only]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: Wang, Yang(Kevin) 
Sent: Tuesday, May 14, 2024 16:15
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Zhou1, Tao 
Subject: [PATCH] drm/amdgpu: add debug flag to enable RAS ACA driver.

Use debug_mask=0x10 (BIT.4) param to help enable RAS ACA driver.
(RAS ACA is disabled by default.)

Signed-off-by: Yang Wang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c | 3 ++-  
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 6 ++
 3 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 846c3550fbda..550a42e3961f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1171,6 +1171,7 @@ struct amdgpu_device {
booldebug_largebar;
booldebug_disable_soft_recovery;
booldebug_use_vram_fw_buf;
+   booldebug_enable_ras_aca;
 };

 static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev, 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c
index 987a1b4d4503..0b1b9911bd99 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c
@@ -686,7 +686,8 @@ static void aca_manager_fini(struct aca_handle_manager *mgr)

 bool amdgpu_aca_is_enabled(struct amdgpu_device *adev)  {
-   return adev->aca.is_enabled;
+   return (adev->aca.is_enabled ||
+   adev->debug_enable_ras_aca);
 }

 int amdgpu_aca_init(struct amdgpu_device *adev) diff --git 
a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index caf89d21b61c..a2de55ab3a6a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -129,6 +129,7 @@ enum AMDGPU_DEBUG_MASK {
AMDGPU_DEBUG_LARGEBAR = BIT(1),
AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY = BIT(2),
AMDGPU_DEBUG_USE_VRAM_FW_BUF = BIT(3),
+   AMDGPU_DEBUG_ENABLE_RAS_ACA = BIT(4),
 };

 unsigned int amdgpu_vram_limit = UINT_MAX; @@ -2192,6 +2193,11 @@ static void 
amdgpu_init_debug_options(struct amdgpu_device *adev)
pr_info("debug: place fw in vram for frontdoor loading\n");
adev->debug_use_vram_fw_buf = true;
}
+
+   if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_RAS_ACA) {
+   pr_info("debug: enable RAS ACA driver\n");
+   adev->debug_enable_ras_aca = true;
+   }
 }

 static unsigned long amdgpu_fix_asic_type(struct pci_dev *pdev, unsigned long 
flags)
--
2.34.1

RE: [PATCH 2/2] drm/amd/pm: Use gpu_metrics_v1_6 for SMUv13.0.6

[Zhang, Hawking]

[AMD Official Use Only - AMD Internal Distribution Only]

Series is

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: Kamal, Asad 
Sent: Tuesday, May 14, 2024 14:23
To: amd-gfx@lists.freedesktop.org
Cc: Lazar, Lijo ; Zhang, Hawking ; 
Ma, Le ; Zhang, Morris ; Kamal, Asad 
; Cheung, Donald ; Khatir, Sepehr 
; Oliveira, Daniel ; Poag, 
Charis ; Liu, Shuzhou (Bill) 
Subject: [PATCH 2/2] drm/amd/pm: Use gpu_metrics_v1_6 for SMUv13.0.6

Use gpu_metrics_v1_6 for SMUv13.0.6 to fill gpu metric info

Signed-off-by: Asad Kamal 
Reviewed-by: Lijo Lazar 
---
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c   | 18 ++
 1 file changed, 14 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
index 46ab70a244af..70e5589f6229 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
@@ -350,7 +350,7 @@ static int smu_v13_0_6_tables_init(struct smu_context *smu)
return -ENOMEM;
smu_table->metrics_time = 0;

-   smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_5);
+   smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_6);
smu_table->gpu_metrics_table =
kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
if (!smu_table->gpu_metrics_table) {
@@ -2176,8 +2176,8 @@ static int smu_v13_0_6_get_current_pcie_link_speed(struct 
smu_context *smu)  static ssize_t smu_v13_0_6_get_gpu_metrics(struct 
smu_context *smu, void **table)  {
struct smu_table_context *smu_table = >smu_table;
-   struct gpu_metrics_v1_5 *gpu_metrics =
-   (struct gpu_metrics_v1_5 *)smu_table->gpu_metrics_table;
+   struct gpu_metrics_v1_6 *gpu_metrics =
+   (struct gpu_metrics_v1_6 *)smu_table->gpu_metrics_table;
struct amdgpu_device *adev = smu->adev;
int ret = 0, xcc_id, inst, i, j;
MetricsTableX_t *metrics_x;
@@ -2193,7 +2193,7 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct 
smu_context *smu, void **table

metrics_a = (MetricsTableA_t *)metrics_x;

-   smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 5);
+   smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 6);

gpu_metrics->temperature_hotspot =
SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketTemperature));
@@ -2235,6 +2235,16 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct 
smu_context *smu, void **table

gpu_metrics->current_uclk = 
SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequency));

+   /* Total accumulated cycle counter */
+   gpu_metrics->accumulation_counter =
+GET_METRIC_FIELD(AccumulationCounter);
+
+   /* Accumulated throttler residencies */
+   gpu_metrics->prochot_residency_acc = 
GET_METRIC_FIELD(ProchotResidencyAcc);
+   gpu_metrics->ppt_residency_acc = GET_METRIC_FIELD(PptResidencyAcc);
+   gpu_metrics->socket_thm_residency_acc = 
GET_METRIC_FIELD(SocketThmResidencyAcc);
+   gpu_metrics->vr_thm_residency_acc = GET_METRIC_FIELD(VrThmResidencyAcc);
+   gpu_metrics->hbm_thm_residency_acc =
+GET_METRIC_FIELD(HbmThmResidencyAcc);
+
/* Throttle status is not reported through metrics now */
gpu_metrics->throttle_status = 0;

--
2.42.0

RE: [PATCH] drm/amdgpu/mes: fix mes12 to map legacy queue

[Zhang, Hawking]

[AMD Official Use Only - General]

Let's use dev_err that is more helpful in multiple-GPU use scenario when there 
are errors. Other than that, the patch is

Reviewed-by: Hawking Zhang 

Regards,
Hawking

-Original Message-
From: Xiao, Jack 
Sent: Thursday, May 9, 2024 14:47
To: amd-gfx@lists.freedesktop.org; Deucher, Alexander 
; Zhang, Hawking ; Min, Frank 
; Gao, Likun 
Cc: Xiao, Jack 
Subject: [PATCH] drm/amdgpu/mes: fix mes12 to map legacy queue

Adjust mes12 initialization sequence to fix mapping legacy queue.

Signed-off-by: Jack Xiao 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 71 -  
drivers/gpu/drm/amd/amdgpu/mes_v12_0.c  | 10 ++--
 2 files changed, 53 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index ca90d6b577c8..a2696c215899 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -599,6 +599,44 @@ int amdgpu_queue_mask_bit_to_set_resource_bit(struct 
amdgpu_device *adev,
return set_resource_bit;
 }

+static int amdgpu_gfx_mes_enable_kcq(struct amdgpu_device *adev, int
+xcc_id) {
+   struct amdgpu_kiq *kiq = >gfx.kiq[xcc_id];
+   struct amdgpu_ring *kiq_ring = >ring;
+   uint64_t queue_mask = ~0ULL;
+   int r, i, j;
+
+   amdgpu_device_flush_hdp(adev, NULL);
+
+   if (!adev->enable_uni_mes) {
+   spin_lock(>ring_lock);
+   r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->set_resources_size);
+   if (r) {
+   DRM_ERROR("Failed to lock KIQ (%d).\n", r);
+   spin_unlock(>ring_lock);
+   return r;
+   }
+
+   kiq->pmf->kiq_set_resources(kiq_ring, queue_mask);
+   r = amdgpu_ring_test_helper(kiq_ring);
+   spin_unlock(>ring_lock);
+   if (r)
+   DRM_ERROR("KIQ failed to set resources\n");
+   }
+
+   for (i = 0; i < adev->gfx.num_compute_rings; i++) {
+   j = i + xcc_id * adev->gfx.num_compute_rings;
+   r = amdgpu_mes_map_legacy_queue(adev,
+   >gfx.compute_ring[j]);
+   if (r) {
+   DRM_ERROR("failed to map compute queue\n");
+   return r;
+   }
+   }
+
+   return 0;
+}
+
 int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev, int xcc_id)  {
struct amdgpu_kiq *kiq = >gfx.kiq[xcc_id]; @@ -606,6 +644,9 @@ 
int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev, int xcc_id)
uint64_t queue_mask = 0;
int r, i, j;

+   if (adev->enable_mes)
+   return amdgpu_gfx_mes_enable_kcq(adev, xcc_id);
+
if (!kiq->pmf || !kiq->pmf->kiq_map_queues || 
!kiq->pmf->kiq_set_resources)
return -EINVAL;

@@ -626,9 +667,6 @@ int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev, int 
xcc_id)

amdgpu_device_flush_hdp(adev, NULL);

-   if (adev->enable_mes)
-   queue_mask = ~0ULL;
-
DRM_INFO("kiq ring mec %d pipe %d q %d\n", kiq_ring->me, kiq_ring->pipe,
 kiq_ring->queue);

@@ -643,13 +681,10 @@ int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev, int 
xcc_id)
}

kiq->pmf->kiq_set_resources(kiq_ring, queue_mask);
-
-   if (!adev->enable_mes) {
-   for (i = 0; i < adev->gfx.num_compute_rings; i++) {
-   j = i + xcc_id * adev->gfx.num_compute_rings;
-   kiq->pmf->kiq_map_queues(kiq_ring,
->gfx.compute_ring[j]);
-   }
+   for (i = 0; i < adev->gfx.num_compute_rings; i++) {
+   j = i + xcc_id * adev->gfx.num_compute_rings;
+   kiq->pmf->kiq_map_queues(kiq_ring,
+>gfx.compute_ring[j]);
}

r = amdgpu_ring_test_helper(kiq_ring);
@@ -657,20 +692,6 @@ int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev, int 
xcc_id)
if (r)
DRM_ERROR("KCQ enable failed\n");

-   if (adev->enable_mes || adev->enable_uni_mes) {
-   for (i = 0; i < adev->gfx.num_compute_rings; i++) {
-   j = i + xcc_id * adev->gfx.num_compute_rings;
-   r = amdgpu_mes_map_legacy_queue(adev,
-  >gfx.compute_ring[j]);
-   if (r) {
-   DRM_ERROR("failed to map compute queue\n");
-   return r;
-   }
-   }
-
-   return 0;
-   }
-
return r;
 }

@@ -685,7 +706,7 @@ int amdgpu_gfx_enable_kgq(struct amdgpu_

RE: [PATCH] drm/amdgpu: fix RAS unload driver issue in SRIOV

[Zhang, Hawking]

[AMD Official Use Only - General]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: Wang, Yang(Kevin) 
Sent: Tuesday, May 7, 2024 10:50
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Zhou1, Tao ; Li, 
Candice 
Subject: [PATCH] drm/amdgpu: fix RAS unload driver issue in SRIOV

Fix null pointer issue when unload driver in SRIOV mode.

Adjust the function position to ensure that the amdgpu_mca/aca_xxx_init() 
related functions can be initialized properly.

Signed-off-by: Yang Wang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 14 --
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 36509fa9fecf..36deac3b1440 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -3611,10 +3611,6 @@ int amdgpu_ras_late_init(struct amdgpu_device *adev)
struct amdgpu_ras_block_object *obj;
int r;

-   /* Guest side doesn't need init ras feature */
-   if (amdgpu_sriov_vf(adev))
-   return 0;
-
amdgpu_ras_event_mgr_init(adev);

if (amdgpu_aca_is_enabled(adev)) {
@@ -3625,7 +3621,8 @@ int amdgpu_ras_late_init(struct amdgpu_device *adev)
if (r)
return r;

-   amdgpu_ras_set_aca_debug_mode(adev, false);
+   if (!amdgpu_sriov_vf(adev))
+   amdgpu_ras_set_aca_debug_mode(adev, false);
} else {
if (amdgpu_in_reset(adev))
r = amdgpu_mca_reset(adev);
@@ -3634,9 +3631,14 @@ int amdgpu_ras_late_init(struct amdgpu_device *adev)
if (r)
return r;

-   amdgpu_ras_set_mca_debug_mode(adev, false);
+   if (!amdgpu_sriov_vf(adev))
+   amdgpu_ras_set_mca_debug_mode(adev, false);
}

+   /* Guest side doesn't need init ras feature */
+   if (amdgpu_sriov_vf(adev))
+   return 0;
+
list_for_each_entry_safe(node, tmp, >ras_list, node) {
obj = node->ras_obj;
if (!obj) {
--
2.34.1

RE: [PATCH] drm/amd/amdxcp: Fix warnings

[Zhang, Hawking]

[AMD Official Use Only - General]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: Lazar, Lijo 
Sent: Monday, May 6, 2024 11:31
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Deucher, Alexander 
; kernel test robot 
Subject: [PATCH] drm/amd/amdxcp: Fix warnings

Range of possible values of pdev_num is 0-63. Use int8_t as data type.
That also fixes below warnings:

>> drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c:59:58: warning: '%d'
>> directive output may be truncated writing between 1 and 11 bytes into
>> a region of size 9 [-Wformat-truncation=]
  59 | snprintf(dev_name, sizeof(dev_name), "amdgpu_xcp_%d", 
pdev_num);
 |  ^~
   drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c:59:46: note: directive argument 
in the range [-2147483648, 63]
  59 | snprintf(dev_name, sizeof(dev_name), "amdgpu_xcp_%d", 
pdev_num);
 |  ^~~
   drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c:59:9: note: 'snprintf' output 
between 13 and 23 bytes into a destination of size 20
  59 | snprintf(dev_name, sizeof(dev_name), "amdgpu_xcp_%d", 
pdev_num);
 | 
^~~

Fixes: f3b4c9a2746c ("drm/amd/amdxcp: Use unique name for partition dev")
Signed-off-by: Lijo Lazar 
Reported-by: kernel test robot 
---
 drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c 
b/drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c
index b4131053b31b..faed84172dd4 100644
--- a/drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c
+++ b/drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c
@@ -43,7 +43,7 @@ static const struct drm_driver amdgpu_xcp_driver = {
.minor = 0,
 };

-static int pdev_num;
+static int8_t pdev_num;
 static struct xcp_device *xcp_dev[MAX_XCP_PLATFORM_DEVICE];

 int amdgpu_xcp_drm_dev_alloc(struct drm_device **ddev)
--
2.25.1

RE: [PATCH] drm/amdgpu: update vf to pf message retry from 2 to 5

[Zhang, Hawking]

[AMD Official Use Only - General]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: Luo, Zhigang 
Sent: Tuesday, April 30, 2024 22:23
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Saye, Sashank 
; Chan, Hing Pong ; Lazar, Lijo 
; Luo, Zhigang 
Subject: [PATCH] drm/amdgpu: update vf to pf message retry from 2 to 5

increase retry times to wait host has enough time to complete reset.

Signed-off-by: Zhigang Luo 
---
 drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c 
b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c
index 89992c1c9a62..8b0ab075b728 100644
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c
@@ -181,7 +181,7 @@ static int xgpu_nv_send_access_requests_with_param(struct 
amdgpu_device *adev,
if (event != -1) {
r = xgpu_nv_poll_msg(adev, event);
if (r) {
-   if (retry++ < 2)
+   if (retry++ < 5)
goto send_request;

if (req != IDH_REQ_GPU_INIT_DATA) {
--
2.25.1

RE: [PATCH] drm/amdgpu: avoid reading vf2pf info size from FB

[Zhang, Hawking]

[AMD Official Use Only - General]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: Luo, Zhigang 
Sent: Tuesday, April 30, 2024 22:24
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Saye, Sashank 
; Chan, Hing Pong ; Lazar, Lijo 
; Luo, Zhigang 
Subject: [PATCH] drm/amdgpu: avoid reading vf2pf info size from FB

VF can't access FB when host is doing mode1 reset. Using sizeof to get vf2pf 
info size, instead of reading it from vf2pf header stored in FB.

Signed-off-by: Zhigang Luo 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index 54ab51a4ada7..c84d2217005e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -583,7 +583,7 @@ static int amdgpu_virt_write_vf2pf_data(struct 
amdgpu_device *adev)
}
vf2pf_info->checksum =
amd_sriov_msg_checksum(
-   vf2pf_info, vf2pf_info->header.size, 0, 0);
+   vf2pf_info, sizeof(struct amd_sriov_msg_vf2pf_info), 0, 0);

return 0;
 }
--
2.25.1

RE: [PATCH 2/2] drm/amdgpu: Remove redundant function call

[Zhang, Hawking]

[AMD Official Use Only - General]

Series is

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: Chai, Thomas 
Sent: Sunday, April 28, 2024 11:33
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Zhou1, Tao ; Li, 
Candice ; Wang, Yang(Kevin) ; Yang, 
Stanley ; Chai, Thomas 
Subject: [PATCH 2/2] drm/amdgpu: Remove redundant function call

Remove redundant function call.

Signed-off-by: YiPeng Chai 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 22 ++
 1 file changed, 6 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 11a70991152c..7f5342539c17 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -2794,8 +2794,8 @@ static void amdgpu_ras_do_page_retirement(struct 
work_struct *work)
mutex_unlock(>umc_ecc_log.lock);
 }

-static int amdgpu_ras_query_ecc_status(struct amdgpu_device *adev,
-   enum amdgpu_ras_block ras_block, uint32_t timeout_ms)
+static void amdgpu_ras_poison_creation_handler(struct amdgpu_device *adev,
+   uint32_t timeout_ms)
 {
int ret = 0;
struct ras_ecc_log_info *ecc_log;
@@ -2804,7 +2804,7 @@ static int amdgpu_ras_query_ecc_status(struct 
amdgpu_device *adev,
struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);

memset(, 0, sizeof(info));
-   info.head.block = ras_block;
+   info.head.block = AMDGPU_RAS_BLOCK__UMC;

ecc_log = >umc_ecc_log;
ecc_log->de_updated = false;
@@ -2812,7 +2812,7 @@ static int amdgpu_ras_query_ecc_status(struct 
amdgpu_device *adev,
ret = amdgpu_ras_query_error_status(adev, );
if (ret) {
dev_err(adev->dev, "Failed to query ras error! 
ret:%d\n", ret);
-   return ret;
+   return;
}

if (timeout && !ecc_log->de_updated) { @@ -2823,21 +2823,11 @@ 
static int amdgpu_ras_query_ecc_status(struct amdgpu_device *adev,

if (timeout_ms && !timeout) {
dev_warn(adev->dev, "Can't find deferred error\n");
-   return -ETIMEDOUT;
+   return;
}

-   return 0;
-}
-
-static void amdgpu_ras_poison_creation_handler(struct amdgpu_device *adev,
-   uint32_t timeout)
-{
-   struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
-   int ret;
-
-   ret = amdgpu_ras_query_ecc_status(adev, AMDGPU_RAS_BLOCK__UMC, timeout);
if (!ret)
-   schedule_delayed_work(>page_retirement_dwork, 0);
+   schedule_delayed_work(>page_retirement_dwork, 0);
 }

 static int amdgpu_ras_poison_consumption_handler(struct amdgpu_device *adev,
--
2.34.1

RE: [PATCH Review 1/1] drm/amdgpu: Adjust XGMI WAFL ras enable bit

[Zhang, Hawking]

[AMD Official Use Only - General]

Hmm... we do expect PSP report the XGMI/WAFL Caps. This is different from 
legacy RAS CAP check through atomfirmware. But if you found the XGMI/WAFL bits 
are not set properly in the new PSP interface, let's reach out to PSP firmware 
team for a fix.

Regards,
Hawking

-Original Message-
From: amd-gfx  On Behalf Of Stanley.Yang
Sent: Thursday, April 25, 2024 15:08
To: amd-gfx@lists.freedesktop.org
Cc: Yang, Stanley 
Subject: [PATCH Review 1/1] drm/amdgpu: Adjust XGMI WAFL ras enable bit

The way to get ras capability has changed for some asics, both of them need 
check XGMI physical nodes number to set XGMI WAFL ras enable bit.

Signed-off-by: Stanley.Yang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index b2a883d3e19d..ea77e00cc002 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -2918,13 +2918,6 @@ static void 
amdgpu_ras_query_ras_capablity_from_vbios(struct amdgpu_device *adev
else
adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__VCN |
  1 << AMDGPU_RAS_BLOCK__JPEG);
-
-   /*
-* XGMI RAS is not supported if xgmi num physical nodes
-* is zero
-*/
-   if (!adev->gmc.xgmi.num_physical_nodes)
-   adev->ras_hw_enabled &= ~(1 << 
AMDGPU_RAS_BLOCK__XGMI_WAFL);
} else {
dev_info(adev->dev, "SRAM ECC is not presented.\n");
}
@@ -3002,6 +2995,13 @@ static void amdgpu_ras_check_supported(struct 
amdgpu_device *adev)
amdgpu_ras_query_poison_mode(adev);

 init_ras_enabled_flag:
+   /*
+* XGMI RAS is not supported if xgmi num physical nodes
+* is zero
+*/
+   if (!adev->gmc.xgmi.num_physical_nodes)
+   adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__XGMI_WAFL);
+
/* hw_supported needs to be aligned with RAS block mask. */
adev->ras_hw_enabled &= AMDGPU_RAS_BLOCK_MASK;

--
2.25.1

RE: [PATCH 06/15] drm/amdgpu: umc v12_0 converts error address

[Zhang, Hawking]

[AMD Official Use Only - General]

I might lose some context here. Can you please elaborate why we don't leverage 
the existing umc_v12_0_convert_error_address implementation?

Regards,
Hawking

-Original Message-
From: Chai, Thomas 
Sent: Thursday, April 18, 2024 10:58
To: amd-gfx@lists.freedesktop.org
Cc: Chai, Thomas ; Zhang, Hawking ; 
Zhou1, Tao ; Li, Candice ; Wang, 
Yang(Kevin) ; Yang, Stanley ; 
Chai, Thomas 
Subject: [PATCH 06/15] drm/amdgpu: umc v12_0 converts error address

Umc v12_0 converts error address.

Signed-off-by: YiPeng Chai 
---
 drivers/gpu/drm/amd/amdgpu/umc_v12_0.c | 94 +-  
drivers/gpu/drm/amd/amdgpu/umc_v12_0.h | 12 
 2 files changed, 105 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c 
b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
index 81435533c4a7..085dcfe16b5e 100644
--- a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
@@ -222,6 +222,66 @@ static void umc_v12_0_convert_error_address(struct 
amdgpu_device *adev,
}
 }

+static int umc_v12_0_convert_err_addr(struct amdgpu_device *adev,
+   struct ta_ras_query_address_input *addr_in,
+   uint64_t *pfns, int len)
+{
+   uint32_t col, row, row_xor, bank, channel_index;
+   uint64_t soc_pa, retired_page, column, err_addr;
+   struct ta_ras_query_address_output addr_out;
+   uint32_t pos = 0;
+
+   err_addr = addr_in->ma.err_addr;
+   addr_in->addr_type = TA_RAS_MCA_TO_PA;
+   if (psp_ras_query_address(>psp, addr_in, _out)) {
+   dev_warn(adev->dev, "Failed to query RAS physical address for 
0x%llx",
+   err_addr);
+   return 0;
+   }
+
+   soc_pa = addr_out.pa.pa;
+   bank = addr_out.pa.bank;
+   channel_index = addr_out.pa.channel_idx;
+
+   col = (err_addr >> 1) & 0x1fULL;
+   row = (err_addr >> 10) & 0x3fffULL;
+   row_xor = row ^ (0x1ULL << 13);
+   /* clear [C3 C2] in soc physical address */
+   soc_pa &= ~(0x3ULL << UMC_V12_0_PA_C2_BIT);
+   /* clear [C4] in soc physical address */
+   soc_pa &= ~(0x1ULL << UMC_V12_0_PA_C4_BIT);
+
+   /* loop for all possibilities of [C4 C3 C2] */
+   for (column = 0; column < UMC_V12_0_NA_MAP_PA_NUM; column++) {
+   retired_page = soc_pa | ((column & 0x3) << UMC_V12_0_PA_C2_BIT);
+   retired_page |= (((column & 0x4) >> 2) << UMC_V12_0_PA_C4_BIT);
+
+   if (pos >= len)
+   return 0;
+   pfns[pos++] = retired_page >> AMDGPU_GPU_PAGE_SHIFT;
+
+   /* include column bit 0 and 1 */
+   col &= 0x3;
+   col |= (column << 2);
+   dev_info(adev->dev,
+   "Error Address(PA):0x%-10llx Row:0x%-4x Col:0x%-2x 
Bank:0x%x Channel:0x%x\n",
+   retired_page, row, col, bank, channel_index);
+
+   /* shift R13 bit */
+   retired_page ^= (0x1ULL << UMC_V12_0_PA_R13_BIT);
+
+   if (pos >= len)
+   return 0;
+   pfns[pos++] = retired_page >> AMDGPU_GPU_PAGE_SHIFT;
+
+   dev_info(adev->dev,
+   "Error Address(PA):0x%-10llx Row:0x%-4x Col:0x%-2x 
Bank:0x%x Channel:0x%x\n",
+   retired_page, row_xor, col, bank, channel_index);
+   }
+
+   return pos;
+}
+
 static int umc_v12_0_query_error_address(struct amdgpu_device *adev,
uint32_t node_inst, uint32_t umc_inst,
uint32_t ch_inst, void *data)
@@ -482,8 +542,12 @@ static int umc_v12_0_ras_late_init(struct amdgpu_device 
*adev, struct ras_common  static int umc_v12_0_update_ecc_status(struct 
amdgpu_device *adev,
uint64_t status, uint64_t ipid, uint64_t addr)  {
-   uint16_t hwid, mcatype;
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
+   uint16_t hwid, mcatype;
+   struct ta_ras_query_address_input addr_in;
+   uint64_t page_pfn[UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL];
+   uint64_t err_addr;
+   int count;

hwid = REG_GET_FIELD(ipid, MCMP1_IPIDT0, HardwareID);
mcatype = REG_GET_FIELD(ipid, MCMP1_IPIDT0, McaType); @@ -497,6 +561,34 
@@ static int umc_v12_0_update_ecc_status(struct amdgpu_device *adev,
if (!umc_v12_0_is_deferred_error(adev, status))
return 0;

+   err_addr = REG_GET_FIELD(addr,
+   MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);
+
+   dev_info(adev->dev,
+   "UMC:IPID:0x%llx, socket:%llu, aid:%llu, inst:%llu, ch:%llu, 
err_addr:0x%llx\n",
+   ipid,
+   MCA_IPID_2_SOCKET_ID(ipid)

RE: [PATCH 11/15] drm/amdgpu: prepare to handle pasid poison consumption

[Zhang, Hawking]

[AMD Official Use Only - General]

+void amdgpu_amdkfd_ras_pasid_poison_consumption_handler(struct amdgpu_device 
*adev,
+   enum amdgpu_ras_block block, uint16_t pasid,
+   pasid_notify pasid_fn, void *data, uint32_t reset);

So we ultimately switch to above poison consumption handler for all the 
existing v9 adapters, right? If so, we shall be able to make this function 
backwards compatible. I'm wondering if we can just change the existing 
amdgpu_amdkfd_ras_poison_consumption_handler.

Pasid_poison_consumption_handler is a little bit confusing.

Regards,
Hawking

-Original Message-
From: Chai, Thomas 
Sent: Thursday, April 18, 2024 10:59
To: amd-gfx@lists.freedesktop.org
Cc: Chai, Thomas ; Zhang, Hawking ; 
Zhou1, Tao ; Li, Candice ; Wang, 
Yang(Kevin) ; Yang, Stanley ; 
Chai, Thomas 
Subject: [PATCH 11/15] drm/amdgpu: prepare to handle pasid poison consumption

Prepare to handle pasid poison consumption.

Signed-off-by: YiPeng Chai 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c|  9 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h|  5 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c   | 20 ---
 drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h   |  3 +++
 .../gpu/drm/amd/amdkfd/kfd_int_process_v9.c   |  3 ++-
 5 files changed, 31 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index 66753940bb4d..287ce431901c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -759,10 +759,17 @@ bool amdgpu_amdkfd_is_fed(struct amdgpu_device *adev)
return amdgpu_ras_get_fed_status(adev);  }

+void amdgpu_amdkfd_ras_pasid_poison_consumption_handler(struct amdgpu_device 
*adev,
+   enum amdgpu_ras_block block, uint16_t pasid,
+   pasid_notify pasid_fn, void *data, uint32_t 
reset) {
+   amdgpu_umc_pasid_poison_handler(adev, block, pasid, pasid_fn, data,
+reset); }
+
 void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev,
enum amdgpu_ras_block block, uint32_t reset)  {
-   amdgpu_umc_poison_handler(adev, block, reset);
+   amdgpu_umc_pasid_poison_handler(adev, block, 0, NULL, NULL, reset);
 }

 int amdgpu_amdkfd_send_close_event_drain_irq(struct amdgpu_device *adev, diff 
--git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index ad50c7bbc326..54e15994d02b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -401,6 +401,11 @@ int amdgpu_amdkfd_get_tile_config(struct amdgpu_device 
*adev,
struct tile_config *config);
 void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev,
enum amdgpu_ras_block block, uint32_t reset);
+
+void amdgpu_amdkfd_ras_pasid_poison_consumption_handler(struct amdgpu_device 
*adev,
+   enum amdgpu_ras_block block, uint16_t pasid,
+   pasid_notify pasid_fn, void *data, uint32_t reset);
+
 bool amdgpu_amdkfd_is_fed(struct amdgpu_device *adev);  bool 
amdgpu_amdkfd_bo_mapped_to_dev(struct amdgpu_device *adev, struct kgd_mem 
*mem);  void amdgpu_amdkfd_block_mmu_notifications(void *p); diff --git 
a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
index dcda3d24bee3..8ebbca9e2e22 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
@@ -252,8 +252,9 @@ int amdgpu_umc_bad_page_polling_timeout(struct 
amdgpu_device *adev,
return 0;
 }

-int amdgpu_umc_poison_handler(struct amdgpu_device *adev,
-   enum amdgpu_ras_block block, uint32_t reset)
+int amdgpu_umc_pasid_poison_handler(struct amdgpu_device *adev,
+   enum amdgpu_ras_block block, uint16_t pasid,
+   pasid_notify pasid_fn, void *data, uint32_t reset)
 {
int ret = AMDGPU_RAS_SUCCESS;

@@ -291,16 +292,14 @@ int amdgpu_umc_poison_handler(struct amdgpu_device *adev,

amdgpu_ras_error_data_fini(_data);
} else {
-   if (reset) {
-   amdgpu_umc_bad_page_polling_timeout(adev,
-   reset, 
MAX_UMC_POISON_POLLING_TIME_SYNC);
-   } else {
struct amdgpu_ras *con = 
amdgpu_ras_get_context(adev);

+   amdgpu_ras_put_poison_req(adev,
+   block, pasid, pasid_fn, data, reset);
+
atomic_inc(>page_retirement_req_cnt);

wake_up(>page_retirement_wq);
-   }
}
} else {
if (adev->virt.ops &&am

RE: [PATCH V2] drm/amdgpu: Fix ras mode2 reset failure in ras aca mode

[Zhang, Hawking]

[AMD Official Use Only - General]

The patch is Reviewed-by: Hawking Zhang 

Kevin, Thomas,

Alternatively, we need to explore the opportunity to centralize legacy ras and 
aca ras implementation in the same API. Take sysfs create/remove interface for 
example, legacy RAS and ACA RAS do share the same logic, just have different 
filesystem node.

For now, ACA RAS is trending to back to IP specific ras late init. Let's 
revisit the code to see if we can re-use the common ras_late_init or create 
aca_ras_late_init api.

Regards,
Hawking

-Original Message-
From: Chai, Thomas 
Sent: Wednesday, April 24, 2024 13:52
To: amd-gfx@lists.freedesktop.org
Cc: Chai, Thomas ; Zhang, Hawking ; 
Zhou1, Tao ; Li, Candice ; Wang, 
Yang(Kevin) ; Yang, Stanley ; 
Chai, Thomas 
Subject: [PATCH V2] drm/amdgpu: Fix ras mode2 reset failure in ras aca mode

Fix ras mode2 reset failure in ras aca mode.

Signed-off-by: YiPeng Chai 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index edb3cd0cef96..11a70991152c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -1254,6 +1254,10 @@ int amdgpu_ras_bind_aca(struct amdgpu_device *adev, enum 
amdgpu_ras_block blk,  {
struct ras_manager *obj;

+   /* in resume phase, no need to create aca fs node */
+   if (adev->in_suspend || amdgpu_in_reset(adev))
+   return 0;
+
obj = get_ras_manager(adev, blk);
if (!obj)
return -EINVAL;
--
2.34.1

RE: [PATCH 04/15] drm/amdgpu: add poison creation handler

[Zhang, Hawking]

[AMD Official Use Only - General]

Is it okay to drop below static function and just implement the logic in poison 
creation handler leveraging the ras query api: amdgpu_ras_query_error_status.

It seems to me the static function may not be able to be used for other IP 
blocks.

Regards,
Hawking

+ static int amdgpu_ras_query_ecc_status(struct amdgpu_device *adev,
+   enum amdgpu_ras_block ras_block, uint32_t timeout_ms) {
+   int ret = 0;
+   struct ras_ecc_log_info *ecc_log;
+   struct ras_query_if info;
+   uint32_t timeout = timeout_ms;
+   struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
+
+   memset(, 0, sizeof(info));
+   info.head.block = ras_block;
+
+   ecc_log = >umc_ecc_log;
+   ecc_log->de_updated = false;
+   do {
+   ret = amdgpu_ras_query_error_status(adev, );
+   if (ret) {
+   dev_err(adev->dev, "Failed to query ras error! 
ret:%d\n", ret);
+   return ret;
+   }
+
+   if (timeout && !ecc_log->de_updated) {
+   msleep(1);
+   timeout--;
+   }
+   } while (timeout && !ecc_log->de_updated);
+
+   if (timeout_ms && !timeout) {
+   dev_warn(adev->dev, "Can't find deferred error\n");
+   return -ETIMEDOUT;
+   }
+
+   return 0;
+}
+
+static void amdgpu_ras_poison_creation_handler(struct amdgpu_device *adev,
+   uint32_t timeout)
+{
+   amdgpu_ras_query_ecc_status(adev, AMDGPU_RAS_BLOCK__UMC, timeout); }
+

-Original Message-
From: amd-gfx  On Behalf Of YiPeng Chai
Sent: Thursday, April 18, 2024 10:58
To: amd-gfx@lists.freedesktop.org
Cc: Chai, Thomas ; Zhang, Hawking ; 
Zhou1, Tao ; Li, Candice ; Wang, 
Yang(Kevin) ; Yang, Stanley ; 
Chai, Thomas 
Subject: [PATCH 04/15] drm/amdgpu: add poison creation handler

Add poison creation handler.

Signed-off-by: YiPeng Chai 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 74 +++--
 1 file changed, 69 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 64e6e20c6de7..126616eaeec1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -2080,6 +2080,17 @@ static void 
amdgpu_ras_interrupt_poison_creation_handler(struct ras_manager *obj  {
dev_info(obj->adev->dev,
"Poison is created\n");
+
+   if (amdgpu_ip_version(obj->adev, UMC_HWIP, 0) >= IP_VERSION(12, 0, 0)) {
+   struct amdgpu_ras *con = amdgpu_ras_get_context(obj->adev);
+
+   amdgpu_ras_put_poison_req(obj->adev,
+   AMDGPU_RAS_BLOCK__UMC, 0, NULL, NULL, false);
+
+   atomic_inc(>page_retirement_req_cnt);
+
+   wake_up(>page_retirement_wq);
+   }
 }

 static void amdgpu_ras_interrupt_umc_handler(struct ras_manager *obj, @@ 
-2754,10 +2765,54 @@ static void amdgpu_ras_ecc_log_fini(struct 
ras_ecc_log_info *ecc_log)
mutex_destroy(_log->lock);
ecc_log->de_updated = false;
 }
+
+static int amdgpu_ras_query_ecc_status(struct amdgpu_device *adev,
+   enum amdgpu_ras_block ras_block, uint32_t timeout_ms) {
+   int ret = 0;
+   struct ras_ecc_log_info *ecc_log;
+   struct ras_query_if info;
+   uint32_t timeout = timeout_ms;
+   struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
+
+   memset(, 0, sizeof(info));
+   info.head.block = ras_block;
+
+   ecc_log = >umc_ecc_log;
+   ecc_log->de_updated = false;
+   do {
+   ret = amdgpu_ras_query_error_status(adev, );
+   if (ret) {
+   dev_err(adev->dev, "Failed to query ras error! 
ret:%d\n", ret);
+   return ret;
+   }
+
+   if (timeout && !ecc_log->de_updated) {
+   msleep(1);
+   timeout--;
+   }
+   } while (timeout && !ecc_log->de_updated);
+
+   if (timeout_ms && !timeout) {
+   dev_warn(adev->dev, "Can't find deferred error\n");
+   return -ETIMEDOUT;
+   }
+
+   return 0;
+}
+
+static void amdgpu_ras_poison_creation_handler(struct amdgpu_device *adev,
+   uint32_t timeout)
+{
+   amdgpu_ras_query_ecc_status(adev, AMDGPU_RAS_BLOCK__UMC, timeout); }
+
 static int amdgpu_ras_page_retirement_thread(void *param)  {
struct amdgpu_device *adev = (struct amdgpu_device *)param;
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
+   struct ras_poison_msg poison_msg;
+   enum amdgpu_ras_block ras_block;

while (!kthread_should_st

RE: [PATCH] drm/amdgpu: Fix ras mode2 reset failure in ras aca mode

[Zhang, Hawking]

[AMD Official Use Only - General]

Shall we move the check to the aca helper function?

Regards,
Hawking

-Original Message-
From: Chai, Thomas 
Sent: Tuesday, April 23, 2024 11:14
To: amd-gfx@lists.freedesktop.org
Cc: Chai, Thomas ; Zhang, Hawking ; 
Zhou1, Tao ; Li, Candice ; Wang, 
Yang(Kevin) ; Yang, Stanley ; 
Chai, Thomas 
Subject: [PATCH] drm/amdgpu: Fix ras mode2 reset failure in ras aca mode

Fix ras mode2 reset failure in ras aca mode for sdma v4_4_2 and gfx v9_4_3.

Signed-off-by: YiPeng Chai 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c  | 4   
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 4 
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index 0e429b7ed036..c8bc34aafdd7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -4324,6 +4324,10 @@ static int gfx_v9_4_3_ras_late_init(struct amdgpu_device 
*adev, struct ras_commo
if (r)
return r;

+   /* in resume phase, no need to create aca fs node */
+   if (adev->in_suspend || amdgpu_in_reset(adev))
+   return 0;
+
r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__GFX,
_v9_4_3_aca_info,
NULL);
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
index 7ea209b68154..77ae943745fb 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
@@ -2249,6 +2249,10 @@ static int sdma_v4_4_2_ras_late_init(struct 
amdgpu_device *adev, struct ras_comm
if (r)
return r;

+   /* in resume phase, no need to create aca fs node */
+   if (adev->in_suspend || amdgpu_in_reset(adev))
+   return 0;
+
return amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__SDMA,
   _v4_4_2_aca_info, NULL);
 }
--
2.34.1

RE: [PATCH] drm/amdgpu: remove virt_init_data_exchange from poison consumption handler

[Zhang, Hawking]

[AMD Official Use Only - General]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: Luo, Zhigang 
Sent: Wednesday, April 17, 2024 15:54
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Saye, Sashank 
; Chan, Hing Pong ; Luo, Zhigang 

Subject: [PATCH] drm/amdgpu: remove virt_init_data_exchange from poison 
consumption handler

Host will initiate an FLR for all poison consumption.
Guest should wait for FLR message to re-init data exchange.

Signed-off-by: Zhigang Luo 
---
 drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c 
b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c
index 89992c1c9a62..aba00d961627 100644
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c
@@ -446,8 +446,6 @@ static void xgpu_nv_ras_poison_handler(struct amdgpu_device 
*adev,
amdgpu_virt_fini_data_exchange(adev);
xgpu_nv_send_access_requests_with_param(adev,
IDH_RAS_POISON, block, 0, 0);
-   if (block != AMDGPU_RAS_BLOCK__SDMA)
-   amdgpu_virt_init_data_exchange(adev);
}
 }

--
2.25.1

RE: [PATCH] drm/amdgpu: Use driver mode reset for data poison

[Zhang, Hawking]

[Public]

Yes, the same strategy

-Original Message-
From: Lazar, Lijo 
Sent: Tuesday, April 16, 2024 02:24
To: Zhang, Hawking ; amd-gfx@lists.freedesktop.org; 
Zhou1, Tao 
Cc: Zhang, Hawking 
Subject: RE: [PATCH] drm/amdgpu: Use driver mode reset for data poison

[Public]

Is this applicable for aldebaran also?

Thanks,
Lijo
-Original Message-
From: amd-gfx  On Behalf Of Hawking Zhang
Sent: Tuesday, April 16, 2024 11:46 AM
To: amd-gfx@lists.freedesktop.org; Zhou1, Tao 
Cc: Zhang, Hawking 
Subject: [PATCH] drm/amdgpu: Use driver mode reset for data poison

mode-2 reset is the only reliable method that can get GC/SDMA back when poison 
is consumed. mmhub requires
mode-1 reset.

Signed-off-by: Hawking Zhang 
---
 .../gpu/drm/amd/amdkfd/kfd_int_process_v9.c   | 27 ++-
 1 file changed, 8 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c
index c368c70df3f4a..c3beb872adf8d 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c
@@ -144,7 +144,7 @@ static void event_interrupt_poison_consumption_v9(struct 
kfd_node *dev,
uint16_t pasid, uint16_t client_id)  {
enum amdgpu_ras_block block = 0;
-   int old_poison, ret = -EINVAL;
+   int old_poison;
uint32_t reset = 0;
struct kfd_process *p = kfd_lookup_process_by_pasid(pasid);

@@ -163,17 +163,13 @@ static void event_interrupt_poison_consumption_v9(struct 
kfd_node *dev,
case SOC15_IH_CLIENTID_SE2SH:
case SOC15_IH_CLIENTID_SE3SH:
case SOC15_IH_CLIENTID_UTCL2:
-   ret = kfd_dqm_evict_pasid(dev->dqm, pasid);
block = AMDGPU_RAS_BLOCK__GFX;
-   if (ret)
-   reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET;
+   reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET;
break;
case SOC15_IH_CLIENTID_VMC:
case SOC15_IH_CLIENTID_VMC1:
-   ret = kfd_dqm_evict_pasid(dev->dqm, pasid);
block = AMDGPU_RAS_BLOCK__MMHUB;
-   if (ret)
-   reset = AMDGPU_RAS_GPU_RESET_MODE1_RESET;
+   reset = AMDGPU_RAS_GPU_RESET_MODE1_RESET;
break;
case SOC15_IH_CLIENTID_SDMA0:
case SOC15_IH_CLIENTID_SDMA1:
@@ -184,22 +180,15 @@ static void event_interrupt_poison_consumption_v9(struct 
kfd_node *dev,
reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET;
break;
default:
-   break;
+   dev_warn(dev->adev->dev,
+"client %d does not support poison consumption\n", 
client_id);
+   return;
}

kfd_signal_poison_consumed_event(dev, pasid);

-   /* resetting queue passes, do page retirement without gpu reset
-* resetting queue fails, fallback to gpu reset solution
-*/
-   if (!ret)
-   dev_warn(dev->adev->dev,
-   "RAS poison consumption, unmap queue flow succeeded: 
client id %d\n",
-   client_id);
-   else
-   dev_warn(dev->adev->dev,
-   "RAS poison consumption, fall back to gpu reset flow: 
client id %d\n",
-   client_id);
+   dev_warn(dev->adev->dev,
+"poison is consumed by client %d, kick off gpu reset
+flow\n", client_id);

amdgpu_amdkfd_ras_poison_consumption_handler(dev->adev, block, reset);  
}
--
2.17.1

RE: [PATCH] drm/amdgpu: Use driver mode reset for data poison handling

[Zhang, Hawking]

[AMD Official Use Only - General]

Please ignore this one, will send out a new one

-Original Message-
From: Zhou1, Tao 
Sent: Tuesday, April 16, 2024 01:08
To: Zhang, Hawking ; amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking 
Subject: RE: [PATCH] drm/amdgpu: Use driver mode reset for data poison handling

[AMD Official Use Only - General]

Reviewed-by: Tao Zhou 

> -Original Message-
> From: Hawking Zhang 
> Sent: Tuesday, April 16, 2024 12:34 PM
> To: amd-gfx@lists.freedesktop.org; Zhou1, Tao 
> Cc: Zhang, Hawking 
> Subject: [PATCH] drm/amdgpu: Use driver mode reset for data poison
> handling
>
> mode-2 reset is the only reliable method that can get GC/SDMA back
> when poison is consumed. mmhub requires
> mode-1 reset.
>
> Signed-off-by: Hawking Zhang 
> ---
>  drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c | 8 ++--
>  1 file changed, 2 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c
> index c368c70df3f4a..b6caf6eda8a0c 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c
> @@ -163,17 +163,13 @@ static void
> event_interrupt_poison_consumption_v9(struct kfd_node *dev,
>   case SOC15_IH_CLIENTID_SE2SH:
>   case SOC15_IH_CLIENTID_SE3SH:
>   case SOC15_IH_CLIENTID_UTCL2:
> - ret = kfd_dqm_evict_pasid(dev->dqm, pasid);
>   block = AMDGPU_RAS_BLOCK__GFX;
> - if (ret)
> - reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET;
> + reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET;
>   break;
>   case SOC15_IH_CLIENTID_VMC:
>   case SOC15_IH_CLIENTID_VMC1:
> - ret = kfd_dqm_evict_pasid(dev->dqm, pasid);
>   block = AMDGPU_RAS_BLOCK__MMHUB;
> - if (ret)
> - reset = AMDGPU_RAS_GPU_RESET_MODE1_RESET;
> + reset = AMDGPU_RAS_GPU_RESET_MODE1_RESET;
>   break;
>   case SOC15_IH_CLIENTID_SDMA0:
>   case SOC15_IH_CLIENTID_SDMA1:
> --
> 2.17.1

RE: [PATCH] drm/amdgpu: Change AID detection logic

[Zhang, Hawking]

[AMD Official Use Only - General]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: Lazar, Lijo 
Sent: Monday, April 15, 2024 00:43
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Deucher, Alexander 
; Kamal, Asad ; Kamal, Asad 

Subject: [PATCH] drm/amdgpu: Change AID detection logic

On GFX 9.4.3 SOCs, only 2 SDMA instances need to be available to be considered 
as a valid AID.

Signed-off-by: Lijo Lazar 
Reviewed-by: Asad Kamal 
---
 drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c 
b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
index fbf5f65ab091..bdab65bc3105 100644
--- a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
+++ b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
@@ -649,7 +649,7 @@ static void aqua_vanjaram_down_config(struct amdgpu_device 
*adev)

 int aqua_vanjaram_init_soc_config(struct amdgpu_device *adev)  {
-   u32 mask, inst_mask = adev->sdma.sdma_mask, sdma_pres;
+   u32 mask, avail_inst, inst_mask = adev->sdma.sdma_mask;
int ret, i;

aqua_vanjaram_down_config(adev);
@@ -662,8 +662,9 @@ int aqua_vanjaram_init_soc_config(struct amdgpu_device 
*adev)

for (mask = (1 << adev->sdma.num_inst_per_aid) - 1; inst_mask;
 inst_mask >>= adev->sdma.num_inst_per_aid, ++i) {
-   sdma_pres = inst_mask & mask;
-   if (sdma_pres == mask || sdma_pres == 0x3 || sdma_pres == 0xc)
+   avail_inst = inst_mask & mask;
+   if (avail_inst == mask || avail_inst == 0x3 ||
+   avail_inst == 0xc)
adev->aid_mask |= (1 << i);
}

--
2.25.1

RE: [PATCH] drm/amdgpu: replace sdma tmz flag on si dma

[Zhang, Hawking]

[AMD Official Use Only - General]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: amd-gfx  On Behalf Of Gao, Likun
Sent: Friday, April 12, 2024 17:41
To: amd-gfx list 
Subject: [PATCH] drm/amdgpu: replace sdma tmz flag on si dma

[AMD Official Use Only - General]

[AMD Official Use Only - General]

From: Likun Gao 

Fix build issue on si dma to replace tmz flag

Signed-off-by: Likun Gao 
---
 drivers/gpu/drm/amd/amdgpu/si_dma.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c 
b/drivers/gpu/drm/amd/amdgpu/si_dma.c
index 42c4547f32ec..6672d8a49d66 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
@@ -776,7 +776,7 @@ static void si_dma_emit_copy_buffer(struct amdgpu_ib *ib,
   uint64_t src_offset,
   uint64_t dst_offset,
   uint32_t byte_count,
-  bool tmz)
+  uint32_t copy_flags)
 {
ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_COPY,
  1, 0, 0, byte_count);
--
2.34.1

RE: [PATCH] drm/amd/pm: Allow setting soft max frequency in VF

[Zhang, Hawking]

[AMD Official Use Only - General]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: Lazar, Lijo 
Sent: Thursday, April 4, 2024 14:53
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Deucher, Alexander 
; Kamal, Asad ; Wang, 
Yang(Kevin) 
Subject: [PATCH] drm/amd/pm: Allow setting soft max frequency in VF

Setting soft max frequency for MCLK is allowed in 1VF mode in SMUv13.0.6 SOCs.

Signed-off-by: Lijo Lazar 
---
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
index a09c89b3db96..d6d5be26e222 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
@@ -138,7 +138,7 @@ static const struct cmn2asic_msg_mapping 
smu_v13_0_6_message_map[SMU_MSG_MAX_COU
MSG_MAP(SetToolsDramAddrHigh,
PPSMC_MSG_SetToolsDramAddrHigh,0),
MSG_MAP(SetToolsDramAddrLow, 
PPSMC_MSG_SetToolsDramAddrLow, 0),
MSG_MAP(SetSoftMinByFreq,
PPSMC_MSG_SetSoftMinByFreq,0),
-   MSG_MAP(SetSoftMaxByFreq,
PPSMC_MSG_SetSoftMaxByFreq,0),
+   MSG_MAP(SetSoftMaxByFreq,
PPSMC_MSG_SetSoftMaxByFreq,1),
MSG_MAP(GetMinDpmFreq,   PPSMC_MSG_GetMinDpmFreq,   
1),
MSG_MAP(GetMaxDpmFreq,   PPSMC_MSG_GetMaxDpmFreq,   
1),
MSG_MAP(GetDpmFreqByIndex,   
PPSMC_MSG_GetDpmFreqByIndex,   1),
@@ -1676,6 +1676,11 @@ static int 
smu_v13_0_6_set_soft_freq_limited_range(struct smu_context *smu,
if (clk_type == SMU_UCLK) {
if (max == pstate_table->uclk_pstate.curr.max)
return 0;
+   /* For VF, only allowed in FW versions 85.102 or 
greater */
+   if (amdgpu_sriov_vf(adev) &&
+   ((smu->smc_fw_version < 0x556600) ||
+(adev->flags & AMD_IS_APU)))
+   return -EOPNOTSUPP;
/* Only max clock limiting is allowed for UCLK */
ret = smu_v13_0_set_soft_freq_limited_range(
smu, SMU_UCLK, 0, max);
--
2.25.1

RE: [PATCH] drm/amdgpu: retire UMC v12 mca_addr_to_pa

[Zhang, Hawking]

[AMD Official Use Only - General]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: amd-gfx  On Behalf Of Tao Zhou
Sent: Tuesday, April 2, 2024 16:51
To: amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao 
Subject: [PATCH] drm/amdgpu: retire UMC v12 mca_addr_to_pa

RAS TA will handle it, the interface is useless.

Signed-off-by: Tao Zhou 
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c  |   1 -
 drivers/gpu/drm/amd/amdgpu/umc_v12_0.c | 105 ++---  
drivers/gpu/drm/amd/amdgpu/umc_v12_0.h |  62 +--
 3 files changed, 7 insertions(+), 161 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 4ba26d7e52bd..afae497cbf40 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -1460,7 +1460,6 @@ static void gmc_v9_0_set_umc_funcs(struct amdgpu_device 
*adev)
adev->umc.channel_offs = UMC_V12_0_PER_CHANNEL_OFFSET;
adev->umc.active_mask = adev->aid_mask;
adev->umc.retire_unit = UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL;
-   adev->umc.channel_idx_tbl = _v12_0_channel_idx_tbl[0][0][0];
if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu)
adev->umc.ras = _v12_0_ras;
break;
diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c 
b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
index f46a176f9b55..a0122b22eda4 100644
--- a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
@@ -28,28 +28,6 @@
 #include "umc/umc_12_0_0_sh_mask.h"
 #include "mp/mp_13_0_6_sh_mask.h"

-const uint32_t
-   umc_v12_0_channel_idx_tbl[]
-   [UMC_V12_0_UMC_INSTANCE_NUM]
-   [UMC_V12_0_CHANNEL_INSTANCE_NUM] = {
-   {{3,   7,   11,  15,  2,   6,   10,  14},  {1,   5,   9,   13,  
0,   4,   8,   12},
-{19,  23,  27,  31,  18,  22,  26,  30},  {17,  21,  25,  29,  
16,  20,  24,  28}},
-   {{47,  43,  39,  35,  46,  42,  38,  34},  {45,  41,  37,  33,  
44,  40,  36,  32},
-{63,  59,  55,  51,  62,  58,  54,  50},  {61,  57,  53,  49,  
60,  56,  52,  48}},
-   {{79,  75,  71,  67,  78,  74,  70,  66},  {77,  73,  69,  65,  
76,  72,  68,  64},
-{95,  91,  87,  83,  94,  90,  86,  82},  {93,  89,  85,  81,  
92,  88,  84,  80}},
-   {{99,  103, 107, 111, 98,  102, 106, 110}, {97,  101, 105, 109, 
96,  100, 104, 108},
-{115, 119, 123, 127, 114, 118, 122, 126}, {113, 117, 121, 125, 
112, 116, 120, 124}}
-   };
-
-/* mapping of MCA error address to normalized address */ -static const 
uint32_t umc_v12_0_ma2na_mapping[] = {
-   0,  5,  6,  8,  9,  14, 12, 13,
-   10, 11, 15, 16, 17, 18, 19, 20,
-   21, 22, 23, 24, 25, 26, 27, 28,
-   24, 7,  29, 30,
-};
-
 static inline uint64_t get_umc_v12_0_reg_offset(struct amdgpu_device *adev,
uint32_t node_inst,
uint32_t umc_inst,
@@ -192,79 +170,6 @@ static void umc_v12_0_query_ras_error_count(struct 
amdgpu_device *adev,
umc_v12_0_reset_error_count(adev);
 }

-static bool umc_v12_0_bit_wise_xor(uint32_t val) -{
-   bool result = 0;
-   int i;
-
-   for (i = 0; i < 32; i++)
-   result = result ^ ((val >> i) & 0x1);
-
-   return result;
-}
-
-static void umc_v12_0_mca_addr_to_pa(struct amdgpu_device *adev,
-   uint64_t err_addr, uint32_t ch_inst, 
uint32_t umc_inst,
-   uint32_t node_inst,
-   struct ta_ras_query_address_output 
*addr_out)
-{
-   uint32_t channel_index, i;
-   uint64_t na, soc_pa;
-   uint32_t bank_hash0, bank_hash1, bank_hash2, bank_hash3, col, row;
-   uint32_t bank0, bank1, bank2, bank3, bank;
-
-   bank_hash0 = (err_addr >> UMC_V12_0_MCA_B0_BIT) & 0x1ULL;
-   bank_hash1 = (err_addr >> UMC_V12_0_MCA_B1_BIT) & 0x1ULL;
-   bank_hash2 = (err_addr >> UMC_V12_0_MCA_B2_BIT) & 0x1ULL;
-   bank_hash3 = (err_addr >> UMC_V12_0_MCA_B3_BIT) & 0x1ULL;
-   col = (err_addr >> 1) & 0x1fULL;
-   row = (err_addr >> 10) & 0x3fffULL;
-
-   /* apply bank hash algorithm */
-   bank0 =
-   bank_hash0 ^ (UMC_V12_0_XOR_EN0 &
-   (umc_v12_0_bit_wise_xor(col & UMC_V12_0_COL_XOR0) ^
-   (umc_v12_0_bit_wise_xor(row & UMC_V12_0_ROW_XOR0;
-   bank1 =
-   bank_hash1 ^ (UMC_V12_0_XOR_EN1 &
-   (umc_v12_0_bit_wise_xor(col & UMC_V12_0_COL_XOR1) ^
-   (umc_v12_0_bit_wise_xor(row & UMC_V12_0_ROW_XOR1;
-   bank2 =
-   bank_hash2 ^ (UMC_V12_0_XOR_EN2 &
-   (umc_v12_0_bit_wise_xor(col & UMC_V12_0_COL_XOR2) ^
-   (umc_v12_0_bit_wise_xor(row & UMC_V12_0_ROW_XOR2;
-   bank3 =
-  

RE: [PATCH] drm/amd/pm: update XGMI RAS UE criteria for sum v13.0.6

[Zhang, Hawking]

[AMD Official Use Only - General]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: amd-gfx  On Behalf Of Tao Zhou
Sent: Monday, April 1, 2024 14:24
To: amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao 
Subject: [PATCH] drm/amd/pm: update XGMI RAS UE criteria for sum v13.0.6

Add more possible ext error code.

v2: still use ext error code instead of UC bit.

Signed-off-by: Tao Zhou 
---
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
index 443233563a52..7a7c7f4b7de3 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
@@ -2694,7 +2694,8 @@ static int mca_pcs_xgmi_mca_get_err_count(const struct 
mca_ras_info *mca_ras, st
ext_error_code = 
MCA_REG__STATUS__ERRORCODEEXT(entry->regs[MCA_REG_IDX_STATUS]);
err_cnt = MCA_REG__MISC0__ERRCNT(entry->regs[MCA_REG_IDX_MISC0]);

-   if (type == AMDGPU_MCA_ERROR_TYPE_UE && ext_error_code == 0)
+   if (type == AMDGPU_MCA_ERROR_TYPE_UE &&
+   (ext_error_code == 0 || ext_error_code == 9))
*count = err_cnt;
else if (type == AMDGPU_MCA_ERROR_TYPE_CE && ext_error_code == 6)
*count = err_cnt;
--
2.34.1

RE: [PATCH] drm/amdgpu: Bypass asd if display hw is not available

[Zhang, Hawking]

[AMD Official Use Only - General]

Please ignore this one. will send v2

Regards,
Hawking

-Original Message-
From: Hawking Zhang 
Sent: Friday, March 29, 2024 17:49
To: amd-gfx@lists.freedesktop.org; Deucher, Alexander 
; Feng, Kenneth 
Cc: Zhang, Hawking 
Subject: [PATCH] drm/amdgpu: Bypass asd if display hw is not available

ASD is not needed by headless GPU.

Signed-off-by: Hawking Zhang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 94b310fdb719d..063203865bbe2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -1053,6 +1053,11 @@ static int psp_asd_initialize(struct psp_context *psp)
if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes)
return 0;

+   /* bypass asd if display hardware is not available */
+   if (!amdgpu_device_has_display_hardware(psp->adev) &&
+   amdgpu_ip_version(adev, MP0_HWIP, 0) >= IP_VERSION(13, 0, 10))
+   return 0;
+
psp->asd_context.mem_context.shared_mc_addr  = 0;
psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE;
psp->asd_context.ta_load_type= GFX_CMD_ID_LOAD_ASD;
--
2.17.1

RE: [PATCH] drm/amdgpu: implement IRQ_STATE_ENABLE for SDMA v4.4.2

[Zhang, Hawking]

[AMD Official Use Only - General]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: Zhou1, Tao 
Sent: Friday, March 29, 2024 11:10
To: amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao ; Zhang, Hawking 
Subject: [PATCH] drm/amdgpu: implement IRQ_STATE_ENABLE for SDMA v4.4.2

SDMA_CNTL is not set in some cases, driver configures it by itself.

v2: simplify code

Signed-off-by: Tao Zhou 
Reviewed-by: Hawking Zhang 
---
 drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 16 +++-
 1 file changed, 3 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
index 71c2f50530cb..f8e2cd514493 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
@@ -1602,19 +1602,9 @@ static int sdma_v4_4_2_set_ecc_irq_state(struct 
amdgpu_device *adev,
u32 sdma_cntl;

sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL);
-   switch (state) {
-   case AMDGPU_IRQ_STATE_DISABLE:
-   sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL,
- DRAM_ECC_INT_ENABLE, 0);
-   WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl);
-   break;
-   /* sdma ecc interrupt is enabled by default
-* driver doesn't need to do anything to
-* enable the interrupt */
-   case AMDGPU_IRQ_STATE_ENABLE:
-   default:
-   break;
-   }
+   sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, DRAM_ECC_INT_ENABLE,
+   state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 
0);
+   WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl);

return 0;
 }
--
2.34.1

RE: [PATCH] drm/amdgpu: implement IRQ_STATE_ENABLE for SDMA v4.4.2

[Zhang, Hawking]

[AMD Official Use Only - General]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: amd-gfx  On Behalf Of Tao Zhou
Sent: Thursday, March 28, 2024 18:28
To: amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao 
Subject: [PATCH] drm/amdgpu: implement IRQ_STATE_ENABLE for SDMA v4.4.2

SDMA_CNTL is not set in some cases, driver configures it by itself.

Signed-off-by: Tao Zhou 
---
 drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
index 71c2f50530cb..d10ae4ce5ddd 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
@@ -1608,10 +1608,11 @@ static int sdma_v4_4_2_set_ecc_irq_state(struct 
amdgpu_device *adev,
  DRAM_ECC_INT_ENABLE, 0);
WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl);
break;
-   /* sdma ecc interrupt is enabled by default
-* driver doesn't need to do anything to
-* enable the interrupt */
case AMDGPU_IRQ_STATE_ENABLE:
+   sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL,
+ DRAM_ECC_INT_ENABLE, 1);
+   WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl);
+   break;
default:
break;
}
--
2.34.1

RE: [PATCH v2 4/4] drm/amd/pm: Categorize RAS messages on SMUv13.0.6

[Zhang, Hawking]

[AMD Official Use Only - General]

Series is

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: Lazar, Lijo 
Sent: Thursday, March 28, 2024 10:36
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Deucher, Alexander 
; Wang, Yang(Kevin) 
Subject: [PATCH v2 4/4] drm/amd/pm: Categorize RAS messages on SMUv13.0.6

Set RAS priority handling capability for SMUv13.0.6 SOCs and categorize RAS 
priority messages allowed.

Signed-off-by: Lijo Lazar 
---
v2: Move setting FW capability flags to IP specific code (Kevin)

 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 11 ++-
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
index 443233563a52..6e06729fb2e3 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
@@ -144,7 +144,7 @@ static const struct cmn2asic_msg_mapping 
smu_v13_0_6_message_map[SMU_MSG_MAX_COU
MSG_MAP(GetDpmFreqByIndex,   
PPSMC_MSG_GetDpmFreqByIndex,   1),
MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 
0),
MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 
1),
-   MSG_MAP(GfxDeviceDriverReset,PPSMC_MSG_GfxDriverReset,  
0),
+   MSG_MAP(GfxDeviceDriverReset,PPSMC_MSG_GfxDriverReset,  
SMU_MSG_RAS_PRI),
MSG_MAP(DramLogSetDramAddrHigh,  
PPSMC_MSG_DramLogSetDramAddrHigh,  0),
MSG_MAP(DramLogSetDramAddrLow,   
PPSMC_MSG_DramLogSetDramAddrLow,   0),
MSG_MAP(DramLogSetDramSize,  
PPSMC_MSG_DramLogSetDramSize,  0),
@@ -167,10 +167,10 @@ static const struct cmn2asic_msg_mapping 
smu_v13_0_6_message_map[SMU_MSG_MAX_COU
MSG_MAP(GetCTFLimit, PPSMC_MSG_GetCTFLimit, 
0),
MSG_MAP(GetThermalLimit, 
PPSMC_MSG_ReadThrottlerLimit,  0),
MSG_MAP(ClearMcaOnRead,  PPSMC_MSG_ClearMcaOnRead,  
0),
-   MSG_MAP(QueryValidMcaCount,  
PPSMC_MSG_QueryValidMcaCount,  0),
-   MSG_MAP(QueryValidMcaCeCount,
PPSMC_MSG_QueryValidMcaCeCount,0),
-   MSG_MAP(McaBankDumpDW,   PPSMC_MSG_McaBankDumpDW,   
0),
-   MSG_MAP(McaBankCeDumpDW, PPSMC_MSG_McaBankCeDumpDW, 
0),
+   MSG_MAP(QueryValidMcaCount,  
PPSMC_MSG_QueryValidMcaCount,  SMU_MSG_RAS_PRI),
+   MSG_MAP(QueryValidMcaCeCount,
PPSMC_MSG_QueryValidMcaCeCount,SMU_MSG_RAS_PRI),
+   MSG_MAP(McaBankDumpDW,   PPSMC_MSG_McaBankDumpDW,   
SMU_MSG_RAS_PRI),
+   MSG_MAP(McaBankCeDumpDW, PPSMC_MSG_McaBankCeDumpDW, 
SMU_MSG_RAS_PRI),
MSG_MAP(SelectPLPDMode,  PPSMC_MSG_SelectPLPDMode,  
0),
MSG_MAP(RmaDueToBadPageThreshold,
PPSMC_MSG_RmaDueToBadPageThreshold,0),
 };
@@ -3218,6 +3218,7 @@ void smu_v13_0_6_set_ppt_funcs(struct smu_context *smu)
smu->feature_map = smu_v13_0_6_feature_mask_map;
smu->table_map = smu_v13_0_6_table_map;
smu->smc_driver_if_version = SMU13_0_6_DRIVER_IF_VERSION;
+   smu->smc_fw_caps |= SMU_FW_CAP_RAS_PRI;
smu_v13_0_set_smu_mailbox_registers(smu);
amdgpu_mca_smu_init_funcs(smu->adev, _v13_0_6_mca_smu_funcs);
amdgpu_aca_set_smu_funcs(smu->adev, _v13_0_6_aca_smu_funcs);
--
2.25.1

RE: [PATCH] drm/amd/pm: fix the high voltage issue after unload

[Zhang, Hawking]

[AMD Official Use Only - General]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: Kenneth Feng 
Sent: Thursday, March 28, 2024 14:02
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Feng, Kenneth 
Subject: [PATCH] drm/amd/pm: fix the high voltage issue after unload

fix the high voltage issue after unload on smu 13.0.10

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 26 ++
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 27 +--
 drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h |  1 +  
.../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c  |  8 +-
 4 files changed, 48 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 12dc71a6b5db..1b9136bb7f62 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -4138,18 +4138,22 @@ int amdgpu_device_init(struct amdgpu_device *adev,
adev->ip_blocks[i].status.hw = true;
}
}
+   } else if (amdgpu_ip_version(adev, MP1_HWIP, 0) == 
IP_VERSION(13, 0, 10) &&
+  !amdgpu_device_has_display_hardware(adev)) {
+   r = psp_gpu_reset(adev);
} else {
-   tmp = amdgpu_reset_method;
-   /* It should do a default reset when loading or 
reloading the driver,
-* regardless of the module parameter reset_method.
-*/
-   amdgpu_reset_method = AMD_RESET_METHOD_NONE;
-   r = amdgpu_asic_reset(adev);
-   amdgpu_reset_method = tmp;
-   if (r) {
-   dev_err(adev->dev, "asic reset on init 
failed\n");
-   goto failed;
-   }
+   tmp = amdgpu_reset_method;
+   /* It should do a default reset when loading or 
reloading the driver,
+* regardless of the module parameter 
reset_method.
+*/
+   amdgpu_reset_method = AMD_RESET_METHOD_NONE;
+   r = amdgpu_asic_reset(adev);
+   amdgpu_reset_method = tmp;
+   }
+
+   if (r) {
+ dev_err(adev->dev, "asic reset on init failed\n");
+ goto failed;
}
}

diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c 
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 246b211b1e85..65333141b1c1 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -735,7 +735,7 @@ static int smu_early_init(void *handle)
smu->adev = adev;
smu->pm_enabled = !!amdgpu_dpm;
smu->is_apu = false;
-   smu->smu_baco.state = SMU_BACO_STATE_EXIT;
+   smu->smu_baco.state = SMU_BACO_STATE_NONE;
smu->smu_baco.platform_support = false;
smu->user_dpm_profile.fan_mode = -1;

@@ -1966,10 +1966,25 @@ static int smu_smc_hw_cleanup(struct smu_context *smu)
return 0;
 }

+static int smu_reset_mp1_state(struct smu_context *smu) {
+   struct amdgpu_device *adev = smu->adev;
+   int ret = 0;
+
+   if ((!adev->in_runpm) && (!adev->in_suspend) &&
+   (!amdgpu_in_reset(adev)) && amdgpu_ip_version(adev, MP1_HWIP, 
0) ==
+   
IP_VERSION(13, 0, 10) &&
+   !amdgpu_device_has_display_hardware(adev))
+   ret = smu_set_mp1_state(smu, PP_MP1_STATE_UNLOAD);
+
+   return ret;
+}
+
 static int smu_hw_fini(void *handle)
 {
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct smu_context *smu = adev->powerplay.pp_handle;
+   int ret;

if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
return 0;
@@ -1987,7 +2002,15 @@ static int smu_hw_fini(void *handle)

adev->pm.dpm_enabled = false;

-   return smu_smc_hw_cleanup(smu);
+   ret = smu_smc_hw_cleanup(smu);
+   if (ret)
+   return ret;
+
+   ret = smu_reset_mp1_state(smu);
+   if (ret)
+   return ret;
+
+   return 0;
 }

 static void smu_late_fini(void *handle) diff --git 
a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
index a870bdd49a4e..1fa81575788c 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
@@ -424,6 +424,7 @@ enum smu_reset_mode {  enum smu_baco_state {

RE: [PATCH v3] drm/amdgpu: Reset dGPU if suspend got aborted

[Zhang, Hawking]

[AMD Official Use Only - General]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: Lazar, Lijo 
Sent: Thursday, March 28, 2024 13:11
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Deucher, Alexander 
; Wang, Yang(Kevin) ; 
Deucher, Alexander ; sta...@vger.kernel.org
Subject: [PATCH v3] drm/amdgpu: Reset dGPU if suspend got aborted

For SOC21 ASICs, there is an issue in re-enabling PM features if a suspend got 
aborted. In such cases, reset the device during resume phase. This is a 
workaround till a proper solution is finalized.

Signed-off-by: Lijo Lazar 
Reviewed-by: Alex Deucher 
Reviewed-by: Yang Wang 

Cc: sta...@vger.kernel.org
---
v2: Read TOS status only if required (Kevin).
Refine log message.

v3: Add stable trees tag

 drivers/gpu/drm/amd/amdgpu/soc21.c | 25 +
 1 file changed, 25 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c 
b/drivers/gpu/drm/amd/amdgpu/soc21.c
index 8526282f4da1..abe319b0f063 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -867,10 +867,35 @@ static int soc21_common_suspend(void *handle)
return soc21_common_hw_fini(adev);
 }

+static bool soc21_need_reset_on_resume(struct amdgpu_device *adev) {
+   u32 sol_reg1, sol_reg2;
+
+   /* Will reset for the following suspend abort cases.
+* 1) Only reset dGPU side.
+* 2) S3 suspend got aborted and TOS is active.
+*/
+   if (!(adev->flags & AMD_IS_APU) && adev->in_s3 &&
+   !adev->suspend_complete) {
+   sol_reg1 = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
+   msleep(100);
+   sol_reg2 = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
+
+   return (sol_reg1 != sol_reg2);
+   }
+
+   return false;
+}
+
 static int soc21_common_resume(void *handle)  {
struct amdgpu_device *adev = (struct amdgpu_device *)handle;

+   if (soc21_need_reset_on_resume(adev)) {
+   dev_info(adev->dev, "S3 suspend aborted, resetting...");
+   soc21_asic_reset(adev);
+   }
+
return soc21_common_hw_init(adev);
 }

--
2.25.1

RE: [PATCH] drm/amdgpu: Update setting EEPROM table version

[Zhang, Hawking]

[AMD Official Use Only - General]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: amd-gfx  On Behalf Of Candice Li
Sent: Tuesday, March 19, 2024 11:26
To: amd-gfx@lists.freedesktop.org
Cc: Li, Candice 
Subject: [PATCH] drm/amdgpu: Update setting EEPROM table version

Use helper function instead of umc callback to set EEPROM table version.

Signed-off-by: Candice Li 
---
 .../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c| 22 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h   |  2 --
 drivers/gpu/drm/amd/amdgpu/umc_v8_10.c|  6 -
 3 files changed, 17 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
index b12808c0c331f2..06a62a8a992e9b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
@@ -404,6 +404,22 @@ static int amdgpu_ras_eeprom_correct_header_tag(
return res;
 }

+static void amdgpu_ras_set_eeprom_table_version(struct
+amdgpu_ras_eeprom_control *control) {
+   struct amdgpu_device *adev = to_amdgpu_device(control);
+   struct amdgpu_ras_eeprom_table_header *hdr = >tbl_hdr;
+
+   switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) {
+   case IP_VERSION(8, 10, 0):
+   case IP_VERSION(12, 0, 0):
+   hdr->version = RAS_TABLE_VER_V2_1;
+   return;
+   default:
+   hdr->version = RAS_TABLE_VER_V1;
+   return;
+   }
+}
+
 /**
  * amdgpu_ras_eeprom_reset_table -- Reset the RAS EEPROM table
  * @control: pointer to control structure @@ -423,11 +439,7 @@ int 
amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control)
mutex_lock(>ras_tbl_mutex);

hdr->header = RAS_TABLE_HDR_VAL;
-   if (adev->umc.ras &&
-   adev->umc.ras->set_eeprom_table_version)
-   adev->umc.ras->set_eeprom_table_version(hdr);
-   else
-   hdr->version = RAS_TABLE_VER_V1;
+   amdgpu_ras_set_eeprom_table_version(control);

if (hdr->version == RAS_TABLE_VER_V2_1) {
hdr->first_rec_offset = RAS_RECORD_START_V2_1; diff --git 
a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
index 26d2ae498daf22..5954e839d5808d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
@@ -66,8 +66,6 @@ struct amdgpu_umc_ras {
void *ras_error_status);
bool (*check_ecc_err_status)(struct amdgpu_device *adev,
enum amdgpu_mca_error_type type, void 
*ras_error_status);
-   /* support different eeprom table version for different asic */
-   void (*set_eeprom_table_version)(struct amdgpu_ras_eeprom_table_header 
*hdr);
 };

 struct amdgpu_umc_funcs {
diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v8_10.c 
b/drivers/gpu/drm/amd/amdgpu/umc_v8_10.c
index c4c77257710c97..a32f87992f2058 100644
--- a/drivers/gpu/drm/amd/amdgpu/umc_v8_10.c
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v8_10.c
@@ -442,11 +442,6 @@ static void 
umc_v8_10_ecc_info_query_ras_error_address(struct amdgpu_device *ade
umc_v8_10_ecc_info_query_error_address, ras_error_status);  }

-static void umc_v8_10_set_eeprom_table_version(struct 
amdgpu_ras_eeprom_table_header *hdr) -{
-   hdr->version = RAS_TABLE_VER_V2_1;
-}
-
 const struct amdgpu_ras_block_hw_ops umc_v8_10_ras_hw_ops = {
.query_ras_error_count = umc_v8_10_query_ras_error_count,
.query_ras_error_address = umc_v8_10_query_ras_error_address,
@@ -460,5 +455,4 @@ struct amdgpu_umc_ras umc_v8_10_ras = {
.query_ras_poison_mode = umc_v8_10_query_ras_poison_mode,
.ecc_info_query_ras_error_count = 
umc_v8_10_ecc_info_query_ras_error_count,
.ecc_info_query_ras_error_address = 
umc_v8_10_ecc_info_query_ras_error_address,
-   .set_eeprom_table_version = umc_v8_10_set_eeprom_table_version,
 };
--
2.25.1

RE: [PATCH 3/3] drm/amdgpu: make reset method configurable for RAS poison

[Zhang, Hawking]

[AMD Official Use Only - General]

Series is

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: amd-gfx  On Behalf Of Tao Zhou
Sent: Monday, March 18, 2024 15:26
To: amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao 
Subject: [PATCH 3/3] drm/amdgpu: make reset method configurable for RAS poison

Each RAS block has different requirement for gpu reset in poison consumption 
handling.
Add support for mmhub RAS poison consumption handling.

v2: remove the mmhub poison support for kfd int v10.

Signed-off-by: Tao Zhou 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c|  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h|  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c   |  4 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c   | 14 ++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h   |  4 ++--
 .../gpu/drm/amd/amdkfd/kfd_int_process_v10.c  | 13 +++-  
.../gpu/drm/amd/amdkfd/kfd_int_process_v11.c  |  9 +
 .../gpu/drm/amd/amdkfd/kfd_int_process_v9.c   | 20 ++-
 8 files changed, 40 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index 0b4910108f61..66753940bb4d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -760,7 +760,7 @@ bool amdgpu_amdkfd_is_fed(struct amdgpu_device *adev)  }

 void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev,
-   enum amdgpu_ras_block block, bool reset)
+   enum amdgpu_ras_block block, uint32_t reset)
 {
amdgpu_umc_poison_handler(adev, block, reset);  } diff --git 
a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index 03bf20e0e3da..ad50c7bbc326 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -400,7 +400,7 @@ void amdgpu_amdkfd_debug_mem_fence(struct amdgpu_device 
*adev);  int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev,
struct tile_config *config);
 void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev,
-   enum amdgpu_ras_block block, bool reset);
+   enum amdgpu_ras_block block, uint32_t reset);
 bool amdgpu_amdkfd_is_fed(struct amdgpu_device *adev);  bool 
amdgpu_amdkfd_bo_mapped_to_dev(struct amdgpu_device *adev, struct kgd_mem 
*mem);  void amdgpu_amdkfd_block_mmu_notifications(void *p); diff --git 
a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index e32a186c2de1..58fe7bebdf1b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -2045,7 +2045,7 @@ static void 
amdgpu_ras_interrupt_poison_consumption_handler(struct ras_manager *
}
}

-   amdgpu_umc_poison_handler(adev, obj->head.block, false);
+   amdgpu_umc_poison_handler(adev, obj->head.block, 0);

if (block_obj->hw_ops && block_obj->hw_ops->handle_poison_consumption)
poison_stat = 
block_obj->hw_ops->handle_poison_consumption(adev);
@@ -2698,7 +2698,7 @@ static int amdgpu_ras_page_retirement_thread(void *param)
atomic_dec(>page_retirement_req_cnt);

amdgpu_umc_bad_page_polling_timeout(adev,
-   false, MAX_UMC_POISON_POLLING_TIME_ASYNC);
+   0, MAX_UMC_POISON_POLLING_TIME_ASYNC);
}

return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
index 20436f81856a..2c02585dcbff 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
@@ -186,9 +186,7 @@ static int amdgpu_umc_do_page_retirement(struct 
amdgpu_device *adev,
amdgpu_umc_handle_bad_pages(adev, ras_error_status);

if (err_data->ue_count && reset) {
-   /* use mode-2 reset for poison consumption */
-   if (!entry)
-   con->gpu_reset_flags |= 
AMDGPU_RAS_GPU_RESET_MODE2_RESET;
+   con->gpu_reset_flags |= reset;
amdgpu_ras_reset_gpu(adev);
}

@@ -196,7 +194,7 @@ static int amdgpu_umc_do_page_retirement(struct 
amdgpu_device *adev,  }

 int amdgpu_umc_bad_page_polling_timeout(struct amdgpu_device *adev,
-   bool reset, uint32_t timeout_ms)
+   uint32_t reset, uint32_t timeout_ms)
 {
struct ras_err_data err_data;
struct ras_common_if head = {
@@ -238,8 +236,7 @@ int amdgpu_umc_bad_page_polling_timeout(struct 
amdgpu_device *adev,
if (reset) {
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);

-   /* use mode-2 reset for poison consumption */
-   con->gpu_reset_flags |= AMDGPU_RAS_GPU_RESET_MODE2_RESET;
+   con->gpu_reset_flags |= reset;

RE: [PATCH] drm/amdgpu: trigger flr_work if reading pf2vf data failed

[Zhang, Hawking]

[AMD Official Use Only - General]

Acked-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: Luo, Zhigang 
Sent: Monday, March 18, 2024 11:38
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Saye, Sashank 
; Chan, Hing Pong ; Luo, Zhigang 

Subject: [PATCH] drm/amdgpu: trigger flr_work if reading pf2vf data failed

if reading pf2vf data failed 30 times continuously, it means something is 
wrong. Need to trigger flr_work to recover the issue.

also use dev_err to print the error message to get which device has issue and 
add warning message if waiting IDH_FLR_NOTIFICATION_CMPL timeout.

Signed-off-by: Zhigang Luo 
Change-Id: Ia7ce934d0c3068ad3934715c14bbffdfcbafc4c2
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 15 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c   | 29 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h   |  3 +++
 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c  |  2 ++
 drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c  |  2 ++
 5 files changed, 41 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index b37113b79483..70261eb9b0bb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -143,6 +143,8 @@ const char *amdgpu_asic_name[] = {
"LAST",
 };

+static inline void amdgpu_device_stop_pending_resets(struct
+amdgpu_device *adev);
+
 /**
  * DOC: pcie_replay_count
  *
@@ -4972,6 +4974,8 @@ static int amdgpu_device_reset_sriov(struct amdgpu_device 
*adev,
 retry:
amdgpu_amdkfd_pre_reset(adev);

+   amdgpu_device_stop_pending_resets(adev);
+
if (from_hypervisor)
r = amdgpu_virt_request_full_gpu(adev, true);
else
@@ -5712,11 +5716,12 @@ int amdgpu_device_gpu_recover(struct amdgpu_device 
*adev,
tmp_adev->asic_reset_res = r;
}

-   /*
-* Drop all pending non scheduler resets. Scheduler resets
-* were already dropped during drm_sched_stop
-*/
-   amdgpu_device_stop_pending_resets(tmp_adev);
+   if (!amdgpu_sriov_vf(tmp_adev))
+   /*
+   * Drop all pending non scheduler resets. Scheduler 
resets
+   * were already dropped during drm_sched_stop
+   */
+   amdgpu_device_stop_pending_resets(tmp_adev);
}

/* Actual ASIC resets if needed.*/
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index 7a4eae36778a..aed60aaf1a55 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -32,6 +32,7 @@

 #include "amdgpu.h"
 #include "amdgpu_ras.h"
+#include "amdgpu_reset.h"
 #include "vi.h"
 #include "soc15.h"
 #include "nv.h"
@@ -424,7 +425,7 @@ static int amdgpu_virt_read_pf2vf_data(struct amdgpu_device 
*adev)
return -EINVAL;

if (pf2vf_info->size > 1024) {
-   DRM_ERROR("invalid pf2vf message size\n");
+   dev_err(adev->dev, "invalid pf2vf message size: 0x%x\n",
+pf2vf_info->size);
return -EINVAL;
}

@@ -435,7 +436,9 @@ static int amdgpu_virt_read_pf2vf_data(struct amdgpu_device 
*adev)
adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size,
adev->virt.fw_reserve.checksum_key, checksum);
if (checksum != checkval) {
-   DRM_ERROR("invalid pf2vf message\n");
+   dev_err(adev->dev,
+   "invalid pf2vf message: header checksum=0x%x 
calculated checksum=0x%x\n",
+   checksum, checkval);
return -EINVAL;
}

@@ -449,7 +452,9 @@ static int amdgpu_virt_read_pf2vf_data(struct amdgpu_device 
*adev)
adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size,
0, checksum);
if (checksum != checkval) {
-   DRM_ERROR("invalid pf2vf message\n");
+   dev_err(adev->dev,
+   "invalid pf2vf message: header checksum=0x%x 
calculated checksum=0x%x\n",
+   checksum, checkval);
return -EINVAL;
}

@@ -485,7 +490,7 @@ static int amdgpu_virt_read_pf2vf_data(struct amdgpu_device 
*adev)
((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->uuid;
break;
default:
-   DRM_ERROR("invalid pf2vf version\n");
+   dev_err(adev->dev, "invalid pf2vf version: 0x%x\n",
+pf2vf_info->version);
   

RE: [PATCH 3/3] drm/amdgpu: make reset method configurable for RAS poison

[Zhang, Hawking]

[AMD Official Use Only - General]

That's fine. It can be in another set of patches. But we should remove the 
incorrect implementation which is copied from previous version. So people will 
not apply changes to an incorrect base.

Regards,
Hawking

-Original Message-
From: Zhou1, Tao 
Sent: Monday, March 18, 2024 11:11
To: Zhang, Hawking ; amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH 3/3] drm/amdgpu: make reset method configurable for RAS 
poison

[AMD Official Use Only - General]

I can remove the support for SOC15_IH_CLIENTID_VMC from v10, but the reset type 
should be changed from bool to uint32 for all versions.

Regards,
Tao

> -Original Message-
> From: Zhang, Hawking 
> Sent: Sunday, March 17, 2024 6:10 PM
> To: Zhou1, Tao ; amd-gfx@lists.freedesktop.org
> Cc: Zhou1, Tao 
> Subject: RE: [PATCH 3/3] drm/amdgpu: make reset method configurable
> for RAS poison
>
> [AMD Official Use Only - General]
>
> Let's not copy kfd interrupt handler and the work queue implementation
> from v9 to v10 since the firmware/hardware design are totally different.
>
> We shall have another patch to fix kfd int v10 for poison consumption
> handling and also v11.
>
> Regards,
> Hawking
>
> -Original Message-
> From: amd-gfx  On Behalf Of Tao
> Zhou
> Sent: Wednesday, March 13, 2024 17:12
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhou1, Tao 
> Subject: [PATCH 3/3] drm/amdgpu: make reset method configurable for
> RAS poison
>
> Each RAS block has different requirement for gpu reset in poison
> consumption handling.
> Add support for mmhub RAS poison consumption handling.
>
> Signed-off-by: Tao Zhou 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c|  2 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h|  2 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c   |  4 ++--
>  drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c   | 14 ++---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h   |  4 ++--
>  .../gpu/drm/amd/amdkfd/kfd_int_process_v10.c  | 20 ++-
>  .../gpu/drm/amd/amdkfd/kfd_int_process_v9.c   | 20 ++-
>  7 files changed, 42 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> index 9687650b0fe3..262d20167039 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> @@ -760,7 +760,7 @@ bool amdgpu_amdkfd_is_fed(struct amdgpu_device
> *adev)  }
>
>  void amdgpu_amdkfd_ras_poison_consumption_handler(struct
> amdgpu_device *adev,
> -   enum amdgpu_ras_block block, bool reset)
> +   enum amdgpu_ras_block block, uint32_t reset)
>  {
> amdgpu_umc_poison_handler(adev, block, reset);  } diff --git
> a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> index 03bf20e0e3da..ad50c7bbc326 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> @@ -400,7 +400,7 @@ void amdgpu_amdkfd_debug_mem_fence(struct
> amdgpu_device *adev);  int amdgpu_amdkfd_get_tile_config(struct
> amdgpu_device *adev,
> struct tile_config *config);  void
> amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device
> *adev,
> -   enum amdgpu_ras_block block, bool reset);
> +   enum amdgpu_ras_block block, uint32_t reset);
>  bool amdgpu_amdkfd_is_fed(struct amdgpu_device *adev);  bool
> amdgpu_amdkfd_bo_mapped_to_dev(struct amdgpu_device *adev, struct
> kgd_mem *mem);  void amdgpu_amdkfd_block_mmu_notifications(void *p);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> index e32a186c2de1..58fe7bebdf1b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> @@ -2045,7 +2045,7 @@ static void
> amdgpu_ras_interrupt_poison_consumption_handler(struct ras_manager *
> }
> }
>
> -   amdgpu_umc_poison_handler(adev, obj->head.block, false);
> +   amdgpu_umc_poison_handler(adev, obj->head.block, 0);
>
> if (block_obj->hw_ops && block_obj->hw_ops->handle_poison_consumption)
> poison_stat =
> block_obj->hw_ops->handle_poison_consumption(adev);
> @@ -2698,7 +2698,7 @@ static int
> amdgpu_ras_page_retirement_thread(void
> *param)
> atomic_dec(>page_retirement_req_cnt);
>
> amdgpu_umc_bad_page_polling_timeout(adev,
> -   false, MAX_UMC_POISON_POLLING_TIME_ASYNC);
> +   0, MAX_UMC_POISON_POLLING_TIME_ASYNC);
> }
&g

RE: [PATCH] drm/amdgpu: add ras event id support for ACA

[Zhang, Hawking]

[AMD Official Use Only - General]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: Wang, Yang(Kevin) 
Sent: Monday, March 18, 2024 10:25
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Zhou1, Tao ; 
Wang, Yang(Kevin) 
Subject: [PATCH] drm/amdgpu: add ras event id support for ACA

add ras event id support for ACA.

Signed-off-by: Yang Wang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c | 29 ++---  
drivers/gpu/drm/amd/amdgpu/amdgpu_aca.h |  2 +-  
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 11 +-
 3 files changed, 23 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c
index 53ad76f590a1..ddcb68e60a73 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c
@@ -116,20 +116,22 @@ static struct aca_regs_dump {
{"CONTROL_MASK",ACA_REG_IDX_CTL_MASK},
 };

-static void aca_smu_bank_dump(struct amdgpu_device *adev, int idx, int total, 
struct aca_bank *bank)
+static void aca_smu_bank_dump(struct amdgpu_device *adev, int idx, int total, 
struct aca_bank *bank,
+ struct ras_query_context *qctx)
 {
+   u64 event_id = qctx ? qctx->event_id: 0ULL;
int i;

-   dev_info(adev->dev, HW_ERR "Accelerator Check Architecture events 
logged\n");
+   RAS_EVENT_LOG(adev, event_id, HW_ERR "Accelerator Check Architecture
+events logged\n");
/* plus 1 for output format, e.g: ACA[08/08]:  */
for (i = 0; i < ARRAY_SIZE(aca_regs); i++)
-   dev_info(adev->dev, HW_ERR "ACA[%02d/%02d].%s=0x%016llx\n",
-idx + 1, total, aca_regs[i].name, 
bank->regs[aca_regs[i].reg_idx]);
+   RAS_EVENT_LOG(adev, event_id, HW_ERR 
"ACA[%02d/%02d].%s=0x%016llx\n",
+ idx + 1, total, aca_regs[i].name,
+bank->regs[aca_regs[i].reg_idx]);
 }

 static int aca_smu_get_valid_aca_banks(struct amdgpu_device *adev, enum 
aca_smu_type type,
   int start, int count,
-  struct aca_banks *banks)
+  struct aca_banks *banks, struct 
ras_query_context *qctx)
 {
struct amdgpu_aca *aca = >aca;
const struct aca_smu_funcs *smu_funcs = aca->smu_funcs; @@ -165,7 
+167,7 @@ static int aca_smu_get_valid_aca_banks(struct amdgpu_device *adev, 
enum aca_smu_

bank.type = type;

-   aca_smu_bank_dump(adev, i, count, );
+   aca_smu_bank_dump(adev, i, count, , qctx);

ret = aca_banks_add_bank(banks, );
if (ret)
@@ -390,7 +392,7 @@ static bool aca_bank_should_update(struct amdgpu_device 
*adev, enum aca_smu_type  }

 static int aca_banks_update(struct amdgpu_device *adev, enum aca_smu_type type,
-   bank_handler_t handler, void *data)
+   bank_handler_t handler, struct ras_query_context 
*qctx, void
+*data)
 {
struct amdgpu_aca *aca = >aca;
struct aca_banks banks;
@@ -412,7 +414,7 @@ static int aca_banks_update(struct amdgpu_device *adev, 
enum aca_smu_type type,

aca_banks_init();

-   ret = aca_smu_get_valid_aca_banks(adev, type, 0, count, );
+   ret = aca_smu_get_valid_aca_banks(adev, type, 0, count, , qctx);
if (ret)
goto err_release_banks;

@@ -489,7 +491,7 @@ static int aca_log_aca_error(struct aca_handle *handle, 
enum aca_error_type type  }

 static int __aca_get_error_data(struct amdgpu_device *adev, struct aca_handle 
*handle, enum aca_error_type type,
-   struct ras_err_data *err_data)
+   struct ras_err_data *err_data, struct 
ras_query_context *qctx)
 {
enum aca_smu_type smu_type;
int ret;
@@ -507,7 +509,7 @@ static int __aca_get_error_data(struct amdgpu_device *adev, 
struct aca_handle *h
}

/* udpate aca bank to aca source error_cache first */
-   ret = aca_banks_update(adev, smu_type, handler_aca_log_bank_error, 
NULL);
+   ret = aca_banks_update(adev, smu_type, handler_aca_log_bank_error,
+qctx, NULL);
if (ret)
return ret;

@@ -523,7 +525,7 @@ static bool aca_handle_is_valid(struct aca_handle *handle)  
}

 int amdgpu_aca_get_error_data(struct amdgpu_device *adev, struct aca_handle 
*handle,
- enum aca_error_type type, void *data)
+ enum aca_error_type type, void *data, void *qctx)
 {
struct ras_err_data *err_data = (struct ras_err_data *)data;

@@ -536,7 +538,8 @@ int amdgpu_aca_get_error_data(struct amdgpu_device *adev, 
struct aca_handle *han
if (!(BIT(type) & handle->mask))
return  0;

-   return __aca_get_error_data(adev, handl

RE: [PATCH] drm/amdgpu: skip call ras_late_init if ras is not enabled

[Zhang, Hawking]

[AMD Official Use Only - General]

Let's not rely on ras_enabled flags. It mixed with hw & sw ras caps. There is 
case that sw ras is disabled, but hardware is still ras capable.

The function actually relies on ras block list to decide if it does anything. 
If ras block is NULL, then it will be skipped by nature.

Let's revisit current implementation - basically it should walk through the ras 
block list before doing anything else.

Regards,
Hawking

-Original Message-
From: Wang, Yang(Kevin) 
Sent: Monday, March 18, 2024 08:55
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Zhou1, Tao ; 
Chai, Thomas ; Wang, Yang(Kevin) 
Subject: [PATCH] drm/amdgpu: skip call ras_late_init if ras is not enabled

skip call ras_late_init if ras is not enabled.

Signed-off-by: Yang Wang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 7d4a1bc30277..4ea35648fdfe 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -3391,10 +3391,14 @@ void amdgpu_ras_suspend(struct amdgpu_device *adev)

 int amdgpu_ras_late_init(struct amdgpu_device *adev)  {
+   struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
struct amdgpu_ras_block_list *node, *tmp;
struct amdgpu_ras_block_object *obj;
int r;

+   if (!adev->ras_enabled || !con)
+   return 0;
+
/* Guest side doesn't need init ras feature */
if (amdgpu_sriov_vf(adev))
return 0;
--
2.34.1

RE: [PATCH 3/3] drm/amdgpu: make reset method configurable for RAS poison

[Zhang, Hawking]

[AMD Official Use Only - General]

Let's not copy kfd interrupt handler and the work queue implementation from v9 
to v10 since the firmware/hardware design are totally different.

We shall have another patch to fix kfd int v10 for poison consumption handling 
and also v11.

Regards,
Hawking

-Original Message-
From: amd-gfx  On Behalf Of Tao Zhou
Sent: Wednesday, March 13, 2024 17:12
To: amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao 
Subject: [PATCH 3/3] drm/amdgpu: make reset method configurable for RAS poison

Each RAS block has different requirement for gpu reset in poison consumption 
handling.
Add support for mmhub RAS poison consumption handling.

Signed-off-by: Tao Zhou 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c|  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h|  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c   |  4 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c   | 14 ++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h   |  4 ++--
 .../gpu/drm/amd/amdkfd/kfd_int_process_v10.c  | 20 ++-
 .../gpu/drm/amd/amdkfd/kfd_int_process_v9.c   | 20 ++-
 7 files changed, 42 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index 9687650b0fe3..262d20167039 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -760,7 +760,7 @@ bool amdgpu_amdkfd_is_fed(struct amdgpu_device *adev)  }

 void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev,
-   enum amdgpu_ras_block block, bool reset)
+   enum amdgpu_ras_block block, uint32_t reset)
 {
amdgpu_umc_poison_handler(adev, block, reset);  } diff --git 
a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index 03bf20e0e3da..ad50c7bbc326 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -400,7 +400,7 @@ void amdgpu_amdkfd_debug_mem_fence(struct amdgpu_device 
*adev);  int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev,
struct tile_config *config);
 void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev,
-   enum amdgpu_ras_block block, bool reset);
+   enum amdgpu_ras_block block, uint32_t reset);
 bool amdgpu_amdkfd_is_fed(struct amdgpu_device *adev);  bool 
amdgpu_amdkfd_bo_mapped_to_dev(struct amdgpu_device *adev, struct kgd_mem 
*mem);  void amdgpu_amdkfd_block_mmu_notifications(void *p); diff --git 
a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index e32a186c2de1..58fe7bebdf1b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -2045,7 +2045,7 @@ static void 
amdgpu_ras_interrupt_poison_consumption_handler(struct ras_manager *
}
}

-   amdgpu_umc_poison_handler(adev, obj->head.block, false);
+   amdgpu_umc_poison_handler(adev, obj->head.block, 0);

if (block_obj->hw_ops && block_obj->hw_ops->handle_poison_consumption)
poison_stat = 
block_obj->hw_ops->handle_poison_consumption(adev);
@@ -2698,7 +2698,7 @@ static int amdgpu_ras_page_retirement_thread(void *param)
atomic_dec(>page_retirement_req_cnt);

amdgpu_umc_bad_page_polling_timeout(adev,
-   false, MAX_UMC_POISON_POLLING_TIME_ASYNC);
+   0, MAX_UMC_POISON_POLLING_TIME_ASYNC);
}

return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
index 20436f81856a..2c02585dcbff 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
@@ -186,9 +186,7 @@ static int amdgpu_umc_do_page_retirement(struct 
amdgpu_device *adev,
amdgpu_umc_handle_bad_pages(adev, ras_error_status);

if (err_data->ue_count && reset) {
-   /* use mode-2 reset for poison consumption */
-   if (!entry)
-   con->gpu_reset_flags |= 
AMDGPU_RAS_GPU_RESET_MODE2_RESET;
+   con->gpu_reset_flags |= reset;
amdgpu_ras_reset_gpu(adev);
}

@@ -196,7 +194,7 @@ static int amdgpu_umc_do_page_retirement(struct 
amdgpu_device *adev,  }

 int amdgpu_umc_bad_page_polling_timeout(struct amdgpu_device *adev,
-   bool reset, uint32_t timeout_ms)
+   uint32_t reset, uint32_t timeout_ms)
 {
struct ras_err_data err_data;
struct ras_common_if head = {
@@ -238,8 +236,7 @@ int amdgpu_umc_bad_page_polling_timeout(struct 
amdgpu_device *adev,
if (reset) {
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);

-   /* use mode-2 reset for poison consumption */
-   con->gpu_reset_flags |= 

RE: [PATCH 1/1] drm/amdgpu: drop setting buffer funcs in sdma442

[Zhang, Hawking]

[AMD Official Use Only - General]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: Ma, Le 
Sent: Friday, March 15, 2024 17:16
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Song, Asher ; 
Deucher, Alexander ; Ma, Le 
Subject: [PATCH 1/1] drm/amdgpu: drop setting buffer funcs in sdma442

To fix the entity rq NULL issue. This setting has been moved to upper level.

Fixes b70438004a14 ("drm/amdgpu: move buffer funcs setting up a level")

Signed-off-by: Le Ma 
---
 drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 20 +---
 1 file changed, 1 insertion(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
index eaa4f5f49949..589a734982a7 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
@@ -431,16 +431,11 @@ static void sdma_v4_4_2_inst_gfx_stop(struct 
amdgpu_device *adev,
struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES];
u32 doorbell_offset, doorbell;
u32 rb_cntl, ib_cntl;
-   int i, unset = 0;
+   int i;

for_each_inst(i, inst_mask) {
sdma[i] = >sdma.instance[i].ring;

-   if ((adev->mman.buffer_funcs_ring == sdma[i]) && unset != 1) {
-   amdgpu_ttm_set_buffer_funcs_status(adev, false);
-   unset = 1;
-   }
-
rb_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_CNTL);
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 
0);
WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl); @@ -490,17 
+485,10 @@ static void sdma_v4_4_2_inst_page_stop(struct amdgpu_device *adev,
struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES];
u32 rb_cntl, ib_cntl;
int i;
-   bool unset = false;

for_each_inst(i, inst_mask) {
sdma[i] = >sdma.instance[i].page;

-   if ((adev->mman.buffer_funcs_ring == sdma[i]) &&
-   (!unset)) {
-   amdgpu_ttm_set_buffer_funcs_status(adev, false);
-   unset = true;
-   }
-
rb_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_CNTL);
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL,
RB_ENABLE, 0);
@@ -950,13 +938,7 @@ static int sdma_v4_4_2_inst_start(struct amdgpu_device 
*adev,
r = amdgpu_ring_test_helper(page);
if (r)
return r;
-
-   if (adev->mman.buffer_funcs_ring == page)
-   amdgpu_ttm_set_buffer_funcs_status(adev, true);
}
-
-   if (adev->mman.buffer_funcs_ring == ring)
-   amdgpu_ttm_set_buffer_funcs_status(adev, true);
}

return r;
--
2.43.2

RE: [PATCH] drm/amdgpu: Bypass display ta if display hw is not available

[Zhang, Hawking]

[AMD Official Use Only - General]

Thanks Alex!

Regards,
Hawking

-Original Message-
From: Alex Deucher 
Sent: Thursday, March 14, 2024 21:23
To: Zhang, Hawking 
Cc: amd-gfx@lists.freedesktop.org; Pillai, Aurabindo 
; Feng, Kenneth ; Deucher, 
Alexander ; Wang, Yang(Kevin) 

Subject: Re: [PATCH] drm/amdgpu: Bypass display ta if display hw is not 
available

On Thu, Mar 14, 2024 at 9:18 AM Hawking Zhang  wrote:
>
> Do not load/invoke display TA if display hardware is not available
>
> Signed-off-by: Hawking Zhang 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 18 ++
>  1 file changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> index 867397fe2e9d..e7d7fd2cc31d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> @@ -1830,6 +1830,10 @@ static int psp_hdcp_initialize(struct psp_context *psp)
> if (amdgpu_sriov_vf(psp->adev))
> return 0;
>
> +   /* bypass hdcp initialization if dmu is harvested */
> +   if (!amdgpu_device_has_display_hardware(psp->adev))
> +   return 0;
> +
> if (!psp->hdcp_context.context.bin_desc.size_bytes ||
> !psp->hdcp_context.context.bin_desc.start_addr) {
> dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode
> is not available\n"); @@ -1862,6 +1866,9 @@ int psp_hdcp_invoke(struct 
> psp_context *psp, uint32_t ta_cmd_id)
> if (amdgpu_sriov_vf(psp->adev))
> return 0;
>
> +   if (!psp->hdcp_context.context.initialized)
> +   return 0;
> +
> return psp_ta_invoke(psp, ta_cmd_id,
> >hdcp_context.context);  }
>
> @@ -1897,6 +1904,10 @@ static int psp_dtm_initialize(struct psp_context *psp)
> if (amdgpu_sriov_vf(psp->adev))
> return 0;
>
> +   /* bypass dtm initialization if dmu is harvested */
> +   if (!amdgpu_device_has_display_hardware(psp->adev))
> +   return 0;
> +
> if (!psp->dtm_context.context.bin_desc.size_bytes ||
> !psp->dtm_context.context.bin_desc.start_addr) {
> dev_info(psp->adev->dev, "DTM: optional dtm ta ucode
> is not available\n"); @@ -1929,6 +1940,9 @@ int psp_dtm_invoke(struct 
> psp_context *psp, uint32_t ta_cmd_id)
> if (amdgpu_sriov_vf(psp->adev))
> return 0;
>
> +   if (!psp->dtm_context.context.initialized)
> +   return 0;
> +
> return psp_ta_invoke(psp, ta_cmd_id,
> >dtm_context.context);  }
>
> @@ -2063,6 +2077,10 @@ static int psp_securedisplay_initialize(struct 
> psp_context *psp)
> if (amdgpu_sriov_vf(psp->adev))
> return 0;
>
> +   /* bypass securedisplay initialization if dmu is harvested */
> +   if (!amdgpu_device_has_display_hardware(psp->adev))
> +return 0;
> +
> if (!psp->securedisplay_context.context.bin_desc.size_bytes ||
> !psp->securedisplay_context.context.bin_desc.start_addr) {
> dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay
> ta ucode is not available\n");
> --
> 2.17.1
>

RE: [PATCH] drm/amdgpu: Bypass display ta if it is harvested

[Zhang, Hawking]

[AMD Official Use Only - General]


Hi Alex,

Please check my comments inline. Please also check v2 where I switch to an 
existing helper to check is display hardware is available.

Regards,
Hawking

-Original Message-
From: Alex Deucher 
Sent: Thursday, March 14, 2024 21:17
To: Zhang, Hawking 
Cc: amd-gfx@lists.freedesktop.org; Pillai, Aurabindo 
; Feng, Kenneth 
Subject: Re: [PATCH] drm/amdgpu: Bypass display ta if it is harvested

On Thu, Mar 14, 2024 at 6:47 AM Hawking Zhang 
mailto:hawking.zh...@amd.com>> wrote:
>
> Display TA doesn't need to be loaded/invoked if it is harvested.
>
> Signed-off-by: Hawking Zhang 
> mailto:hawking.zh...@amd.com>>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 18 ++
>  1 file changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> index 867397fe2e9d..bb4988c45ca9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> @@ -1830,6 +1830,10 @@ static int psp_hdcp_initialize(struct psp_context *psp)
> if (amdgpu_sriov_vf(psp->adev))
> return 0;
>
> +   /* bypass hdcp initialization if dmu is harvested */
> +   if (psp->adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK)
> +   return 0;
> +
> if (!psp->hdcp_context.context.bin_desc.size_bytes ||
> !psp->hdcp_context.context.bin_desc.start_addr) {
> dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode
> is not available\n"); @@ -1862,6 +1866,9 @@ int psp_hdcp_invoke(struct 
> psp_context *psp, uint32_t ta_cmd_id)
> if (amdgpu_sriov_vf(psp->adev))
> return 0;
>
> +   if (!psp->hdcp_context.context.initialized)
> +   return 0;
> +
> return psp_ta_invoke(psp, ta_cmd_id,
> >hdcp_context.context);  }
>
> @@ -1897,6 +1904,10 @@ static int psp_dtm_initialize(struct psp_context *psp)
> if (amdgpu_sriov_vf(psp->adev))
> return 0;
>
> +   /* bypass dtm initialization if dmu is harvested */
> +   if (psp->adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK)
> +   return 0;

I think there may be some SKUs where the display blocks are not harvested, but 
they are not used so the atombios tables are empty.
This gets fixed up in dm_early_init() so the harvest flag should be set by the 
end of early_init.  That should come before this code gets called so I think we 
should be fine.

[Hawking]: Yes. it comes before psp_hw_init. so we know display hardware is not 
available before loading psp firmware

> +
> if (!psp->dtm_context.context.bin_desc.size_bytes ||
> !psp->dtm_context.context.bin_desc.start_addr) {
> dev_info(psp->adev->dev, "DTM: optional dtm ta ucode
> is not available\n"); @@ -1929,6 +1940,9 @@ int psp_dtm_invoke(struct 
> psp_context *psp, uint32_t ta_cmd_id)
> if (amdgpu_sriov_vf(psp->adev))
> return 0;
>
> +   if (!psp->dtm_context.context.initialized)
> +   return 0;

Doesn't the dtm_initialize function need a harvest check?

[Hawking]: yes, the same check is applied for dtm
+   /* bypass dtm initialization if dmu is harvested */
+   if (psp->adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK)
+   return 0;
+


> +
> return psp_ta_invoke(psp, ta_cmd_id,
> >dtm_context.context);  }
>
> @@ -2063,6 +2077,10 @@ static int psp_securedisplay_initialize(struct 
> psp_context *psp)
> if (amdgpu_sriov_vf(psp->adev))
> return 0;
>
> +   /* bypass securedisplay initialization if dmu is harvested */
> +   if (psp->adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK)
> +return 0;

Don't we need to check if the context is initialized in 
psp_securedisplay_invoke()?

[Hawking]: The check is already in psp_securedisplay_invoke.

> +
> if (!psp->securedisplay_context.context.bin_desc.size_bytes ||
> !psp->securedisplay_context.context.bin_desc.start_addr) {
> dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay
> ta ucode is not available\n");
> --
> 2.17.1
>

RE: [PATCH] drm/amdgpu: Bypass display ta if it is harvested

[Zhang, Hawking]

[AMD Official Use Only - General]

Never mind. There is helper function to check if display hardware is available. 
I will move to the helper in v2. Thanks @Wang, 
Yang(Kevin)<mailto:kevinyang.w...@amd.com> for his reminder.

Regards,
Hawking

From: amd-gfx  On Behalf Of Zhang, 
Hawking
Sent: Thursday, March 14, 2024 18:45
To: amd-gfx@lists.freedesktop.org; Pillai, Aurabindo 
; Feng, Kenneth ; Deucher, 
Alexander 
Subject: RE: [PATCH] drm/amdgpu: Bypass display ta if it is harvested


[AMD Official Use Only - General]

[AMD Official Use Only - General]

Copy @Deucher, Alexander<mailto:alexander.deuc...@amd.com> for the awareness.

Regards,
Hawking

-Original Message-
From: Zhang, Hawking mailto:hawking.zh...@amd.com>>
Sent: Thursday, March 14, 2024 18:36
To: amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org>; 
Pillai, Aurabindo mailto:aurabindo.pil...@amd.com>>; 
Feng, Kenneth mailto:kenneth.f...@amd.com>>
Cc: Zhang, Hawking mailto:hawking.zh...@amd.com>>
Subject: [PATCH] drm/amdgpu: Bypass display ta if it is harvested

Display TA doesn't need to be loaded/invoked if it is harvested.

Signed-off-by: Hawking Zhang 
mailto:hawking.zh...@amd.com>>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 18 ++
1 file changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 867397fe2e9d..bb4988c45ca9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -1830,6 +1830,10 @@ static int psp_hdcp_initialize(struct psp_context *psp)
 if (amdgpu_sriov_vf(psp->adev))
 return 0;

+   /* bypass hdcp initialization if dmu is harvested */
+   if (psp->adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK)
+   return 0;
+
 if (!psp->hdcp_context.context.bin_desc.size_bytes ||
 !psp->hdcp_context.context.bin_desc.start_addr) {
 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not 
available\n"); @@ -1862,6 +1866,9 @@ int psp_hdcp_invoke(struct psp_context 
*psp, uint32_t ta_cmd_id)
 if (amdgpu_sriov_vf(psp->adev))
 return 0;

+   if (!psp->hdcp_context.context.initialized)
+   return 0;
+
 return psp_ta_invoke(psp, ta_cmd_id, >hdcp_context.context);  }

@@ -1897,6 +1904,10 @@ static int psp_dtm_initialize(struct psp_context *psp)
 if (amdgpu_sriov_vf(psp->adev))
 return 0;

+   /* bypass dtm initialization if dmu is harvested */
+   if (psp->adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK)
+   return 0;
+
 if (!psp->dtm_context.context.bin_desc.size_bytes ||
 !psp->dtm_context.context.bin_desc.start_addr) {
 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not 
available\n"); @@ -1929,6 +1940,9 @@ int psp_dtm_invoke(struct psp_context 
*psp, uint32_t ta_cmd_id)
 if (amdgpu_sriov_vf(psp->adev))
 return 0;

+   if (!psp->dtm_context.context.initialized)
+   return 0;
+
 return psp_ta_invoke(psp, ta_cmd_id, >dtm_context.context);  }

@@ -2063,6 +2077,10 @@ static int psp_securedisplay_initialize(struct 
psp_context *psp)
 if (amdgpu_sriov_vf(psp->adev))
 return 0;

+   /* bypass securedisplay initialization if dmu is harvested */
+   if (psp->adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK)
+return 0;
+
 if (!psp->securedisplay_context.context.bin_desc.size_bytes ||
 !psp->securedisplay_context.context.bin_desc.start_addr) {
 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta 
ucode is not available\n");
--
2.17.1

RE: [PATCH] drm/amdgpu: Bypass display ta if it is harvested

[Zhang, Hawking]

[AMD Official Use Only - General]


Copy @Deucher, Alexander<mailto:alexander.deuc...@amd.com> for the awareness.

Regards,
Hawking

-Original Message-
From: Zhang, Hawking 
Sent: Thursday, March 14, 2024 18:36
To: amd-gfx@lists.freedesktop.org; Pillai, Aurabindo 
; Feng, Kenneth 
Cc: Zhang, Hawking 
Subject: [PATCH] drm/amdgpu: Bypass display ta if it is harvested

Display TA doesn't need to be loaded/invoked if it is harvested.

Signed-off-by: Hawking Zhang 
mailto:hawking.zh...@amd.com>>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 867397fe2e9d..bb4988c45ca9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -1830,6 +1830,10 @@ static int psp_hdcp_initialize(struct psp_context *psp)
if (amdgpu_sriov_vf(psp->adev))
return 0;

+   /* bypass hdcp initialization if dmu is harvested */
+   if (psp->adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK)
+   return 0;
+
if (!psp->hdcp_context.context.bin_desc.size_bytes ||
!psp->hdcp_context.context.bin_desc.start_addr) {
dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not 
available\n"); @@ -1862,6 +1866,9 @@ int psp_hdcp_invoke(struct psp_context 
*psp, uint32_t ta_cmd_id)
if (amdgpu_sriov_vf(psp->adev))
return 0;

+   if (!psp->hdcp_context.context.initialized)
+   return 0;
+
return psp_ta_invoke(psp, ta_cmd_id, >hdcp_context.context);  }

@@ -1897,6 +1904,10 @@ static int psp_dtm_initialize(struct psp_context *psp)
if (amdgpu_sriov_vf(psp->adev))
return 0;

+   /* bypass dtm initialization if dmu is harvested */
+   if (psp->adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK)
+   return 0;
+
if (!psp->dtm_context.context.bin_desc.size_bytes ||
!psp->dtm_context.context.bin_desc.start_addr) {
dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not 
available\n"); @@ -1929,6 +1940,9 @@ int psp_dtm_invoke(struct psp_context 
*psp, uint32_t ta_cmd_id)
if (amdgpu_sriov_vf(psp->adev))
return 0;

+   if (!psp->dtm_context.context.initialized)
+   return 0;
+
return psp_ta_invoke(psp, ta_cmd_id, >dtm_context.context);  }

@@ -2063,6 +2077,10 @@ static int psp_securedisplay_initialize(struct 
psp_context *psp)
if (amdgpu_sriov_vf(psp->adev))
return 0;

+   /* bypass securedisplay initialization if dmu is harvested */
+   if (psp->adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK)
+return 0;
+
if (!psp->securedisplay_context.context.bin_desc.size_bytes ||
!psp->securedisplay_context.context.bin_desc.start_addr) {
dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode 
is not available\n");
--
2.17.1

RE: [PATCH 1/5] drm/amdgpu: add new bit definitions for GC 9.0 PROTECTION_FAULT_STATUS

[Zhang, Hawking]

[AMD Official Use Only - General]

Series is

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: amd-gfx  On Behalf Of Zhou1, Tao
Sent: Monday, March 11, 2024 10:45
To: amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH 1/5] drm/amdgpu: add new bit definitions for GC 9.0 
PROTECTION_FAULT_STATUS

[AMD Official Use Only - General]

[AMD Official Use Only - General]

Ping for the series...

> -Original Message-
> From: Zhou1, Tao 
> Sent: Friday, February 23, 2024 4:24 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhou1, Tao 
> Subject: [PATCH 1/5] drm/amdgpu: add new bit definitions for GC 9.0
> PROTECTION_FAULT_STATUS
>
> Add UCE and FED bit definitions.
>
> Signed-off-by: Tao Zhou 
> ---
>  drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h | 4 
>  1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h
> b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h
> index efc16ddf274a..2dfa0e5b1aa3 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h
> @@ -6822,6 +6822,8 @@
>  #define VM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT
> 0x14
>  #define VM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT
> 0x18
>  #define VM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT
> 0x19
> +#define VM_L2_PROTECTION_FAULT_STATUS__UCE__SHIFT
> 0x1d
> +#define VM_L2_PROTECTION_FAULT_STATUS__FED__SHIFT
> 0x1e
>  #define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK
> 0x0001L
>  #define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK
> 0x000EL
>  #define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK
> 0x00F0L
> @@ -6832,6 +6834,8 @@
>  #define VM_L2_PROTECTION_FAULT_STATUS__VMID_MASK
> 0x00F0L
>  #define VM_L2_PROTECTION_FAULT_STATUS__VF_MASK
> 0x0100L
>  #define VM_L2_PROTECTION_FAULT_STATUS__VFID_MASK
> 0x1E00L
> +#define VM_L2_PROTECTION_FAULT_STATUS__UCE_MASK
> 0x2000L
> +#define VM_L2_PROTECTION_FAULT_STATUS__FED_MASK
> 0x4000L
>  //VM_L2_PROTECTION_FAULT_ADDR_LO32
>  #define
> VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIF
> T   0x0
>  #define
> VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK
> 0xL
> --
> 2.34.1

Re: [PATCH] drm/amdgpu: add deferred error check for UMC v12 address query

[Zhang, Hawking]

[AMD Official Use Only - General]

Reviewed-by: Hawking Zhang 

Regards,
Hawking

Get Outlook for iOS

From: amd-gfx  on behalf of Tao Zhou 

Sent: Thursday, February 29, 2024 11:45:47 AM
To: amd-gfx@lists.freedesktop.org 
Cc: Zhou1, Tao 
Subject: [PATCH] drm/amdgpu: add deferred error check for UMC v12 address query

Both RAS UE and deferred errors need page retirement.

Signed-off-by: Tao Zhou 
---
 drivers/gpu/drm/amd/amdgpu/umc_v12_0.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c 
b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
index 14ef7a24be7b..77af4e25ff46 100644
--- a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
@@ -348,7 +348,8 @@ static int umc_v12_0_query_error_address(struct 
amdgpu_device *adev,
 }

 /* calculate error address if ue error is detected */
-   if (umc_v12_0_is_uncorrectable_error(adev, mc_umc_status)) {
+   if (umc_v12_0_is_uncorrectable_error(adev, mc_umc_status) ||
+   umc_v12_0_is_deferred_error(adev, mc_umc_status)) {
 mc_umc_addrt0 =
 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_ADDRT0);

--
2.34.1

RE: [PATCH 3/3] drm/amdgpu: Remove pcie bw sys entry

[Zhang, Hawking]

[AMD Official Use Only - General]

Series is

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: Kamal, Asad 
Sent: Friday, February 16, 2024 20:59
To: amd-gfx@lists.freedesktop.org
Cc: Lazar, Lijo ; Zhang, Hawking ; 
Ma, Le ; Zhang, Morris ; Kamal, Asad 

Subject: [PATCH 3/3] drm/amdgpu: Remove pcie bw sys entry

Remove pcie bw sys entry for asics not supporting such function

Signed-off-by: Asad Kamal 
Reviewed-by: Lijo Lazar 
---
 drivers/gpu/drm/amd/amdgpu/soc15.c | 1 -  drivers/gpu/drm/amd/pm/amdgpu_pm.c | 
3 ++-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 7fc55e3262eb..20a4582885cc 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -895,7 +895,6 @@ static const struct amdgpu_asic_funcs 
aqua_vanjaram_asic_funcs =
.get_config_memsize = _get_config_memsize,
.need_full_reset = _need_full_reset,
.init_doorbell_index = _vanjaram_doorbell_index_init,
-   .get_pcie_usage = _get_pcie_usage,
.need_reset_on_init = _need_reset_on_init,
.get_pcie_replay_count = _nbio_get_pcie_replay_count,
.supports_baco = _supports_baco, diff --git 
a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 087d57850304..1ff7fc821871 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -2174,7 +2174,8 @@ static int default_attr_update(struct amdgpu_device 
*adev, struct amdgpu_device_
*states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(pcie_bw)) {
/* PCIe Perf counters won't work on APU nodes */
-   if (adev->flags & AMD_IS_APU)
+   if (adev->flags & AMD_IS_APU ||
+   !adev->asic_funcs->get_pcie_usage)
*states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(unique_id)) {
switch (gc_ver) {
--
2.42.0

RE: [PATCH] drm/amdgpu/psp: update define to better align with its meaning

[Zhang, Hawking]

[AMD Official Use Only - General]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: amd-gfx  On Behalf Of Alex Deucher
Sent: Friday, February 9, 2024 05:15
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander 
Subject: [PATCH] drm/amdgpu/psp: update define to better align with its meaning

MEM_TRAINING_ENCROACHED_SIZE is for BIST training data.  It's not memory type 
specific.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 2 +-  
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c  | 2 +-  
drivers/gpu/drm/amd/amdgpu/psp_v13_0.c  | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index 9951bdd022de..47ffaa796264 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -203,7 +203,7 @@ struct psp_ras_context {
 #define GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES  0x1000
 #define GDDR6_MEM_TRAINING_OFFSET  0x8000
 /*Define the VRAM size that will be encroached by BIST training.*/
-#define GDDR6_MEM_TRAINING_ENCROACHED_SIZE 0x200
+#define BIST_MEM_TRAINING_ENCROACHED_SIZE  0x200

 enum psp_memory_training_init_flag {
PSP_MEM_TRAIN_NOT_SUPPORT   = 0x0,
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 
b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index efa37e3b7931..2395f1856962 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -506,7 +506,7 @@ static int psp_v11_0_memory_training(struct psp_context 
*psp, uint32_t ops)
 * before training, and restore it after training to avoid
 * VRAM corruption.
 */
-   sz = GDDR6_MEM_TRAINING_ENCROACHED_SIZE;
+   sz = BIST_MEM_TRAINING_ENCROACHED_SIZE;

if (adev->gmc.visible_vram_size < sz || 
!adev->mman.aper_base_kaddr) {
DRM_ERROR("visible_vram_size %llx or aper_base_kaddr %p 
is not initialized.\n", diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c 
b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
index 722b6066ce07..0e4329640ecb 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
@@ -561,7 +561,7 @@ static int psp_v13_0_memory_training(struct psp_context 
*psp, uint32_t ops)
 * before training, and restore it after training to avoid
 * VRAM corruption.
 */
-   sz = GDDR6_MEM_TRAINING_ENCROACHED_SIZE;
+   sz = BIST_MEM_TRAINING_ENCROACHED_SIZE;

if (adev->gmc.visible_vram_size < sz || 
!adev->mman.aper_base_kaddr) {
dev_err(adev->dev, "visible_vram_size %llx or 
aper_base_kaddr %p is not initialized.\n",
--
2.42.0

RE: [PATCH v2 1/2] drm/amdgpu: implement smu send rma reason for smu v13.0.6

[Zhang, Hawking]

[AMD Official Use Only - General]

With a nitpick below, the series is

Reviewed-by: Hawking Zhang 

+   MSG_MAP(BadPageThreshold,
PPSMC_MSG_RmaDueToBadPageThreshold,0),

Might be better name it to RmaDueToBadPageThreshold/SMU_MSG_ 
RmaDueToBadPageThreshold

Regards,
Hawking

-Original Message-
From: Wang, Yang(Kevin) 
Sent: Wednesday, February 7, 2024 21:54
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Zhou1, Tao ; 
Lazar, Lijo ; Wang, Yang(Kevin) 
Subject: [PATCH v2 1/2] drm/amdgpu: implement smu send rma reason for smu 
v13.0.6

implement smu send rma reason function for smu v13.0.6

Signed-off-by: Yang Wang 
Reviewed-by: Tao Zhou 
---
 drivers/gpu/drm/amd/pm/amdgpu_dpm.c   | 15 ++
 drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h   |  1 +
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 10 ++
 drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h |  6 ++  
.../pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h  |  3 ++-  
drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h  |  3 ++-  
.../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c  | 20 +++
 7 files changed, 56 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c 
b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
index 6627ee07d52d..f84bfed50681 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
@@ -693,6 +693,21 @@ int amdgpu_dpm_send_hbm_bad_channel_flag(struct 
amdgpu_device *adev, uint32_t si
return ret;
 }

+int amdgpu_dpm_send_rma_reason(struct amdgpu_device *adev) {
+   struct smu_context *smu = adev->powerplay.pp_handle;
+   int ret;
+
+   if (!is_support_sw_smu(adev))
+   return -EOPNOTSUPP;
+
+   mutex_lock(>pm.mutex);
+   ret = smu_send_rma_reason(smu);
+   mutex_unlock(>pm.mutex);
+
+   return ret;
+}
+
 int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev,
  enum pp_clock_type type,
  uint32_t *min,
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h 
b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
index 3047ffe7f244..621200e0823f 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
@@ -450,6 +450,7 @@ int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, 
uint32_t *smu_versio  int amdgpu_dpm_handle_passthrough_sbr(struct 
amdgpu_device *adev, bool enable);  int 
amdgpu_dpm_send_hbm_bad_pages_num(struct amdgpu_device *adev, uint32_t size);  
int amdgpu_dpm_send_hbm_bad_channel_flag(struct amdgpu_device *adev, uint32_t 
size);
+int amdgpu_dpm_send_rma_reason(struct amdgpu_device *adev);
 int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev,
   enum pp_clock_type type,
   uint32_t *min,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c 
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 0ad947df777a..138dcb8724b6 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -3669,3 +3669,13 @@ int smu_send_hbm_bad_channel_flag(struct smu_context 
*smu, uint32_t size)

return ret;
 }
+
+int smu_send_rma_reason(struct smu_context *smu) {
+   int ret = 0;
+
+   if (smu->ppt_funcs && smu->ppt_funcs->send_rma_reason)
+   ret = smu->ppt_funcs->send_rma_reason(smu);
+
+   return ret;
+}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
index 66e84defd0b6..a870bdd49a4e 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
@@ -1341,6 +1341,11 @@ struct pptable_funcs {
 */
int (*send_hbm_bad_pages_num)(struct smu_context *smu, uint32_t size);

+   /**
+* @send_rma_reason: message rma reason event to SMU.
+*/
+   int (*send_rma_reason)(struct smu_context *smu);
+
/**
 * @get_ecc_table:  message SMU to get ECC INFO table.
 */
@@ -1588,5 +1593,6 @@ int smu_stb_collect_info(struct smu_context *smu, void 
*buff, uint32_t size);  void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device 
*adev);  int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t 
size);  int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t 
size);
+int smu_send_rma_reason(struct smu_context *smu);
 #endif
 #endif
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h 
b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h
index 509e3cd483fb..86758051cb93 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h
@@ -91,7 +91,8 @@
 #define PPSMC_MSG_QueryValidMcaCeCount  0x3A
 #define PPSMC_MSG_McaBankCeDumpDW   0x3B
 #define PPSMC_MSG_SelectPLPDMode0

RE: [PATCH] drm/amdgpu: Fix HDP flush for VFs on nbio v7.9

[Zhang, Hawking]

[AMD Official Use Only - General]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: Lazar, Lijo 
Sent: Wednesday, February 7, 2024 10:22
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Deucher, Alexander 
; Ming, Davis ; Kamal, Asad 
; Ma, Le 
Subject: [PATCH] drm/amdgpu: Fix HDP flush for VFs on nbio v7.9

HDP flush remapping is not done for VFs. Keep the original offsets in VF 
environment.

Signed-off-by: Lijo Lazar 
---
 drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c 
b/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c
index e90f33780803..b4723d68eab0 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c
@@ -431,6 +431,12 @@ static void nbio_v7_9_init_registers(struct amdgpu_device 
*adev)
u32 inst_mask;
int i;

+   if (amdgpu_sriov_vf(adev))
+   adev->rmmio_remap.reg_offset =
+   SOC15_REG_OFFSET(
+   NBIO, 0,
+   
regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL)
+   << 2;
WREG32_SOC15(NBIO, 0, regXCC_DOORBELL_FENCE,
0xff & ~(adev->gfx.xcc_mask));

--
2.25.1

RE: [PATCH Review 1/1] drm/amdgpu: Fix shared buff copy to user

[Zhang, Hawking]

[AMD Official Use Only - General]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: amd-gfx  On Behalf Of Stanley.Yang
Sent: Monday, February 5, 2024 16:10
To: amd-gfx@lists.freedesktop.org
Cc: Yang, Stanley 
Subject: [PATCH Review 1/1] drm/amdgpu: Fix shared buff copy to user

ta if invoke node buffer
| ta type --|
|  ta id  --|
| cmd  id --|
|-- shared buf len -|
|-- shared buffer --|

ta if invoke node buffer is as above, copy shared buffer data to correct 
location

Signed-off-by: Stanley.Yang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c
index 468a67b302d4..ca5c86e5f7cd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c
@@ -362,7 +362,7 @@ static ssize_t ta_if_invoke_debugfs_write(struct file *fp, 
const char *buf, size
}
}

-   if (copy_to_user((char *)buf, context->mem_context.shared_buf, 
shared_buf_len))
+   if (copy_to_user((char *)[copy_pos], 
context->mem_context.shared_buf, shared_buf_len))
ret = -EFAULT;

 err_free_shared_buf:
--
2.25.1

RE: [PATCH] drm/amd/pm: Retrieve UMC ODECC error count from aca bank

[Zhang, Hawking]

[AMD Official Use Only - General]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: amd-gfx  On Behalf Of Candice Li
Sent: Friday, February 2, 2024 19:13
To: amd-gfx@lists.freedesktop.org
Cc: Li, Candice 
Subject: [PATCH] drm/amd/pm: Retrieve UMC ODECC error count from aca bank

Instead of software managed counters.

Signed-off-by: Candice Li 
---
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
index d6e14a5f406e63..03873d784be6d6 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
@@ -2552,8 +2552,12 @@ static int mca_umc_mca_get_err_count(const struct 
mca_ras_info *mca_ras, struct
 enum amdgpu_mca_error_type type, struct 
mca_bank_entry *entry, uint32_t *count)  {
uint64_t status0;
+   uint32_t ext_error_code;
+   uint32_t odecc_err_cnt;

status0 = entry->regs[MCA_REG_IDX_STATUS];
+   ext_error_code = MCA_REG__STATUS__ERRORCODEEXT(status0);
+   odecc_err_cnt =
+MCA_REG__MISC0__ERRCNT(entry->regs[MCA_REG_IDX_MISC0]);

if (!REG_GET_FIELD(status0, MCMP1_STATUST0, Val)) {
*count = 0;
@@ -2563,7 +2567,7 @@ static int mca_umc_mca_get_err_count(const struct 
mca_ras_info *mca_ras, struct
if (umc_v12_0_is_deferred_error(adev, status0) ||
umc_v12_0_is_uncorrectable_error(adev, status0) ||
umc_v12_0_is_correctable_error(adev, status0))
-   *count = 1;
+   *count = (ext_error_code == 0) ? odecc_err_cnt : 1;

return 0;
 }
--
2.25.1

RE: [PATCH] drm/amdgpu: Avoid fetching VRAM vendor info

[Zhang, Hawking]

[AMD Official Use Only - General]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: Lazar, Lijo 
Sent: Friday, February 2, 2024 23:36
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Deucher, Alexander 
; Kamal, Asad ; Ma, Le 

Subject: [PATCH] drm/amdgpu: Avoid fetching VRAM vendor info

The present way to fetch VRAM vendor information turns out to be not reliable 
on GFX 9.4.3 dGPUs as well. Avoid using the data.

Signed-off-by: Lijo Lazar 
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 8 
 1 file changed, 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index a3a11538207b..c1161f465b37 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -1949,14 +1949,6 @@ static int gmc_v9_0_init_mem_ranges(struct amdgpu_device 
*adev)

 static void gmc_v9_4_3_init_vram_info(struct amdgpu_device *adev)  {
-   static const u32 regBIF_BIOS_SCRATCH_4 = 0x50;
-   u32 vram_info;
-
-   /* Only for dGPU, vendor informaton is reliable */
-   if (!amdgpu_sriov_vf(adev) && !(adev->flags & AMD_IS_APU)) {
-   vram_info = RREG32(regBIF_BIOS_SCRATCH_4);
-   adev->gmc.vram_vendor = vram_info & 0xF;
-   }
adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM;
adev->gmc.vram_width = 128 * 64;
 }
--
2.25.1

RE: [PATCH 2/2] use PSP address query command

[Zhang, Hawking]

[AMD Official Use Only - General]

Series is

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: amd-gfx  On Behalf Of Tao Zhou
Sent: Tuesday, January 30, 2024 19:09
To: amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao 
Subject: [PATCH 2/2] use PSP address query command

Get UMC physical address from PSP in RAS error address coversion.

Signed-off-by: Tao Zhou 
---
 drivers/gpu/drm/amd/amdgpu/umc_v12_0.c | 46 ++
 1 file changed, 39 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c 
b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
index 836a4cc1134e..14ef7a24be7b 100644
--- a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
@@ -203,14 +203,14 @@ static bool umc_v12_0_bit_wise_xor(uint32_t val)
return result;
 }

-static void umc_v12_0_convert_error_address(struct amdgpu_device *adev,
-   struct ras_err_data *err_data, 
uint64_t err_addr,
-   uint32_t ch_inst, uint32_t umc_inst,
-   uint32_t node_inst)
+static void umc_v12_0_mca_addr_to_pa(struct amdgpu_device *adev,
+   uint64_t err_addr, uint32_t ch_inst, 
uint32_t umc_inst,
+   uint32_t node_inst,
+   struct ta_ras_query_address_output 
*addr_out)
 {
uint32_t channel_index, i;
-   uint64_t soc_pa, na, retired_page, column;
-   uint32_t bank_hash0, bank_hash1, bank_hash2, bank_hash3, col, row, 
row_xor;
+   uint64_t na, soc_pa;
+   uint32_t bank_hash0, bank_hash1, bank_hash2, bank_hash3, col, row;
uint32_t bank0, bank1, bank2, bank3, bank;

bank_hash0 = (err_addr >> UMC_V12_0_MCA_B0_BIT) & 0x1ULL; @@ -260,12 
+260,44 @@ static void umc_v12_0_convert_error_address(struct amdgpu_device 
*adev,
/* the umc channel bits are not original values, they are hashed */
UMC_V12_0_SET_CHANNEL_HASH(channel_index, soc_pa);

+   addr_out->pa.pa = soc_pa;
+   addr_out->pa.bank = bank;
+   addr_out->pa.channel_idx = channel_index; }
+
+static void umc_v12_0_convert_error_address(struct amdgpu_device *adev,
+   struct ras_err_data *err_data, 
uint64_t err_addr,
+   uint32_t ch_inst, uint32_t umc_inst,
+   uint32_t node_inst)
+{
+   uint32_t col, row, row_xor, bank, channel_index;
+   uint64_t soc_pa, retired_page, column;
+   struct ta_ras_query_address_input addr_in;
+   struct ta_ras_query_address_output addr_out;
+
+   addr_in.addr_type = TA_RAS_MCA_TO_PA;
+   addr_in.ma.err_addr = err_addr;
+   addr_in.ma.ch_inst = ch_inst;
+   addr_in.ma.umc_inst = umc_inst;
+   addr_in.ma.node_inst = node_inst;
+
+   if (psp_ras_query_address(>psp, _in, _out))
+   /* fallback to old path if fail to get pa from psp */
+   umc_v12_0_mca_addr_to_pa(adev, err_addr, ch_inst, umc_inst,
+   node_inst, _out);
+
+   soc_pa = addr_out.pa.pa;
+   bank = addr_out.pa.bank;
+   channel_index = addr_out.pa.channel_idx;
+
+   col = (err_addr >> 1) & 0x1fULL;
+   row = (err_addr >> 10) & 0x3fffULL;
+   row_xor = row ^ (0x1ULL << 13);
/* clear [C3 C2] in soc physical address */
soc_pa &= ~(0x3ULL << UMC_V12_0_PA_C2_BIT);
/* clear [C4] in soc physical address */
soc_pa &= ~(0x1ULL << UMC_V12_0_PA_C4_BIT);

-   row_xor = row ^ (0x1ULL << 13);
/* loop for all possibilities of [C4 C3 C2] */
for (column = 0; column < UMC_V12_0_NA_MAP_PA_NUM; column++) {
retired_page = soc_pa | ((column & 0x3) << UMC_V12_0_PA_C2_BIT);
--
2.34.1

RE: [PATCH] drm/amdgpu: Need to resume ras during gpu reset for gfx v9_4_3 sriov

[Zhang, Hawking]

[AMD Official Use Only - General]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: amd-gfx  On Behalf Of YiPeng Chai
Sent: Tuesday, January 30, 2024 20:10
To: amd-gfx@lists.freedesktop.org
Cc: Wang, Yang(Kevin) ; Zhou1, Tao ; 
Chai, Thomas ; Yang, Stanley ; Chai, 
Thomas ; Li, Candice ; Zhang, Hawking 

Subject: [PATCH] drm/amdgpu: Need to resume ras during gpu reset for gfx v9_4_3 
sriov

Need to resume ras during gpu reset for
gfx v9_4_3 sriov

Signed-off-by: YiPeng Chai 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index afc0b4eb7f8e..3c393d7d9672 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -5724,6 +5724,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
/* Aldebaran and gfx_11_0_3 support ras in SRIOV, so need 
resume ras during reset */
if (amdgpu_ip_version(adev, GC_HWIP, 0) ==
IP_VERSION(9, 4, 2) ||
+   amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) 
||
amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 3))
amdgpu_ras_resume(adev);
} else {
--
2.34.1

RE: [PATCH] drm/amdgpu: use helper macro HW_ERR instead of Hardware error string

[Zhang, Hawking]

[AMD Official Use Only - General]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: Wang, Yang(Kevin) 
Sent: Monday, January 29, 2024 17:10
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Zhou1, Tao ; 
Wang, Yang(Kevin) 
Subject: [PATCH] drm/amdgpu: use helper macro HW_ERR instead of Hardware error 
string

use helper macro HW_ERR to instead of Hardwareare error string.

Signed-off-by: Yang Wang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c |  4 ++--  
drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c | 12 ++--
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c
index d7d2ec3ce399..be525cf3a182 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c
@@ -120,10 +120,10 @@ static void aca_smu_bank_dump(struct amdgpu_device *adev, 
int idx, int total, st  {
int i;

-   dev_info(adev->dev, "[Hardware error] Accelerator Check Architecture 
events logged\n");
+   dev_info(adev->dev, HW_ERR "Accelerator Check Architecture events
+logged\n");
/* plus 1 for output format, e.g: ACA[08/08]:  */
for (i = 0; i < ARRAY_SIZE(aca_regs); i++)
-   dev_info(adev->dev, "[Hardware error] 
ACA[%02d/%02d].%s=0x%016llx\n",
+   dev_info(adev->dev, HW_ERR "ACA[%02d/%02d].%s=0x%016llx\n",
 idx + 1, total, aca_regs[i].name, 
bank->regs[aca_regs[i].reg_idx]);  }

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c
index 6452c09f22c6..24ad4b97177b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c
@@ -212,16 +212,16 @@ int amdgpu_mca_smu_set_debug_mode(struct amdgpu_device 
*adev, bool enable)

 static void amdgpu_mca_smu_mca_bank_dump(struct amdgpu_device *adev, int idx, 
struct mca_bank_entry *entry)  {
-   dev_info(adev->dev, "[Hardware error] Accelerator Check Architecture 
events logged\n");
-   dev_info(adev->dev, "[Hardware error] aca 
entry[%02d].STATUS=0x%016llx\n",
+   dev_info(adev->dev, HW_ERR "Accelerator Check Architecture events 
logged\n");
+   dev_info(adev->dev, HW_ERR "aca entry[%02d].STATUS=0x%016llx\n",
 idx, entry->regs[MCA_REG_IDX_STATUS]);
-   dev_info(adev->dev, "[Hardware error] aca entry[%02d].ADDR=0x%016llx\n",
+   dev_info(adev->dev, HW_ERR "aca entry[%02d].ADDR=0x%016llx\n",
 idx, entry->regs[MCA_REG_IDX_ADDR]);
-   dev_info(adev->dev, "[Hardware error] aca 
entry[%02d].MISC0=0x%016llx\n",
+   dev_info(adev->dev, HW_ERR "aca entry[%02d].MISC0=0x%016llx\n",
 idx, entry->regs[MCA_REG_IDX_MISC0]);
-   dev_info(adev->dev, "[Hardware error] aca entry[%02d].IPID=0x%016llx\n",
+   dev_info(adev->dev, HW_ERR "aca entry[%02d].IPID=0x%016llx\n",
 idx, entry->regs[MCA_REG_IDX_IPID]);
-   dev_info(adev->dev, "[Hardware error] aca entry[%02d].SYND=0x%016llx\n",
+   dev_info(adev->dev, HW_ERR "aca entry[%02d].SYND=0x%016llx\n",
 idx, entry->regs[MCA_REG_IDX_SYND]);  }

--
2.34.1

RE: [PATCH] drm/amdgpu: disable ras feature when fini

[Zhang, Hawking]

[AMD Official Use Only - General]

The patch is

Reviewed-by: Hawking Zhang 

BTW, we could take further step to retire the if branch (bypass == 1) with 
proper RAS_TA changes on legacy Vega20/Arcturus

if (bypass) {
if (__amdgpu_ras_feature_enable(adev, >head, 0))
break;
}
Regards,
Hawking

-Original Message-
From: amd-gfx  On Behalf Of Tao Zhou
Sent: Monday, January 29, 2024 11:54
To: amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao 
Subject: [PATCH] drm/amdgpu: disable ras feature when fini

Send ras disable feature command in fini.

Signed-off-by: Tao Zhou 
Change-Id: I95f1d1e0a46fb613631e5cd77497e64c0551c4c7
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index a249f24ed038..a9fa2d134670 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -3437,7 +3437,7 @@ int amdgpu_ras_fini(struct amdgpu_device *adev)
WARN(AMDGPU_RAS_GET_FEATURES(con->features), "Feature mask is not 
cleared");

if (AMDGPU_RAS_GET_FEATURES(con->features))
-   amdgpu_ras_disable_all_features(adev, 1);
+   amdgpu_ras_disable_all_features(adev, 0);

cancel_delayed_work_sync(>ras_counte_delay_work);

--
2.34.1

RE: [PATCH 1/3] drm/amdgpu: Support passing poison consumption ras block to SRIOV

[Zhang, Hawking]

[AMD Official Use Only - General]


@@ -210,8 +211,10 @@ static void event_interrupt_poison_consumption_v11(struct 
kfd_node *dev,
case SOC15_INTSRC_SQ_INTERRUPT_MSG:
if (dev->dqm->ops.reset_queues)
ret = dev->dqm->ops.reset_queues(dev->dqm, pasid);
+   block = AMDGPU_RAS_BLOCK__GFX;
break;
case SOC21_INTSRC_SDMA_ECC:
+   block = AMDGPU_RAS_BLOCK__SDMA;

Hi @Chai, Thomas<mailto:yipeng.c...@amd.com>/@Luo, 
Zhigang<mailto:zhigang@amd.com>,

event_interrupt_poison_consumption_v11 was duplicated from v9 generation. 
However, the hardware/firmware takes completely different approach to handle 
poison consumption in gfx11.

At this stage, let's just initialize block to AMDGPU_RAS_BLOCK__GFX for all the 
IQR sources (i.e., gfx 11 poison consumption notification was centralized to 
RLC). I believe we still need a few series to correct the v11 implementation.

With above addressed, the series is

Reviewed-by: Hawking Zhang 

Regards,
Hawking

-Original Message-
From: Luo, Zhigang mailto:zhigang@amd.com>>
Sent: Thursday, January 25, 2024 07:22
To: amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org>
Cc: Zhang, Hawking mailto:hawking.zh...@amd.com>>; 
Skvortsov, Victor mailto:victor.skvort...@amd.com>>; 
Saye, Sashank mailto:sashank.s...@amd.com>>; Chai, Thomas 
mailto:yipeng.c...@amd.com>>
Subject: [PATCH 1/3] drm/amdgpu: Support passing poison consumption ras block 
to SRIOV

From: YiPeng Chai mailto:yipeng.c...@amd.com>>

Support passing poison consumption ras blocks to SRIOV.

Signed-off-by: YiPeng Chai mailto:yipeng.c...@amd.com>>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c|  5 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h|  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c   |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c   |  5 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h   |  3 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c   |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h  |  3 ++-
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0_3.c  |  2 +-
 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c |  3 ++-
 drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c | 23 +++
 .../gpu/drm/amd/amdkfd/kfd_int_process_v10.c  |  7 --  
.../gpu/drm/amd/amdkfd/kfd_int_process_v11.c  |  7 --
 .../gpu/drm/amd/amdkfd/kfd_int_process_v9.c   |  7 --
 13 files changed, 49 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index 77e263660288..dfb93664e866 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -732,9 +732,10 @@ void amdgpu_amdkfd_debug_mem_fence(struct amdgpu_device 
*adev)
amdgpu_device_flush_hdp(adev, NULL);
 }

-void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev, 
bool reset)
+void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev,
+   enum amdgpu_ras_block block, bool reset)
 {
-   amdgpu_umc_poison_handler(adev, reset);
+   amdgpu_umc_poison_handler(adev, block, reset);
 }

 int amdgpu_amdkfd_send_close_event_drain_irq(struct amdgpu_device *adev, diff 
--git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index 584a0cea5572..50d3e0149032 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -334,7 +334,7 @@ void amdgpu_amdkfd_debug_mem_fence(struct amdgpu_device 
*adev);  int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev,
struct tile_config *config);
 void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev,
-   bool reset);
+   enum amdgpu_ras_block block, bool reset);
 bool amdgpu_amdkfd_bo_mapped_to_dev(struct amdgpu_device *adev, struct kgd_mem 
*mem);  void amdgpu_amdkfd_block_mmu_notifications(void *p);  int 
amdgpu_amdkfd_criu_resume(void *p); diff --git 
a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index ebcd1cb60052..79bf6bd428a5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -2041,7 +2041,7 @@ static void 
amdgpu_ras_interrupt_poison_consumption_handler(struct ras_manager *
}
}

-   amdgpu_umc_poison_handler(adev, false);
+   amdgpu_umc_poison_handler(adev, obj->head.block, false);

if (block_obj->hw_ops && block_obj->hw_ops->handle_poison_consumption)
poison_stat = 
block_obj->hw_ops->handle_poison_consumption(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
index a6cdb69897f2..20436f81856a 100644
--- a/drivers/

RE: [PATCH 2/2] drm/amdgpu: adjust aca init/fini sequence to match gpu reset

[Zhang, Hawking]

[AMD Official Use Only - General]

Series is

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: amd-gfx  On Behalf Of Yang Wang
Sent: Wednesday, January 24, 2024 13:59
To: amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao ; Wang, Yang(Kevin) ; 
Zhang, Hawking 
Subject: [PATCH 2/2] drm/amdgpu: adjust aca init/fini sequence to match gpu 
reset

- move aca init/fini function into ras init/fini to adapt gpu reset
  sequence.
- add new function amdgpu_aca_reset()

Signed-off-by: Yang Wang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c|  7 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_aca.h|  1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  6 --
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c| 15 +--
 4 files changed, 21 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c
index 52a0ea2f0ebf..40c1d5c4a9d2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c
@@ -688,6 +688,13 @@ void amdgpu_aca_fini(struct amdgpu_device *adev)
aca_manager_fini(>mgr);
 }

+int amdgpu_aca_reset(struct amdgpu_device *adev) {
+   amdgpu_aca_fini(adev);
+
+   return amdgpu_aca_init(adev);
+}
+
 void amdgpu_aca_set_smu_funcs(struct amdgpu_device *adev, const struct 
aca_smu_funcs *smu_funcs)  {
struct amdgpu_aca *aca = >aca;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.h
index 6e9a35eda683..2da50e095883 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.h
@@ -185,6 +185,7 @@ struct aca_info {

 int amdgpu_aca_init(struct amdgpu_device *adev);  void amdgpu_aca_fini(struct 
amdgpu_device *adev);
+int amdgpu_aca_reset(struct amdgpu_device *adev);
 void amdgpu_aca_set_smu_funcs(struct amdgpu_device *adev, const struct 
aca_smu_funcs *smu_funcs);  bool amdgpu_aca_is_enabled(struct amdgpu_device 
*adev);

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 56d9dfa61290..dac73f8fbda4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -4039,10 +4039,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,

amdgpu_device_get_pcie_info(adev);

-   r = amdgpu_aca_init(adev);
-   if (r)
-   return r;
-
r = amdgpu_device_get_job_timeout_settings(adev);
if (r) {
dev_err(adev->dev, "invalid lockup_timeout parameter 
syntax\n"); @@ -4437,8 +4433,6 @@ void amdgpu_device_fini_sw(struct 
amdgpu_device *adev)

amdgpu_reset_fini(adev);

-   amdgpu_aca_fini(adev);
-
/* free i2c buses */
if (!amdgpu_device_has_dc_support(adev))
amdgpu_i2c_fini(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 5b519dc4df01..f7c6ea60316d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -3348,10 +3348,18 @@ int amdgpu_ras_late_init(struct amdgpu_device *adev)
if (amdgpu_sriov_vf(adev))
return 0;

-   if (amdgpu_aca_is_enabled(adev))
+   if (amdgpu_aca_is_enabled(adev)) {
+   if (amdgpu_in_reset(adev))
+   r = amdgpu_aca_reset(adev);
+else
+   r = amdgpu_aca_init(adev);
+   if (r)
+   return r;
+
amdgpu_ras_set_aca_debug_mode(adev, false);
-   else
+   } else {
amdgpu_ras_set_mca_debug_mode(adev, false);
+   }

list_for_each_entry_safe(node, tmp, >ras_list, node) {
obj = node->ras_obj;
@@ -3420,6 +3428,9 @@ int amdgpu_ras_fini(struct amdgpu_device *adev)
amdgpu_ras_fs_fini(adev);
amdgpu_ras_interrupt_remove_all(adev);

+   if (amdgpu_aca_is_enabled(adev))
+   amdgpu_aca_fini(adev);
+
WARN(AMDGPU_RAS_GET_FEATURES(con->features), "Feature mask is not 
cleared");

if (AMDGPU_RAS_GET_FEATURES(con->features))
--
2.34.1

RE: [PATCH] drm/amdgpu: Fix module unload hang with RAS enabled

[Zhang, Hawking]

[AMD Official Use Only - General]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: Joshi, Mukul 
Sent: Wednesday, January 24, 2024 05:01
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Chai, Thomas ; 
Joshi, Mukul 
Subject: [PATCH] drm/amdgpu: Fix module unload hang with RAS enabled

The driver unload hangs because the page retirement kthread cannot be stopped 
as it is sleeping and waiting on page retirement event to occur. Add 
kthread_should_stop() to the event condition to wake up the kthread when 
kthread stop is called during driver unload.

Fixes: 45c3d468793d ("drm/amdgpu: Prepare for asynchronous processing of umc 
page retirement")
Signed-off-by: Mukul Joshi 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index a32e7eb31354..80816c4ec1f1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -2670,8 +2670,12 @@ static int amdgpu_ras_page_retirement_thread(void *param)
while (!kthread_should_stop()) {

wait_event_interruptible(con->page_retirement_wq,
+   kthread_should_stop() ||
atomic_read(>page_retirement_req_cnt));

+   if (kthread_should_stop())
+   break;
+
dev_info(adev->dev, "Start processing page retirement. 
request:%d\n",
atomic_read(>page_retirement_req_cnt));

--
2.35.1

RE: [PATCH 2/2] drm/amdgpu: Show vram vendor only if available

[Zhang, Hawking]

[AMD Official Use Only - General]

Series is

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: Lazar, Lijo 
Sent: Saturday, January 20, 2024 18:19
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Deucher, Alexander 

Subject: [PATCH 2/2] drm/amdgpu: Show vram vendor only if available

Ony if vram vendor info is available, show in sysfs.

Signed-off-by: Lijo Lazar 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 17 -
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
index 08916538a615..8db880244324 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
@@ -221,8 +221,23 @@ static struct attribute *amdgpu_vram_mgr_attributes[] = {
NULL
 };

+static umode_t amdgpu_vram_attrs_is_visible(struct kobject *kobj,
+   struct attribute *attr, int i) {
+   struct device *dev = kobj_to_dev(kobj);
+   struct drm_device *ddev = dev_get_drvdata(dev);
+   struct amdgpu_device *adev = drm_to_adev(ddev);
+
+   if (attr == _attr_mem_info_vram_vendor.attr &&
+   !adev->gmc.vram_vendor)
+   return 0;
+
+   return attr->mode;
+}
+
 const struct attribute_group amdgpu_vram_mgr_attr_group = {
-   .attrs = amdgpu_vram_mgr_attributes
+   .attrs = amdgpu_vram_mgr_attributes,
+   .is_visible = amdgpu_vram_attrs_is_visible
 };

 /**
--
2.25.1

RE: [PATCH V2 5/5] drm/amdgpu:Support retiring multiple MCA error address pages

[Zhang, Hawking]

[AMD Official Use Only - General]

Series is

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: Chai, Thomas 
Sent: Thursday, January 18, 2024 14:43
To: amd-gfx@lists.freedesktop.org
Cc: Chai, Thomas ; Zhang, Hawking ; 
Zhou1, Tao ; Li, Candice ; Wang, 
Yang(Kevin) ; Yang, Stanley ; 
Chai, Thomas 
Subject: [PATCH V2 5/5] drm/amdgpu:Support retiring multiple MCA error address 
pages

Support retiring multiple MCA error address pages in one in-band query for umc 
v12_0.

Signed-off-by: YiPeng Chai 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 43 +---  
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h |  8 ++-  
drivers/gpu/drm/amd/amdgpu/umc_v12_0.c  | 66 +
 3 files changed, 77 insertions(+), 40 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 61a02dbac087..879e1e59ac76 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -3909,8 +3909,7 @@ static int ras_err_info_cmp(void *priv, struct list_head 
*a, struct list_head *b  }

 static struct ras_err_info *amdgpu_ras_error_get_info(struct ras_err_data 
*err_data,
-   struct amdgpu_smuio_mcm_config_info *mcm_info,
-   struct ras_err_addr *err_addr)
+   struct amdgpu_smuio_mcm_config_info *mcm_info)
 {
struct ras_err_node *err_node;

@@ -3922,10 +3921,9 @@ static struct ras_err_info 
*amdgpu_ras_error_get_info(struct ras_err_data *err_d
if (!err_node)
return NULL;

-   memcpy(_node->err_info.mcm_info, mcm_info, sizeof(*mcm_info));
+   INIT_LIST_HEAD(_node->err_info.err_addr_list);

-   if (err_addr)
-   memcpy(_node->err_info.err_addr, err_addr, 
sizeof(*err_addr));
+   memcpy(_node->err_info.mcm_info, mcm_info, sizeof(*mcm_info));

err_data->err_list_count++;
list_add_tail(_node->node, _data->err_node_list); @@ -3934,6 
+3932,29 @@ static struct ras_err_info *amdgpu_ras_error_get_info(struct 
ras_err_data *err_d
return _node->err_info;
 }

+void amdgpu_ras_add_mca_err_addr(struct ras_err_info *err_info, struct
+ras_err_addr *err_addr) {
+   struct ras_err_addr *mca_err_addr;
+
+   mca_err_addr = kzalloc(sizeof(*mca_err_addr), GFP_KERNEL);
+   if (!mca_err_addr)
+   return;
+
+   INIT_LIST_HEAD(_err_addr->node);
+
+   mca_err_addr->err_status = err_addr->err_status;
+   mca_err_addr->err_ipid = err_addr->err_ipid;
+   mca_err_addr->err_addr = err_addr->err_addr;
+
+   list_add_tail(_err_addr->node, _info->err_addr_list); }
+
+void amdgpu_ras_del_mca_err_addr(struct ras_err_info *err_info, struct
+ras_err_addr *mca_err_addr) {
+   list_del(_err_addr->node);
+   kfree(mca_err_addr);
+}
+
 int amdgpu_ras_error_statistic_ue_count(struct ras_err_data *err_data,
struct amdgpu_smuio_mcm_config_info *mcm_info,
struct ras_err_addr *err_addr, u64 count) @@ -3946,10 +3967,13 
@@ int amdgpu_ras_error_statistic_ue_count(struct ras_err_data *err_data,
if (!count)
return 0;

-   err_info = amdgpu_ras_error_get_info(err_data, mcm_info, err_addr);
+   err_info = amdgpu_ras_error_get_info(err_data, mcm_info);
if (!err_info)
return -EINVAL;

+   if (err_addr && err_addr->err_status)
+   amdgpu_ras_add_mca_err_addr(err_info, err_addr);
+
err_info->ue_count += count;
err_data->ue_count += count;

@@ -3968,7 +3992,7 @@ int amdgpu_ras_error_statistic_ce_count(struct 
ras_err_data *err_data,
if (!count)
return 0;

-   err_info = amdgpu_ras_error_get_info(err_data, mcm_info, err_addr);
+   err_info = amdgpu_ras_error_get_info(err_data, mcm_info);
if (!err_info)
return -EINVAL;

@@ -3990,10 +4014,13 @@ int amdgpu_ras_error_statistic_de_count(struct 
ras_err_data *err_data,
if (!count)
return 0;

-   err_info = amdgpu_ras_error_get_info(err_data, mcm_info, err_addr);
+   err_info = amdgpu_ras_error_get_info(err_data, mcm_info);
if (!err_info)
return -EINVAL;

+   if (err_addr && err_addr->err_status)
+   amdgpu_ras_add_mca_err_addr(err_info, err_addr);
+
err_info->de_count += count;
err_data->de_count += count;

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
index 9c3df9985fad..a25aea6ae230 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
@@ -474,6 +474,7 @@ struct ras_fs_data {  };

 struct ras_err_addr {
+   struct list_head node;
uint64_t err_status;
uint64_t err_ipid;
uint64_t err_addr;
@@ -484,7 +485,7 @@ struct ras_err

RE: [PATCH 2/2] update check condition of query for ras page retire

[Zhang, Hawking]

[AMD Official Use Only - General]

Series is

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: amd-gfx  On Behalf Of Tao Zhou
Sent: Thursday, January 18, 2024 15:36
To: amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao 
Subject: [PATCH 2/2] update check condition of query for ras page retire

Support page retirement handling in debug mode.

v2: revert smu_v13_0_6_get_ecc_info directly.

Signed-off-by: Tao Zhou 
Change-Id: I0aaa807d7fe87b3da0f023c380e57ab6dd446fcf
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
index 9d1cf41cf483..d8d263956e85 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
@@ -93,11 +93,14 @@ static int amdgpu_umc_do_page_retirement(struct 
amdgpu_device *adev,
struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
int ret = 0;
+   unsigned int error_query_mode;
unsigned long err_count;

kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
+   amdgpu_ras_get_error_query_mode(adev, _query_mode);
ret = amdgpu_dpm_get_ecc_info(adev, (void *)&(con->umc_ecc));
-   if (ret == -EOPNOTSUPP) {
+   if (ret == -EOPNOTSUPP &&
+   error_query_mode == AMDGPU_RAS_DIRECT_ERROR_QUERY) {
if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
adev->umc.ras->ras_block.hw_ops->query_ras_error_count)

adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, ras_error_status); 
@@ -121,7 +124,8 @@ static int amdgpu_umc_do_page_retirement(struct 
amdgpu_device *adev,
 */

adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, 
ras_error_status);
}
-   } else if (!ret) {
+   } else if (error_query_mode == AMDGPU_RAS_FIRMWARE_ERROR_QUERY ||
+   (!ret && error_query_mode == AMDGPU_RAS_DIRECT_ERROR_QUERY)) {
if (adev->umc.ras &&
adev->umc.ras->ecc_info_query_ras_error_count)
adev->umc.ras->ecc_info_query_ras_error_count(adev, 
ras_error_status);
--
2.34.1

RE: [PATCH 2/2] update check condition of query for ras page retire

[Zhang, Hawking]

[AMD Official Use Only - General]

static ssize_t smu_v13_0_6_get_ecc_info(struct smu_context *smu,
void *table)
 {
-   /* Support ecc info by default */
-   return 0;
+   /* we use debug mode flag instead of this interface */
+   return -EOPNOTSUPP;
 }

Shall we just drop the callback implementation? smu_get_ecc_info will return 
-EOPNOTSUPP if the callback is not supported.

Regards,
Hawking

-Original Message-
From: amd-gfx  On Behalf Of Tao Zhou
Sent: Wednesday, January 17, 2024 17:15
To: amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao 
Subject: [PATCH 2/2] update check condition of query for ras page retire

Support page retirement handling in debug mode.

Signed-off-by: Tao Zhou 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c  | 9 +++--
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 4 ++--
 2 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
index 41139bac7643..6df32f0afd89 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
@@ -90,12 +90,16 @@ static void amdgpu_umc_handle_bad_pages(struct 
amdgpu_device *adev,  {
struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
+   unsigned int error_query_mode;
int ret = 0;

+   amdgpu_ras_get_error_query_mode(adev, _query_mode);
+
mutex_lock(>page_retirement_lock);

ret = amdgpu_dpm_get_ecc_info(adev, (void *)&(con->umc_ecc));
-   if (ret == -EOPNOTSUPP) {
+   if (ret == -EOPNOTSUPP &&
+   error_query_mode == AMDGPU_RAS_DIRECT_ERROR_QUERY) {
if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
adev->umc.ras->ras_block.hw_ops->query_ras_error_count)

adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, ras_error_status); 
@@ -119,7 +123,8 @@ static void amdgpu_umc_handle_bad_pages(struct 
amdgpu_device *adev,
 */

adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, 
ras_error_status);
}
-   } else if (!ret) {
+   } else if (error_query_mode == AMDGPU_RAS_FIRMWARE_ERROR_QUERY ||
+   (!ret && error_query_mode == AMDGPU_RAS_DIRECT_ERROR_QUERY)) {
if (adev->umc.ras &&
adev->umc.ras->ecc_info_query_ras_error_count)
adev->umc.ras->ecc_info_query_ras_error_count(adev, 
ras_error_status); diff --git 
a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
index c560f4af214d..d86c9e7fc64b 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
@@ -2909,8 +2909,8 @@ static int smu_v13_0_6_select_xgmi_plpd_policy(struct 
smu_context *smu,  static ssize_t smu_v13_0_6_get_ecc_info(struct smu_context 
*smu,
void *table)
 {
-   /* Support ecc info by default */
-   return 0;
+   /* we use debug mode flag instead of this interface */
+   return -EOPNOTSUPP;
 }

 static const struct pptable_funcs smu_v13_0_6_ppt_funcs = {
--
2.35.1

RE: [PATCH 1/2] update error condition check for umc_v12_0_query_error_address

[Zhang, Hawking]

[AMD Official Use Only - General]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: amd-gfx  On Behalf Of Tao Zhou
Sent: Wednesday, January 17, 2024 17:14
To: amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao 
Subject: [PATCH 1/2] update error condition check for 
umc_v12_0_query_error_address

Deferred error is also taken into account.

Signed-off-by: Tao Zhou 
---
 drivers/gpu/drm/amd/amdgpu/umc_v12_0.c | 5 +
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c 
b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
index 10edf818acf5..2e0bd4312f2c 100644
--- a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
@@ -337,10 +337,7 @@ static int umc_v12_0_query_error_address(struct 
amdgpu_device *adev,
}

/* calculate error address if ue error is detected */
-   if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 
&&
-   REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, AddrV) == 
1 &&
-   REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1) 
{
-
+   if (umc_v12_0_is_uncorrectable_error(adev, mc_umc_status)) {
mc_umc_addrt0 =
SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_ADDRT0);

--
2.35.1

RE: [PATCH 3/5] drm/amdgpu: Use asynchronous polling to handle umc_v12_0 poisoning

[Zhang, Hawking]

[AMD Official Use Only - General]


Please check my comments inline

Regards,
Hawking

-Original Message-
From: Chai, Thomas 
Sent: Tuesday, January 16, 2024 16:21
To: amd-gfx@lists.freedesktop.org
Cc: Chai, Thomas ; Zhang, Hawking ; 
Zhou1, Tao ; Li, Candice ; Wang, 
Yang(Kevin) ; Yang, Stanley ; 
Chai, Thomas 
Subject: [PATCH 3/5] drm/amdgpu: Use asynchronous polling to handle umc_v12_0 
poisoning

Use asynchronous polling to handle umc_v12_0 poisoning.

Signed-off-by: YiPeng Chai mailto:yipeng.c...@amd.com>>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c |   5 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 143 +++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h |   3 +
 3 files changed, 120 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 856206e95842..44929281840e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -118,6 +118,8 @@ const char *get_ras_block_str(struct ras_common_if 
*ras_block)
 /* typical ECC bad page rate is 1 bad page per 100MB VRAM */
 #define RAS_BAD_PAGE_COVER  (100 * 1024 * 1024ULL)

+#define MAX_UMC_POISON_POLLING_TIME_ASYNC  100  //ms
+
 enum amdgpu_ras_retire_page_reservation {
AMDGPU_RAS_RETIRE_PAGE_RESERVED,
AMDGPU_RAS_RETIRE_PAGE_PENDING,
@@ -2670,6 +2672,9 @@ static int amdgpu_ras_page_retirement_thread(void *param)
atomic_read(>page_retirement_req_cnt));

atomic_dec(>page_retirement_req_cnt);
+
+   amdgpu_umc_poison_retire_page_polling_timeout(adev,
+   false, MAX_UMC_POISON_POLLING_TIME_ASYNC);
}

return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
index 9d1cf41cf483..2dde29cb807d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
@@ -23,6 +23,7 @@

 #include "amdgpu.h"
 #include "umc_v6_7.h"
+#define MAX_UMC_POISON_POLLING_TIME_SYNC   20  //ms

 static int amdgpu_umc_convert_error_address(struct amdgpu_device *adev,
struct ras_err_data *err_data, uint64_t 
err_addr, @@ -85,17 +86,14 @@ int amdgpu_umc_page_retirement_mca(struct 
amdgpu_device *adev,
return ret;
 }

-static int amdgpu_umc_do_page_retirement(struct amdgpu_device *adev,
-   void *ras_error_status,
-   struct amdgpu_iv_entry *entry,
-   bool reset)
+static void amdgpu_umc_handle_bad_pages(struct amdgpu_device *adev,
+   void *ras_error_status)
 {
struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
int ret = 0;
unsigned long err_count;
-
-   kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
+   mutex_lock(>page_retirement_lock);
ret = amdgpu_dpm_get_ecc_info(adev, (void *)&(con->umc_ecc));
if (ret == -EOPNOTSUPP) {
if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && @@ 
-163,19 +161,86 @@ static int amdgpu_umc_do_page_retirement(struct 
amdgpu_device *adev,
con->update_channel_flag = false;
}
}
-
-   if (reset) {
-   /* use mode-2 reset for poison consumption */
-   if (!entry)
-   con->gpu_reset_flags |= 
AMDGPU_RAS_GPU_RESET_MODE2_RESET;
-   amdgpu_ras_reset_gpu(adev);
-   }
}

kfree(err_data->err_addr);
+
+   mutex_unlock(>page_retirement_lock);
+}
+
+static int amdgpu_umc_do_page_retirement(struct amdgpu_device *adev,
+   void *ras_error_status,
+   struct amdgpu_iv_entry *entry,
+   bool reset)
+{
+   struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
+   struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
+
+   kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
+   amdgpu_umc_handle_bad_pages(adev, ras_error_status);
+
+   if (err_data->ue_count && reset) {
+   /* use mode-2 reset for poison consumption */
+   if (!entry)
+   con->gpu_reset_flags |= 
AMDGPU_RAS_GPU_RESET_MODE2_RESET;

[Hawking]: Shall we do further check on con->poison_supported flag to decide 
issuing mode-2 or mode-1.

+   amdgpu_ras_reset_gpu(adev);
+   }
+
return AMDGPU_RAS_SUCCESS;
 }

+int amdgpu_umc_poison_retire_page_polling_timeout(struct amdgpu_device *adev,
+   bool reset, uint32_t timeout_ms)
[Hawking] int amdgpu_umc_bad_page_polling_timeout(struct amdgpu_device *adev, 
boot reset, uint32_t timeout_ms)
+{
+   struct ras_err_data err_data;
+   s

RE: [PATCH 1/5] drm/amdgpu: Add log info for umc_v12_0 and smu_v13_0_6

[Zhang, Hawking]

[AMD Official Use Only - General]

Please ignore my first comment. It doesn't necessarily associated with socket  
id in UMC MCA status log at this stage.

Regards,
Hawking

-Original Message-
From: amd-gfx  On Behalf Of Zhang, 
Hawking
Sent: Wednesday, January 17, 2024 19:12
To: Chai, Thomas ; amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao ; Yang, Stanley ; Wang, 
Yang(Kevin) ; Li, Candice 
Subject: RE: [PATCH 1/5] drm/amdgpu: Add log info for umc_v12_0 and smu_v13_0_6

[AMD Official Use Only - General]

[AMD Official Use Only - General]

+   dev_info(adev->dev,
+   "MCA_UMC_STATUS(0x%llx): Val:%llu, Poison:%llu, Deferred:%llu, 
PCC:%llu, UC:%llu, TCC:%llu\n",
+   mc_umc_status,

Please also print out socket id for UMC MCA status.

+   dev_info(smu->adev->dev, "MSG %s(%d) query %s MCA count result:%u\n",
+   (msg == SMU_MSG_QueryValidMcaCeCount) ?
+   "SMU_MSG_QueryValidMcaCeCount" : 
"SMU_MSG_QueryValidMcaCount",
+   msg,
+   (msg == SMU_MSG_QueryValidMcaCeCount) ? "CE" : "UE",
+   *count);
+

This seems redundant or was added for debugging purpose. We can drop this print 
since there is log to cover failures.

Regards,
Hawking


-Original Message-
From: Chai, Thomas 
Sent: Tuesday, January 16, 2024 16:21
To: amd-gfx@lists.freedesktop.org
Cc: Chai, Thomas ; Zhang, Hawking ; 
Zhou1, Tao ; Li, Candice ; Wang, 
Yang(Kevin) ; Yang, Stanley ; 
Chai, Thomas 
Subject: [PATCH 1/5] drm/amdgpu: Add log info for umc_v12_0 and smu_v13_0_6

Add log info for umc_v12_0 and smu_v13_0_6.

Signed-off-by: YiPeng Chai 
---
 drivers/gpu/drm/amd/amdgpu/umc_v12_0.c  | 11 +++
 drivers/gpu/drm/amd/amdkfd/kfd_events.c |  6 +-
 .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c| 13 +
 3 files changed, 29 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c 
b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
index 6423dca5b777..fa2168f1d3bf 100644
--- a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
@@ -91,6 +91,17 @@ static void umc_v12_0_reset_error_count(struct amdgpu_device 
*adev)

 bool umc_v12_0_is_deferred_error(struct amdgpu_device *adev, uint64_t 
mc_umc_status)  {
+   dev_info(adev->dev,
+   "MCA_UMC_STATUS(0x%llx): Val:%llu, Poison:%llu, Deferred:%llu, 
PCC:%llu, UC:%llu, TCC:%llu\n",
+   mc_umc_status,
+   REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val),
+   REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, 
Poison),
+   REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, 
Deferred),
+   REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC),
+   REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC),
+   REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC)
+   );
+
return (amdgpu_ras_is_poison_mode_supported(adev) &&
(REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) 
== 1) &&
(REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, 
Deferred) == 1)); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
index 11923964ce9a..51bb98db5d7a 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_events.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
@@ -1297,8 +1297,10 @@ void kfd_signal_poison_consumed_event(struct kfd_node 
*dev, u32 pasid)
uint32_t id = KFD_FIRST_NONSIGNAL_EVENT_ID;
int user_gpu_id;

-   if (!p)
+   if (!p) {
+   dev_warn(dev->adev->dev, "Not find process with pasid:%d\n", 
pasid);
return; /* Presumably process exited. */
+   }

user_gpu_id = kfd_process_get_user_gpu_id(p, dev->id);
if (unlikely(user_gpu_id == -EINVAL)) { @@ -1334,6 +1336,8 @@ void 
kfd_signal_poison_consumed_event(struct kfd_node *dev, u32 pasid)
}
}

+   dev_warn(dev->adev->dev, "Send SIGBUS to process %s(pasid:%d)\n",
+   p->lead_thread->comm, pasid);
rcu_read_unlock();

/* user application will handle SIGBUS signal */ diff --git 
a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
index 952a983da49a..cee8ee5afcb6 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
@@ -2406,10 +2406,23 @@ static int smu_v13_0_6_get_valid_mca_count(struct 
smu_context *smu, enum amdgpu_

ret = smu_cmn_send_smc_msg(smu, msg, count);
if (ret) {
+   dev_err(smu->adev->dev, "%s(%d) failed to query %s MCA count, 
ret:%d\n",
+   (msg == 

RE: [PATCH 1/5] drm/amdgpu: Add log info for umc_v12_0 and smu_v13_0_6

[Zhang, Hawking]

[AMD Official Use Only - General]

+   dev_info(adev->dev,
+   "MCA_UMC_STATUS(0x%llx): Val:%llu, Poison:%llu, Deferred:%llu, 
PCC:%llu, UC:%llu, TCC:%llu\n",
+   mc_umc_status,

Please also print out socket id for UMC MCA status.

+   dev_info(smu->adev->dev, "MSG %s(%d) query %s MCA count result:%u\n",
+   (msg == SMU_MSG_QueryValidMcaCeCount) ?
+   "SMU_MSG_QueryValidMcaCeCount" : 
"SMU_MSG_QueryValidMcaCount",
+   msg,
+   (msg == SMU_MSG_QueryValidMcaCeCount) ? "CE" : "UE",
+   *count);
+

This seems redundant or was added for debugging purpose. We can drop this print 
since there is log to cover failures.

Regards,
Hawking


-Original Message-
From: Chai, Thomas 
Sent: Tuesday, January 16, 2024 16:21
To: amd-gfx@lists.freedesktop.org
Cc: Chai, Thomas ; Zhang, Hawking ; 
Zhou1, Tao ; Li, Candice ; Wang, 
Yang(Kevin) ; Yang, Stanley ; 
Chai, Thomas 
Subject: [PATCH 1/5] drm/amdgpu: Add log info for umc_v12_0 and smu_v13_0_6

Add log info for umc_v12_0 and smu_v13_0_6.

Signed-off-by: YiPeng Chai 
---
 drivers/gpu/drm/amd/amdgpu/umc_v12_0.c  | 11 +++
 drivers/gpu/drm/amd/amdkfd/kfd_events.c |  6 +-
 .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c| 13 +
 3 files changed, 29 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c 
b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
index 6423dca5b777..fa2168f1d3bf 100644
--- a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
@@ -91,6 +91,17 @@ static void umc_v12_0_reset_error_count(struct amdgpu_device 
*adev)

 bool umc_v12_0_is_deferred_error(struct amdgpu_device *adev, uint64_t 
mc_umc_status)  {
+   dev_info(adev->dev,
+   "MCA_UMC_STATUS(0x%llx): Val:%llu, Poison:%llu, Deferred:%llu, 
PCC:%llu, UC:%llu, TCC:%llu\n",
+   mc_umc_status,
+   REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val),
+   REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, 
Poison),
+   REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, 
Deferred),
+   REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC),
+   REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC),
+   REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC)
+   );
+
return (amdgpu_ras_is_poison_mode_supported(adev) &&
(REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) 
== 1) &&
(REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, 
Deferred) == 1)); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
index 11923964ce9a..51bb98db5d7a 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_events.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
@@ -1297,8 +1297,10 @@ void kfd_signal_poison_consumed_event(struct kfd_node 
*dev, u32 pasid)
uint32_t id = KFD_FIRST_NONSIGNAL_EVENT_ID;
int user_gpu_id;

-   if (!p)
+   if (!p) {
+   dev_warn(dev->adev->dev, "Not find process with pasid:%d\n", 
pasid);
return; /* Presumably process exited. */
+   }

user_gpu_id = kfd_process_get_user_gpu_id(p, dev->id);
if (unlikely(user_gpu_id == -EINVAL)) { @@ -1334,6 +1336,8 @@ void 
kfd_signal_poison_consumed_event(struct kfd_node *dev, u32 pasid)
}
}

+   dev_warn(dev->adev->dev, "Send SIGBUS to process %s(pasid:%d)\n",
+   p->lead_thread->comm, pasid);
rcu_read_unlock();

/* user application will handle SIGBUS signal */ diff --git 
a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
index 952a983da49a..cee8ee5afcb6 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
@@ -2406,10 +2406,23 @@ static int smu_v13_0_6_get_valid_mca_count(struct 
smu_context *smu, enum amdgpu_

ret = smu_cmn_send_smc_msg(smu, msg, count);
if (ret) {
+   dev_err(smu->adev->dev, "%s(%d) failed to query %s MCA count, 
ret:%d\n",
+   (msg == SMU_MSG_QueryValidMcaCeCount) ?
+   "SMU_MSG_QueryValidMcaCeCount" : 
"SMU_MSG_QueryValidMcaCount",
+   msg,
+   (msg == SMU_MSG_QueryValidMcaCeCount) ? "CE" : "UE",
+   ret);
*count = 0;
return ret;
}

+   dev_info(smu->adev->dev, "MSG %s(%d) query %s MCA count result:%u\n",
+   (msg == SMU_MSG_QueryValidMca

RE: [PATCH 2/2] drm/amdgpu: Do bad page retirement for deferred errors

[Zhang, Hawking]

[AMD Official Use Only - General]

Let's drop the following message.

+   dev_info(adev->dev, "%ld uncorrectable hardware errors and "
+   "%ld deferred hardware errors detected in UMC 
block\n",
+   err_data->ue_count, err_data->de_count);

With that fixed, the series is

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: amd-gfx  On Behalf Of Candice Li
Sent: Wednesday, January 10, 2024 16:39
To: amd-gfx@lists.freedesktop.org
Cc: Li, Candice 
Subject: [PATCH 2/2] drm/amdgpu: Do bad page retirement for deferred errors

Needs to do bad page retirement for deferred errors.

Signed-off-by: Candice Li 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 12 +++-
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
index 848df7acdd3210..df61df7e9b155f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
@@ -93,6 +93,7 @@ static int amdgpu_umc_do_page_retirement(struct amdgpu_device 
*adev,
struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
int ret = 0;
+   unsigned long err_count;

kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
ret = amdgpu_dpm_get_ecc_info(adev, (void *)&(con->umc_ecc)); @@ 
-147,16 +148,17 @@ static int amdgpu_umc_do_page_retirement(struct 
amdgpu_device *adev,
}

/* only uncorrectable error needs gpu reset */
-   if (err_data->ue_count) {
-   dev_info(adev->dev, "%ld uncorrectable hardware errors "
-   "detected in UMC block\n",
-   err_data->ue_count);
+   if (err_data->ue_count || err_data->de_count) {
+   dev_info(adev->dev, "%ld uncorrectable hardware errors and "
+   "%ld deferred hardware errors detected in UMC 
block\n",
+   err_data->ue_count, err_data->de_count);

+   err_count = err_data->ue_count + err_data->de_count;
if ((amdgpu_bad_page_threshold != 0) &&
err_data->err_addr_cnt) {
amdgpu_ras_add_bad_pages(adev, err_data->err_addr,
err_data->err_addr_cnt);
-   amdgpu_ras_save_bad_pages(adev, &(err_data->ue_count));
+   amdgpu_ras_save_bad_pages(adev, _count);

amdgpu_dpm_send_hbm_bad_pages_num(adev, 
con->eeprom_control.ras_num_recs);

--
2.25.1

RE: [PATCH] drm/amd/pm: Enable smu v13_0_6 eccinfo in firmware query mode

[Zhang, Hawking]

[AMD Official Use Only - General]

Let' s see if we can retire the get_ecc_info callback since from smu_v13. 
(i.e., do not provide the callback implementation). What we just need to ensure 
the driver can fallback to direct poll mode when aca debug mode is enabled, 
this applies to both error query and bad page retirement.

Thoughts?

Regards,
Hawking

-Original Message-
From: amd-gfx  On Behalf Of Candice Li
Sent: Wednesday, January 10, 2024 10:26
To: amd-gfx@lists.freedesktop.org
Cc: Li, Candice 
Subject: [PATCH] drm/amd/pm: Enable smu v13_0_6 eccinfo in firmware query mode

smu v13_0_6 eccinfo is supported in firmware query mode only.

Signed-off-by: Candice Li 
---
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
index 4ebc6b421c2cb4..29396424a99609 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
@@ -2896,8 +2896,11 @@ static int smu_v13_0_6_select_xgmi_plpd_policy(struct 
smu_context *smu,  static ssize_t smu_v13_0_6_get_ecc_info(struct smu_context 
*smu,
void *table)
 {
-   /* Support ecc info by default */
-   return 0;
+   struct amdgpu_device *adev = smu->adev;
+   unsigned int error_query_mode;
+
+   return (amdgpu_ras_get_error_query_mode(adev, _query_mode) &&
+   error_query_mode == AMDGPU_RAS_FIRMWARE_ERROR_QUERY) ? 0 :
+-EOPNOTSUPP;
 }

 static const struct pptable_funcs smu_v13_0_6_ppt_funcs = {
--
2.25.1

RE: [PATCH] drm/amdgpu: drop exp hw support check for GC 9.4.3

[Zhang, Hawking]

[AMD Official Use Only - General]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: amd-gfx  On Behalf Of Alex Deucher
Sent: Tuesday, January 9, 2024 23:46
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander 
Subject: [PATCH] drm/amdgpu: drop exp hw support check for GC 9.4.3

No longer needed.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index b8fde08aec8e..f96811bbe40e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -1963,8 +1963,6 @@ static int amdgpu_discovery_set_gc_ip_blocks(struct 
amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, _v9_0_ip_block);
break;
case IP_VERSION(9, 4, 3):
-   if (!amdgpu_exp_hw_support)
-   return -EINVAL;
amdgpu_device_ip_block_add(adev, _v9_4_3_ip_block);
break;
case IP_VERSION(10, 1, 10):
--
2.42.0

RE: [PATCH V2] drm/amdgpu: correct the cu count for gfx v11

[Zhang, Hawking]

[AMD Official Use Only - General]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: Gao, Likun 
Sent: Monday, January 8, 2024 11:31
To: amd-gfx list 
Cc: Zhang, Hawking 
Subject: [PATCH V2] drm/amdgpu: correct the cu count for gfx v11

[AMD Official Use Only - General]

From: Likun Gao 

Correct the algorithm of active CU to skip disabled sa for gfx v11.

Signed-off-by: Likun Gao 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 2fbcd9765980..c7242877d5d3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -6383,6 +6383,9 @@ static int gfx_v11_0_get_cu_info(struct amdgpu_device 
*adev,
mutex_lock(>grbm_idx_mutex);
for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
+   bitmap = i * adev->gfx.config.max_sh_per_se + j;
+   if (!((gfx_v11_0_get_sa_active_bitmap(adev) >> bitmap) 
& 1))
+   continue;
mask = 1;
counter = 0;
gfx_v11_0_select_se_sh(adev, i, j, 0x, 0);
--
2.34.1

RE: [PATCH v2 01/12] drm/amdgpu: implement RAS ACA driver framework

[Zhang, Hawking]

[AMD Official Use Only - General]

Series is

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: Wang, Yang(Kevin) 
Sent: Thursday, January 4, 2024 19:49
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Zhou1, Tao ; 
Chai, Thomas ; Wang, Yang(Kevin) 
Subject: [PATCH v2 01/12] drm/amdgpu: implement RAS ACA driver framework

v1:
implement new RAS ACA driver code framework.

v2:
- rename aca_bank_set to aca_banks.
- rename aca_source_xxx to aca_handle_xxx

v3:
- Optimize some function implementation details. (from Hawking's suggestion)

Signed-off-by: Yang Wang 
---
 drivers/gpu/drm/amd/amdgpu/Makefile|   2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu.h|   4 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c| 665 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_aca.h| 196 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |   6 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h|   1 +
 6 files changed, 873 insertions(+), 1 deletion(-)  create mode 100644 
drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c
 create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_aca.h

diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile 
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 260e32ef7bae..4c989da4d2f3 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -80,7 +80,7 @@ amdgpu-y += amdgpu_device.o amdgpu_doorbell_mgr.o 
amdgpu_kms.o \
amdgpu_umc.o smu_v11_0_i2c.o amdgpu_fru_eeprom.o amdgpu_rap.o \
amdgpu_fw_attestation.o amdgpu_securedisplay.o \
amdgpu_eeprom.o amdgpu_mca.o amdgpu_psp_ta.o amdgpu_lsdma.o \
-   amdgpu_ring_mux.o amdgpu_xcp.o amdgpu_seq64.o
+   amdgpu_ring_mux.o amdgpu_xcp.o amdgpu_seq64.o amdgpu_aca.o

 amdgpu-$(CONFIG_PROC_FS) += amdgpu_fdinfo.o

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 9da14436a373..eb182225f548 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -107,6 +107,7 @@
 #include "amdgpu_smuio.h"
 #include "amdgpu_fdinfo.h"
 #include "amdgpu_mca.h"
+#include "amdgpu_aca.h"
 #include "amdgpu_ras.h"
 #include "amdgpu_xcp.h"
 #include "amdgpu_seq64.h"
@@ -1047,6 +1048,9 @@ struct amdgpu_device {
/* MCA */
struct amdgpu_mca   mca;

+   /* ACA */
+   struct amdgpu_aca   aca;
+
struct amdgpu_ip_block  ip_blocks[AMDGPU_MAX_IP_NUM];
uint32_tharvest_ip_mask;
int num_ip_blocks;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c
new file mode 100644
index ..756b40bde38b
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c
@@ -0,0 +1,665 @@
+/*
+ * Copyright 2023 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person
+obtaining a
+ * copy of this software and associated documentation files (the
+"Software"),
+ * to deal in the Software without restriction, including without
+limitation
+ * the rights to use, copy, modify, merge, publish, distribute,
+sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom
+the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT
+SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM,
+DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
+OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include 
+#include "amdgpu.h"
+#include "amdgpu_aca.h"
+#include "amdgpu_ras.h"
+
+#define ACA_BANK_HWID(type, hwid, mcatype) [ACA_HWIP_TYPE_##type] =
+{hwid, mcatype}
+
+typedef int bank_handler_t(struct aca_handle *handle, struct aca_bank
+*bank, enum aca_error_type type, void *data);
+
+struct aca_banks {
+   int nr_banks;
+   struct list_head list;
+};
+
+struct aca_hwip {
+   int hwid;
+   int mcatype;
+};
+
+static struct aca_hwip aca_hwid_mcatypes[ACA_HWIP_TYPE_COUNT] = {
+   ACA_BANK_HWID(SMU,  0x01,   0x01),
+   ACA_BANK_HWID(PCS_XGMI, 0x50,   0x00),
+   ACA_BANK_HWID(UMC,  0x96,   0x00),
+};
+
+static void aca_banks_init(struct aca_banks *banks) {
+   if (!banks)
+   return;
+
+   memset(banks, 0, sizeof(*banks));
+   INIT_LIST_HEAD(>list);
+}
+
+static int aca_banks_add_bank(struct aca_banks *banks, struct aca_bank
+*bank) {
+   

RE: [PATCH v2 3/5] drm/amdgpu: Add ras helper to query boot errors v2

[Zhang, Hawking]

[AMD Official Use Only - General]


Please check my comments inline.

Regards,
Hawking

-Original Message-
From: Zhang, Morris 
Sent: Wednesday, January 3, 2024 17:46
To: Zhang, Hawking ; amd-gfx@lists.freedesktop.org; 
Zhou1, Tao ; Yang, Stanley ; Wang, 
Yang(Kevin) ; Chai, Thomas ; Li, 
Candice 
Cc: Deucher, Alexander ; Ma, Le ; 
Lazar, Lijo ; Zhang, Hawking 
Subject: RE: [PATCH v2 3/5] drm/amdgpu: Add ras helper to query boot errors v2

[AMD Official Use Only - General]

--Brs,
Morris Zhang
MLSE Linux  ML SRDC
Ext. 25147

> -Original Message-
> From: amd-gfx 
> mailto:amd-gfx-boun...@lists.freedesktop.org>>
>  On Behalf Of
> Hawking Zhang
> Sent: Tuesday, January 2, 2024 10:08 PM
> To: amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org>; 
> Zhou1, Tao mailto:tao.zh...@amd.com>>;
> Yang, Stanley mailto:stanley.y...@amd.com>>; Wang, 
> Yang(Kevin)
> mailto:kevinyang.w...@amd.com>>; Chai, Thomas 
> mailto:yipeng.c...@amd.com>>; Li,
> Candice mailto:candice...@amd.com>>
> Cc: Deucher, Alexander 
> mailto:alexander.deuc...@amd.com>>; Ma, Le
> mailto:le...@amd.com>>; Lazar, Lijo 
> mailto:lijo.la...@amd.com>>; Zhang, Hawking
> mailto:hawking.zh...@amd.com>>
> Subject: [PATCH v2 3/5] drm/amdgpu: Add ras helper to query boot
> errors v2
>
> Add ras helper function to query boot time gpu errors.
> v2: use aqua_vanjaram smn addressing pattern
>
> Signed-off-by: Hawking Zhang 
> mailto:hawking.zh...@amd.com>>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h |  1 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 95
> +  drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h |
> 15 +++-
>  3 files changed, 110 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 616b6c911767..cd91533d641c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1328,6 +1328,7 @@ int emu_soc_asic_init(struct amdgpu_device
> *adev);  #define WREG32_FIELD_OFFSET(reg, offset, field, val) \
>   WREG32(mm##reg + offset, (RREG32(mm##reg + offset) &
> ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
>
> +#define AMDGPU_GET_REG_FIELD(x, h, l) (((x) & GENMASK_ULL(h, l)) >>
> +(l))
>  /*
>   * BIOS helpers.
>   */
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> index fc42fb6ee191..a901b00d4949 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> @@ -3763,3 +3763,98 @@ int amdgpu_ras_error_statistic_ce_count(struct
> ras_err_data *err_data,
>
>   return 0;
>  }
> +
> +#define mmMP0_SMN_C2PMSG_92  0x1609C
> +#define mmMP0_SMN_C2PMSG_126 0x160BE
> +static void amdgpu_ras_boot_time_error_reporting(struct amdgpu_device
> *adev,
> +  u32 instance, u32
> +boot_error) {
> + u32 socket_id, aid_id, hbm_id;
> + u32 reg_data;
> + u64 reg_addr;
> +
> + socket_id = AMDGPU_RAS_GPU_ERR_SOCKET_ID(boot_error);
> + aid_id = AMDGPU_RAS_GPU_ERR_AID_ID(boot_error);
> + hbm_id = AMDGPU_RAS_GPU_ERR_HBM_ID(boot_error);
> +
> + /* The pattern for smn addressing in other SOC could be different from
> +  * the one for aqua_vanjaram. We should revisit the code if the pattern
> +  * is changed. In such case, replace the aqua_vanjaram implementation
> +  * with more common helper */
> + reg_addr = (mmMP0_SMN_C2PMSG_92 << 2) +
> +aqua_vanjaram_encode_ext_smn_addressing(instance);
> +
> + reg_data = amdgpu_device_indirect_rreg_ext(adev, reg_addr);
> + dev_err(adev->dev, "socket: %d, aid: %d, firmware boot failed,
> + fw status
> is 0x%x\n",
> + socket_id, aid_id, reg_data);
> +
> + if (AMDGPU_RAS_GPU_ERR_MEM_TRAINING(boot_error))
> + dev_info(adev->dev, "socket: %d, aid: %d, hbm: %d,
> + memory
> training failed\n",
> +  socket_id, aid_id, hbm_id);
> +
> + if (AMDGPU_RAS_GPU_ERR_FW_LOAD(boot_error))
> + dev_info(adev->dev, "socket: %d, aid: %d, firmware load
> + failed at
> boot time\n",
> +  socket_id, aid_id);
> +
> + if (AMDGPU_RAS_GPU_ERR_WAFL_LINK_TRAINING(boot_error))
> + dev_info(adev->dev, "socket: %d, aid: %d, wafl link
> + training
> failed\n",
> +  socket_id, aid_id);
> +
> + if (AMDGPU_RAS_GPU_ERR_XGMI_LINK_TRAINING(boot_error))
> + dev_info(adev->dev, &quo

RE: [PATCH 3/3] drm/amdgpu/gmc11: re-enable AGP

[Zhang, Hawking]

[AMD Official Use Only - General]

Series is

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: amd-gfx  On Behalf Of Alex Deucher
Sent: Thursday, January 4, 2024 05:56
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander 
Subject: [PATCH 3/3] drm/amdgpu/gmc11: re-enable AGP

It should be fixed with
commit ca0b006939f9 ("drm/amdgpu: fix AGP addressing when GART is not at 0") so 
re-enable it.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
index 6c68135cac9f..906f23d13975 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
@@ -643,7 +643,7 @@ static void gmc_v11_0_vram_gtt_location(struct 
amdgpu_device *adev,
amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_HIGH);
if (!amdgpu_sriov_vf(adev) &&
(amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(11, 5, 0)) &&
-   (amdgpu_agp == 1))
+   (amdgpu_agp != 0))
amdgpu_gmc_agp_location(adev, mc);

/* base offset of vram pages */
--
2.42.0

RE: [PATCH] drm/amdgpu: Drop unnecessary sentences about CE and deferred error.

[Zhang, Hawking]

[AMD Official Use Only - General]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: amd-gfx  On Behalf Of Candice Li
Sent: Thursday, January 4, 2024 13:25
To: amd-gfx@lists.freedesktop.org
Cc: Li, Candice 
Subject: [PATCH] drm/amdgpu: Drop unnecessary sentences about CE and deferred 
error.

Remove "no user action is needed" for correctable and deferred error to avoid 
confusion.

Signed-off-by: Candice Li 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 14 +-  
drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c  |  3 +--  
drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c  |  3 +--
 drivers/gpu/drm/amd/amdgpu/umc_v6_7.c   |  2 +-
 4 files changed, 8 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index b21eadd7c975df..caf00df669bf7e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -1069,8 +1069,7 @@ static void amdgpu_ras_error_print_error_data(struct 
amdgpu_device *adev,
mcm_info = _info->mcm_info;
if (err_info->ce_count) {
dev_info(adev->dev, "socket: %d, die: %d, "
-"%lld new correctable hardware errors 
detected in %s block, "
-"no user action is needed\n",
+"%lld new correctable hardware errors 
detected in %s block\n",
 mcm_info->socket_id,
 mcm_info->die_id,
 err_info->ce_count,
@@ -1082,8 +1081,7 @@ static void amdgpu_ras_error_print_error_data(struct 
amdgpu_device *adev,
err_info = _node->err_info;
mcm_info = _info->mcm_info;
dev_info(adev->dev, "socket: %d, die: %d, "
-"%lld correctable hardware errors detected in 
total in %s block, "
-"no user action is needed\n",
+"%lld correctable hardware errors detected in 
total in %s
+block\n",
 mcm_info->socket_id, mcm_info->die_id, 
err_info->ce_count, blk_name);
}
break;
@@ -1139,16 +1137,14 @@ static void amdgpu_ras_error_generate_report(struct 
amdgpu_device *adev,
   adev->smuio.funcs->get_die_id) {
dev_info(adev->dev, "socket: %d, die: %d "
 "%ld correctable hardware errors "
-"detected in %s block, no user "
-"action is needed.\n",
+"detected in %s block\n",
 adev->smuio.funcs->get_socket_id(adev),
 adev->smuio.funcs->get_die_id(adev),
 ras_mgr->err_data.ce_count,
 blk_name);
} else {
dev_info(adev->dev, "%ld correctable hardware errors "
-"detected in %s block, no user "
-"action is needed.\n",
+"detected in %s block\n",
 ras_mgr->err_data.ce_count,
 blk_name);
}
@@ -1978,7 +1974,7 @@ static void 
amdgpu_ras_interrupt_poison_creation_handler(struct ras_manager *obj
struct amdgpu_iv_entry *entry)
 {
dev_info(obj->adev->dev,
-   "Poison is created, no user action is needed.\n");
+   "Poison is created\n");
 }

 static void amdgpu_ras_interrupt_umc_handler(struct ras_manager *obj, diff 
--git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c 
b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
index 6d24c84924cb5d..19986ff6a48d7e 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
@@ -401,8 +401,7 @@ static void 
nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device

if (err_data.ce_count)
dev_info(adev->dev, "%ld correctable hardware "
-   "errors detected in %s block, "
-   "no user action is needed.\n",
+   "errors detected in %s block\n",
obj->err_data.ce_count,

get_ras_block_str(adev->nbio.ras_if));

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c 
b/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c
index 25a3da83e0fb97..e90f3378080345 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c
@@ -597,8 +597,7 @@ static void 

RE: [PATCH 05/14] drm/amdgpu: add amdgpu ras aca query interface

[Zhang, Hawking]

[AMD Official Use Only - General]

I assume we are leveraging error_query_mode to differentiate aca path from 
legacy ras path, right?

But given in-band error reporting is just the start of transition from legacy 
ras to aca, do we need a flag in amdgpu_aca to indicate whether aca is 
supported or not? Accordingly, we can initialize the flag in 
amdgpu_ras_check_supported. it should help us to differentiate aca from legacy 
ras when implementing other features, thoughts?

Regards,
Hawking

-Original Message-
From: Wang, Yang(Kevin) 
Sent: Wednesday, January 3, 2024 16:02
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Zhou1, Tao ; 
Chai, Thomas ; Wang, Yang(Kevin) 
Subject: [PATCH 05/14] drm/amdgpu: add amdgpu ras aca query interface

use new ACA error query interface to instead of legacy MCA query.

Signed-off-by: Yang Wang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 88 -  
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 12 +++-
 2 files changed, 79 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 038bd1b17cef..bbae41f86e00 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -1168,6 +1168,53 @@ static void 
amdgpu_rasmgr_error_data_statistic_update(struct ras_manager *obj, s
}
 }

+static struct ras_manager *get_ras_manager(struct amdgpu_device *adev,
+enum amdgpu_ras_block blk) {
+   struct ras_common_if head;
+
+   memset(, 0, sizeof(head));
+   head.block = blk;
+
+   return amdgpu_ras_find_obj(adev, ); }
+
+int amdgpu_ras_bind_aca(struct amdgpu_device *adev, enum amdgpu_ras_block blk,
+   const struct aca_info *aca_info, void *data) {
+   struct ras_manager *obj;
+
+   obj = get_ras_manager(adev, blk);
+   if (!obj)
+   return -EINVAL;
+
+   return amdgpu_aca_add_handle(adev, >aca_handle,
+ras_block_str(blk), aca_info, data); }
+
+int amdgpu_ras_unbind_aca(struct amdgpu_device *adev, enum
+amdgpu_ras_block blk) {
+   struct ras_manager *obj;
+
+   obj = get_ras_manager(adev, blk);
+   if (!obj)
+   return -EINVAL;
+
+   amdgpu_aca_remove_handle(>aca_handle);
+
+   return 0;
+}
+
+static int amdgpu_aca_log_ras_error_data(struct amdgpu_device *adev, enum 
amdgpu_ras_block blk,
+enum aca_error_type type, struct 
ras_err_data *err_data) {
+   struct ras_manager *obj;
+
+   obj = get_ras_manager(adev, blk);
+   if (!obj)
+   return -EINVAL;
+
+   return amdgpu_aca_get_error_data(adev, >aca_handle, type,
+err_data); }
+
 static int amdgpu_ras_query_error_status_helper(struct amdgpu_device *adev,
struct ras_query_if *info,
struct ras_err_data *err_data,
@@ -1175,6 +1222,7 @@ static int amdgpu_ras_query_error_status_helper(struct 
amdgpu_device *adev,  {
enum amdgpu_ras_block blk = info ? info->head.block : 
AMDGPU_RAS_BLOCK_COUNT;
struct amdgpu_ras_block_object *block_obj = NULL;
+   int ret;

if (blk == AMDGPU_RAS_BLOCK_COUNT)
return -EINVAL;
@@ -1204,9 +1252,13 @@ static int amdgpu_ras_query_error_status_helper(struct 
amdgpu_device *adev,
}
}
} else {
-   /* FIXME: add code to check return value later */
-   amdgpu_mca_smu_log_ras_error(adev, blk, 
AMDGPU_MCA_ERROR_TYPE_UE, err_data);
-   amdgpu_mca_smu_log_ras_error(adev, blk, 
AMDGPU_MCA_ERROR_TYPE_CE, err_data);
+   ret = amdgpu_aca_log_ras_error_data(adev, blk, 
ACA_ERROR_TYPE_UE, err_data);
+   if (ret)
+   return ret;
+
+   ret = amdgpu_aca_log_ras_error_data(adev, blk, 
ACA_ERROR_TYPE_CE, err_data);
+   if (ret)
+   return ret;
}

return 0;
@@ -1254,7 +1306,7 @@ int amdgpu_ras_reset_error_count(struct amdgpu_device 
*adev,  {
struct amdgpu_ras_block_object *block_obj = 
amdgpu_ras_get_ras_block(adev, block, 0);
struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
-   const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs;
+   const struct aca_smu_funcs *smu_funcs = adev->aca.smu_funcs;
struct amdgpu_hive_info *hive;
int hive_ras_recovery = 0;

@@ -1265,7 +1317,7 @@ int amdgpu_ras_reset_error_count(struct amdgpu_device 
*adev,
}

if (!amdgpu_ras_is_supported(adev, block) ||
-   !amdgpu_ras_get_mca_debug_mode(adev))
+   !amdgpu_ras_get_aca_debug_mode(adev))
return -EOPNOTSUPP;

hive = amdgpu_get_xgmi_hive(adev);
@@ -1277,7 +1329,7 @@ int amdgpu_ras_reset_error_count(struct amdgpu_device 
*adev,
/* skip ras error reset in gpu reset */
if ((am

RE: [PATCH 08/14] drm/amdgpu: add gfx v9.4.3 ACA support

[Zhang, Hawking]

[AMD Official Use Only - General]

Simiar as patch #9 and #10, let's use macro to define the magic numbers

+   case 0x36430400: /* SMNAID XCD 0 */
+   case 0x38430400: /* SMNAID XCD 1 */
+   case 0x40430400: /* SMNXCD XCD 0, NOTE: FIXME: fix this error later */

Regards,
Hawking

-Original Message-
From: Wang, Yang(Kevin) 
Sent: Wednesday, January 3, 2024 16:02
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Zhou1, Tao ; 
Chai, Thomas ; Wang, Yang(Kevin) 
Subject: [PATCH 08/14] drm/amdgpu: add gfx v9.4.3 ACA support

add gfx v9.4.3 ACA driver support

Signed-off-by: Yang Wang 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 85 +
 1 file changed, 85 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index 131cddbdda0d..18b8e4dbe9a7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -38,6 +38,7 @@

 #include "gfx_v9_4_3.h"
 #include "amdgpu_xcp.h"
+#include "amdgpu_aca.h"

 MODULE_FIRMWARE("amdgpu/gc_9_4_3_mec.bin");
 MODULE_FIRMWARE("amdgpu/gc_9_4_3_rlc.bin");
@@ -675,6 +676,67 @@ static const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs 
= {
.ih_node_to_logical_xcc = _v9_4_3_ih_to_xcc_inst,  };

+static int gfx_v9_4_3_aca_bank_generate_report(struct aca_handle *handle,
+  struct aca_bank *bank, enum 
aca_error_type type,
+  struct aca_bank_report *report, 
void *data) {
+   u64 status, misc0;
+   u32 instlo;
+   int ret;
+
+   status = bank->regs[ACA_REG_IDX_STATUS];
+   if ((type == ACA_ERROR_TYPE_UE &&
+ACA_REG__STATUS__ERRORCODEEXT(status) == ACA_EXTERROR_CODE_FAULT) 
||
+   (type == ACA_ERROR_TYPE_CE &&
+ACA_REG__STATUS__ERRORCODEEXT(status) == ACA_EXTERROR_CODE_CE)) {
+
+   ret = aca_bank_info_decode(bank, >info);
+   if (ret)
+   return ret;
+
+   /* NOTE: overwrite info.die_id with xcd id for gfx */
+   instlo = 
ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]);
+   instlo &= GENMASK(31, 1);
+   report->info.die_id = instlo == 0x36430400 ? 0 : 1;
+
+   misc0 = bank->regs[ACA_REG_IDX_MISC0];
+   report->count = ACA_REG__MISC0__ERRCNT(misc0);
+   report->type = type;
+   }
+
+   return 0;
+}
+
+static bool gfx_v9_4_3_aca_bank_is_valid(struct aca_handle *handle, struct 
aca_bank *bank,
+enum aca_error_type type, void *data) {
+   u32 instlo;
+
+   instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]);
+   instlo &= GENMASK(31, 1);
+   switch (instlo) {
+   case 0x36430400: /* SMNAID XCD 0 */
+   case 0x38430400: /* SMNAID XCD 1 */
+   case 0x40430400: /* SMNXCD XCD 0, NOTE: FIXME: fix this error later */
+   return true;
+   default:
+   return false;
+   }
+
+   return false;
+}
+
+static const struct aca_bank_ops gfx_v9_4_3_aca_bank_ops = {
+   .aca_bank_generate_report = gfx_v9_4_3_aca_bank_generate_report,
+   .aca_bank_is_valid = gfx_v9_4_3_aca_bank_is_valid, };
+
+static const struct aca_info gfx_v9_4_3_aca_info = {
+   .hwip = ACA_HWIP_TYPE_SMU,
+   .mask = ACA_ERROR_UE_MASK | ACA_ERROR_CE_MASK,
+   .bank_ops = _v9_4_3_aca_bank_ops,
+};
+
 static int gfx_v9_4_3_gpu_early_init(struct amdgpu_device *adev)  {
u32 gb_addr_config;
@@ -4242,9 +4304,32 @@ struct amdgpu_ras_block_hw_ops  gfx_v9_4_3_ras_ops = {
.reset_ras_error_count = _v9_4_3_reset_ras_error_count,
 };

+static int gfx_v9_4_3_ras_late_init(struct amdgpu_device *adev, struct
+ras_common_if *ras_block) {
+   int r;
+
+   r = amdgpu_ras_block_late_init(adev, ras_block);
+   if (r)
+   return r;
+
+   r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__GFX,
+   _v9_4_3_aca_info,
+   NULL);
+   if (r)
+   goto late_fini;
+
+   return 0;
+
+late_fini:
+   amdgpu_ras_block_late_fini(adev, ras_block);
+
+   return r;
+}
+
 struct amdgpu_gfx_ras gfx_v9_4_3_ras = {
.ras_block = {
.hw_ops = _v9_4_3_ras_ops,
+   .ras_late_init = _v9_4_3_ras_late_init,
},
.enable_watchdog_timer = _v9_4_3_enable_watchdog_timer,
 };
--
2.34.1

RE: [PATCH 10/14] drm/amdgpu: add mmhub v1.8 ACA support

[Zhang, Hawking]

[AMD Official Use Only - General]

+   if (instlo != 0x03b30400)

Just nitpick. Let's still use macro to define magic number 0x36430400, 
0x38430400, etc., although the same magic number has different representation 
depending on the IP blocks.

Regards,
Hawking

-Original Message-
From: Wang, Yang(Kevin) 
Sent: Wednesday, January 3, 2024 16:02
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Zhou1, Tao ; 
Chai, Thomas ; Wang, Yang(Kevin) 
Subject: [PATCH 10/14] drm/amdgpu: add mmhub v1.8 ACA support

add mmhub v1.8 ACA driver support

Signed-off-by: Yang Wang 
---
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c | 87 +
 1 file changed, 87 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c 
b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
index fb53aacdcba2..a0a4a2f3227f 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
@@ -705,8 +705,95 @@ static const struct amdgpu_ras_block_hw_ops 
mmhub_v1_8_ras_hw_ops = {
.reset_ras_error_count = mmhub_v1_8_reset_ras_error_count,  };

+static int mmhub_v1_8_aca_bank_generate_report(struct aca_handle *handle,
+  struct aca_bank *bank, enum 
aca_error_type type,
+  struct aca_bank_report *report, 
void *data) {
+   u64 status, misc0;
+   int ret;
+
+   status = bank->regs[ACA_REG_IDX_STATUS];
+   if ((type == ACA_ERROR_TYPE_UE &&
+ACA_REG__STATUS__ERRORCODEEXT(status) == ACA_EXTERROR_CODE_FAULT) 
||
+   (type == ACA_ERROR_TYPE_CE &&
+ACA_REG__STATUS__ERRORCODEEXT(status) == ACA_EXTERROR_CODE_CE)) {
+
+   ret = aca_bank_info_decode(bank, >info);
+   if (ret)
+   return ret;
+
+   misc0 = bank->regs[ACA_REG_IDX_MISC0];
+   report->count = ACA_REG__MISC0__ERRCNT(misc0);
+   report->type = type;
+   }
+
+   return 0;
+}
+
+/* reference to smu driver if header file */ static int
+mmhub_v1_8_err_codes[] = {
+   0, 1, 2, 3, 4, /* CODE_DAGB0 - 4 */
+   5, 6, 7, 8, 9, /* CODE_EA0 - 4 */
+   10, /* CODE_UTCL2_ROUTER */
+   11, /* CODE_VML2 */
+   12, /* CODE_VML2_WALKER */
+   13, /* CODE_MMCANE */
+};
+
+static bool mmhub_v1_8_aca_bank_is_valid(struct aca_handle *handle, struct 
aca_bank *bank,
+enum aca_error_type type, void *data) {
+   u32 instlo;
+
+   instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]);
+   instlo &= GENMASK(31, 1);
+
+   if (instlo != 0x03b30400)
+   return false;
+
+   if (aca_bank_check_error_codes(handle->adev, bank,
+  mmhub_v1_8_err_codes,
+  ARRAY_SIZE(mmhub_v1_8_err_codes)))
+   return false;
+
+   return true;
+}
+
+static const struct aca_bank_ops mmhub_v1_8_aca_bank_ops = {
+   .aca_bank_generate_report = mmhub_v1_8_aca_bank_generate_report,
+   .aca_bank_is_valid = mmhub_v1_8_aca_bank_is_valid, };
+
+static const struct aca_info mmhub_v1_8_aca_info = {
+   .hwip = ACA_HWIP_TYPE_SMU,
+   .mask = ACA_ERROR_UE_MASK,
+   .bank_ops = _v1_8_aca_bank_ops,
+};
+
+static int mmhub_v1_8_ras_late_init(struct amdgpu_device *adev, struct
+ras_common_if *ras_block) {
+   int r;
+
+   r = amdgpu_ras_block_late_init(adev, ras_block);
+   if (r)
+   return r;
+
+   r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__MMHUB,
+   _v1_8_aca_info, NULL);
+   if (r)
+   goto late_fini;
+
+   return 0;
+
+late_fini:
+   amdgpu_ras_block_late_fini(adev, ras_block);
+
+   return r;
+}
+
 struct amdgpu_mmhub_ras mmhub_v1_8_ras = {
.ras_block = {
.hw_ops = _v1_8_ras_hw_ops,
+   .ras_late_init = mmhub_v1_8_ras_late_init,
},
 };
--
2.34.1

RE: [PATCH 11/14] drm/amdgpu: add xgmi v6.4.0 ACA support

[Zhang, Hawking]

[AMD Official Use Only - General]

+   if ((type == ACA_ERROR_TYPE_UE && ext_error_code == 0) ||
+   (type == ACA_ERROR_TYPE_CE && ext_error_code == 6)) {
+   report->type = type;
+   report->count = 
ACA_REG__MISC0__ERRCNT(bank->regs[ACA_REG_IDX_MISC0]);
+   }

Gentle reminder that we should be able to extend the error logging to all the 
pcs errors. Just read back the config registers so we know which error is 
configured to UE and which error is configured to CE.

Regards,
Hawking


-Original Message-
From: Wang, Yang(Kevin) 
Sent: Wednesday, January 3, 2024 16:02
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Zhou1, Tao ; 
Chai, Thomas ; Wang, Yang(Kevin) 
Subject: [PATCH 11/14] drm/amdgpu: add xgmi v6.4.0 ACA support

add xgmi v6.4.0 ACA driver support

Signed-off-by: Yang Wang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 63 +++-
 1 file changed, 62 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
index a6c88f2fe6e5..61208ca94442 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
@@ -1035,15 +1035,76 @@ int amdgpu_xgmi_remove_device(struct amdgpu_device 
*adev)
return 0;
 }

+static int xgmi_v6_4_0_aca_bank_generate_report(struct aca_handle *handle, 
struct aca_bank *bank, enum aca_error_type type,
+   struct aca_bank_report *report, 
void *data) {
+   struct amdgpu_device *adev = handle->adev;
+   const char *error_str;
+   u64 status;
+   int ret, ext_error_code;
+
+   ret = aca_bank_info_decode(bank, >info);
+   if (ret)
+   return ret;
+
+   status = bank->regs[MCA_REG_IDX_STATUS];
+   ext_error_code = MCA_REG__STATUS__ERRORCODEEXT(status);
+
+   error_str = ext_error_code < ARRAY_SIZE(xgmi_v6_4_0_ras_error_code_ext) 
?
+   xgmi_v6_4_0_ras_error_code_ext[ext_error_code] : NULL;
+   if (error_str)
+   dev_info(adev->dev, "%s detected\n", error_str);
+
+   if ((type == ACA_ERROR_TYPE_UE && ext_error_code == 0) ||
+   (type == ACA_ERROR_TYPE_CE && ext_error_code == 6)) {
+   report->type = type;
+   report->count = 
ACA_REG__MISC0__ERRCNT(bank->regs[ACA_REG_IDX_MISC0]);
+   }
+
+   return 0;
+}
+
+static const struct aca_bank_ops xgmi_v6_4_0_aca_bank_ops = {
+   .aca_bank_generate_report = xgmi_v6_4_0_aca_bank_generate_report,
+};
+
+static const struct aca_info xgmi_v6_4_0_aca_info = {
+   .hwip = ACA_HWIP_TYPE_PCS_XGMI,
+   .mask = ACA_ERROR_UE_MASK | ACA_ERROR_CE_MASK,
+   .bank_ops = _v6_4_0_aca_bank_ops, };
+
 static int amdgpu_xgmi_ras_late_init(struct amdgpu_device *adev, struct 
ras_common_if *ras_block)  {
+   int r;
+
if (!adev->gmc.xgmi.supported ||
adev->gmc.xgmi.num_physical_nodes == 0)
return 0;

amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__XGMI_WAFL);

-   return amdgpu_ras_block_late_init(adev, ras_block);
+   r = amdgpu_ras_block_late_init(adev, ras_block);
+   if (r)
+   return r;
+
+   switch (amdgpu_ip_version(adev, XGMI_HWIP, 0)) {
+   case IP_VERSION(6, 4, 0):
+   r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__XGMI_WAFL,
+   _v6_4_0_aca_info, NULL);
+   if (r)
+   goto late_fini;
+   break;
+   default:
+   break;
+   }
+
+   return 0;
+
+late_fini:
+   amdgpu_ras_block_late_fini(adev, ras_block);
+
+   return r;
 }

 uint64_t amdgpu_xgmi_get_relative_phy_addr(struct amdgpu_device *adev,
--
2.34.1

RE: [PATCH 2/2] drm/amdgpu: skip gpu_info fw loading on navi12

[Zhang, Hawking]

[AMD Official Use Only - General]

Series is

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: amd-gfx  On Behalf Of Alex Deucher
Sent: Friday, December 22, 2023 02:11
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander 
Subject: [PATCH 2/2] drm/amdgpu: skip gpu_info fw loading on navi12

It's no longer required.

Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2318
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 11 ++-
 1 file changed, 2 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 9c1ff893c03c..71e8fe2144b4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2251,15 +2251,8 @@ static int amdgpu_device_parse_gpu_info_fw(struct 
amdgpu_device *adev)

adev->firmware.gpu_info_fw = NULL;

-   if (adev->mman.discovery_bin) {
-   /*
-* FIXME: The bounding box is still needed by Navi12, so
-* temporarily read it from gpu_info firmware. Should be dropped
-* when DAL no longer needs it.
-*/
-   if (adev->asic_type != CHIP_NAVI12)
-   return 0;
-   }
+   if (adev->mman.discovery_bin)
+   return 0;

switch (adev->asic_type) {
default:
--
2.42.0

RE: [PATCH 02/14] drm/amdgpu: add ACA kernel hardware error log support

[Zhang, Hawking]

[AMD Official Use Only - General]


+   dev_info(adev->dev, "[Hardware error] Accelerator Check Architecture 
events logged\n");
+   /* plus 1 for output format, e.g: ACA[08/08]:  */
+   for (i = 0; i < ARRAY_SIZE(aca_regs); i++)
+   dev_info(adev->dev, "[Hardware error] 
ACA[%02d/%02d].%s=0x%016llx\n",
+idx + 1, total, aca_regs[i].name, 
bank->regs[aca_regs[i].reg_idx]);

We should keep the ACA log format simple since there are tools like crash 
dumper that grab these logs.

How about formatting log as below
dev_info(adev->dev, "[Hardware error] Accelerator Check Architecture (ACA) 
events logged\n");
dev_info(adev→dev, "[Hardware error] ACA.%s=0x%016llx\n");

In general, if the idx doesn't convey useful information, then just replace it 
with ACA.Reg.

Thoughts?

Regards,
Hawking

-Original Message-
From: Wang, Yang(Kevin) mailto:kevinyang.w...@amd.com>>
Sent: Wednesday, January 3, 2024 16:02
To: amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org>
Cc: Zhang, Hawking mailto:hawking.zh...@amd.com>>; 
Zhou1, Tao mailto:tao.zh...@amd.com>>; Chai, Thomas 
mailto:yipeng.c...@amd.com>>; Wang, Yang(Kevin) 
mailto:kevinyang.w...@amd.com>>
Subject: [PATCH 02/14] drm/amdgpu: add ACA kernel hardware error log support

add ACA kernel hardware error log support.

Signed-off-by: Yang Wang mailto:kevinyang.w...@amd.com>>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c | 29 +
 1 file changed, 29 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c
index 6a6f167b5380..cadeda64eded 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c
@@ -100,6 +100,33 @@ static int aca_smu_get_valid_aca_count(struct 
amdgpu_device *adev, enum aca_erro
return smu_funcs->get_valid_aca_count(adev, type, count);  }

+static struct aca_regs_dump {
+   const char *name;
+   int reg_idx;
+} aca_regs[] = {
+   {"CONTROL", ACA_REG_IDX_CTL},
+   {"STATUS",  ACA_REG_IDX_STATUS},
+   {"ADDR",ACA_REG_IDX_ADDR},
+   {"MISC",ACA_REG_IDX_MISC0},
+   {"CONFIG",  ACA_REG_IDX_CONFG},
+   {"IPID",ACA_REG_IDX_IPID},
+   {"SYND",ACA_REG_IDX_SYND},
+   {"DESTAT",  ACA_REG_IDX_DESTAT},
+   {"DEADDR",  ACA_REG_IDX_DEADDR},
+   {"CONTROL_MASK",ACA_REG_IDX_CTL_MASK},
+};
+
+static void aca_smu_bank_dump(struct amdgpu_device *adev, int idx, int
+total, struct aca_bank *bank) {
+   int i;
+
+   dev_info(adev->dev, "[Hardware error] Accelerator Check Architecture 
events logged\n");
+   /* plus 1 for output format, e.g: ACA[08/08]:  */
+   for (i = 0; i < ARRAY_SIZE(aca_regs); i++)
+   dev_info(adev->dev, "[Hardware error] 
ACA[%02d/%02d].%s=0x%016llx\n",
+idx + 1, total, aca_regs[i].name, 
bank->regs[aca_regs[i].reg_idx]);
+}
+
 static int aca_smu_get_valid_aca_banks(struct amdgpu_device *adev, enum 
aca_error_type type,
   int start, int count,
   struct aca_banks *banks)
@@ -137,6 +164,8 @@ static int aca_smu_get_valid_aca_banks(struct amdgpu_device 
*adev, enum aca_erro
if (ret)
return ret;

+   aca_smu_bank_dump(adev, i, count, );
+
ret = aca_banks_add_bank(banks, );
if (ret)
return ret;
--
2.34.1

RE: [PATCH 1/1] drm/amdgpu: add param to specify fw bo location for front-door loading

[Zhang, Hawking]

[AMD Official Use Only - General]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: Ma, Le 
Sent: Wednesday, January 3, 2024 16:07
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Lazar, Lijo 
Subject: [PATCH 1/1] drm/amdgpu: add param to specify fw bo location for 
front-door loading

This param can help isolating data path issues on new systems in early phase.

Change-Id: I0a972dd74fe2aad6b56628cea32ad72dcd17e283
Signed-off-by: Le Ma 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h   | 2 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c   | 5 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c   | 2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 3 ++-
 4 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 616b6c911767..9da14436a373 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -254,6 +254,8 @@ extern int amdgpu_agp;

 extern int amdgpu_wbrf;

+extern int fw_bo_location;
+
 #define AMDGPU_VM_MAX_NUM_CTX  4096
 #define AMDGPU_SG_THRESHOLD(256*1024*1024)
 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 880137774b4e..852cec98ff26 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -210,6 +210,7 @@ int amdgpu_seamless = -1; /* auto */  uint 
amdgpu_debug_mask;  int amdgpu_agp = -1; /* auto */  int amdgpu_wbrf = -1;
+int fw_bo_location = -1;

 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work);

@@ -989,6 +990,10 @@ MODULE_PARM_DESC(wbrf,
"Enable Wifi RFI interference mitigation (0 = disabled, 1 = enabled, -1 
= auto(default)");  module_param_named(wbrf, amdgpu_wbrf, int, 0444);

+MODULE_PARM_DESC(fw_bo_location,
+   "location to put firmware bo for frontdoor loading (-1 = auto
+(default), 0 = on ram, 1 = on vram"); module_param(fw_bo_location, int,
+0644);
+
 /* These devices are not supported by amdgpu.
  * They are supported by the mach64, r128, radeon drivers
  */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 1bf975b8d083..2addbdf88394 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -466,7 +466,7 @@ static int psp_sw_init(void *handle)
}

ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
- amdgpu_sriov_vf(adev) ?
+ (amdgpu_sriov_vf(adev) || fw_bo_location 
== 1) ?
  AMDGPU_GEM_DOMAIN_VRAM : 
AMDGPU_GEM_DOMAIN_GTT,
  >fw_pri_bo,
  >fw_pri_mc_addr,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index b14127429f30..1f67914568f6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -1062,7 +1062,8 @@ int amdgpu_ucode_create_bo(struct amdgpu_device *adev)  {
if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT) {
amdgpu_bo_create_kernel(adev, adev->firmware.fw_size, PAGE_SIZE,
-   amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : 
AMDGPU_GEM_DOMAIN_GTT,
+   (amdgpu_sriov_vf(adev) || fw_bo_location == 1) ?
+   AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
>firmware.fw_buf,
>firmware.fw_buf_mc,
>firmware.fw_buf_ptr);
--
2.38.1

RE: [PATCH 2/5] drm/amdgpu: Init pcie_index/data address as fallback

[Zhang, Hawking]

[AMD Official Use Only - General]

Sure, will do in v2

Regards,
Hawking

-Original Message-
From: Alex Deucher 
Sent: Wednesday, January 3, 2024 03:44
To: Zhang, Hawking 
Cc: amd-gfx@lists.freedesktop.org; Zhou1, Tao ; Yang, 
Stanley ; Wang, Yang(Kevin) ; 
Chai, Thomas ; Li, Candice ; Deucher, 
Alexander ; Ma, Le ; Lazar, Lijo 

Subject: Re: [PATCH 2/5] drm/amdgpu: Init pcie_index/data address as fallback

On Mon, Jan 1, 2024 at 10:50 PM Hawking Zhang  wrote:
>
> To allow using this helper for indirect access when nbio funcs is not
> available. For instance, in ip discovery phase.
>
> Signed-off-by: Hawking Zhang 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 20 +++-
>  1 file changed, 15 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 001a35fa0f19..873419a5b9aa 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -781,12 +781,22 @@ u32 amdgpu_device_indirect_rreg_ext(struct 
> amdgpu_device *adev,
> void __iomem *pcie_index_hi_offset;
> void __iomem *pcie_data_offset;
>
> -   pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
> -   pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
> -   if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offset))
> -   pcie_index_hi = 
> adev->nbio.funcs->get_pcie_index_hi_offset(adev);
> -   else
> +   if (unlikely(!adev->nbio.funcs)) {
> +   pcie_index = (0x38 >> 2);
> +   pcie_data = (0x3C >> 2);
> +   } else {
> +   pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
> +   pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
> +   }
> +
> +   if (reg_addr >> 32) {
> +   if (unlikely(!adev->nbio.funcs))
> +   pcie_index_hi = (0x44 >> 2);

I'd still use a define for these, E.g.,

#define AMDGPU_PCIE_INDEX_FALLBACK (0x38 >> 2) etc.
Or something similar.

Alex

> +   else
> +   pcie_index_hi = 
> adev->nbio.funcs->get_pcie_index_hi_offset(adev);
> +   } else {
> pcie_index_hi = 0;
> +   }
>
> spin_lock_irqsave(>pcie_idx_lock, flags);
> pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index *
> 4;
> --
> 2.17.1
>

RE: [PATCH 4/5] drm/amdgpu: Query boot status if discovery failed

[Zhang, Hawking]

[AMD Official Use Only - General]

Yes, it is.

Regards,
Hawking

From: Deucher, Alexander 
Sent: Wednesday, January 3, 2024 03:45
To: Zhang, Hawking ; amd-gfx@lists.freedesktop.org; 
Zhou1, Tao ; Yang, Stanley ; Wang, 
Yang(Kevin) ; Chai, Thomas ; Li, 
Candice 
Cc: Lazar, Lijo ; Ma, Le 
Subject: Re: [PATCH 4/5] drm/amdgpu: Query boot status if discovery failed


[AMD Official Use Only - General]

Is mmIP_DISCOVERY_VERSION at the same offset across ASIC families?

Alex


From: Hawking Zhang mailto:hawking.zh...@amd.com>>
Sent: Monday, January 1, 2024 10:43 PM
To: amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org> 
mailto:amd-gfx@lists.freedesktop.org>>; Zhou1, 
Tao mailto:tao.zh...@amd.com>>; Yang, Stanley 
mailto:stanley.y...@amd.com>>; Wang, Yang(Kevin) 
mailto:kevinyang.w...@amd.com>>; Chai, Thomas 
mailto:yipeng.c...@amd.com>>; Li, Candice 
mailto:candice...@amd.com>>
Cc: Zhang, Hawking mailto:hawking.zh...@amd.com>>; 
Deucher, Alexander 
mailto:alexander.deuc...@amd.com>>; Lazar, Lijo 
mailto:lijo.la...@amd.com>>; Ma, Le 
mailto:le...@amd.com>>
Subject: [PATCH 4/5] drm/amdgpu: Query boot status if discovery failed

Check and report boot status if discovery failed.

Signed-off-by: Hawking Zhang 
mailto:hawking.zh...@amd.com>>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index b8fde08aec8e..302b71e9f1e2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -27,6 +27,7 @@
 #include "amdgpu_discovery.h"
 #include "soc15_hw_ip.h"
 #include "discovery.h"
+#include "amdgpu_ras.h"

 #include "soc15.h"
 #include "gfx_v9_0.h"
@@ -98,6 +99,7 @@
 #define FIRMWARE_IP_DISCOVERY "amdgpu/ip_discovery.bin"
 MODULE_FIRMWARE(FIRMWARE_IP_DISCOVERY);

+#define mmIP_DISCOVERY_VERSION  0x16A00
 #define mmRCC_CONFIG_MEMSIZE0xde3
 #define mmMP0_SMN_C2PMSG_33 0x16061
 #define mmMM_INDEX  0x0
@@ -518,7 +520,9 @@ static int amdgpu_discovery_init(struct amdgpu_device *adev)
 out:
 kfree(adev->mman.discovery_bin);
 adev->mman.discovery_bin = NULL;
-
+   if ((amdgpu_discovery != 2) &&
+   (RREG32(mmIP_DISCOVERY_VERSION) == 4))
+   amdgpu_ras_query_boot_status(adev, 4);
 return r;
 }

--
2.17.1

RE: [PATCH 4/5] drm/amdgpu: Query boot status if discovery failed

[Zhang, Hawking]

[AMD Official Use Only - General]

RE - I'm not sure about hard-coding 4 instances here. The code you dropped in 
patch 1 was using adev->aid_mask. But I guess that's not even initialized 
correctly if IP discovery failed. Will this work correctly on the APU version?

Yes aid_mask is not initialized. IP_DISCOVERY_VERSION is the only available 
fuse setting that can be used to identify or equivalent to 4 instances of aid 
in such case. We switched to a common mailbox reg that works for both APU and 
dGPU. The expectation is for APU, driver still reports fw boot status, while it 
gives next level information on the failures if boot fails on dGPU.

Regards,
Hawking

-Original Message-
From: Kuehling, Felix 
Sent: Wednesday, January 3, 2024 01:49
To: Zhang, Hawking ; amd-gfx@lists.freedesktop.org; 
Zhou1, Tao ; Yang, Stanley ; Wang, 
Yang(Kevin) ; Chai, Thomas ; Li, 
Candice 
Cc: Deucher, Alexander ; Ma, Le ; 
Lazar, Lijo 
Subject: Re: [PATCH 4/5] drm/amdgpu: Query boot status if discovery failed


On 2024-01-02 09:07, Hawking Zhang wrote:
> Check and report boot status if discovery failed.
>
> Signed-off-by: Hawking Zhang 
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 6 +-
>   1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> index b8fde08aec8e..302b71e9f1e2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> @@ -27,6 +27,7 @@
>   #include "amdgpu_discovery.h"
>   #include "soc15_hw_ip.h"
>   #include "discovery.h"
> +#include "amdgpu_ras.h"
>
>   #include "soc15.h"
>   #include "gfx_v9_0.h"
> @@ -98,6 +99,7 @@
>   #define FIRMWARE_IP_DISCOVERY "amdgpu/ip_discovery.bin"
>   MODULE_FIRMWARE(FIRMWARE_IP_DISCOVERY);
>
> +#define mmIP_DISCOVERY_VERSION  0x16A00
>   #define mmRCC_CONFIG_MEMSIZE0xde3
>   #define mmMP0_SMN_C2PMSG_33 0x16061
>   #define mmMM_INDEX  0x0
> @@ -518,7 +520,9 @@ static int amdgpu_discovery_init(struct amdgpu_device 
> *adev)
>   out:
>   kfree(adev->mman.discovery_bin);
>   adev->mman.discovery_bin = NULL;
> -
> + if ((amdgpu_discovery != 2) &&
> + (RREG32(mmIP_DISCOVERY_VERSION) == 4))
> + amdgpu_ras_query_boot_status(adev, 4);
I'm not sure about hard-coding 4 instances here. The code you dropped in patch 
1 was using adev->aid_mask. But I guess that's not even initialized correctly 
if IP discovery failed. Will this work correctly on the APU version?

Regards,
   Felix


>   return r;
>   }
>

RE: [PATCH 2/3] drm/amdgpu: Query ras capablity from psp

[Zhang, Hawking]

[AMD Official Use Only - General]

Oh, that's good point. I guess Kevin mentioned the same thing. Yes. Returning 
directly is reasonable to me.

Regards,
Hawking

-Original Message-
From: Zhou1, Tao 
Sent: Tuesday, January 2, 2024 16:49
To: Zhang, Hawking ; Wang, Yang(Kevin) 
; amd-gfx@lists.freedesktop.org; Yang, Stanley 
; Chai, Thomas ; Li, Candice 

Cc: Deucher, Alexander ; Lazar, Lijo 
; Ma, Le 
Subject: RE: [PATCH 2/3] drm/amdgpu: Query ras capablity from psp

[AMD Official Use Only - General]

> -Original Message-
> From: Zhang, Hawking 
> Sent: Tuesday, January 2, 2024 1:38 PM
> To: Wang, Yang(Kevin) ; amd-
> g...@lists.freedesktop.org; Zhou1, Tao ; Yang,
> Stanley ; Chai, Thomas ;
> Li, Candice 
> Cc: Deucher, Alexander ; Lazar, Lijo
> ; Ma, Le 
> Subject: RE: [PATCH 2/3] drm/amdgpu: Query ras capablity from psp
>
> [AMD Official Use Only - General]
>
> The ret gives us a chance to fallback to legacy query approach (from vbios).
>
>
> You might want to see patch #3 of the series for more details, go to
> the following lines in patch #3
>
> +   /* query ras capability from psp */
> +   if (amdgpu_psp_get_ras_capability(>psp))
> +   goto init_ras_enabled_flag;
>
>
> Regards,
> Hawking
>
> -Original Message-
> From: Wang, Yang(Kevin) 
> Sent: Tuesday, January 2, 2024 13:19
> To: Zhang, Hawking ;
> amd-gfx@lists.freedesktop.org; Zhou1, Tao ; Yang,
> Stanley ; Chai, Thomas ;
> Li, Candice 
> Cc: Zhang, Hawking ; Deucher, Alexander
> ; Lazar, Lijo ; Ma, Le
> 
> Subject: RE: [PATCH 2/3] drm/amdgpu: Query ras capablity from psp
>
> [AMD Official Use Only - General]
>
> -Original Message-
> From: Hawking Zhang 
> Sent: Tuesday, January 2, 2024 11:45 AM
> To: amd-gfx@lists.freedesktop.org; Zhou1, Tao ;
> Yang, Stanley ; Wang, Yang(Kevin)
> ; Chai, Thomas ; Li,
> Candice 
> Cc: Zhang, Hawking ; Deucher, Alexander
> ; Lazar, Lijo ; Ma, Le
> 
> Subject: [PATCH 2/3] drm/amdgpu: Query ras capablity from psp
>
> Instead of traditional atomfirmware interfaces for RAS capability,
> host driver can query ras capability from psp starting from psp v13_0_6.
>
> Signed-off-by: Hawking Zhang 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 13 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h |  2 ++
> drivers/gpu/drm/amd/amdgpu/psp_v13_0.c  | 26 +
>  3 files changed, 41 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> index 94b536e3cada..8a3847d3041f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> @@ -2125,6 +2125,19 @@ int amdgpu_psp_wait_for_bootloader(struct
> amdgpu_device *adev)
> return ret;
>  }
>
> +bool amdgpu_psp_get_ras_capability(struct psp_context *psp) {
> +   bool ret;
> +
> +   if (psp->funcs &&
> +   psp->funcs->get_ras_capability) {
> +   ret = psp->funcs->get_ras_capability(psp);
> +   return ret;

[Tao] I think the code can be simplified as:

return psp->funcs->get_ras_capability(psp);

and drop the ret variable.

> [kevin]:
> This variable 'ret' seems to have no other purpose, can we remove it
> and return directly ?
>
> Best Regards,
> Kevin
> +   } else {
> +   return false;
> +   }
> +}
> +
>  static int psp_hw_start(struct psp_context *psp)  {
> struct amdgpu_device *adev = psp->adev; diff --git
> a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
> index 09d1f8f72a9c..652b0a01854a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
> @@ -134,6 +134,7 @@ struct psp_funcs {
> int (*update_spirom)(struct psp_context *psp, uint64_t 
> fw_pri_mc_addr);
> int (*vbflash_stat)(struct psp_context *psp);
> int (*fatal_error_recovery_quirk)(struct psp_context *psp);
> +   bool (*get_ras_capability)(struct psp_context *psp);
>  };
>
>  struct ta_funcs {
> @@ -537,4 +538,5 @@ int psp_spatial_partition(struct psp_context *psp,
> int mode);  int is_psp_fw_valid(struct psp_bin_desc bin);
>
>  int amdgpu_psp_wait_for_bootloader(struct amdgpu_device *adev);
> +bool amdgpu_psp_get_ras_capability(struct psp_context *psp);
>  #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
> b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
> index 676bec2cc157..722b6066ce07 100644
> --- a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
> @@ -27,6 +27,7 @@
>  #include "amdgpu_ucode.h"
>  #include &

RE: [PATCH 3/5] drm/amdgpu: Add ras helper to query boot errors

[Zhang, Hawking]

[AMD Official Use Only - General]

Good point, Le, will switch to the existing helper for the cross die access in 
v2.

Regards,
Hawking

-Original Message-
From: Ma, Le 
Sent: Tuesday, January 2, 2024 14:45
To: Zhang, Hawking ; amd-gfx@lists.freedesktop.org; 
Zhou1, Tao ; Yang, Stanley ; Wang, 
Yang(Kevin) ; Chai, Thomas ; Li, 
Candice 
Cc: Zhang, Hawking ; Deucher, Alexander 
; Lazar, Lijo 
Subject: RE: [PATCH 3/5] drm/amdgpu: Add ras helper to query boot errors

[AMD Official Use Only - General]

> -Original Message-
> From: Hawking Zhang 
> Sent: Tuesday, January 2, 2024 11:44 AM
> To: amd-gfx@lists.freedesktop.org; Zhou1, Tao ;
> Yang, Stanley ; Wang, Yang(Kevin)
> ; Chai, Thomas ; Li,
> Candice 
> Cc: Zhang, Hawking ; Deucher, Alexander
> ; Lazar, Lijo ; Ma, Le
> 
> Subject: [PATCH 3/5] drm/amdgpu: Add ras helper to query boot errors
>
> Add ras helper function to query boot time gpu errors.
>
> Signed-off-by: Hawking Zhang 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h |  3 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 95
> +  drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h |
> 15 +++-
>  3 files changed, 112 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 616b6c911767..db44ec857a31 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1328,6 +1328,9 @@ int emu_soc_asic_init(struct amdgpu_device
> *adev);  #define WREG32_FIELD_OFFSET(reg, offset, field, val) \
>   WREG32(mm##reg + offset, (RREG32(mm##reg + offset) &
> ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
>
> +#define AMDGPU_SMN_TARGET_AID(x) ((u64)(x) << 32) #define
> +AMDGPU_SMN_CROSS_AID (1ULL << 34) #define AMDGPU_GET_REG_FIELD(x,
> h, l)
> +(((x) & GENMASK_ULL(h, l)) >> (l))
>  /*
>   * BIOS helpers.
>   */
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> index 39399d0f2ce5..5f302b7693b3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> @@ -3764,3 +3764,98 @@ int amdgpu_ras_error_statistic_ce_count(struct
> ras_err_data *err_data,
>
>   return 0;
>  }
> +
> +#define mmMP0_SMN_C2PMSG_92  0x1609C
> +#define mmMP0_SMN_C2PMSG_126 0x160BE
> +static void amdgpu_ras_boot_time_error_reporting(struct amdgpu_device
> *adev,
> +  u32 instance, u32
> +boot_error) {
> + u32 socket_id, aid_id, hbm_id;
> + u32 reg_data;
> + u64 reg_addr;
> +
> + socket_id = AMDGPU_RAS_GPU_ERR_SOCKET_ID(boot_error);
> + aid_id = AMDGPU_RAS_GPU_ERR_AID_ID(boot_error);
> + hbm_id = AMDGPU_RAS_GPU_ERR_HBM_ID(boot_error);
> +
> + if (instance)
> + reg_addr = (mmMP0_SMN_C2PMSG_92 << 2) +
> +AMDGPU_SMN_TARGET_AID(instance) +
> +AMDGPU_SMN_CROSS_AID;
Hi Hawking,

We have asic function "aqua_vanjaram_encode_ext_smn_addressing" for this stuff, 
maybe it could also be re-used here.

Thanks.
> + else
> + reg_addr = (mmMP0_SMN_C2PMSG_92 << 2);
> +
> + reg_data = amdgpu_device_indirect_rreg_ext(adev, reg_addr);
> + dev_err(adev->dev, "socket: %d, aid: %d, firmware boot failed,
> + fw
> status is 0x%x\n",
> + socket_id, aid_id, reg_data);
> +
> + if (AMDGPU_RAS_GPU_ERR_MEM_TRAINING(boot_error))
> + dev_info(adev->dev, "socket: %d, aid: %d, hbm: %d,
> + memory
> training failed\n",
> +  socket_id, aid_id, hbm_id);
> +
> + if (AMDGPU_RAS_GPU_ERR_FW_LOAD(boot_error))
> + dev_info(adev->dev, "socket: %d, aid: %d, firmware load
> + failed
> at boot time\n",
> +  socket_id, aid_id);
> +
> + if (AMDGPU_RAS_GPU_ERR_WAFL_LINK_TRAINING(boot_error))
> + dev_info(adev->dev, "socket: %d, aid: %d, wafl link
> + training
> failed\n",
> +  socket_id, aid_id);
> +
> + if (AMDGPU_RAS_GPU_ERR_XGMI_LINK_TRAINING(boot_error))
> + dev_info(adev->dev, "socket: %d, aid: %d, xgmi link
> + training
> failed\n",
> +  socket_id, aid_id);
> +
> + if (AMDGPU_RAS_GPU_ERR_USR_CP_LINK_TRAINING(boot_error))
> + dev_info(adev->dev, "socket: %d, aid: %d, usr cp link
> + training
> failed\n",
> +  socket_id, aid_id);
> +
> + if (AMDGPU_RAS_GPU_ERR_USR_DP_LINK_TRAINING(boot_error))
> + dev_info(adev->dev, &

RE: [PATCH 3/5] drm/amdgpu: Add ras helper to query boot errors

[Zhang, Hawking]

[AMD Official Use Only - General]

I was hoping the macro could be used for 64bit registers as well. i.e., the aca 
regs.

Regards,
Hawking

-Original Message-
From: Wang, Yang(Kevin) 
Sent: Tuesday, January 2, 2024 13:24
To: Zhang, Hawking ; amd-gfx@lists.freedesktop.org; 
Zhou1, Tao ; Yang, Stanley ; Chai, 
Thomas ; Li, Candice 
Cc: Zhang, Hawking ; Deucher, Alexander 
; Lazar, Lijo ; Ma, Le 

Subject: RE: [PATCH 3/5] drm/amdgpu: Add ras helper to query boot errors

[AMD Official Use Only - General]

-Original Message-
From: Hawking Zhang 
Sent: Tuesday, January 2, 2024 11:44 AM
To: amd-gfx@lists.freedesktop.org; Zhou1, Tao ; Yang, 
Stanley ; Wang, Yang(Kevin) ; 
Chai, Thomas ; Li, Candice 
Cc: Zhang, Hawking ; Deucher, Alexander 
; Lazar, Lijo ; Ma, Le 

Subject: [PATCH 3/5] drm/amdgpu: Add ras helper to query boot errors

Add ras helper function to query boot time gpu errors.

Signed-off-by: Hawking Zhang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h |  3 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 95 +  
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 15 +++-
 3 files changed, 112 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 616b6c911767..db44ec857a31 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1328,6 +1328,9 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
 #define WREG32_FIELD_OFFSET(reg, offset, field, val)   \
WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & 
~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))

+#define AMDGPU_SMN_TARGET_AID(x) ((u64)(x) << 32) #define
+AMDGPU_SMN_CROSS_AID (1ULL << 34) #define AMDGPU_GET_REG_FIELD(x, h, l)
+(((x) & GENMASK_ULL(h, l)) >> (l))

[kevin]:
The macro GENMASK_ULL() will return a 64bit mask value, but the register is 32 
bits (in this patch),  do we need to change it to GENMASK() ? or you want to 
cover 64bit register cases..
Thanks.

Best Regards,
Kevin
 /*
  * BIOS helpers.
  */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 39399d0f2ce5..5f302b7693b3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -3764,3 +3764,98 @@ int amdgpu_ras_error_statistic_ce_count(struct 
ras_err_data *err_data,

return 0;
 }
+
+#define mmMP0_SMN_C2PMSG_920x1609C
+#define mmMP0_SMN_C2PMSG_126   0x160BE
+static void amdgpu_ras_boot_time_error_reporting(struct amdgpu_device *adev,
+u32 instance, u32
+boot_error) {
+   u32 socket_id, aid_id, hbm_id;
+   u32 reg_data;
+   u64 reg_addr;
+
+   socket_id = AMDGPU_RAS_GPU_ERR_SOCKET_ID(boot_error);
+   aid_id = AMDGPU_RAS_GPU_ERR_AID_ID(boot_error);
+   hbm_id = AMDGPU_RAS_GPU_ERR_HBM_ID(boot_error);
+
+   if (instance)
+   reg_addr = (mmMP0_SMN_C2PMSG_92 << 2) +
+  AMDGPU_SMN_TARGET_AID(instance) +
+  AMDGPU_SMN_CROSS_AID;
+   else
+   reg_addr = (mmMP0_SMN_C2PMSG_92 << 2);
+
+   reg_data = amdgpu_device_indirect_rreg_ext(adev, reg_addr);
+   dev_err(adev->dev, "socket: %d, aid: %d, firmware boot failed, fw 
status is 0x%x\n",
+   socket_id, aid_id, reg_data);
+
+   if (AMDGPU_RAS_GPU_ERR_MEM_TRAINING(boot_error))
+   dev_info(adev->dev, "socket: %d, aid: %d, hbm: %d, memory 
training failed\n",
+socket_id, aid_id, hbm_id);
+
+   if (AMDGPU_RAS_GPU_ERR_FW_LOAD(boot_error))
+   dev_info(adev->dev, "socket: %d, aid: %d, firmware load failed 
at boot time\n",
+socket_id, aid_id);
+
+   if (AMDGPU_RAS_GPU_ERR_WAFL_LINK_TRAINING(boot_error))
+   dev_info(adev->dev, "socket: %d, aid: %d, wafl link training 
failed\n",
+socket_id, aid_id);
+
+   if (AMDGPU_RAS_GPU_ERR_XGMI_LINK_TRAINING(boot_error))
+   dev_info(adev->dev, "socket: %d, aid: %d, xgmi link training 
failed\n",
+socket_id, aid_id);
+
+   if (AMDGPU_RAS_GPU_ERR_USR_CP_LINK_TRAINING(boot_error))
+   dev_info(adev->dev, "socket: %d, aid: %d, usr cp link training 
failed\n",
+socket_id, aid_id);
+
+   if (AMDGPU_RAS_GPU_ERR_USR_DP_LINK_TRAINING(boot_error))
+   dev_info(adev->dev, "socket: %d, aid: %d, usr dp link training 
failed\n",
+socket_id, aid_id);
+
+   if (AMDGPU_RAS_GPU_ERR_HBM_MEM_TEST(boot_error))
+   dev_info(adev->dev, "socket: %d, aid: %d, hbm: %d, hbm memory 
test failed\n",
+socket_id, aid_id, hbm_id);
+
+   if (AMDGPU_RAS_GPU_ERR_HBM_BIST_TEST(boot_err

RE: [PATCH 2/3] drm/amdgpu: Query ras capablity from psp

[Zhang, Hawking]

[AMD Official Use Only - General]

The ret gives us a chance to fallback to legacy query approach (from vbios).


You might want to see patch #3 of the series for more details, go to the 
following lines in patch #3

+   /* query ras capability from psp */
+   if (amdgpu_psp_get_ras_capability(>psp))
+   goto init_ras_enabled_flag;


Regards,
Hawking

-Original Message-
From: Wang, Yang(Kevin) 
Sent: Tuesday, January 2, 2024 13:19
To: Zhang, Hawking ; amd-gfx@lists.freedesktop.org; 
Zhou1, Tao ; Yang, Stanley ; Chai, 
Thomas ; Li, Candice 
Cc: Zhang, Hawking ; Deucher, Alexander 
; Lazar, Lijo ; Ma, Le 

Subject: RE: [PATCH 2/3] drm/amdgpu: Query ras capablity from psp

[AMD Official Use Only - General]

-Original Message-
From: Hawking Zhang 
Sent: Tuesday, January 2, 2024 11:45 AM
To: amd-gfx@lists.freedesktop.org; Zhou1, Tao ; Yang, 
Stanley ; Wang, Yang(Kevin) ; 
Chai, Thomas ; Li, Candice 
Cc: Zhang, Hawking ; Deucher, Alexander 
; Lazar, Lijo ; Ma, Le 

Subject: [PATCH 2/3] drm/amdgpu: Query ras capablity from psp

Instead of traditional atomfirmware interfaces for RAS capability, host driver 
can query ras capability from psp starting from psp v13_0_6.

Signed-off-by: Hawking Zhang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 13 +  
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h |  2 ++  
drivers/gpu/drm/amd/amdgpu/psp_v13_0.c  | 26 +
 3 files changed, 41 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 94b536e3cada..8a3847d3041f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -2125,6 +2125,19 @@ int amdgpu_psp_wait_for_bootloader(struct amdgpu_device 
*adev)
return ret;
 }

+bool amdgpu_psp_get_ras_capability(struct psp_context *psp) {
+   bool ret;
+
+   if (psp->funcs &&
+   psp->funcs->get_ras_capability) {
+   ret = psp->funcs->get_ras_capability(psp);
+   return ret;
[kevin]:
This variable 'ret' seems to have no other purpose, can we remove it and return 
directly ?

Best Regards,
Kevin
+   } else {
+   return false;
+   }
+}
+
 static int psp_hw_start(struct psp_context *psp)  {
struct amdgpu_device *adev = psp->adev; diff --git 
a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index 09d1f8f72a9c..652b0a01854a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -134,6 +134,7 @@ struct psp_funcs {
int (*update_spirom)(struct psp_context *psp, uint64_t fw_pri_mc_addr);
int (*vbflash_stat)(struct psp_context *psp);
int (*fatal_error_recovery_quirk)(struct psp_context *psp);
+   bool (*get_ras_capability)(struct psp_context *psp);
 };

 struct ta_funcs {
@@ -537,4 +538,5 @@ int psp_spatial_partition(struct psp_context *psp, int 
mode);  int is_psp_fw_valid(struct psp_bin_desc bin);

 int amdgpu_psp_wait_for_bootloader(struct amdgpu_device *adev);
+bool amdgpu_psp_get_ras_capability(struct psp_context *psp);
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c 
b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
index 676bec2cc157..722b6066ce07 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
@@ -27,6 +27,7 @@
 #include "amdgpu_ucode.h"
 #include "soc15_common.h"
 #include "psp_v13_0.h"
+#include "amdgpu_ras.h"

 #include "mp/mp_13_0_2_offset.h"
 #include "mp/mp_13_0_2_sh_mask.h"
@@ -770,6 +771,30 @@ static int psp_v13_0_fatal_error_recovery_quirk(struct 
psp_context *psp)
return 0;
 }

+static bool psp_v13_0_get_ras_capability(struct psp_context *psp) {
+   struct amdgpu_device *adev = psp->adev;
+   struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
+   u32 reg_data;
+
+   /* query ras cap should be done from host side */
+   if (amdgpu_sriov_vf(adev))
+   return false;
+
+   if (!con)
+   return false;
+
+   if ((amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6)) &&
+   (!(adev->flags & AMD_IS_APU))) {
+   reg_data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_127);
+   adev->ras_hw_enabled = (reg_data & GENMASK_ULL(23, 0));
+   con->poison_supported = ((reg_data & GENMASK_ULL(24, 24)) >> 
24) ? true : false;
+   return true;
+   } else {
+   return false;
+   }
+}
+
 static const struct psp_funcs psp_v13_0_funcs = {
.init_microcode = psp_v13_0_init_microcode,
.wait_for_bootloader = psp_v13_0_wait_for_bootloader_steady_state,
@@ -792,6 +817,7 @@ static const struct psp_funcs psp_v13_0_funcs = {
.update_spirom = psp_v13_0_update_spirom,
.vbflash_stat = ps

RE: [PATCH v2] drm/amdgpu: Fix possible NULL dereference in amdgpu_ras_query_error_status_helper()

[Zhang, Hawking]

[AMD Official Use Only - General]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: SHANMUGAM, SRINIVASAN 
Sent: Wednesday, December 27, 2023 12:37
To: Deucher, Alexander ; Koenig, Christian 

Cc: amd-gfx@lists.freedesktop.org; SHANMUGAM, SRINIVASAN 
; Zhang, Hawking ; Zhou1, 
Tao 
Subject: [PATCH v2] drm/amdgpu: Fix possible NULL dereference in 
amdgpu_ras_query_error_status_helper()

Return invalid error code -EINVAL for invalid block id.

Fixes the below:

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:1183 
amdgpu_ras_query_error_status_helper() error: we previously assumed 'info' 
could be null (see line 1176)

Suggested-by: Hawking Zhang 
Cc: Tao Zhou 
Cc: Hawking Zhang 
Cc: Christian König 
Cc: Alex Deucher 
Signed-off-by: Srinivasan Shanmugam 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index bad62141f708..9c4db031e5ee 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -1176,6 +1176,9 @@ static int amdgpu_ras_query_error_status_helper(struct 
amdgpu_device *adev,
enum amdgpu_ras_block blk = info ? info->head.block : 
AMDGPU_RAS_BLOCK_COUNT;
struct amdgpu_ras_block_object *block_obj = NULL;

+   if (blk == AMDGPU_RAS_BLOCK_COUNT)
+   return -EINVAL;
+
if (error_query_mode == AMDGPU_RAS_INVALID_ERROR_QUERY)
return -EINVAL;

--
2.34.1

RE: [PATCH] drm/amdgpu: Fix possible NULL dereference in amdgpu_ras_query_error_status_helper()

[Zhang, Hawking]

[AMD Official Use Only - General]

Invalid block id should return invalid error code.

Regards,
Hawking

-Original Message-
From: SHANMUGAM, SRINIVASAN 
Sent: Tuesday, December 26, 2023 18:04
To: Deucher, Alexander ; Koenig, Christian 

Cc: amd-gfx@lists.freedesktop.org; SHANMUGAM, SRINIVASAN 
; Zhou1, Tao ; Zhang, Hawking 

Subject: [PATCH] drm/amdgpu: Fix possible NULL dereference in 
amdgpu_ras_query_error_status_helper()

Return 0, if blk is >= AMDGPU_RAS_BLOCK_COUNT

Fixes the below:

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:1183 
amdgpu_ras_query_error_status_helper() error: we previously assumed 'info' 
could be null (see line 1176)

Cc: Tao Zhou 
Cc: Hawking Zhang 
Cc: Christian König 
Cc: Alex Deucher 
Signed-off-by: Srinivasan Shanmugam 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index bad62141f708..327415a15b05 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -1176,6 +1176,9 @@ static int amdgpu_ras_query_error_status_helper(struct 
amdgpu_device *adev,
enum amdgpu_ras_block blk = info ? info->head.block : 
AMDGPU_RAS_BLOCK_COUNT;
struct amdgpu_ras_block_object *block_obj = NULL;

+   if (blk >= AMDGPU_RAS_BLOCK_COUNT)
+   return 0;
+
if (error_query_mode == AMDGPU_RAS_INVALID_ERROR_QUERY)
return -EINVAL;

--
2.34.1

RE: [PATCH v2] drm/amdgpu/gfx11: need acquire mutex before access CP_VMID_RESET v2

[Zhang, Hawking]

[AMD Official Use Only - General]

Better to use dev_err or DRM_ERROR. Apart from that, the patch is

Reviewed-by: Hawking Zhang 

Regards,
Hawking

-Original Message-
From: Xiao, Jack 
Sent: Thursday, December 21, 2023 18:29
To: amd-gfx@lists.freedesktop.org; Deucher, Alexander 
; Zhang, Hawking 
Cc: Xiao, Jack 
Subject: [PATCH v2] drm/amdgpu/gfx11: need acquire mutex before access 
CP_VMID_RESET v2

It's required to take the gfx mutex before access to CP_VMID_RESET, for there 
is a race condition with CP firmware to write the register.

v2: add extra code to ensure the mutex releasing is successful.

Signed-off-by: Jack Xiao 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 48 +-
 1 file changed, 47 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index bdcf96df69e6..44f5b3135931 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -4474,11 +4474,43 @@ static int gfx_v11_0_wait_for_idle(void *handle)
return -ETIMEDOUT;
 }

+static int gfx_v11_0_request_gfx_index_mutex(struct amdgpu_device *adev,
+int req)
+{
+   u32 i, tmp, val;
+
+   for (i = 0; i < adev->usec_timeout; i++) {
+   /* Request with MeId=2, PipeId=0 */
+   tmp = REG_SET_FIELD(0, CP_GFX_INDEX_MUTEX, REQUEST, req);
+   tmp = REG_SET_FIELD(tmp, CP_GFX_INDEX_MUTEX, CLIENTID, 4);
+   WREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX, tmp);
+
+   val = RREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX);
+   if (req) {
+   if (val == tmp)
+   break;
+   } else {
+   tmp = REG_SET_FIELD(tmp, CP_GFX_INDEX_MUTEX,
+   REQUEST, 1);
+
+   /* unlocked or locked by firmware */
+   if (val != tmp)
+   break;
+   }
+   udelay(1);
+   }
+
+   if (i >= adev->usec_timeout)
+   return -EINVAL;
+
+   return 0;
+}
+
 static int gfx_v11_0_soft_reset(void *handle)  {
u32 grbm_soft_reset = 0;
u32 tmp;
-   int i, j, k;
+   int r, i, j, k;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;

tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL); @@ -4518,6 +4550,13 @@ 
static int gfx_v11_0_soft_reset(void *handle)
}
}

+   /* Try to acquire the gfx mutex before access to CP_VMID_RESET */
+   r = gfx_v11_0_request_gfx_index_mutex(adev, 1);
+   if (r) {
+   printk("Failed to acquire the gfx mutex during soft reset\n");
+   return r;
+   }
+
WREG32_SOC15(GC, 0, regCP_VMID_RESET, 0xfffe);

// Read CP_VMID_RESET register three times.
@@ -4526,6 +4565,13 @@ static int gfx_v11_0_soft_reset(void *handle)
RREG32_SOC15(GC, 0, regCP_VMID_RESET);
RREG32_SOC15(GC, 0, regCP_VMID_RESET);

+   /* release the gfx mutex */
+   r = gfx_v11_0_request_gfx_index_mutex(adev, 0);
+   if (r) {
+   printk("Failed to release the gfx mutex during soft reset\n");
+   return r;
+   }
+
for (i = 0; i < adev->usec_timeout; i++) {
if (!RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) &&
!RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE))
--
2.41.0

RE: [PATCH Review V3 1/1] drm/amdgpu: Fix ecc irq enable/disable unpaired

[Zhang, Hawking]

[AMD Official Use Only - General]

Feel free to drop the check as below since amdgpu_xxx_ras_late_init applies the 
check for interrupt enablement.
+   amdgpu_ras_is_supported(tmp_adev, 
AMDGPU_RAS_BLOCK__SDMA)
+   amdgpu_ras_is_supported(tmp_adev, 
AMDGPU_RAS_BLOCK__GFX)

Apart from that, the change is

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: amd-gfx  On Behalf Of Stanley.Yang
Sent: Thursday, December 21, 2023 14:05
To: amd-gfx@lists.freedesktop.org; Zhang, Hawking 
Cc: Yang, Stanley 
Subject: [PATCH Review V3 1/1] drm/amdgpu: Fix ecc irq enable/disable unpaired

The ecc_irq is disabled while GPU mode2 reset suspending process, but not be 
enabled during GPU mode2 reset resume process.

Changed from V1:
only do sdma/gfx ras_late_init in aldebaran_mode2_restore_ip
delete amdgpu_ras_late_resume function

Changed from V2:
check umc ras supported before put ecc_irq

Signed-off-by: Stanley.Yang 
---
 drivers/gpu/drm/amd/amdgpu/aldebaran.c | 28 +-  
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c |  4   
drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c |  5 +  
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c  |  4 
 4 files changed, 40 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/aldebaran.c 
b/drivers/gpu/drm/amd/amdgpu/aldebaran.c
index 02f4c6f9d4f6..b60a3c1bd0f2 100644
--- a/drivers/gpu/drm/amd/amdgpu/aldebaran.c
+++ b/drivers/gpu/drm/amd/amdgpu/aldebaran.c
@@ -330,6 +330,7 @@ aldebaran_mode2_restore_hwcontext(struct 
amdgpu_reset_control *reset_ctl,  {
struct list_head *reset_device_list = reset_context->reset_device_list;
struct amdgpu_device *tmp_adev = NULL;
+   struct amdgpu_ras *con;
int r;

if (reset_device_list == NULL)
@@ -355,7 +356,32 @@ aldebaran_mode2_restore_hwcontext(struct 
amdgpu_reset_control *reset_ctl,
 */
amdgpu_register_gpu_instance(tmp_adev);

-   /* Resume RAS */
+   /* Resume RAS, ecc_irq */
+   con = amdgpu_ras_get_context(tmp_adev);
+   if (!amdgpu_sriov_vf(tmp_adev) && con) {
+   if (tmp_adev->sdma.ras &&
+   amdgpu_ras_is_supported(tmp_adev, 
AMDGPU_RAS_BLOCK__SDMA) &&
+   tmp_adev->sdma.ras->ras_block.ras_late_init) {
+   r = 
tmp_adev->sdma.ras->ras_block.ras_late_init(tmp_adev,
+   
_adev->sdma.ras->ras_block.ras_comm);
+   if (r) {
+   dev_err(tmp_adev->dev, "SDMA failed to 
execute ras_late_init! ret:%d\n", r);
+   goto end;
+   }
+   }
+
+   if (tmp_adev->gfx.ras &&
+   amdgpu_ras_is_supported(tmp_adev, 
AMDGPU_RAS_BLOCK__GFX) &&
+   tmp_adev->gfx.ras->ras_block.ras_late_init) {
+   r = 
tmp_adev->gfx.ras->ras_block.ras_late_init(tmp_adev,
+   
_adev->gfx.ras->ras_block.ras_comm);
+   if (r) {
+   dev_err(tmp_adev->dev, "GFX failed to 
execute ras_late_init! ret:%d\n", r);
+   goto end;
+   }
+   }
+   }
+
amdgpu_ras_resume(tmp_adev);

/* Update PSP FW topology after reset */ diff --git 
a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index 09cbca596bb5..4048539205cb 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -1043,6 +1043,10 @@ static int gmc_v10_0_hw_fini(void *handle)

amdgpu_irq_put(adev, >gmc.vm_fault, 0);

+   if (adev->gmc.ecc_irq.funcs &&
+   amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC))
+   amdgpu_irq_put(adev, >gmc.ecc_irq, 0);
+
return 0;
 }

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
index 416f3e4f0438..e1ca5a599971 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
@@ -941,6 +941,11 @@ static int gmc_v11_0_hw_fini(void *handle)
}

amdgpu_irq_put(adev, >gmc.vm_fault, 0);
+
+   if (adev->gmc.ecc_irq.funcs &&
+   amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC))
+   amdgpu_irq_put(adev, >gmc.ecc_irq, 0);
+
gmc_v11_0_gart_disable(adev);

return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_

RE: [PATCH Review V2 1/1] drm/amdgpu: Fix ecc irq enable/disable unpaired

[Zhang, Hawking]

[AMD Official Use Only - General]

+   if (adev->gmc.ecc_irq.funcs)
+   amdgpu_irq_put(adev, >gmc.ecc_irq, 0);
+

This doesn't match with amdgpu_irq_get call for gmc.ecc_irq, where driver 
checks ras cap to decide whether enabling the interrupt or not (see 
amdgpu_umc_ras_late_init). We do the same check for amdgpu_irq_put call.

Regards,
Hawking

-Original Message-
From: Yang, Stanley 
Sent: Tuesday, December 19, 2023 20:48
To: amd-gfx@lists.freedesktop.org; Zhang, Hawking 
Cc: Yang, Stanley 
Subject: [PATCH Review V2 1/1] drm/amdgpu: Fix ecc irq enable/disable unpaired

The ecc_irq is disabled while GPU mode2 reset suspending process, but not be 
enabled during GPU mode2 reset resume process.

Changed from V1:
only do sdma/gfx ras_late_init in aldebaran_mode2_restore_ip,
delete amdgpu_ras_late_resume function.

Signed-off-by: Stanley.Yang 
---
 drivers/gpu/drm/amd/amdgpu/aldebaran.c | 28 +-  
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c |  3 +++  
drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c |  4   
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c  |  3 +++
 4 files changed, 37 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/aldebaran.c 
b/drivers/gpu/drm/amd/amdgpu/aldebaran.c
index 02f4c6f9d4f6..b60a3c1bd0f2 100644
--- a/drivers/gpu/drm/amd/amdgpu/aldebaran.c
+++ b/drivers/gpu/drm/amd/amdgpu/aldebaran.c
@@ -330,6 +330,7 @@ aldebaran_mode2_restore_hwcontext(struct 
amdgpu_reset_control *reset_ctl,  {
struct list_head *reset_device_list = reset_context->reset_device_list;
struct amdgpu_device *tmp_adev = NULL;
+   struct amdgpu_ras *con;
int r;

if (reset_device_list == NULL)
@@ -355,7 +356,32 @@ aldebaran_mode2_restore_hwcontext(struct 
amdgpu_reset_control *reset_ctl,
 */
amdgpu_register_gpu_instance(tmp_adev);

-   /* Resume RAS */
+   /* Resume RAS, ecc_irq */
+   con = amdgpu_ras_get_context(tmp_adev);
+   if (!amdgpu_sriov_vf(tmp_adev) && con) {
+   if (tmp_adev->sdma.ras &&
+   amdgpu_ras_is_supported(tmp_adev, 
AMDGPU_RAS_BLOCK__SDMA) &&
+   tmp_adev->sdma.ras->ras_block.ras_late_init) {
+   r = 
tmp_adev->sdma.ras->ras_block.ras_late_init(tmp_adev,
+   
_adev->sdma.ras->ras_block.ras_comm);
+   if (r) {
+   dev_err(tmp_adev->dev, "SDMA failed to 
execute ras_late_init! ret:%d\n", r);
+   goto end;
+   }
+   }
+
+   if (tmp_adev->gfx.ras &&
+   amdgpu_ras_is_supported(tmp_adev, 
AMDGPU_RAS_BLOCK__GFX) &&
+   tmp_adev->gfx.ras->ras_block.ras_late_init) {
+   r = 
tmp_adev->gfx.ras->ras_block.ras_late_init(tmp_adev,
+   
_adev->gfx.ras->ras_block.ras_comm);
+   if (r) {
+   dev_err(tmp_adev->dev, "GFX failed to 
execute ras_late_init! ret:%d\n", r);
+   goto end;
+   }
+   }
+   }
+
amdgpu_ras_resume(tmp_adev);

/* Update PSP FW topology after reset */ diff --git 
a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index 09cbca596bb5..b93a0baeb2d3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -1043,6 +1043,9 @@ static int gmc_v10_0_hw_fini(void *handle)

amdgpu_irq_put(adev, >gmc.vm_fault, 0);

+   if (adev->gmc.ecc_irq.funcs)
+   amdgpu_irq_put(adev, >gmc.ecc_irq, 0);
+
return 0;
 }

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
index 416f3e4f0438..e633e60850b3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
@@ -941,6 +941,10 @@ static int gmc_v11_0_hw_fini(void *handle)
}

amdgpu_irq_put(adev, >gmc.vm_fault, 0);
+
+   if (adev->gmc.ecc_irq.funcs)
+   amdgpu_irq_put(adev, >gmc.ecc_irq, 0);
+
gmc_v11_0_gart_disable(adev);

return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 205db28a9803..8ac4d5b7fb37 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -2388,6 +2388,9 @@ static int gmc_v9_0_hw_fini(void *handle)

amdgpu_irq_put(adev, >gmc.vm_fault, 0);

+   if (adev->gmc.ecc_irq.funcs)
+   amdgpu_irq_put(adev, >gmc.ecc_irq, 0);
+
return 0;
 }

--
2.25.1

RE: [PATCH] drm/amdgpu/gfx11: need acquire mutex before access CP_VMID_RESET

[Zhang, Hawking]

[AMD Official Use Only - General]

+   /* release the gfx mutex */
+   tmp = REG_SET_FIELD(tmp, CP_GFX_INDEX_MUTEX, REQUEST, 0);
+   WREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX, tmp);

Shall we add a check by reading back CP_GFX_INDEX_MUTEX to ensure the release 
is done correctly?

Regards,
Hawking

-Original Message-
From: Xiao, Jack 
Sent: Tuesday, December 19, 2023 17:24
To: amd-gfx@lists.freedesktop.org; Deucher, Alexander 
; Zhang, Hawking 
Cc: Xiao, Jack 
Subject: [PATCH] drm/amdgpu/gfx11: need acquire mutex before access 
CP_VMID_RESET

It's required to take the gfx mutex before access to CP_VMID_RESET, for there 
is a race condition with CP firmware to write the register.

Signed-off-by: Jack Xiao 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 20 
 1 file changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index bdcf96df69e6..ae3370d34d11 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -4518,6 +4518,22 @@ static int gfx_v11_0_soft_reset(void *handle)
}
}

+   /* Try to require the gfx mutex before access to CP_VMID_RESET */
+   for (i = 0; i < adev->usec_timeout; i++) {
+   /* Request with MeId=2, PipeId=0 */
+   tmp = REG_SET_FIELD(0, CP_GFX_INDEX_MUTEX, REQUEST, 1);
+   tmp = REG_SET_FIELD(tmp, CP_GFX_INDEX_MUTEX, CLIENTID, 4);
+   WREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX, tmp);
+   if (RREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX) == tmp)
+   break;
+   udelay(1);
+   }
+
+   if (i >= adev->usec_timeout) {
+   printk("Failed to require the gfx mutex during soft reset\n");
+   return -EINVAL;
+   }
+
WREG32_SOC15(GC, 0, regCP_VMID_RESET, 0xfffe);

// Read CP_VMID_RESET register three times.
@@ -4526,6 +4542,10 @@ static int gfx_v11_0_soft_reset(void *handle)
RREG32_SOC15(GC, 0, regCP_VMID_RESET);
RREG32_SOC15(GC, 0, regCP_VMID_RESET);

+   /* release the gfx mutex */
+   tmp = REG_SET_FIELD(tmp, CP_GFX_INDEX_MUTEX, REQUEST, 0);
+   WREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX, tmp);
+
for (i = 0; i < adev->usec_timeout; i++) {
if (!RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) &&
!RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE))
--
2.41.0