RE: [PATCH] drm/amdgpu: avoid clearing freed bo with sdma in gpu reset
[AMD Official Use Only - Internal Distribution Only] Thanks, Christian, Is this the fix that you are mentioning: commit 1675c3a24d075d484377003789245f48c2114a0b Author: Christian König Date: Fri Feb 21 15:10:31 2020 +0100 drm/amdgpu: stop disable the scheduler during HW fini When we stop the HW for example for GPU reset we should not stop the front-end scheduler. Otherwise we run into intermediate failures during command submission. The scheduler should only be stopped in very few cases: 1. We can't get the hardware working in ring or IB test after a GPU reset. 2. The KIQ scheduler is not used in the front-end and should be disabled during GPU reset. 3. In amdgpu_ring_fini() when the driver unloads. Signed-off-by: Christian König Reviewed-by: Alex Deucher Acked-by: Nirmoy Das Test-by: Dennis Li Signed-off-by: Alex Deucher Thanks Tiecheng -Original Message- From: Christian König Sent: Wednesday, May 6, 2020 5:44 PM To: Zhou, Tiecheng ; amd-gfx@lists.freedesktop.org Subject: Re: [PATCH] drm/amdgpu: avoid clearing freed bo with sdma in gpu reset NAK, the fundamental problem was that we disabled the SDMA paging queue during reset: > [ 885.694682] [drm] schedpage0 is not ready, skipping [ 885.694682] > [drm] schedpage1 is not ready, skipping This is fixed by now, so the problem should not happen any more. Regards, Christian. Am 06.05.20 um 11:36 schrieb Tiecheng Zhou: > WHY: > For V320 passthrough and "modprobe amdgpu lockup_timeout=500", there > will be kernel NULL pointer when using quark ~ BACO reset, for instance: >hang_vm_compute0_bad_cs_dispatch.lua >hang_vm_dma0_corrupted_header.lua >etc. > - > [ 884.792885] [drm:amdgpu_job_timedout [amdgpu]] *ERROR* ring > comp_1.0.0 timeout, signaled seq=3, emitted seq=4 [ 884.793772] > [drm:amdgpu_job_timedout [amdgpu]] *ERROR* Process information: > process quark pid 16939 thread quark pid 16940 [ 884.859979] amdgpu: > [powerplay] set virtualization GFX DPM policy success [ 884.861003] > amdgpu: [powerplay] activate virtualization GFX DPM policy success [ > 884.861065] amdgpu: [powerplay] set virtualization VCE DPM policy success [ > 885.693554] [drm:amdgpu_cs_ioctl [amdgpu]] *ERROR* Failed to initialize > parser -125! > [ 885.694682] [drm] schedpage0 is not ready, skipping [ 885.694682] > [drm] schedpage1 is not ready, skipping [ 885.694720] > [drm:amdgpu_gem_va_ioctl [amdgpu]] *ERROR* Couldn't update BO_VA (-2) > [ 885.695328] BUG: unable to handle kernel NULL pointer dereference > at 0008 [ 885.695909] PGD 0 P4D 0 [ 885.696104] Oops: > [#1] SMP PTI > [ 885.696368] CPU: 2 PID: 16940 Comm: quark Tainted: G OE > 4.19.52+ #6 > [ 885.696945] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), > BIOS 1.10.2-1 04/01/2014 [ 885.697593] RIP: > 0010:amdgpu_vm_sdma_commit+0x59/0x130 [amdgpu] ... > [ 885.705042] Call Trace: > [ 885.705251] ? amdgpu_vm_bo_update_mapping+0xdf/0xf0 [amdgpu] [ > 885.705696] ? amdgpu_vm_clear_freed+0xcc/0x1b0 [amdgpu] [ > 885.706112] ? amdgpu_gem_va_ioctl+0x4a1/0x510 [amdgpu] [ 885.706493] > ? __radix_tree_delete+0x7e/0xa0 [ 885.706822] ? > amdgpu_gem_va_map_flags+0x70/0x70 [amdgpu] [ 885.707220] ? > drm_ioctl_kernel+0xaa/0xf0 [drm] [ 885.707568] ? > amdgpu_gem_va_map_flags+0x70/0x70 [amdgpu] [ 885.707962] ? > drm_ioctl_kernel+0xaa/0xf0 [drm] [ 885.708294] ? > drm_ioctl+0x3a7/0x3f0 [drm] [ 885.708632] ? > amdgpu_gem_va_map_flags+0x70/0x70 [amdgpu] [ 885.709032] ? > unmap_region+0xd9/0x120 [ 885.709328] ? amdgpu_drm_ioctl+0x49/0x80 > [amdgpu] [ 885.709684] ? do_vfs_ioctl+0xa1/0x620 [ 885.709971] ? > do_munmap+0x32e/0x430 [ 885.710232] ? ksys_ioctl+0x66/0x70 [ > 885.710513] ? __x64_sys_ioctl+0x16/0x20 [ 885.710806] ? > do_syscall_64+0x55/0x100 [ 885.711092] ? > entry_SYSCALL_64_after_hwframe+0x44/0xa9 > ... > [ 885.719408] ---[ end trace 7ee3180f42e9f572 ]--- [ 885.719766] > RIP: 0010:amdgpu_vm_sdma_commit+0x59/0x130 [amdgpu] ... > - > > the NULL pointer (entity->rq == NULL in amdgpu_vm_sdma_commit()) as follows: > 1. quark sends bad job that triggers job timeout; 2. guest KMD detects > the job timeout and goes to gpu recovery, and it goes to > ip_suspend for SDMA, and it sets sdma[].sched.ready to false; 3. > quark sends UNMAP operation through amdgpu_gem_va_ioctl, and guest KMD goes > through amdgpu_gem_va_update_vm and finally goes to amdgpu_vm_sdma_commit, > it goes to amdgpu_job_submit to drm_sched_job_init 4. > drm_sched_job_init fails at drm_sched_pick_best() since > sdma[].sched.ready is set to false; in the meanwhile entity->rq > becomes NULL; 5. q
RE: [PATCH 2/2] drm/amd/powerplay: avoid using pm_en before it is initialized revised
[AMD Official Use Only - Internal Distribution Only] Sorry for bothering, I'm going to send another one, It seems pm_en should not be used in get_asic_baco_capability, get_asic_baco_state, set_asic_baco_state. -Original Message- From: Tiecheng Zhou Sent: Monday, April 27, 2020 9:57 AM To: amd-gfx@lists.freedesktop.org Cc: Zhou, Tiecheng ; Tao, Yintian Subject: [PATCH 2/2] drm/amd/powerplay: avoid using pm_en before it is initialized revised hwmgr->pm_en is initialized at hwmgr_hw_init. during amdgpu_device_init, there is amdgpu_asic_reset that calls to pp_get_asic_baco_capability, while hwmgr->pm_en has not yet been initialized. this is to avoid using pm_en in pp_get_asic_baco_capability Signed-off-by: Tiecheng Zhou Signed-off-by: Yintian Tao --- drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c index 71b843f542d8..fb4ca614f6e3 100644 --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c @@ -1438,7 +1438,8 @@ static int pp_get_asic_baco_capability(void *handle, bool *cap) if (!hwmgr) return -EINVAL; - if (!hwmgr->pm_en || !hwmgr->hwmgr_func->get_asic_baco_capability) + if (!(hwmgr->not_vf && amdgpu_dpm) || + !hwmgr->hwmgr_func->get_asic_baco_capability) return 0; mutex_lock(>smu_lock); -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH] drm/amd/powerplay: avoid using pm_en before it is initialized
[AMD Official Use Only - Internal Distribution Only] Ping... -Original Message- From: Tiecheng Zhou Sent: Thursday, April 2, 2020 5:29 PM To: amd-gfx@lists.freedesktop.org Cc: Zhou, Tiecheng ; Tao, Yintian Subject: [PATCH] drm/amd/powerplay: avoid using pm_en before it is initialized hwmgr->pm_en is initialized at hwmgr_hw_init. during amdgpu_device_init, there is amdgpu_asic_reset that calls to pp_get_asic_baco_capability, while hwmgr->pm_en has not yet been initialized. so avoid using pm_en in pp_get_asic_baco_capability. Signed-off-by: Tiecheng Zhou Signed-off-by: Yintian Tao --- drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c index 71b843f542d8..fdff3e1c5e95 100644 --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c @@ -1455,7 +1455,8 @@ static int pp_get_asic_baco_state(void *handle, int *state) if (!hwmgr) return -EINVAL; - if (!hwmgr->pm_en || !hwmgr->hwmgr_func->get_asic_baco_state) + if (!(hwmgr->not_vf && amdgpu_dpm) || + !hwmgr->hwmgr_func->get_asic_baco_state) return 0; mutex_lock(>smu_lock); -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH] drm/amdgpu/sriov: skip programing some regs with new L1 policy
[AMD Official Use Only - Internal Distribution Only]
Ping
-Original Message-
From: Tiecheng Zhou
Sent: Monday, March 2, 2020 3:08 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhou, Tiecheng
Subject: [PATCH] drm/amdgpu/sriov: skip programing some regs with new L1 policy
With new L1 policy, some regs are blocked at guest and they are programed at
host side. So skip programing the regs under sriov.
the regs are:
GCMC_VM_FB_LOCATION_TOP
GCMC_VM_FB_LOCATION_BASE
MMMC_VM_FB_LOCATION_TOP
MMMC_VM_FB_LOCATION_BASE
GCMC_VM_SYSTEM_APERTURE_HIGH_ADDR
GCMC_VM_SYSTEM_APERTURE_LOW_ADDR
MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR
MMMC_VM_SYSTEM_APERTURE_LOW_ADDR
HDP_NONSURFACE_BASE
HDP_NONSURFACE_BASE_HI
GCMC_VM_AGP_TOP
GCMC_VM_AGP_BOT
GCMC_VM_AGP_BASE
Signed-off-by: Tiecheng Zhou
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c | 55 +++-
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 29 ++---
2 files changed, 37 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
index e0654a216ab5..cc866c367939 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
@@ -81,24 +81,31 @@ static void gfxhub_v2_0_init_system_aperture_regs(struct
amdgpu_device *adev) {
uint64_t value;
- /* Disable AGP. */
- WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0);
- WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, 0);
- WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, 0x00FF);
-
- /* Program the system aperture low logical page number. */
- WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR,
-adev->gmc.vram_start >> 18);
- WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
-adev->gmc.vram_end >> 18);
-
- /* Set default page address. */
- value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start
- + adev->vm_manager.vram_base_offset;
- WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
-(u32)(value >> 12));
- WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
-(u32)(value >> 44));
+ if (!amdgpu_sriov_vf(adev)) {
+ /*
+* the new L1 policy will block SRIOV guest from writing
+* these regs, and they will be programed at host.
+* so skip programing these regs.
+*/
+ /* Disable AGP. */
+ WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0);
+ WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, 0);
+ WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, 0x00FF);
+
+ /* Program the system aperture low logical page number. */
+ WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR,
+adev->gmc.vram_start >> 18);
+ WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
+adev->gmc.vram_end >> 18);
+
+ /* Set default page address. */
+ value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start
+ + adev->vm_manager.vram_base_offset;
+ WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
+(u32)(value >> 12));
+ WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
+(u32)(value >> 44));
+ }
/* Program "protection fault". */
WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
@@ -260,18 +267,6 @@ static void gfxhub_v2_0_program_invalidation(struct
amdgpu_device *adev)
int gfxhub_v2_0_gart_enable(struct amdgpu_device *adev) {
- if (amdgpu_sriov_vf(adev)) {
- /*
-* GCMC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
-* VF copy registers so vbios post doesn't program them, for
-* SRIOV driver need to program them
-*/
- WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE,
-adev->gmc.vram_start >> 24);
- WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_TOP,
-adev->gmc.vram_end >> 24);
- }
-
/* GART Enable. */
gfxhub_v2_0_init_gart_aperture_regs(adev);
gfxhub_v2_0_init_system_aperture_regs(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
index bde189680521..fb3f228458e5 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
@@ -72,11 +72,18 @@ static void mmhub_v2_0_init_system_aperture_regs(struct
amdgpu_device *adev)
WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_TOP, 0);
WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BOT, 0x00F
RE: [PATCH] drm/amdgpu/gfx_v8_0: Reorder the gfx, kiq and kcq rings test sequence
Ping...
-Original Message-
From: amd-gfx On Behalf Of Tiecheng Zhou
Sent: Thursday, December 27, 2018 4:15 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhou, Tiecheng
Subject: [PATCH] drm/amdgpu/gfx_v8_0: Reorder the gfx, kiq and kcq rings test
sequence
The kiq ring and the very first compute ring may fail occasionally if they are
tested directly following kiq_kcq_enable.
Insert the gfx ring test before kiq ring test to delay the kiq and kcq ring
tests will fix the issue.
Signed-off-by: Tiecheng Zhou
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 48 +--
1 file changed, 35 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 381f593b..164ffc9 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4278,9 +4278,8 @@ static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device
*adev)
amdgpu_ring_clear_ring(ring);
gfx_v8_0_cp_gfx_start(adev);
ring->sched.ready = true;
- r = amdgpu_ring_test_helper(ring);
- return r;
+ return 0;
}
static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool
enable) @@ -4369,10 +4368,9 @@ static int gfx_v8_0_kiq_kcq_enable(struct
amdgpu_device *adev)
amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
}
- r = amdgpu_ring_test_helper(kiq_ring);
- if (r)
- DRM_ERROR("KCQ enable failed\n");
- return r;
+ amdgpu_ring_commit(kiq_ring);
+
+ return 0;
}
static int gfx_v8_0_deactivate_hqd(struct amdgpu_device *adev, u32 req) @@
-4709,16 +4707,32 @@ static int gfx_v8_0_kcq_resume(struct amdgpu_device *adev)
if (r)
goto done;
- /* Test KCQs - reversing the order of rings seems to fix ring test
failure
-* after GPU reset
-*/
- for (i = adev->gfx.num_compute_rings - 1; i >= 0; i--) {
+done:
+ return r;
+}
+
+static int gfx_v8_0_cp_test_all_rings(struct amdgpu_device *adev) {
+ int r, i;
+ struct amdgpu_ring *ring;
+
+ /* collect all the ring_tests here, gfx, kiq, compute */
+ ring = >gfx.gfx_ring[0];
+ r = amdgpu_ring_test_helper(ring);
+ if (r)
+ return r;
+
+ ring = >gfx.kiq.ring;
+ r = amdgpu_ring_test_helper(ring);
+ if (r)
+ return r;
+
+ for (i = 0; i < adev->gfx.num_compute_rings; i++) {
ring = >gfx.compute_ring[i];
- r = amdgpu_ring_test_helper(ring);
+ amdgpu_ring_test_helper(ring);
}
-done:
- return r;
+ return 0;
}
static int gfx_v8_0_cp_resume(struct amdgpu_device *adev) @@ -4739,6 +4753,11
@@ static int gfx_v8_0_cp_resume(struct amdgpu_device *adev)
r = gfx_v8_0_kcq_resume(adev);
if (r)
return r;
+
+ r = gfx_v8_0_cp_test_all_rings(adev);
+ if (r)
+ return r;
+
gfx_v8_0_enable_gui_idle_interrupt(adev, true);
return 0;
@@ -5056,6 +5075,7 @@ static int gfx_v8_0_post_soft_reset(void *handle) {
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
u32 grbm_soft_reset = 0;
+ struct amdgpu_ring *ring;
if ((!adev->gfx.grbm_soft_reset) &&
(!adev->gfx.srbm_soft_reset))
@@ -5086,6 +5106,8 @@ static int gfx_v8_0_post_soft_reset(void *handle)
REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_GFX))
gfx_v8_0_cp_gfx_resume(adev);
+ gfx_v8_0_cp_test_all_rings(adev);
+
adev->gfx.rlc.funcs->start(adev);
return 0;
--
2.7.4
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RE: [PATCH] amd/amdgpu: fix typo about amdgpu_sriov_vf
Reviewed-by: Tiecheng Zhou
-Original Message-
From: amd-gfx On Behalf Of Gui, Jack
Sent: Monday, December 10, 2018 4:05 PM
To: amd-gfx@lists.freedesktop.org
Cc: Gui, Jack
Subject: [PATCH] amd/amdgpu: fix typo about amdgpu_sriov_vf
Signed-off-by: Chengming Gui
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index a9c853a..08f443f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4068,7 +4068,7 @@ static void gfx_v8_0_rlc_start(struct amdgpu_device *adev)
static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev) {
- if (amdgpu_sriov(adev)) {
+ if (amdgpu_sriov_vf(adev)) {
gfx_v8_0_init_csb(adev);
return 0;
}
--
2.7.4
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RE: build broken on drm-next
Thanks to Jack and Ray,
I'll pay more attention.
Tiecheng
-Original Message-
From: Huang, Ray
Sent: Monday, December 10, 2018 8:15 PM
To: StDenis, Tom ; Zhou, Tiecheng ;
amd-gfx mailing list
Cc: Deucher, Alexander ; Gui, Jack
Subject: RE: build broken on drm-next
Jack already have a patch to fix this issue.
Thanks,
Ray
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of StDenis, Tom
> Sent: Monday, December 10, 2018 8:07 PM
> To: Zhou, Tiecheng ; amd-gfx mailing list g...@lists.freedesktop.org>
> Cc: Deucher, Alexander
> Subject: build broken on drm-next
>
> Hi,
>
> This commit
>
> commit e421c656beefa1044f65cf50d7a7455df60cd703
>
> Refs: v4.20-rc3-530-ge421c656beef
>
> Author: Tiecheng Zhou
>
> AuthorDate: Fri Dec 7 09:11:35 2018 +0800
>
> Commit: Tiecheng Zhou
>
> CommitDate: Mon Dec 10 11:14:27 2018 +0800
>
>
> drm/amdgpu: bypass RLC init under sriov for Tonga
>
> RLC will go wrong in soft_reset under sriov
>
> Workaroound: only need to init RLC csb, and skip RLC stop, reset, start
> this is because host-driver has already done full
> initialization on RLC
>
> Signed-off-by: Tiecehng Zhou
>
> Acked-by: Alex Deucher
>
>
> Causes a build error on amd-staging-drm-next:
>
> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c: In function
> ‘gfx_v8_0_rlc_resume’:
> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c:4071:6: error: implicit
> declaration of function ‘amdgpu_sriov’; did you mean ‘amdgpu_sriov_vf’?
> [-Werror=implicit-function-declaration]
>if (amdgpu_sriov(adev)) {
>^~~~
>amdgpu_sriov_vf
>CC [M] drivers/gpu/drm/amd/amdgpu/sdma_v3_0.o
>CC [M] drivers/gpu/drm/amd/amdgpu/sdma_v4_0.o
>CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.o
> cc1: some warnings being treated as errors
> make[4]: *** [scripts/Makefile.build:293:
> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.o] Error 1
> make[4]: *** Waiting for unfinished jobs
> make[3]: *** [scripts/Makefile.build:518: drivers/gpu/drm/amd/amdgpu]
> Error 2
> make[2]: *** [scripts/Makefile.build:518: drivers/gpu/drm] Error 2
> make[1]: *** [scripts/Makefile.build:518: drivers/gpu] Error 2
> make: *** [Makefile:1060: drivers] Error 2
>
>
> Tom
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