[PATCH v2 2/2] drm/amd/display: Move PRIMARY plane zpos higher

[sunpeng.li]

From: Leo Li 

[Why]

Compositors have different ways of assigning surfaces to DRM planes for
render offloading. It may decide between various strategies: overlay,
underlay, or a mix of both (see here for more info:
https://gitlab.freedesktop.org/emersion/libliftoff/-/issues/76)

One way for compositors to implement the underlay strategy is to assign
a higher zpos to the DRM_PRIMARY plane than the DRM_OVERLAY planes,
effectively turning the DRM_OVERLAY plane into an underlay plane.

Today, amdgpu attaches an immutable zpos of 0 to the DRM_PRIMARY plane.
This however, is an arbitrary restriction. DCN pipes are general
purpose, and can be arranged in any z-order. To support compositors
using this allocation scheme, we can set a non-zero immutable zpos for
the PRIMARY, allowing the placement of OVERLAYS (mutable zpos range
0-254) beneath the PRIMARY.

[How]

Assign a zpos = #no of OVERLAY planes to the PRIMARY plane. Then, clean
up any assumptions in the driver of PRIMARY plane having the lowest
zpos.

Signed-off-by: Leo Li 
Reviewed-by: Harry Wentland 
Acked-by: Pekka Paalanen 

v2: Fix typo s/decending/descending/
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 34 +--
 .../amd/display/amdgpu_dm/amdgpu_dm_plane.c   | 18 +++---
 2 files changed, 44 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index b4b5b73707c1..6782ca1137d4 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -80,6 +80,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
@@ -375,6 +376,20 @@ static inline void reverse_planes_order(struct 
dc_surface_update *array_of_surfa
swap(array_of_surface_update[i], array_of_surface_update[j]);
 }
 
+/*
+ * DC will program planes with their z-order determined by their ordering
+ * in the dc_surface_updates array. This comparator is used to sort them
+ * by descending zpos.
+ */
+static int dm_plane_layer_index_cmp(const void *a, const void *b)
+{
+   const struct dc_surface_update *sa = (struct dc_surface_update *)a;
+   const struct dc_surface_update *sb = (struct dc_surface_update *)b;
+
+   /* Sort by descending dc_plane layer_index (i.e. normalized_zpos) */
+   return sb->surface->layer_index - sa->surface->layer_index;
+}
+
 /**
  * update_planes_and_stream_adapter() - Send planes to be updated in DC
  *
@@ -399,7 +414,8 @@ static inline bool update_planes_and_stream_adapter(struct 
dc *dc,
struct dc_stream_update 
*stream_update,
struct dc_surface_update 
*array_of_surface_update)
 {
-   reverse_planes_order(array_of_surface_update, planes_count);
+   sort(array_of_surface_update, planes_count,
+sizeof(*array_of_surface_update), dm_plane_layer_index_cmp, NULL);
 
/*
 * Previous frame finished and HW is ready for optimization.
@@ -9503,6 +9519,8 @@ static void amdgpu_dm_atomic_commit_tail(struct 
drm_atomic_state *state)
for (j = 0; j < status->plane_count; j++)
dummy_updates[j].surface = status->plane_states[0];
 
+   sort(dummy_updates, status->plane_count,
+sizeof(*dummy_updates), dm_plane_layer_index_cmp, NULL);
 
mutex_lock(>dc_lock);
dc_update_planes_and_stream(dm->dc,
@@ -10237,6 +10255,16 @@ static bool should_reset_plane(struct drm_atomic_state 
*state,
if (new_crtc_state->color_mgmt_changed)
return true;
 
+   /*
+* On zpos change, planes need to be reordered by removing and re-adding
+* them one by one to the dc state, in order of descending zpos.
+*
+* TODO: We can likely skip bandwidth validation if the only thing that
+* changed about the plane was it'z z-ordering.
+*/
+   if (new_crtc_state->zpos_changed)
+   return true;
+
if (drm_atomic_crtc_needs_modeset(new_crtc_state))
return true;
 
@@ -11076,7 +11104,7 @@ static int amdgpu_dm_atomic_check(struct drm_device 
*dev,
}
 
/* Remove exiting planes if they are modified */
-   for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, 
new_plane_state, i) {
+   for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, 
new_plane_state) {
if (old_plane_state->fb && new_plane_state->fb &&
get_mem_type(old_plane_state->fb) !=
get_mem_type(new_plane_state->fb))
@@ -11121,7 +11149,7 @@ static int amdgpu_dm_atomic_check(struct drm_device 
*dev,
}
 
/* Add new/modified planes */
-   for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, 
new_plane_state, i) {
+   

[PATCH v2 1/2] drm/amd/display: Introduce overlay cursor mode

[sunpeng.li]

From: Leo Li 

[Why]

DCN is the display hardware for amdgpu. DRM planes are backed by DCN
hardware pipes, which carry pixel data from one end (memory), to the
other (output encoder).

Each DCN pipe has the ability to blend in a cursor early on in the
pipeline. In other words, there are no dedicated cursor planes in DCN,
which makes cursor behavior somewhat unintuitive for compositors.

For example, if the cursor is in RGB format, but the top-most DRM plane
is in YUV format, DCN will not be able to blend them. Because of this,
amdgpu_dm rejects all configurations where a cursor needs to be enabled
on top of a YUV formatted plane.

>From a compositor's perspective, when computing an allocation for
hardware plane offloading, this cursor-on-yuv configuration result in an
atomic test failure. Since the failure reason is not obvious at all,
compositors will likely fall back to full rendering, which is not ideal.

Instead, amdgpu_dm can try to accommodate the cursor-on-yuv
configuration by opportunistically reserving a separate DCN pipe just
for the cursor. We can refer to this as "overlay cursor mode". It is
contrasted with "native cursor mode", where the native DCN per-pipe
cursor is used.

[How]

On each crtc, compute whether the cursor plane should be enabled in
overlay mode. If it is, mark the CRTC as requesting overlay cursor mode.

Overlay cursor should be enabled whenever there exists a underlying
plane that has YUV format, or is scaled differently than the cursor. It
should also be enabled if there is no underlying plane, or if underlying
planes do not cover the entire CRTC.

During DC validation, attempt to enable a separate DCN pipe for the
cursor if it's in overlay mode. If that fails, or if no overlay mode is
requested, then fallback to native mode.

v2:
* Update commit message for when overlay cursor should be enabled
* Also consider scale and no-underlying-plane case (cursor on crtc bg)
* Consider all underlying planes when determinig overlay/native, not
  just the plane immediately beneath the cursor, as it may not cover the
  entire CRTC.
* Fix typo s/decending/descending/
* Force native cursor on pre-DCN hardware

Signed-off-by: Leo Li 
Acked-by: Harry Wentland 
Acked-by: Pekka Paalanen 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 490 +-
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |   7 +
 .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c|   1 +
 .../amd/display/amdgpu_dm/amdgpu_dm_plane.c   |  13 +-
 4 files changed, 386 insertions(+), 125 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 8245cc63712f..b4b5b73707c1 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -8490,8 +8490,22 @@ static void amdgpu_dm_commit_planes(struct 
drm_atomic_state *state,
 * Disable the cursor first if we're disabling all the planes.
 * It'll remain on the screen after the planes are re-enabled
 * if we don't.
+*
+* If the cursor is transitioning from native to overlay mode, the
+* native cursor needs to be disabled first.
 */
-   if (acrtc_state->active_planes == 0)
+   if (acrtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE &&
+   dm_old_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) {
+   struct dc_cursor_position cursor_position = {0};
+
+   dc_stream_set_cursor_position(acrtc_state->stream,
+ _position);
+   bundle->stream_update.cursor_position =
+   _state->stream->cursor_position;
+   }
+
+   if (acrtc_state->active_planes == 0 &&
+   dm_old_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE)
amdgpu_dm_commit_cursors(state);
 
/* update planes when needed */
@@ -8505,7 +8519,8 @@ static void amdgpu_dm_commit_planes(struct 
drm_atomic_state *state,
struct dm_plane_state *dm_new_plane_state = 
to_dm_plane_state(new_plane_state);
 
/* Cursor plane is handled after stream updates */
-   if (plane->type == DRM_PLANE_TYPE_CURSOR) {
+   if (plane->type == DRM_PLANE_TYPE_CURSOR &&
+   acrtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) {
if ((fb && crtc == pcrtc) ||
(old_plane_state->fb && old_plane_state->crtc == 
pcrtc)) {
cursor_update = true;
@@ -8863,7 +8878,8 @@ static void amdgpu_dm_commit_planes(struct 
drm_atomic_state *state,
 * to be disabling a single plane - those pipes are being disabled.
 */
if (acrtc_state->active_planes &&
-   (!updated_planes_and_streams || amdgpu_ip_version(dm->adev, 
DCE_HWIP, 0) == 0))
+   (!updated_planes_and_streams || amdgpu_ip_version(dm->adev, 
DCE_HWIP, 0) == 0) &&
+   

[PATCH 2/2] drm/amd/display: Move PRIMARY plane zpos higher

[sunpeng.li]

From: Leo Li 

[Why]

Compositors have different ways of assigning surfaces to DRM planes for
render offloading. It may decide between various strategies: overlay,
underlay, or a mix of both

One way for compositors to implement the underlay strategy is to assign
a higher zpos to the DRM_PRIMARY plane than the DRM_OVERLAY planes,
effectively turning the DRM_OVERLAY plane into an underlay plane.

Today, amdgpu attaches an immutable zpos of 0 to the DRM_PRIMARY plane.
This however, is an arbitrary restriction. DCN pipes are general
purpose, and can be arranged in any z-order. To support compositors
using this allocation scheme, we can set a non-zero immutable zpos for
the PRIMARY, allowing the placement of OVERLAYS (mutable zpos range
0-254) beneath the PRIMARY.

[How]

Assign a zpos = #no of OVERLAY planes to the PRIMARY plane. Then, clean
up any assumptions in the driver of PRIMARY plane having the lowest
zpos.

Signed-off-by: Leo Li 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 96 ++-
 .../amd/display/amdgpu_dm/amdgpu_dm_plane.c   | 17 +++-
 2 files changed, 104 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 09ab330aed17..01b00f587701 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -80,6 +80,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
@@ -369,6 +370,20 @@ static inline void reverse_planes_order(struct 
dc_surface_update *array_of_surfa
swap(array_of_surface_update[i], array_of_surface_update[j]);
 }
 
+/*
+ * DC will program planes with their z-order determined by their ordering
+ * in the dc_surface_updates array. This comparator is used to sort them
+ * by descending zpos.
+ */
+static int dm_plane_layer_index_cmp(const void *a, const void *b)
+{
+   const struct dc_surface_update *sa = (struct dc_surface_update *)a;
+   const struct dc_surface_update *sb = (struct dc_surface_update *)b;
+
+   /* Sort by descending dc_plane layer_index (i.e. normalized_zpos) */
+   return sb->surface->layer_index - sa->surface->layer_index;
+}
+
 /**
  * update_planes_and_stream_adapter() - Send planes to be updated in DC
  *
@@ -393,7 +408,8 @@ static inline bool update_planes_and_stream_adapter(struct 
dc *dc,
struct dc_stream_update 
*stream_update,
struct dc_surface_update 
*array_of_surface_update)
 {
-   reverse_planes_order(array_of_surface_update, planes_count);
+   sort(array_of_surface_update, planes_count,
+sizeof(*array_of_surface_update), dm_plane_layer_index_cmp, NULL);
 
/*
 * Previous frame finished and HW is ready for optimization.
@@ -9363,6 +9379,8 @@ static void amdgpu_dm_atomic_commit_tail(struct 
drm_atomic_state *state)
for (j = 0; j < status->plane_count; j++)
dummy_updates[j].surface = status->plane_states[0];
 
+   sort(dummy_updates, status->plane_count,
+sizeof(*dummy_updates), dm_plane_layer_index_cmp, NULL);
 
mutex_lock(>dc_lock);
dc_update_planes_and_stream(dm->dc,
@@ -10097,6 +10115,17 @@ static bool should_reset_plane(struct drm_atomic_state 
*state,
if (new_crtc_state->color_mgmt_changed)
return true;
 
+   /*
+* On zpos change, planes need to be reordered by removing and re-adding
+* them one by one to the dc state, in order of descending zpos.
+*
+* TODO: We can likely skip bandwidth validation if the only thing that
+* changed about the plane was it'z z-ordering.
+*/
+   if (new_crtc_state->zpos_changed) {
+   return true;
+   }
+
if (drm_atomic_crtc_needs_modeset(new_crtc_state))
return true;
 
@@ -10509,6 +10538,65 @@ dm_get_plane_scale(struct drm_plane_state *plane_state,
*out_plane_scale_h = plane_state->crtc_h * 1000 / plane_src_h;
 }
 
+/*
+ * The normalized_zpos value cannot be used by this iterator directly. It's 
only
+ * calculated for enabled planes, potentially causing normalized_zpos 
collisions
+ * between enabled/disabled planes in the atomic state. We need a unique value
+ * so that the iterator will not generate the same object twice, or loop
+ * indefinitely.
+ */
+static inline struct __drm_planes_state *__get_next_zpos(
+   struct drm_atomic_state *state,
+   struct __drm_planes_state *prev)
+{
+   unsigned int highest_zpos = 0, prev_zpos = 256;
+   uint32_t highest_id = 0, prev_id = UINT_MAX;
+   struct drm_plane_state *new_plane_state;
+   struct drm_plane *plane;
+   int i, highest_i = -1;
+
+   if (prev != NULL) {
+   prev_zpos = prev->new_state->zpos;
+   prev_id = 

[PATCH 1/2] drm/amd/display: Introduce overlay cursor mode

[sunpeng.li]

From: Leo Li 

[Why]

DCN is the display hardware for amdgpu. DRM planes are backed by DCN
hardware pipes, which carry pixel data from one end (memory), to the
other (output encoder).

Each DCN pipe has the ability to blend in a cursor early on in the
pipeline. In other words, there are no dedicated cursor planes in DCN,
which makes cursor behavior somewhat unintuitive for compositors.

For example, if the cursor is in RGB format, but the top-most DRM plane
is in YUV format, DCN will not be able to blend them. Because of this,
amdgpu_dm rejects all configurations where a cursor needs to be enabled
on top of a YUV formatted plane.

>From a compositor's perspective, when computing an allocation for
hardware plane offloading, this cursor-on-yuv configuration result in an
atomic test failure. Since the failure reason is not obvious at all,
compositors will likely fall back to full rendering, which is not ideal.

Instead, amdgpu_dm can try to accommodate the cursor-on-yuv
configuration by opportunistically reserving a separate DCN pipe just
for the cursor. We can refer to this as "overlay cursor mode". It is
contrasted with "native cursor mode", where the native DCN per-pipe
cursor is used.

[How]

On each crtc, compute whether the cursor plane should be enabled in
overlay mode (which currently, is iff the immediate plane below has a
YUV format). If it is, mark the CRTC as requesting overlay cursor mode.

During DC validation, attempt to enable a separate DCN pipe for the
cursor if it's in overlay mode. If that fails, or if no overlay mode is
requested, then fallback to native mode.

Signed-off-by: Leo Li 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 309 +++---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |   7 +
 .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c|   1 +
 .../amd/display/amdgpu_dm/amdgpu_dm_plane.c   |  13 +-
 4 files changed, 288 insertions(+), 42 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 21a61454c878..09ab330aed17 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -8359,8 +8359,19 @@ static void amdgpu_dm_commit_planes(struct 
drm_atomic_state *state,
 * Disable the cursor first if we're disabling all the planes.
 * It'll remain on the screen after the planes are re-enabled
 * if we don't.
+*
+* If the cursor is transitioning from native to overlay mode, the
+* native cursor needs to be disabled first.
 */
-   if (acrtc_state->active_planes == 0)
+   if (acrtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE &&
+   dm_old_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) {
+   struct dc_cursor_position cursor_position = {0};
+   dc_stream_set_cursor_position(acrtc_state->stream,
+ _position);
+   }
+
+   if (acrtc_state->active_planes == 0 &&
+   dm_old_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE)
amdgpu_dm_commit_cursors(state);
 
/* update planes when needed */
@@ -8374,7 +8385,8 @@ static void amdgpu_dm_commit_planes(struct 
drm_atomic_state *state,
struct dm_plane_state *dm_new_plane_state = 
to_dm_plane_state(new_plane_state);
 
/* Cursor plane is handled after stream updates */
-   if (plane->type == DRM_PLANE_TYPE_CURSOR) {
+   if (plane->type == DRM_PLANE_TYPE_CURSOR &&
+   acrtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) {
if ((fb && crtc == pcrtc) ||
(old_plane_state->fb && old_plane_state->crtc == 
pcrtc))
cursor_update = true;
@@ -8727,7 +8739,8 @@ static void amdgpu_dm_commit_planes(struct 
drm_atomic_state *state,
 * This avoids redundant programming in the case where we're going
 * to be disabling a single plane - those pipes are being disabled.
 */
-   if (acrtc_state->active_planes)
+   if (acrtc_state->active_planes &&
+   acrtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE)
amdgpu_dm_commit_cursors(state);
 
 cleanup:
@@ -10039,7 +10052,8 @@ static bool should_reset_plane(struct drm_atomic_state 
*state,
 {
struct drm_plane *other;
struct drm_plane_state *old_other_state, *new_other_state;
-   struct drm_crtc_state *new_crtc_state;
+   struct drm_crtc_state *old_crtc_state, *new_crtc_state;
+   struct dm_crtc_state *old_dm_crtc_state, *new_dm_crtc_state;
struct amdgpu_device *adev = drm_to_adev(plane->dev);
int i;
 
@@ -10061,10 +10075,24 @@ static bool should_reset_plane(struct 
drm_atomic_state *state,
 
new_crtc_state =
drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
+   old_crtc_state =
+   

[PATCH 0/2] drm/amdgpu/display: Make multi-plane configurations more flexible

[sunpeng.li]

From: Leo Li 

These patches aim to make the amdgpgu KMS driver play nicer with compositors
when building multi-plane scanout configurations. They do so by:

1. Making cursor behavior more sensible.
2. Allowing placement of DRM OVERLAY planes underneath the PRIMARY plane for
   'underlay' configurations (perhaps more of a RFC, see below).

Please see the commit messages for details.


For #2, the simplest way to accomplish this was to increase the value of the
immutable zpos property for the PRIMARY plane. This allowed OVERLAY planes with
a mutable zpos range of (0-254) to be positioned underneath the PRIMARY for an
underlay scanout configuration.

Technically speaking, DCN hardware does not have a concept of primary or overlay
planes - there are simply 4 general purpose hardware pipes that can be maped in
any configuration. So the immutable zpos restriction on the PRIMARY plane is
kind of arbitrary; it can have a mutable range of (0-254) just like the
OVERLAYs. The distinction between PRIMARY and OVERLAY planes is also somewhat
arbitrary. We can interpret PRIMARY as the first plane that should be enabled on
a CRTC, but beyond that, it doesn't mean much for amdgpu.

Therefore, I'm curious about how compositors devs understand KMS planes and
their zpos properties, and how we would like to use them. It isn't clear to me
how compositors wish to interpret and use the DRM zpos property, or
differentiate between OVERLAY and PRIMARY planes, when it comes to setting up
multi-plane scanout.

Ultimately, what I'd like to answer is "What can we do on the KMS driver and DRM
plane API side, that can make building multi-plane scanout configurations easier
for compositors?" I'm hoping we can converge on something, whether that be
updating the existing documentation to better define the usage, or update the
API to provide support for something that is lacking.

Thanks,
Leo


Some links to provide context and details:
* What is underlay?: 
https://gitlab.freedesktop.org/emersion/libliftoff/-/issues/76
* Discussion on how to implement underlay on Weston: 
https://gitlab.freedesktop.org/wayland/weston/-/merge_requests/1258#note_2325164

Cc: Joshua Ashton 
Cc: Michel Dänzer 
Cc: Chao Guo 
Cc: Xaver Hugl 
Cc: Vikas Korjani 
Cc: Robert Mader 
Cc: Pekka Paalanen 
Cc: Sean Paul 
Cc: Simon Ser 
Cc: Shashank Sharma 
Cc: Harry Wentland 
Cc: Sebastian Wick 

Leo Li (2):
  drm/amd/display: Introduce overlay cursor mode
  drm/amd/display: Move PRIMARY plane zpos higher

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 405 --
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |   7 +
 .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c|   1 +
 .../amd/display/amdgpu_dm/amdgpu_dm_plane.c   |  28 +-
 4 files changed, 391 insertions(+), 50 deletions(-)

-- 
2.44.0

[PATCH] drm/amd/display: Fail atomic_check early on normalize_zpos error

[sunpeng.li]

From: Leo Li 

[Why]

drm_atomic_normalize_zpos() can return an error code when there's
modeset lock contention. This was being ignored.

[How]

Bail out of atomic check if normalize_zpos() returns an error.

Fixes: b261509952bc ("drm/amd/display: Fix double cursor on non-video RGB MPO")
Signed-off-by: Leo Li 
Tested-by: Mikhail Gavrilov 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index c10982f841f98..cb2a57503000d 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -9889,7 +9889,11 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
 * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in
 * atomic state, so call drm helper to normalize zpos.
 */
-   drm_atomic_normalize_zpos(dev, state);
+   ret = drm_atomic_normalize_zpos(dev, state);
+   if (ret) {
+   drm_dbg(dev, "drm_atomic_normalize_zpos() failed\n");
+   goto fail;
+   }
 
/* Remove exiting planes if they are modified */
for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, 
new_plane_state, i) {
-- 
2.39.1

[PATCH v2] drm/amd/display: Prevent OTG shutdown during PSR SU

[sunpeng.li]

From: Leo Li 

[Why]

Enabling Z10 optimizations allows DMUB to disable the OTG during PSR
link-off. This theoretically saves power by putting more of the display
hardware to sleep. However, we observe that with PSR SU, it causes
visual artifacts, higher power usage, and potential system hang.

This is partly due to an odd behavior with the VStartup interrupt used
to signal DRM vblank events. If the OTG is toggled on/off during a PSR
link on/off cycle, the vstartup interrupt fires twice in quick
succession. This generates incorrectly timed vblank events.
Additionally, it can cause cursor updates to generate visual artifacts.

Note that this is not observed with PSR1 since PSR is fully disabled
when there are vblank event requestors. Cursor updates are also
artifact-free, likely because there are no selectively-updated (SU)
frames that can generate artifacts.

[How]

A potential solution is to disable z10 idle optimizations only when fast
updates (flips & cursor updates) are committed. A mechanism to do so
would require some thoughtful design. Let's just disable idle
optimizations for PSR2 for now.

Fixes: 7cc191ee7621 ("drm/amd/display: Implement MPO PSR SU")
Reported-by: August Wikerfors 
Link: 
https://lore.kernel.org/r/c1f8886a-5624-8f49-31b1-e42b6d20d...@augustwikerfors.se/
Tested-by: August Wikerfors 
Reviewed-by: Harry Wentland 
Signed-off-by: Leo Li 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
index c8da18e45b0e..8ca10ab3dfc1 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
@@ -170,7 +170,13 @@ bool amdgpu_dm_psr_enable(struct dc_stream_state *stream)
   , 1,
   );
 
-   power_opt |= psr_power_opt_z10_static_screen;
+   /*
+* Only enable static-screen optimizations for PSR1. For PSR SU, this
+* causes vstartup interrupt issues, used by amdgpu_dm to send vblank
+* events.
+*/
+   if (link->psr_settings.psr_version < DC_PSR_VERSION_SU_1)
+   power_opt |= psr_power_opt_z10_static_screen;
 
return dc_link_set_psr_allow_active(link, _enable, false, false, 
_opt);
 }
-- 
2.37.3

[PATCH] drm/amdgpu: Fix mc_umc_status used uninitialized warning

[sunpeng.li]

From: Leo Li 

On ChromeOS clang build, the following warning is seen:

/mnt/host/source/src/third_party/kernel/v5.15/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c:463:6:
 error: variable 'mc_umc_status' is used uninitialized whenever 'if' condition 
is false [-Werror,-Wsometimes-uninitialized]
if (mca_addr == UMC_INVALID_ADDR) {
^~~~
/mnt/host/source/src/third_party/kernel/v5.15/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c:485:21:
 note: uninitialized use occurs here
if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 
1 &&
   ^
/mnt/host/source/src/third_party/kernel/v5.15/drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu.h:1208:5:
 note: expanded from macro 'REG_GET_FIELD'
(((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
   ^
/mnt/host/source/src/third_party/kernel/v5.15/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c:463:2:
 note: remove the 'if' if its condition is always true
if (mca_addr == UMC_INVALID_ADDR) {
^~
/mnt/host/source/src/third_party/kernel/v5.15/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c:460:24:
 note: initialize the variable 'mc_umc_status' to silence this warning
uint64_t mc_umc_status, mc_umc_addrt0;
  ^
   = 0
1 error generated.
make[5]: *** 
[/mnt/host/source/src/third_party/kernel/v5.15/scripts/Makefile.build:289: 
drivers/gpu/drm/amd/amdgpu/umc_v6_7.o] Error 1

Fix by initializing mc_umc_status = 0.

Fixes: d8e19e32945e ("drm/amdgpu: support to convert dedicated umc mca address")
Signed-off-by: Leo Li 
---
 drivers/gpu/drm/amd/amdgpu/umc_v6_7.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c 
b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
index 2cc961534542..a0d19b768346 100644
--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
@@ -457,7 +457,7 @@ static void umc_v6_7_query_error_address(struct 
amdgpu_device *adev,
 {
uint32_t mc_umc_status_addr;
uint32_t channel_index;
-   uint64_t mc_umc_status, mc_umc_addrt0;
+   uint64_t mc_umc_status = 0, mc_umc_addrt0;
uint64_t err_addr, soc_pa, retired_page, column;
 
if (mca_addr == UMC_INVALID_ADDR) {
-- 
2.37.3

[PATCH] drm/amd/display: Prevent OTG shutdown during PSR SU

[sunpeng.li]

From: Leo Li 

[Why]

Enabling Z10 optimizations allows DMUB to disable the OTG during PSR
link-off. This theoretically saves power by putting more of the display
hardware to sleep. However, we observe that with PSR SU, it causes
visual artifacts, higher power usage, and potential system hang.

This is partly due to an odd behavior with the VStartup interrupt used
to signal DRM vblank events. If the OTG is toggled on/off during a PSR
link on/off cycle, the vstartup interrupt fires twice in quick
succession. This generates incorrectly timed vblank events.
Additionally, it can cause cursor updates to generate visual artifacts.

Note that this is not observed with PSR1 since PSR is fully disabled
when there are vblank event requestors. Cursor updates are also
artifact-free, likely because there are no selectively-updated (SU)
frames that can generate artifacts.

[How]

A potential solution is to disable z10 idle optimizations only when fast
updates (flips & cursor updates) are committed. A mechanism to do so
would require some thoughtful design. Let's just disable idle
optimizations for PSR2 for now.

Fixes: 7cc191ee7621 ("drm/amd/display: Implement MPO PSR SU")
Signed-off-by: Leo Li 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
index c8da18e45b0e..8ca10ab3dfc1 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
@@ -170,7 +170,13 @@ bool amdgpu_dm_psr_enable(struct dc_stream_state *stream)
   , 1,
   );
 
-   power_opt |= psr_power_opt_z10_static_screen;
+   /*
+* Only enable static-screen optimizations for PSR1. For PSR SU, this
+* causes vstartup interrupt issues, used by amdgpu_dm to send vblank
+* events.
+*/
+   if (link->psr_settings.psr_version < DC_PSR_VERSION_SU_1)
+   power_opt |= psr_power_opt_z10_static_screen;
 
return dc_link_set_psr_allow_active(link, _enable, false, false, 
_opt);
 }
-- 
2.37.3

[PATCH v2] drm/amdgpu: Check BO's requested pinning domains against its preferred_domains

[sunpeng.li]

From: Leo Li 

When pinning a buffer, we should check to see if there are any
additional restrictions imposed by bo->preferred_domains. This will
prevent the BO from being moved to an invalid domain when pinning.

For example, this can happen if the user requests to create a BO in GTT
domain for display scanout. amdgpu_dm will allow pinning to either VRAM
or GTT domains, since DCN can scanout from either or. However, in
amdgpu_bo_pin_restricted(), pinning to VRAM is preferred if there is
adequate carveout. This can lead to pinning to VRAM despite the user
requesting GTT placement for the BO.

v2: Allow the kernel to override the domain, which can happen when
exporting a BO to a V4L camera (for example).

Signed-off-by: Leo Li 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 8a7b0f6162da..bbd3b8b14cfb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -883,6 +883,10 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 
domain,
if (WARN_ON_ONCE(min_offset > max_offset))
return -EINVAL;
 
+   /* Check domain to be pinned to against preferred domains */
+   if (bo->preferred_domains & domain)
+   domain = bo->preferred_domains & domain;
+
/* A shared bo cannot be migrated to VRAM */
if (bo->tbo.base.import_attach) {
if (domain & AMDGPU_GEM_DOMAIN_GTT)
-- 
2.37.0

[PATCH] drm/amdgpu: Check BO's requested pinning domains against its preferred_domains

[sunpeng.li]

From: Leo Li 

When pinning a buffer, we should check to see if there are any
additional restrictions imposed by bo->preferred_domains. This will
prevent the BO from being moved to an invalid domain when pinning.

For example, this can happen if the user requests to create a BO in GTT
domain for display scanout. amdgpu_dm will allow pinning to either VRAM
or GTT domains, since DCN can scanout from either or. However, in
amdgpu_bo_pin_restricted(), pinning to VRAM is preferred if there is
adequate carveout. This can lead to pinning to VRAM despite the user
requesting GTT placement for the BO.

Signed-off-by: Leo Li 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 8a7b0f6162da..50400d70ef12 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -883,6 +883,9 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 
domain,
if (WARN_ON_ONCE(min_offset > max_offset))
return -EINVAL;
 
+   /* Check domain to be pinned to against preferred domains */
+   domain = bo->preferred_domains & domain;
+
/* A shared bo cannot be migrated to VRAM */
if (bo->tbo.base.import_attach) {
if (domain & AMDGPU_GEM_DOMAIN_GTT)
-- 
2.37.0

[PATCH 2/2] drm/amd/display: Add dcdebugmask option for disabling MPO

[sunpeng.li]

From: Leo Li 

[Why & How]

It's useful to disable MPO when debugging or testing. Therefore, add a
dcdebugmask option to disable MPO.

Signed-off-by: Leo Li 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 
 drivers/gpu/drm/amd/include/amd_shared.h  | 1 +
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index d7208c0b76b1..4cf11bcc01a4 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4194,6 +4194,10 @@ static int amdgpu_dm_initialize_drm_device(struct 
amdgpu_device *adev)
for (i = 0; i < dm->dc->caps.max_planes; ++i) {
struct dc_plane_cap *plane = >dc->caps.planes[i];
 
+   /* Do not create overlay if MPO disabled */
+   if (amdgpu_dc_debug_mask & DC_DISABLE_MPO)
+   break;
+
if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
continue;
 
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h 
b/drivers/gpu/drm/amd/include/amd_shared.h
index 1db21d13726d..f175e65b853a 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -249,6 +249,7 @@ enum DC_DEBUG_MASK {
DC_DISABLE_CLOCK_GATING = 0x8,
DC_DISABLE_PSR = 0x10,
DC_FORCE_SUBVP_MCLK_SWITCH = 0x20,
+   DC_DISABLE_MPO = 0x40,
 };
 
 enum amd_dpm_forced_level;
-- 
2.37.0

[PATCH 1/2] drm/amd/display: Add visualconfirm module parameter

[sunpeng.li]

From: Leo Li 

[Why]

Being able to configure visual confirm at boot or in cmdline is helpful
when debugging.

[How]

Add a module parameter to configure DC visual confirm, which works the
same way as the equivalent debugfs entry.

Signed-off-by: Leo Li 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h   | 1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c   | 4 
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++
 3 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 845d6054992a..4629bef6c44e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -197,6 +197,7 @@ extern uint amdgpu_smu_memory_pool_size;
 extern int amdgpu_smu_pptable_id;
 extern uint amdgpu_dc_feature_mask;
 extern uint amdgpu_dc_debug_mask;
+extern uint amdgpu_dc_visual_confirm;
 extern uint amdgpu_dm_abm_level;
 extern int amdgpu_backlight;
 extern struct amdgpu_mgpu_info mgpu_info;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 1cc9260e75de..e1e8cf70e719 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -167,6 +167,7 @@ int amdgpu_smu_pptable_id = -1;
  */
 uint amdgpu_dc_feature_mask = 2;
 uint amdgpu_dc_debug_mask;
+uint amdgpu_dc_visual_confirm;
 int amdgpu_async_gfx_ring = 1;
 int amdgpu_mcbp;
 int amdgpu_discovery = -1;
@@ -827,6 +828,9 @@ module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, 
uint, 0444);
 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))");
 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444);
 
+MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 
= PSR)");
+module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444);
+
 /**
  * DOC: abmlevel (uint)
  * Override the default ABM (Adaptive Backlight Management) level used for DC
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index eb5efb4aa2ba..d7208c0b76b1 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1562,6 +1562,8 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH)
adev->dm.dc->debug.force_subvp_mclk_switch = true;
 
+   adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm;
+
r = dm_dmub_hw_init(adev);
if (r) {
DRM_ERROR("DMUB interface failed to initialize: status=%d\n", 
r);
-- 
2.37.0

[PATCH] drm/amd/display: Use pre-allocated temp struct for bounding box update

[sunpeng.li]

From: Leo Li 

[Why]

There is a theoretical problem in prior patches for reducing the stack
size of *update_bw_bounding_box() functions.

By modifying the soc.clock_limits[n] struct directly, this can cause
unintended behavior as the for loop attempts to swap rows in
clock_limits[n]. A temporary struct is still required to make sure we
stay functinoally equivalent.

[How]

Add a temporary clock_limits table to the SOC struct, and use it when
swapping rows.

Signed-off-by: Leo Li 
---
 .../drm/amd/display/dc/dml/dcn20/dcn20_fpu.c  | 33 +-
 .../amd/display/dc/dml/dcn301/dcn301_fpu.c| 36 ++-
 .../drm/amd/display/dc/dml/dcn31/dcn31_fpu.c  | 64 +++
 .../amd/display/dc/dml/display_mode_structs.h |  5 ++
 4 files changed, 82 insertions(+), 56 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
index c2fec0d85da4..e247b2270b1d 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
@@ -2015,9 +2015,8 @@ void dcn21_update_bw_bounding_box(struct dc *dc, struct 
clk_bw_params *bw_params
 
ASSERT(clk_table->num_entries);
/* Copy dcn2_1_soc.clock_limits to clock_limits to avoid copying over 
null states later */
-   for (i = 0; i < dcn2_1_soc.num_states + 1; i++) {
-   dcn2_1_soc.clock_limits[i] = dcn2_1_soc.clock_limits[i];
-   }
+   memcpy(_1_soc._clock_tmp, _1_soc.clock_limits,
+  sizeof(dcn2_1_soc.clock_limits));
 
for (i = 0; i < clk_table->num_entries; i++) {
/* loop backwards*/
@@ -2032,22 +2031,26 @@ void dcn21_update_bw_bounding_box(struct dc *dc, struct 
clk_bw_params *bw_params
if (i == 1)
k++;
 
-   dcn2_1_soc.clock_limits[k].state = k;
-   dcn2_1_soc.clock_limits[k].dcfclk_mhz = 
clk_table->entries[i].dcfclk_mhz;
-   dcn2_1_soc.clock_limits[k].fabricclk_mhz = 
clk_table->entries[i].fclk_mhz;
-   dcn2_1_soc.clock_limits[k].socclk_mhz = 
clk_table->entries[i].socclk_mhz;
-   dcn2_1_soc.clock_limits[k].dram_speed_mts = 
clk_table->entries[i].memclk_mhz * 2;
+   dcn2_1_soc._clock_tmp[k].state = k;
+   dcn2_1_soc._clock_tmp[k].dcfclk_mhz = 
clk_table->entries[i].dcfclk_mhz;
+   dcn2_1_soc._clock_tmp[k].fabricclk_mhz = 
clk_table->entries[i].fclk_mhz;
+   dcn2_1_soc._clock_tmp[k].socclk_mhz = 
clk_table->entries[i].socclk_mhz;
+   dcn2_1_soc._clock_tmp[k].dram_speed_mts = 
clk_table->entries[i].memclk_mhz * 2;
 
-   dcn2_1_soc.clock_limits[k].dispclk_mhz = 
dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
-   dcn2_1_soc.clock_limits[k].dppclk_mhz = 
dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
-   dcn2_1_soc.clock_limits[k].dram_bw_per_chan_gbps = 
dcn2_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
-   dcn2_1_soc.clock_limits[k].dscclk_mhz = 
dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
-   dcn2_1_soc.clock_limits[k].dtbclk_mhz = 
dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
-   dcn2_1_soc.clock_limits[k].phyclk_d18_mhz = 
dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
-   dcn2_1_soc.clock_limits[k].phyclk_mhz = 
dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
+   dcn2_1_soc._clock_tmp[k].dispclk_mhz = 
dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
+   dcn2_1_soc._clock_tmp[k].dppclk_mhz = 
dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
+   dcn2_1_soc._clock_tmp[k].dram_bw_per_chan_gbps = 
dcn2_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
+   dcn2_1_soc._clock_tmp[k].dscclk_mhz = 
dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
+   dcn2_1_soc._clock_tmp[k].dtbclk_mhz = 
dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
+   dcn2_1_soc._clock_tmp[k].phyclk_d18_mhz = 
dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
+   dcn2_1_soc._clock_tmp[k].phyclk_mhz = 
dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
 
k++;
}
+
+   memcpy(_1_soc.clock_limits, _1_soc._clock_tmp,
+  sizeof(dcn2_1_soc.clock_limits));
+
if (clk_table->num_entries) {
dcn2_1_soc.num_states = clk_table->num_entries + 1;
/* fill in min DF PState */
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c
index 62cf283d9f41..e4863f0bf0f6 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c
@@ -254,6 +254,9 @@ void dcn301_update_bw_bounding_box(struct dc *dc, struct 
clk_bw_params *bw_param
 
dc_assert_fp_enabled();
 
+   

[PATCH v2 3/4] drm/amd/display: pass panel instance in DMUB dirty rect command

[sunpeng.li]

From: David Zhang 

[Why]

In cases where there are multiple eDP instances, DMUB needs to know
which instance the command is for. Today, the field for specifying the
panel_inst exists in both dmub_cmd_update_dirty_rect_data and
dmub_cmd_update_cursor_info_data.

For cursor updates, we already specify the panel_inst, but that's not
the case for dirty_rect updates. Today, a value of '0' is used (due
to initial memsetting of the cmd struct to 0)

[how]

In dc_dmub_update_dirty_rect(), Call dc_get_edp_link_panel_inst() to get
the panel_inst, and fill it in the DMUB cmd struct.

v2: Update commit message for clarity.

Signed-off-by: Mikita Lipski 
Signed-off-by: David Zhang 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index d4173be11903..31d83297bcb5 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2837,10 +2837,14 @@ void dc_dmub_update_dirty_rect(struct dc *dc,
struct dc_context *dc_ctx = dc->ctx;
struct dmub_cmd_update_dirty_rect_data *update_dirty_rect;
unsigned int i, j;
+   unsigned int panel_inst = 0;
 
if (stream->link->psr_settings.psr_version != DC_PSR_VERSION_SU_1)
return;
 
+   if (!dc_get_edp_link_panel_inst(dc, stream->link, _inst))
+   return;
+
memset(, 0x0, sizeof(cmd));
cmd.update_dirty_rect.header.type = DMUB_CMD__UPDATE_DIRTY_RECT;
cmd.update_dirty_rect.header.sub_type = 0;
@@ -2869,6 +2873,7 @@ void dc_dmub_update_dirty_rect(struct dc *dc,
if (pipe_ctx->plane_state != plane_state)
continue;
 
+   update_dirty_rect->panel_inst = panel_inst;
update_dirty_rect->pipe_idx = j;
dc_dmub_srv_cmd_queue(dc_ctx->dmub_srv, );
dc_dmub_srv_cmd_execute(dc_ctx->dmub_srv);
-- 
2.36.1

[PATCH 4/4] drm/amd/display: refactor dirty rect dmub command decision

[sunpeng.li]

From: Robin Chen 

[Why]
To wrap the decision logic of sending dirty rect dmub command
for both frame update and cursor update path.

Signed-off-by: Robin Chen 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c  | 14 ++-
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 24 ++-
 2 files changed, 31 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 31d83297bcb5..645ec5bc3a7d 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2827,6 +2827,18 @@ static void commit_planes_do_stream_update(struct dc *dc,
}
 }
 
+static bool dc_dmub_should_send_dirty_rect_cmd(struct dc *dc, struct 
dc_stream_state *stream)
+{
+   if (stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1)
+   return true;
+
+   if (stream->link->psr_settings.psr_version == DC_PSR_VERSION_1 &&
+   dc->debug.enable_sw_cntl_psr)
+   return true;
+
+   return false;
+}
+
 void dc_dmub_update_dirty_rect(struct dc *dc,
   int surface_count,
   struct dc_stream_state *stream,
@@ -2839,7 +2851,7 @@ void dc_dmub_update_dirty_rect(struct dc *dc,
unsigned int i, j;
unsigned int panel_inst = 0;
 
-   if (stream->link->psr_settings.psr_version != DC_PSR_VERSION_SU_1)
+   if (!dc_dmub_should_send_dirty_rect_cmd(dc, stream))
return;
 
if (!dc_get_edp_link_panel_inst(dc, stream->link, _inst))
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 7fe06a2c0c04..5b5e0dd13fd0 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -3325,6 +3325,23 @@ static bool dcn10_can_pipe_disable_cursor(struct 
pipe_ctx *pipe_ctx)
return false;
 }
 
+static bool dcn10_dmub_should_update_cursor_data(
+   struct pipe_ctx *pipe_ctx,
+   struct dc_debug_options *debug)
+{
+   if (pipe_ctx->plane_state->address.type == 
PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
+   return false;
+
+   if (pipe_ctx->stream->link->psr_settings.psr_version == 
DC_PSR_VERSION_SU_1)
+   return true;
+
+   if (pipe_ctx->stream->link->psr_settings.psr_version == 
DC_PSR_VERSION_1 &&
+   debug->enable_sw_cntl_psr)
+   return true;
+
+   return false;
+}
+
 static void dcn10_dmub_update_cursor_data(
struct pipe_ctx *pipe_ctx,
struct hubp *hubp,
@@ -3346,13 +3363,8 @@ static void dcn10_dmub_update_cursor_data(
 
struct dc_debug_options *debug = >ctx->dc->debug;
 
-   if (!debug->enable_sw_cntl_psr && 
pipe_ctx->stream->link->psr_settings.psr_version != DC_PSR_VERSION_SU_1)
+   if (!dcn10_dmub_should_update_cursor_data(pipe_ctx, debug))
return;
-
-   if (pipe_ctx->stream->link->psr_settings.psr_version == 
DC_PSR_VERSION_UNSUPPORTED ||
-   pipe_ctx->plane_state->address.type == 
PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
-   return;
-
/**
 * if cur_pos == NULL means the caller is from cursor_set_attribute
 * then driver use previous cursor position data
-- 
2.36.1

[PATCH 2/4] drm/amd/display: Add PSR-SU-RC support in DC

[sunpeng.li]

From: David Zhang 

[Why]

PSR-SU Rate Control - or PSR-SU-RC - enables PSR-SU panels to work with
variable refresh rate to allow for more power savings. Lowering the
refresh rate can increase PSR residency by expanding the eDP main link
shut down duration. It can also lower panel power consumption.

There is a complication with With PSR, since the eDP main link can be
shut down. Therefore, the timing controller (TCON) on the eDP sink nees
to be able to scan out its remote buffer independant of the main link.
To allow the eDP source to specify the sink's refresh rate while the
link is off, vendor-specific DPCD registers are used. This allows the
eDP source to then "Rate Control" the panel during PSR active.

[How]

Add DC support to communicate with PSR-SU-RC supported eDP sinks. The
sink will need to know the desired VTotal during PSR active.

This change only adds support to DC, support in amdgpu_dm is still pending to
enable this fully.

Signed-off-by: David Zhang 
Signed-off-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 22 ++
 drivers/gpu/drm/amd/display/dc/dc_link.h  |  3 +++
 drivers/gpu/drm/amd/display/dc/dc_types.h |  2 ++
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 23 +++
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h |  2 ++
 .../drm/amd/display/dc/inc/hw/link_encoder.h  |  8 +++
 6 files changed, 60 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 31ffb961e18b..3d6dcaa6a483 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1795,6 +1795,7 @@ static bool dc_link_construct_legacy(struct dc_link *link,
 */
program_hpd_filter(link);
 
+   link->psr_settings.psr_vtotal_control_support = false;
link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
 
DC_LOG_DC("BIOS object table - %s finished successfully.\n", __func__);
@@ -3207,6 +3208,7 @@ bool dc_link_setup_psr(struct dc_link *link,
/* updateSinkPsrDpcdConfig*/
union dpcd_psr_configuration psr_configuration;
union dpcd_alpm_configuration alpm_configuration;
+   union dpcd_sink_active_vtotal_control_mode vtotal_control = {0};
 
psr_context->controllerId = CONTROLLER_ID_UNDEFINED;
 
@@ -3276,6 +3278,13 @@ bool dc_link_setup_psr(struct dc_link *link,
psr_config->su_y_granularity;
psr_context->line_time_in_us =
psr_config->line_time_in_us;
+
+   if (link->psr_settings.psr_vtotal_control_support) {
+   psr_context->rate_control_caps = 
psr_config->rate_control_caps;
+   vtotal_control.bits.ENABLE = true;
+   core_link_write_dpcd(link, 
DP_SINK_PSR_ACTIVE_VTOTAL_CONTROL_MODE,
+   _control.raw, 
sizeof(vtotal_control.raw));
+   }
}
 
psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel;
@@ -3408,6 +3417,19 @@ void dc_link_get_psr_residency(const struct dc_link 
*link, uint32_t *residency)
*residency = 0;
 }
 
+bool dc_link_set_sink_vtotal_in_psr_active(const struct dc_link *link, 
uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su)
+{
+   struct dc *dc = link->ctx->dc;
+   struct dmub_psr *psr = dc->res_pool->psr;
+
+   if (psr == NULL || !link->psr_settings.psr_feature_enabled || 
!link->psr_settings.psr_vtotal_control_support)
+   return false;
+
+   psr->funcs->psr_set_sink_vtotal_in_psr_active(psr, psr_vtotal_idle, 
psr_vtotal_su);
+
+   return true;
+}
+
 const struct dc_link_status *dc_link_get_status(const struct dc_link *link)
 {
return >link_status;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h 
b/drivers/gpu/drm/amd/display/dc/dc_link.h
index 0bec986a6de8..3ec189dd73da 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
@@ -100,6 +100,7 @@ struct psr_settings {
bool psr_feature_enabled;   // PSR is supported by sink
bool psr_allow_active;  // PSR is currently active
enum dc_psr_version psr_version;// Internal PSR 
version, determined based on DPCD
+   bool psr_vtotal_control_support;// Vtotal control is supported 
by sink
 
/* These parameters are calculated in Driver,
 * based on display timing and Sink capabilities.
@@ -324,6 +325,8 @@ void dc_link_get_psr_residency(const struct dc_link *link, 
uint32_t *residency);
 void dc_link_blank_all_dp_displays(struct dc *dc);
 
 void dc_link_blank_dp_stream(struct dc_link *link, bool hw_init);
+bool dc_link_set_sink_vtotal_in_psr_active(const struct dc_link *link,
+   uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su);
 
 /* Request DC to detect if there is a Panel connected.
  * 

[PATCH 3/4] drm/amd/display: pass panel instance in dirty rect message

[sunpeng.li]

From: David Zhang 

[why]
DMUB FW uses OTG instance to get eDP panel instance. But in case
of MPO multiple pipe indexes are passed to updated the same panel.
The other OTG instance passed would be ignored causing in DMUB not
acknowledging the messages.

[how]
Add panel instance to dirty rectangle data and cursor update data
structures and pass to DMUB.

Signed-off-by: Mikita Lipski 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index d4173be11903..31d83297bcb5 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2837,10 +2837,14 @@ void dc_dmub_update_dirty_rect(struct dc *dc,
struct dc_context *dc_ctx = dc->ctx;
struct dmub_cmd_update_dirty_rect_data *update_dirty_rect;
unsigned int i, j;
+   unsigned int panel_inst = 0;
 
if (stream->link->psr_settings.psr_version != DC_PSR_VERSION_SU_1)
return;
 
+   if (!dc_get_edp_link_panel_inst(dc, stream->link, _inst))
+   return;
+
memset(, 0x0, sizeof(cmd));
cmd.update_dirty_rect.header.type = DMUB_CMD__UPDATE_DIRTY_RECT;
cmd.update_dirty_rect.header.sub_type = 0;
@@ -2869,6 +2873,7 @@ void dc_dmub_update_dirty_rect(struct dc *dc,
if (pipe_ctx->plane_state != plane_state)
continue;
 
+   update_dirty_rect->panel_inst = panel_inst;
update_dirty_rect->pipe_idx = j;
dc_dmub_srv_cmd_queue(dc_ctx->dmub_srv, );
dc_dmub_srv_cmd_execute(dc_ctx->dmub_srv);
-- 
2.36.1

[PATCH 0/4] PSR-SU-RC DC support and some PSR-SU fixes

[sunpeng.li]

From: Leo Li 

The first two patches here add PSR SU Rate Control support to DC. Support in
amdgpu_dm is still pending to enable this fully.

The last two patches are some fixes for PSR SU.

David Zhang (3):
  drm/amd/display: expose AMD specific DPCD for PSR-SU-RC support
  drm/amd/display: Add PSR-SU-RC support in DC
  drm/amd/display: pass panel instance in dirty rect message

Robin Chen (1):
  drm/amd/display: refactor dirty rect dmub command decision

 drivers/gpu/drm/amd/display/dc/core/dc.c  | 19 ++-
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 22 +
 drivers/gpu/drm/amd/display/dc/dc_link.h  |  3 +++
 drivers/gpu/drm/amd/display/dc/dc_types.h |  2 ++
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 23 ++
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h |  2 ++
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 24 ++-
 .../drm/amd/display/dc/inc/hw/link_encoder.h  |  8 +++
 .../amd/display/include/ddc_service_types.h   |  4 
 9 files changed, 100 insertions(+), 7 deletions(-)

-- 
2.36.1

[PATCH 1/4] drm/amd/display: expose AMD specific DPCD for PSR-SU-RC support

[sunpeng.li]

From: David Zhang 

[why & how]

Expose vendor specific DPCD registers for rate controlling the eDP sink
TCON's refresh rate during PSR active. When used in combination with
PSR-SU and Freesync, it is called PSR-SU Rate Contorol, or PSR-SU-RC for
short.

v2: Add all DPCD registers required

Signed-off-by: David Zhang 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/include/ddc_service_types.h | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/include/ddc_service_types.h 
b/drivers/gpu/drm/amd/display/include/ddc_service_types.h
index 20a3d4e23f66..05096c644a60 100644
--- a/drivers/gpu/drm/amd/display/include/ddc_service_types.h
+++ b/drivers/gpu/drm/amd/display/include/ddc_service_types.h
@@ -41,6 +41,10 @@
 #define DP_DEVICE_ID_38EC11 0x38EC11
 #define DP_FORCE_PSRSU_CAPABILITY 0x40F
 
+#define DP_SINK_PSR_ACTIVE_VTOTAL  0x373
+#define DP_SINK_PSR_ACTIVE_VTOTAL_CONTROL_MODE 0x375
+#define DP_SOURCE_PSR_ACTIVE_VTOTAL0x376
+
 enum ddc_result {
DDC_RESULT_UNKNOWN = 0,
DDC_RESULT_SUCESSFULL,
-- 
2.36.1

[PATCH] drm/amd/display: Fix DC definition of PMFW Pstate table for DCN316

[sunpeng.li]

From: Leo Li 

[Why]

During DC init, we read power management tables from PMFW. This info is
exchanged in the form of a binary blob inside gpu memory. In order to
parse the binary blob, the correct struct needs to be used.

[How]

Fix dcn316's definition of the DfPstateTable_t struct to align with PMFW

Signed-off-by: Leo Li 
---
 .../amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c| 11 ++-
 .../drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h|  9 +
 2 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
index 02a59adff90d..c940635b7a74 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
@@ -530,7 +530,16 @@ static void dcn316_clk_mgr_helper_populate_bw_params(
bw_params->clk_table.entries[i].fclk_mhz = 
clock_table->DfPstateTable[j].FClk;
bw_params->clk_table.entries[i].memclk_mhz = 
clock_table->DfPstateTable[j].MemClk;
bw_params->clk_table.entries[i].voltage = 
clock_table->DfPstateTable[j].Voltage;
-   bw_params->clk_table.entries[i].wck_ratio = 1;
+   switch (clock_table->DfPstateTable[j].WckRatio) {
+   case WCK_RATIO_1_2:
+   bw_params->clk_table.entries[i].wck_ratio = 2;
+   break;
+   case WCK_RATIO_1_4:
+   bw_params->clk_table.entries[i].wck_ratio = 4;
+   break;
+   default:
+   bw_params->clk_table.entries[i].wck_ratio = 1;
+   }
temp = find_clk_for_voltage(clock_table, 
clock_table->DcfClocks, clock_table->DfPstateTable[j].Voltage);
if (temp)
bw_params->clk_table.entries[i].dcfclk_mhz = temp;
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h
index 4c6b202fe622..658b36d0e107 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h
@@ -57,10 +57,19 @@ typedef enum {
   WM_COUNT,
 } WM_CLOCK_e;
 
+typedef enum{
+  WCK_RATIO_1_1 = 0,  // DDR5, Wck:ck is always 1:1;
+  WCK_RATIO_1_2,
+  WCK_RATIO_1_4,
+  WCK_RATIO_MAX
+} WCK_RATIO_e;
+
 typedef struct {
   uint32_t FClk;
   uint32_t MemClk;
   uint32_t Voltage;
+  uint8_t  WckRatio;
+  uint8_t  Spare[3];
 } DfPstateTable_t;
 
 //Freq in MHz
-- 
2.35.1

[PATCH] drm/amd/display: Fix DC_FP_START/END use on non-DCN builds

[sunpeng.li]

From: Leo Li 

DC_FP_START/END is only defined for CONFIG_DRM_AMD_DC_DCN enabled
builds, and update_bw_bounding_box() is only valid for DCN ASICs.

Therefore, wrap the entire thing in the ifdef guard.

Acked-by: Alex Deucher 
Signed-off-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 4ea114725d61..b1ce3c0cf477 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -987,13 +987,13 @@ static bool dc_construct(struct dc *dc,
goto fail;
 #ifdef CONFIG_DRM_AMD_DC_DCN
dc->clk_mgr->force_smu_not_present = init_params->force_smu_not_present;
-#endif
 
if (dc->res_pool->funcs->update_bw_bounding_box) {
DC_FP_START();
dc->res_pool->funcs->update_bw_bounding_box(dc, 
dc->clk_mgr->bw_params);
DC_FP_END();
}
+#endif
 
/* Creation of current_state must occur after dc->dml
 * is initialized in dc_create_resource_pool because
-- 
2.34.1

[PATCH] drm: Add PSR version 4 macro

[sunpeng.li]

From: Leo Li 

eDP 1.5 specification defines PSR version 4.

It defines PSR1 and PSR2 support with selective-update (SU)
capabilities, with additional support for Y-coordinate and Early
Transport of the selective-update region.

This differs from PSR version 3 in that early transport is supported
for version 4, but not for version 3.

Signed-off-by: Leo Li 
---
 include/drm/drm_dp_helper.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 3f2715eb965f..05268c51acaa 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -360,6 +360,7 @@ struct drm_dp_aux;
 # define DP_PSR_IS_SUPPORTED1
 # define DP_PSR2_IS_SUPPORTED  2   /* eDP 1.4 */
 # define DP_PSR2_WITH_Y_COORD_IS_SUPPORTED  3  /* eDP 1.4a */
+# define DP_PSR2_WITH_ET_IS_SUPPORTED   4  /* eDP 1.5 (eDP 1.4b SCR) */
 
 #define DP_PSR_CAPS 0x071   /* XXX 1.2? */
 # define DP_PSR_NO_TRAIN_ON_EXIT1
-- 
2.34.1

[PATCH v4] drm/amd/display: Disable VUpdate interrupt for DCN hardware

[sunpeng.li]

From: Leo Li 

[Why]

On DCN hardware, the crtc_high_irq handler makes vupdate_high_irq
handler redundant.

All the vupdate handler does is handle vblank events, and update vrr
for DCE hw (excluding VEGA, more on that later). As far as usermode is
concerned. vstartup happens close enough to vupdate on DCN that it can
be considered the "same". Handling vblank and updating vrr at vstartup
effectively replaces vupdate on DCN.

Vega is a bit special. Like DCN, the VRR registers on Vega are
double-buffered, and swapped at vupdate. But Unlike DCN, it lacks a
vstartup interrupt. This means we can't quite remove the vupdate handler
for it, since delayed user events due to vrr are sent off there.

[How]

Remove registration of vupdate interrupt handler for DCN. Disable
vupdate interrupt if asic family DCN, enable otherwise.

Signed-off-by: Leo Li 
---

v2: Don't exclude vega when enabling vupdate interrupts

v3: Move FAMILY_AI check inside dm_set_vupdate_irq()

v4: Correct a brain fart

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 32 +++
 1 file changed, 4 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 256a23a0ec28..d40185dfd0c0 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2241,34 +2241,6 @@ static int dcn10_register_irq_handlers(struct 
amdgpu_device *adev)
dm_dcn_crtc_high_irq, c_irq_params);
}

-   /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
-* the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
-* to trigger at end of each vblank, regardless of state of the lock,
-* matching DCE behaviour.
-*/
-   for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
-i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + 
adev->mode_info.num_crtc - 1;
-i++) {
-   r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, 
>vupdate_irq);
-
-   if (r) {
-   DRM_ERROR("Failed to add vupdate irq id!\n");
-   return r;
-   }
-
-   int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
-   int_params.irq_source =
-   dc_interrupt_to_irq_source(dc, i, 0);
-
-   c_irq_params = >dm.vupdate_params[int_params.irq_source - 
DC_IRQ_SOURCE_VUPDATE1];
-
-   c_irq_params->adev = adev;
-   c_irq_params->irq_src = int_params.irq_source;
-
-   amdgpu_dm_irq_register_interrupt(adev, _params,
-   dm_vupdate_high_irq, c_irq_params);
-   }
-
/* Use GRPH_PFLIP interrupt */
for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + 
adev->mode_info.num_crtc - 1;
@@ -4249,6 +4221,10 @@ static inline int dm_set_vupdate_irq(struct drm_crtc 
*crtc, bool enable)
struct amdgpu_device *adev = crtc->dev->dev_private;
int rc;

+   /* Do not set vupdate for DCN hardware */
+   if (adev->family > AMDGPU_FAMILY_AI)
+   return 0;
+
irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst;

rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
--
2.23.0

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[PATCH v3] drm/amd/display: Disable VUpdate interrupt for DCN hardware

[sunpeng.li]

From: Leo Li 

[Why]

On DCN hardware, the crtc_high_irq handler makes vupdate_high_irq
handler redundant.

All the vupdate handler does is handle vblank events, and update vrr
for DCE hw (excluding VEGA, more on that later). As far as usermode is
concerned. vstartup happens close enough to vupdate on DCN that it can
be considered the "same". Handling vblank and updating vrr at vstartup
effectively replaces vupdate on DCN.

Vega is a bit special. Like DCN, the VRR registers on Vega are
double-buffered, and swapped at vupdate. But Unlike DCN, it lacks a
vstartup interrupt. This means we can't quite remove the vupdate handler
for it, since delayed user events due to vrr are sent off there.

[How]

Remove registration of vupdate interrupt handler for DCN. Disable
vupdate interrupt if asic family DCN, enable otherwise.

Signed-off-by: Leo Li 
---

v2: Don't exclude vega when enabling vupdate interrupts

v3: Move FAMILY_AI check inside dm_set_vupdate_irq()

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 32 +++
 1 file changed, 4 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 256a23a0ec28..d40185dfd0c0 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2241,34 +2241,6 @@ static int dcn10_register_irq_handlers(struct 
amdgpu_device *adev)
dm_dcn_crtc_high_irq, c_irq_params);
}
 
-   /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
-* the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
-* to trigger at end of each vblank, regardless of state of the lock,
-* matching DCE behaviour.
-*/
-   for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
-i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + 
adev->mode_info.num_crtc - 1;
-i++) {
-   r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, 
>vupdate_irq);
-
-   if (r) {
-   DRM_ERROR("Failed to add vupdate irq id!\n");
-   return r;
-   }
-
-   int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
-   int_params.irq_source =
-   dc_interrupt_to_irq_source(dc, i, 0);
-
-   c_irq_params = >dm.vupdate_params[int_params.irq_source - 
DC_IRQ_SOURCE_VUPDATE1];
-
-   c_irq_params->adev = adev;
-   c_irq_params->irq_src = int_params.irq_source;
-
-   amdgpu_dm_irq_register_interrupt(adev, _params,
-   dm_vupdate_high_irq, c_irq_params);
-   }
-
/* Use GRPH_PFLIP interrupt */
for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + 
adev->mode_info.num_crtc - 1;
@@ -4249,6 +4221,10 @@ static inline int dm_set_vupdate_irq(struct drm_crtc 
*crtc, bool enable)
struct amdgpu_device *adev = crtc->dev->dev_private;
int rc;
 
+   /* Do not set vupdate for DCN hardware */
+   if (adev->family <= AMDGPU_FAMILY_AI)
+   return 0;
+
irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst;
 
rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
-- 
2.23.0

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[PATCH 2/2 v2] drm/amd/display: Disable VUpdate interrupt for DCN hardware

[sunpeng.li]

From: Leo Li 

[Why]

On DCN hardware, the crtc_high_irq handler makes vupdate_high_irq
handler redundant.

All the vupdate handler does is handle vblank events, and update vrr
for DCE hw (excluding VEGA, more on that later). As far as usermode is
concerned. vstartup happens close enough to vupdate on DCN that it can
be considered the "same". Handling vblank and updating vrr at vstartup
effectively replaces vupdate on DCN.

Vega is a bit special. Like DCN, the VRR registers on Vega are
double-buffered, and swapped at vupdate. But Unlike DCN, it lacks a
vstartup interrupt. This means we can't quite remove the vupdate handler
for it, since delayerd user events due to vrr are sent off there.

[How]

Remove registration of VUpdate interrupt handler for DCN. Disable
vupdate interrupt if asic family DCN, enable otherwise.

Signed-off-by: Leo Li 
---

v2: Don't exclude vega when enabling vupdate interrupts

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 34 +++
 1 file changed, 4 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 256a23a0ec28..3664af3b41a1 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2241,34 +2241,6 @@ static int dcn10_register_irq_handlers(struct 
amdgpu_device *adev)
dm_dcn_crtc_high_irq, c_irq_params);
}

-   /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
-* the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
-* to trigger at end of each vblank, regardless of state of the lock,
-* matching DCE behaviour.
-*/
-   for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
-i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + 
adev->mode_info.num_crtc - 1;
-i++) {
-   r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, 
>vupdate_irq);
-
-   if (r) {
-   DRM_ERROR("Failed to add vupdate irq id!\n");
-   return r;
-   }
-
-   int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
-   int_params.irq_source =
-   dc_interrupt_to_irq_source(dc, i, 0);
-
-   c_irq_params = >dm.vupdate_params[int_params.irq_source - 
DC_IRQ_SOURCE_VUPDATE1];
-
-   c_irq_params->adev = adev;
-   c_irq_params->irq_src = int_params.irq_source;
-
-   amdgpu_dm_irq_register_interrupt(adev, _params,
-   dm_vupdate_high_irq, c_irq_params);
-   }
-
/* Use GRPH_PFLIP interrupt */
for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + 
adev->mode_info.num_crtc - 1;
@@ -4266,7 +4238,7 @@ static inline int dm_set_vblank(struct drm_crtc *crtc, 
bool enable)
struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
int rc = 0;

-   if (enable) {
+   if (enable && adev->family <= AMDGPU_FAMILY_AI) {
/* vblank irq on -> Only need vupdate irq in vrr mode */
if (amdgpu_dm_vrr_active(acrtc_state))
rc = dm_set_vupdate_irq(crtc, true);
@@ -6243,6 +6215,7 @@ static void pre_update_freesync_state_on_stream(
 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
struct dm_crtc_state *new_state)
 {
+   struct amdgpu_device *adev = old_state->base.crtc->dev->dev_private;
bool old_vrr_active = amdgpu_dm_vrr_active(old_state);
bool new_vrr_active = amdgpu_dm_vrr_active(new_state);

@@ -6255,7 +6228,8 @@ static void amdgpu_dm_handle_vrr_transition(struct 
dm_crtc_state *old_state,
 * We also need vupdate irq for the actual core vblank handling
 * at end of vblank.
 */
-   dm_set_vupdate_irq(new_state->base.crtc, true);
+   if (adev->family <= AMDGPU_FAMILY_AI)
+   dm_set_vupdate_irq(new_state->base.crtc, true);
drm_crtc_vblank_get(new_state->base.crtc);
DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
 __func__, new_state->base.crtc->base.id);
--
2.23.0

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[PATCH 2/2] drm/amd/display: Disable VUpdate interrupt for DCN hardware

[sunpeng.li]

From: Leo Li 

[Why]

On DCN hardware, the crtc_high_irq handler makes vupdate_high_irq
handler redundant.

All the vupdate handler does is handle vblank events, and update vrr
for DCE hw (excluding VEGA, more on that later). As far as usermode is
concerned. vstartup happens close enough to vupdate on DCN that it can
be considered the "same". Handling vblank and updating vrr at vstartup
effectively replaces vupdate on DCN.

Vega is a bit special. Like DCN, the VRR registers on Vega are
double-buffered, and swapped at vupdate. But Unlike DCN, it lacks a
vstartup interrupt. This means we can't quite remove the vupdate handler
for it, since delayerd user events due to vrr are sent off there.

[How]

Remove registration of VUpdate interrupt handler for DCN. Disable
vupdate interrupt if asic family DCN, enable otherwise.

Signed-off-by: Leo Li 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 34 +++
 1 file changed, 4 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 256a23a0ec28..568df046b2fe 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2241,34 +2241,6 @@ static int dcn10_register_irq_handlers(struct 
amdgpu_device *adev)
dm_dcn_crtc_high_irq, c_irq_params);
}

-   /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
-* the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
-* to trigger at end of each vblank, regardless of state of the lock,
-* matching DCE behaviour.
-*/
-   for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
-i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + 
adev->mode_info.num_crtc - 1;
-i++) {
-   r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, 
>vupdate_irq);
-
-   if (r) {
-   DRM_ERROR("Failed to add vupdate irq id!\n");
-   return r;
-   }
-
-   int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
-   int_params.irq_source =
-   dc_interrupt_to_irq_source(dc, i, 0);
-
-   c_irq_params = >dm.vupdate_params[int_params.irq_source - 
DC_IRQ_SOURCE_VUPDATE1];
-
-   c_irq_params->adev = adev;
-   c_irq_params->irq_src = int_params.irq_source;
-
-   amdgpu_dm_irq_register_interrupt(adev, _params,
-   dm_vupdate_high_irq, c_irq_params);
-   }
-
/* Use GRPH_PFLIP interrupt */
for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + 
adev->mode_info.num_crtc - 1;
@@ -4266,7 +4238,7 @@ static inline int dm_set_vblank(struct drm_crtc *crtc, 
bool enable)
struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
int rc = 0;

-   if (enable) {
+   if (enable && adev->family < AMDGPU_FAMILY_AI) {
/* vblank irq on -> Only need vupdate irq in vrr mode */
if (amdgpu_dm_vrr_active(acrtc_state))
rc = dm_set_vupdate_irq(crtc, true);
@@ -6243,6 +6215,7 @@ static void pre_update_freesync_state_on_stream(
 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
struct dm_crtc_state *new_state)
 {
+   struct amdgpu_device *adev = old_state->base.crtc->dev->dev_private;
bool old_vrr_active = amdgpu_dm_vrr_active(old_state);
bool new_vrr_active = amdgpu_dm_vrr_active(new_state);

@@ -6255,7 +6228,8 @@ static void amdgpu_dm_handle_vrr_transition(struct 
dm_crtc_state *old_state,
 * We also need vupdate irq for the actual core vblank handling
 * at end of vblank.
 */
-   dm_set_vupdate_irq(new_state->base.crtc, true);
+   if (adev->family < AMDGPU_FAMILY_AI)
+   dm_set_vupdate_irq(new_state->base.crtc, true);
drm_crtc_vblank_get(new_state->base.crtc);
DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
 __func__, new_state->base.crtc->base.id);
--
2.23.0

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[PATCH 1/2] drm/amd/display: Send vblank and user events at vsartup for DCN

[sunpeng.li]

From: Leo Li 

[Why]

For DCN hardware, the crtc_high_irq handler is assigned to the vstartup
interrupt. This is different from DCE, which has it assigned to vblank
start.

We'd like to send vblank and user events at vstartup because:

* It happens close enough to vupdate - the point of no return for HW.

* It is programmed as lines relative to vblank end - i.e. it is not in
  the variable portion when VRR is enabled. We should signal user
  events here.

* The pflip interrupt responsible for sending user events today only
  fires if the DCH HUBP component is not clock gated. In situations
  where planes are disabled - but the CRTC is enabled - user events won't
  be sent out, leading to flip done timeouts.

Consequently, this makes vupdate on DCN hardware redundant. It will be
removed in the next change.

[How]

Add a DCN-specific crtc_high_irq handler, and hook it to the VStartup
signal. Inside the DCN handler, we send off user events if the pflip
handler hasn't already done so.

Signed-off-by: Leo Li 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 65 ++-
 1 file changed, 64 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 00017b91c91a..256a23a0ec28 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -485,6 +485,69 @@ static void dm_crtc_high_irq(void *interrupt_params)
}
 }

+
+/**
+ * dm_dcn_crtc_high_irq() - Handles VStartup interrupt for DCN generation ASICs
+ * @interrupt params - interrupt parameters
+ *
+ * Notify DRM's vblank event handler at VSTARTUP
+ *
+ * Unlike DCE hardware, we trigger the handler at VSTARTUP. at which:
+ * * We are close enough to VUPDATE - the point of no return for hw
+ * * We are in the fixed portion of variable front porch when vrr is enabled
+ * * We are before VUPDATE, where double-buffered vrr registers are swapped
+ *
+ * It is therefore the correct place to signal vblank, send user flip events,
+ * and update VRR.
+ */
+static void dm_dcn_crtc_high_irq(void *interrupt_params)
+{
+   struct common_irq_params *irq_params = interrupt_params;
+   struct amdgpu_device *adev = irq_params->adev;
+   struct amdgpu_crtc *acrtc;
+   struct dm_crtc_state *acrtc_state;
+   unsigned long flags;
+
+   acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - 
IRQ_TYPE_VBLANK);
+
+   if (!acrtc)
+   return;
+
+   acrtc_state = to_dm_crtc_state(acrtc->base.state);
+
+   DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id,
+   amdgpu_dm_vrr_active(acrtc_state));
+
+   amdgpu_dm_crtc_handle_crc_irq(>base);
+   drm_crtc_handle_vblank(>base);
+
+   spin_lock_irqsave(>ddev->event_lock, flags);
+
+   if (acrtc_state->vrr_params.supported &&
+   acrtc_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE) {
+   mod_freesync_handle_v_update(
+   adev->dm.freesync_module,
+   acrtc_state->stream,
+   _state->vrr_params);
+
+   dc_stream_adjust_vmin_vmax(
+   adev->dm.dc,
+   acrtc_state->stream,
+   _state->vrr_params.adjust);
+   }
+
+   if (acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED) {
+   if (acrtc->event) {
+   drm_crtc_send_vblank_event(>base, acrtc->event);
+   acrtc->event = NULL;
+   drm_crtc_vblank_put(>base);
+   }
+   acrtc->pflip_status = AMDGPU_FLIP_NONE;
+   }
+
+   spin_unlock_irqrestore(>ddev->event_lock, flags);
+}
+
 static int dm_set_clockgating_state(void *handle,
  enum amd_clockgating_state state)
 {
@@ -2175,7 +2238,7 @@ static int dcn10_register_irq_handlers(struct 
amdgpu_device *adev)
c_irq_params->irq_src = int_params.irq_source;

amdgpu_dm_irq_register_interrupt(adev, _params,
-   dm_crtc_high_irq, c_irq_params);
+   dm_dcn_crtc_high_irq, c_irq_params);
}

/* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
--
2.23.0

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[PATCH v2] drm/amdgpu: Add DC feature mask to disable fractional pwm

[sunpeng.li]

From: Leo Li 

[Why]

Some LED panel drivers might not like fractional PWM. In such cases,
backlight flickering may be observed.

[How]

Add a DC feature mask to disable fractional PWM, and associate it with
the preexisting dc_config flag.

The flag is only plumbed through the dmcu firmware, so plumb it through
the driver path as well.

To disable, add the following to the linux cmdline:
amdgpu.dcfeaturemask=0x4

Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=204957
Signed-off-by: Leo Li 
---

v2: Add bugzilla link

 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +++
 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c  | 4 
 drivers/gpu/drm/amd/include/amd_shared.h  | 1 +
 3 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 1cf4beb76835..73f917d4d1e1 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -728,6 +728,9 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
init_data.flags.multi_mon_pp_mclk_switch = true;
 
+   if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)
+   init_data.flags.disable_fractional_pwm = true;
+
init_data.flags.power_down_display_on_boot = true;
 
 #ifdef CONFIG_DRM_AMD_DC_DCN2_0
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
index d759fdca7fdb..b8a3fc505c9b 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
@@ -404,6 +404,10 @@ static bool dce_abm_init_backlight(struct abm *abm)
/* Enable the backlight output */
REG_UPDATE(BL_PWM_CNTL, BL_PWM_EN, 1);
 
+   /* Disable fractional pwm if configured */
+   REG_UPDATE(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN,
+  abm->ctx->dc->config.disable_fractional_pwm ? 0 : 1);
+
/* Unlock group 2 backlight registers */
REG_UPDATE(BL_PWM_GRP1_REG_LOCK,
BL_PWM_GRP1_REG_LOCK, 0);
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h 
b/drivers/gpu/drm/amd/include/amd_shared.h
index 8889aaceec60..5450ed762b7a 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -143,6 +143,7 @@ enum PP_FEATURE_MASK {
 enum DC_FEATURE_MASK {
DC_FBC_MASK = 0x1,
DC_MULTI_MON_PP_MCLK_SWITCH_MASK = 0x2,
+   DC_DISABLE_FRACTIONAL_PWM_MASK = 0x4,
 };
 
 enum amd_dpm_forced_level;
-- 
2.23.0

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[PATCH] drm/amdgpu: Add DC feature mask to disable fractional pwm

[sunpeng.li]

From: Leo Li 

[Why]

Some LED panel drivers might not like fractional PWM. In such cases,
backlight flickering may be observed.

[How]

Add a DC feature mask to disable fractional PWM, and associate it with
the preexisting dc_config flag.

The flag is only plumbed through the dmcu firmware, so plumb it through
the driver path as well.

To disable, add the following to the linux cmdline:
amdgpu.dcfeaturemask=0x4

Signed-off-by: Leo Li 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +++
 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c  | 4 
 drivers/gpu/drm/amd/include/amd_shared.h  | 1 +
 3 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 1cf4beb76835..73f917d4d1e1 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -728,6 +728,9 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
init_data.flags.multi_mon_pp_mclk_switch = true;
 
+   if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)
+   init_data.flags.disable_fractional_pwm = true;
+
init_data.flags.power_down_display_on_boot = true;
 
 #ifdef CONFIG_DRM_AMD_DC_DCN2_0
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
index d759fdca7fdb..b8a3fc505c9b 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
@@ -404,6 +404,10 @@ static bool dce_abm_init_backlight(struct abm *abm)
/* Enable the backlight output */
REG_UPDATE(BL_PWM_CNTL, BL_PWM_EN, 1);
 
+   /* Disable fractional pwm if configured */
+   REG_UPDATE(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN,
+  abm->ctx->dc->config.disable_fractional_pwm ? 0 : 1);
+
/* Unlock group 2 backlight registers */
REG_UPDATE(BL_PWM_GRP1_REG_LOCK,
BL_PWM_GRP1_REG_LOCK, 0);
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h 
b/drivers/gpu/drm/amd/include/amd_shared.h
index 8889aaceec60..5450ed762b7a 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -143,6 +143,7 @@ enum PP_FEATURE_MASK {
 enum DC_FEATURE_MASK {
DC_FBC_MASK = 0x1,
DC_MULTI_MON_PP_MCLK_SWITCH_MASK = 0x2,
+   DC_DISABLE_FRACTIONAL_PWM_MASK = 0x4,
 };
 
 enum amd_dpm_forced_level;
-- 
2.23.0

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[PATCH 37/37] drm/amd/display: Apply vactive dram clock change workaround to dcn2 DMLv2

[sunpeng.li]

From: Joshua Aberback 

[Why]
This workaround was put in dcn2 DMLv1, and now we need it in DMLv2.

Signed-off-by: Joshua Aberback 
Reviewed-by: Jun Lei 
Acked-by: Leo Li 
---
 .../gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c   | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
index 841ed6c23f93..3c70dd577292 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
@@ -2611,7 +2611,8 @@ static void 
dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP
mode_lib->vba.MinActiveDRAMClockChangeMargin
+ mode_lib->vba.DRAMClockChangeLatency;
 
-   if (mode_lib->vba.MinActiveDRAMClockChangeMargin > 0) {
+   if (mode_lib->vba.MinActiveDRAMClockChangeMargin > 50) {
+   mode_lib->vba.DRAMClockChangeWatermark += 25;
mode_lib->vba.DRAMClockChangeSupport[0][0] = 
dm_dram_clock_change_vactive;
} else {
if (mode_lib->vba.SynchronizedVBlank || 
mode_lib->vba.NumberOfActivePlanes == 1) {
-- 
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[PATCH 29/37] drm/amd/display: Only use EETF when maxCL > max display

[sunpeng.li]

From: Krunoslav Kovac 

[Why]
BT.2390 EETF is used for tone mapping/range reduction.
Say display is 0.1 - 500 nits.
The problematic case is when content is 0-400. We apply EETF because
0<0.1 so we need to reduce the range by 0.1.

In the commit, we ignore the bottom range. Most displays map 0 to min and
then have a ramp to 0.1, so sending 0.1 is actually >0.1.
Furthermode, HW that uses 3D LUT also assumes min=0.

Signed-off-by: Krunoslav Kovac 
Reviewed-by: Aric Cyr 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/modules/color/color_gamma.c | 6 +-
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c 
b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
index 85dad356c9d5..1de4805cb8c7 100644
--- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
@@ -959,11 +959,7 @@ static bool build_freesync_hdr(struct pwl_float_data_ex 
*rgb_regamma,
if (fs_params->max_display < 100) // cap at 100 at the top
max_display = dc_fixpt_from_int(100);
 
-   if (fs_params->min_content < fs_params->min_display)
-   use_eetf = true;
-   else
-   min_content = min_display;
-
+   // only max used, we don't adjust min luminance
if (fs_params->max_content > fs_params->max_display)
use_eetf = true;
else
-- 
2.23.0

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[PATCH 27/37] drm/amd/display: do not synchronize "drr" displays

[sunpeng.li]

From: Jun Lei 

[why]
A display that supports DRR can never really be considered
"synchronized" with any other display because we can dynamically
enable DRR (i.e. without modeset).  this will cause their
relative CRTC positions to drift and lose sync.  this will disrupt
features such as MCLK switching that assume and depend on
their permanent alignment (that can only change with modeset)

[how]
check for ignore_msa in stream when considered synchronizability
this ignore_msa is basically actually implemented as "supports drr"

Signed-off-by: Jun Lei 
Reviewed-by: Yongqiang Sun 
Acked-by: Anthony Koo 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index da9e2e5f5c0d..8fe39fdefc27 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -404,6 +404,9 @@ bool resource_are_streams_timing_synchronizable(
if (stream1->view_format != stream2->view_format)
return false;
 
+   if (stream1->ignore_msa_timing_param || 
stream2->ignore_msa_timing_param)
+   return false;
+
return true;
 }
 static bool is_dp_and_hdmi_sharable(
@@ -1540,6 +1543,9 @@ bool dc_is_stream_unchanged(
if (!are_stream_backends_same(old_stream, stream))
return false;
 
+   if (old_stream->ignore_msa_timing_param != 
stream->ignore_msa_timing_param)
+   return false;
+
return true;
 }
 
-- 
2.23.0

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[PATCH 16/37] drm/amd/display: audio endpoint cannot switch

[sunpeng.li]

From: Paul Hsieh 

[Why]
On some systems, we need to check the dcn version in runtime
system, not in compile time.

[How]
Stub in dcn version parameter to find_first_free_audio

Signed-off-by: Paul Hsieh 
Reviewed-by: Charlene Liu 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 25da0c45d828..da9e2e5f5c0d 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1629,7 +1629,8 @@ static int acquire_first_free_pipe(
 static struct audio *find_first_free_audio(
struct resource_context *res_ctx,
const struct resource_pool *pool,
-   enum engine_id id)
+   enum engine_id id,
+   enum dce_version dc_version)
 {
int i, available_audio_count;
 
@@ -1965,7 +1966,7 @@ enum dc_status resource_map_pool_resources(
dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&
stream->audio_info.mode_count && stream->audio_info.flags.all) {
pipe_ctx->stream_res.audio = find_first_free_audio(
-   >res_ctx, pool, pipe_ctx->stream_res.stream_enc->id);
+   >res_ctx, pool, pipe_ctx->stream_res.stream_enc->id, 
dc_ctx->dce_version);
 
/*
 * Audio assigned in order first come first get.
-- 
2.23.0

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[PATCH 11/37] drm/amd/display: split dcn20 fast validate into more functions

[sunpeng.li]

From: Dmytro Laktyushkin 

Split a large function into smaller, reusable chunks.

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Nevenko Stupar 
Acked-by: Leo Li 
---
 .../drm/amd/display/dc/dcn20/dcn20_resource.c | 182 ++
 .../drm/amd/display/dc/dcn20/dcn20_resource.h |  31 +++
 .../drm/amd/display/dc/dcn21/dcn21_resource.c |   1 +
 3 files changed, 136 insertions(+), 78 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 893e44ca90f8..ab1fc8c5ed10 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -1612,7 +1612,7 @@ static void swizzle_to_dml_params(
}
 }
 
-static bool dcn20_split_stream_for_odm(
+bool dcn20_split_stream_for_odm(
struct resource_context *res_ctx,
const struct resource_pool *pool,
struct pipe_ctx *prev_odm_pipe,
@@ -1690,7 +1690,7 @@ static bool dcn20_split_stream_for_odm(
return true;
 }
 
-static void dcn20_split_stream_for_mpc(
+void dcn20_split_stream_for_mpc(
struct resource_context *res_ctx,
const struct resource_pool *pool,
struct pipe_ctx *primary_pipe,
@@ -2148,7 +2148,7 @@ void dcn20_set_mcif_arb_params(
 }
 
 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
-static bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)
+bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)
 {
int i;
 
@@ -2183,7 +2183,7 @@ static bool dcn20_validate_dsc(struct dc *dc, struct 
dc_state *new_ctx)
 }
 #endif
 
-static struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,
+struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,
struct resource_context *res_ctx,
const struct resource_pool *pool,
const struct pipe_ctx *primary_pipe)
@@ -2260,24 +2260,11 @@ static struct pipe_ctx 
*dcn20_find_secondary_pipe(struct dc *dc,
return secondary_pipe;
 }
 
-bool dcn20_fast_validate_bw(
+void dcn20_merge_pipes_for_validate(
struct dc *dc,
-   struct dc_state *context,
-   display_e2e_pipe_params_st *pipes,
-   int *pipe_cnt_out,
-   int *pipe_split_from,
-   int *vlevel_out)
+   struct dc_state *context)
 {
-   bool out = false;
-
-   int pipe_cnt, i, pipe_idx, vlevel, vlevel_unsplit;
-   bool force_split = false;
-   int split_threshold = dc->res_pool->pipe_count / 2;
-   bool avoid_split = dc->debug.pipe_split_policy != MPC_SPLIT_DYNAMIC;
-
-   ASSERT(pipes);
-   if (!pipes)
-   return false;
+   int i;
 
/* merge previously split odm pipes since mode support needs to make 
the decision */
for (i = 0; i < dc->res_pool->pipe_count; i++) {
@@ -2332,31 +2319,18 @@ bool dcn20_fast_validate_bw(
if (pipe->plane_state)
resource_build_scaling_params(pipe);
}
+}
 
-   if (dc->res_pool->funcs->populate_dml_pipes)
-   pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
-   >res_ctx, pipes);
-   else
-   pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
-   >res_ctx, pipes);
-
-   *pipe_cnt_out = pipe_cnt;
-
-   if (!pipe_cnt) {
-   out = true;
-   goto validate_out;
-   }
-
-   vlevel = dml_get_voltage_level(>bw_ctx.dml, pipes, pipe_cnt);
-
-   if (vlevel > context->bw_ctx.dml.soc.num_states)
-   goto validate_fail;
-
-   /*initialize pipe_just_split_from to invalid idx*/
-   for (i = 0; i < MAX_PIPES; i++)
-   pipe_split_from[i] = -1;
+int dcn20_validate_apply_pipe_split_flags(
+   struct dc *dc,
+   struct dc_state *context,
+   int vlevel,
+   bool *split)
+{
+   int i, pipe_idx, vlevel_unsplit;
+   bool force_split = false;
+   bool avoid_split = dc->debug.pipe_split_policy != MPC_SPLIT_DYNAMIC;
 
-   /* Single display only conditionals get set here */
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe = >res_ctx.pipe_ctx[i];
bool exit_loop = false;
@@ -2383,38 +2357,105 @@ bool dcn20_fast_validate_bw(
if (exit_loop)
break;
}
-
-   if (context->stream_count > split_threshold)
+   /* TODO: fix dc bugs and remove this split threshold thing */
+   if (context->stream_count > dc->res_pool->pipe_count / 2)
avoid_split = true;
 
-   vlevel_unsplit = vlevel;
+   if (avoid_split) {
+   for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
+   if (!context->res_ctx.pipe_ctx[i].stream)
+   continue;
+
+   for 

[PATCH 15/37] drm/amd/display: Fix MPO & pipe split on 3-pipe dcn2x

[sunpeng.li]

From: Michael Strauss 

[WHY]
DML is incorrectly initialized with 4 pipes on 3 pipe configs
RequiredDPPCLK is halved on unsplit pipe due to an incorrectly handled 3 pipe
case, causing underflow with 2 planes & pipe split (MPO, 8K + 2nd display)

[HOW]
Set correct number of DPP/OTGs for dml init to generate correct DPP topology
Double RequiredDPPCLK after clock is halved for pipe split
and find_secondary_pipe fails to fix underflow

Signed-off-by: Michael Strauss 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 5 +++--
 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 8 
 2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 9bc0ffad7093..2596d4ac6263 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -2482,9 +2482,10 @@ bool dcn20_fast_validate_bw(
/* pipe not split previously needs split */
hsplit_pipe = dcn20_find_secondary_pipe(dc, 
>res_ctx, dc->res_pool, pipe);
ASSERT(hsplit_pipe);
-   if (!hsplit_pipe)
+   if (!hsplit_pipe) {
+   
context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx]
 *= 2;
continue;
-
+   }
if 
(context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
if (!dcn20_split_stream_for_odm(
>res_ctx, 
dc->res_pool,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index d2e851e7a97f..5e3b48bb04f1 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -1722,6 +1722,14 @@ static bool construct(
 
pool->base.pp_smu = dcn21_pp_smu_create(ctx);
 
+   uint32_t num_pipes = dcn2_1_ip.max_num_dpp;
+
+   for (i = 0; i < dcn2_1_ip.max_num_dpp; i++)
+   if (pipe_fuses & 1 << i)
+   num_pipes--;
+   dcn2_1_ip.max_num_dpp = num_pipes;
+   dcn2_1_ip.max_num_otg = num_pipes;
+
dml_init_instance(>dml, _1_soc, _1_ip, DML_PROJECT_DCN21);
 
init_data.ctx = dc->ctx;
-- 
2.23.0

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[PATCH 26/37] drm/amd/display: Proper return of result when aux engine acquire fails

[sunpeng.li]

From: Anthony Koo 

[Why]
When aux engine acquire fails, we missed populating the operation_result
that describes the failure reason.

[How]
Set operation_result to new type:
AUX_CHANNEL_OPERATION_FAILED_ENGINE_ACQUIRE
in the case aux engine acquire has failed.

Signed-off-by: Anthony Koo 
Reviewed-by: Aric Cyr 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 1 +
 drivers/gpu/drm/amd/display/dc/dc_ddc_types.h   | 3 ++-
 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c| 5 -
 3 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 3af2b429ff1b..779d0b60cac9 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -113,6 +113,7 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
result = -EIO;
break;
case AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY:
+   case AUX_CHANNEL_OPERATION_FAILED_ENGINE_ACQUIRE:
result = -EBUSY;
break;
case AUX_CHANNEL_OPERATION_FAILED_TIMEOUT:
diff --git a/drivers/gpu/drm/amd/display/dc/dc_ddc_types.h 
b/drivers/gpu/drm/amd/display/dc/dc_ddc_types.h
index 4ef97f65e55d..4f8f576d5fcf 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_ddc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_ddc_types.h
@@ -49,7 +49,8 @@ enum aux_channel_operation_result {
AUX_CHANNEL_OPERATION_FAILED_REASON_UNKNOWN,
AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY,
AUX_CHANNEL_OPERATION_FAILED_TIMEOUT,
-   AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON
+   AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON,
+   AUX_CHANNEL_OPERATION_FAILED_ENGINE_ACQUIRE
 };
 
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
index 976bd4987a28..22abb345ddc1 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
@@ -538,8 +538,10 @@ int dce_aux_transfer_raw(struct ddc_service *ddc,
memset(_rep, 0, sizeof(aux_rep));
 
aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en];
-   if (!acquire(aux_engine, ddc_pin))
+   if (!acquire(aux_engine, ddc_pin)) {
+   *operation_result = AUX_CHANNEL_OPERATION_FAILED_ENGINE_ACQUIRE;
return -1;
+   }
 
if (payload->i2c_over_aux)
aux_req.type = AUX_TRANSACTION_TYPE_I2C;
@@ -663,6 +665,7 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
break;
 
case AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON:
+   case AUX_CHANNEL_OPERATION_FAILED_ENGINE_ACQUIRE:
case AUX_CHANNEL_OPERATION_FAILED_REASON_UNKNOWN:
default:
goto fail;
-- 
2.23.0

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[PATCH 09/37] drm/amd/display: Enable PSR

[sunpeng.li]

From: Roman Li 

[Why]
PSR (Panel Self-Refresh) is a power-saving feature for eDP panels.
The feature has support in DMCU (Display MicroController Unit).
DMCU/driver communication is implemented in DC.
DM can use existing DC PSR interface to use PSR feature.

[How]
- Read psr caps via dpcd
- Send vsc infoframe if panel supports psr
- Disable psr before h/w programming (FULL_UPDATE)
- Enable psr after h/w programming
- Disable psr for fb console

Signed-off-by: Roman Li 
Reviewed-by: Nicholas Kazlauskas 
Acked-by: Leo Li 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 133 +-
 1 file changed, 130 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 10cce584719f..5e3bf4f86e52 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -147,6 +147,12 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
 static void handle_cursor_update(struct drm_plane *plane,
 struct drm_plane_state *old_plane_state);
 
+static void amdgpu_dm_set_psr_caps(struct dc_link *link);
+static bool amdgpu_dm_psr_enable(struct dc_stream_state *stream);
+static bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream);
+static bool amdgpu_dm_psr_disable(struct dc_stream_state *stream);
+
+
 /*
  * dm_vblank_get_counter
  *
@@ -2418,6 +2424,7 @@ static int amdgpu_dm_initialize_drm_device(struct 
amdgpu_device *adev)
} else if (dc_link_detect(link, DETECT_REASON_BOOT)) {
amdgpu_dm_update_connector_after_detect(aconnector);
register_backlight_device(dm, link);
+   amdgpu_dm_set_psr_caps(link);
}
 
 
@@ -3813,7 +3820,16 @@ create_stream_for_sink(struct amdgpu_dm_connector 
*aconnector,
 
if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
mod_build_hf_vsif_infopacket(stream, >vsp_infopacket, 
false, false);
+   if (stream->link->psr_feature_enabled)  {
+   struct dc  *core_dc = stream->link->ctx->dc;
 
+   if (dc_is_dmcu_initialized(core_dc)) {
+   struct dmcu *dmcu = core_dc->res_pool->dmcu;
+
+   stream->psr_version = dmcu->dmcu_version.psr_version;
+   mod_build_vsc_infopacket(stream, 
>vsc_infopacket);
+   }
+   }
 finish:
dc_sink_release(sink);
 
@@ -5908,6 +5924,7 @@ static void amdgpu_dm_commit_planes(struct 
drm_atomic_state *state,
uint32_t target_vblank, last_flip_vblank;
bool vrr_active = amdgpu_dm_vrr_active(acrtc_state);
bool pflip_present = false;
+   bool swizzle = true;
struct {
struct dc_surface_update surface_updates[MAX_SURFACES];
struct dc_plane_info plane_infos[MAX_SURFACES];
@@ -5953,6 +5970,9 @@ static void amdgpu_dm_commit_planes(struct 
drm_atomic_state *state,
 
dc_plane = dm_new_plane_state->dc_state;
 
+   if (dc_plane && !dc_plane->tiling_info.gfx9.swizzle)
+   swizzle = false;
+
bundle->surface_updates[planes_count].surface = dc_plane;
if (new_pcrtc_state->color_mgmt_changed) {
bundle->surface_updates[planes_count].gamma = 
dc_plane->gamma_correction;
@@ -6144,14 +6164,29 @@ static void amdgpu_dm_commit_planes(struct 
drm_atomic_state *state,
_state->vrr_params.adjust);
spin_unlock_irqrestore(>dev->event_lock, flags);
}
-
mutex_lock(>dc_lock);
+   if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
+   acrtc_state->stream->link->psr_allow_active)
+   amdgpu_dm_psr_disable(acrtc_state->stream);
+
dc_commit_updates_for_stream(dm->dc,
 bundle->surface_updates,
 planes_count,
 acrtc_state->stream,
 >stream_update,
 dc_state);
+
+   if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
+   
acrtc_state->stream->psr_version &&
+   
!acrtc_state->stream->link->psr_feature_enabled)
+   amdgpu_dm_link_setup_psr(acrtc_state->stream);
+   else if ((acrtc_state->update_type == UPDATE_TYPE_FAST) &&
+   
acrtc_state->stream->link->psr_feature_enabled &&
+   
!acrtc_state->stream->link->psr_allow_active &&
+   swizzle) {
+ 

[PATCH 06/37] drm/amd/display: remove unused code

[sunpeng.li]

From: Dmytro Laktyushkin 

Commit hints are unnecessary after front end programming redesign.

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Eric Bernstein 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c  | 2 --
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 5 -
 drivers/gpu/drm/amd/display/dc/inc/core_types.h   | 4 
 3 files changed, 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 41b51f43a64b..55b82ca44c3b 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1248,8 +1248,6 @@ static enum dc_status dc_commit_state_no_check(struct dc 
*dc, struct dc_state *c
for (i = 0; i < context->stream_count; i++)
context->streams[i]->mode_changed = false;
 
-   memset(>commit_hints, 0, sizeof(context->commit_hints));
-
dc_release_state(dc->current_state);
 
dc->current_state = context;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index c9792c47978a..893e44ca90f8 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -2275,7 +2275,6 @@ bool dcn20_fast_validate_bw(
int split_threshold = dc->res_pool->pipe_count / 2;
bool avoid_split = dc->debug.pipe_split_policy != MPC_SPLIT_DYNAMIC;
 
-
ASSERT(pipes);
if (!pipes)
return false;
@@ -2353,10 +2352,6 @@ bool dcn20_fast_validate_bw(
if (vlevel > context->bw_ctx.dml.soc.num_states)
goto validate_fail;
 
-   if ((context->stream_count > split_threshold && 
dc->current_state->stream_count <= split_threshold)
-   || (context->stream_count <= split_threshold && 
dc->current_state->stream_count > split_threshold))
-   context->commit_hints.full_update_needed = true;
-
/*initialize pipe_just_split_from to invalid idx*/
for (i = 0; i < MAX_PIPES; i++)
pipe_split_from[i] = -1;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h 
b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index eee78a73d88c..a831079607cd 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -398,10 +398,6 @@ struct dc_state {
 
struct clk_mgr *clk_mgr;
 
-   struct {
-   bool full_update_needed : 1;
-   } commit_hints;
-
struct kref refcount;
 };
 
-- 
2.23.0

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[PATCH 31/37] drm/amd/display: 3.2.56

[sunpeng.li]

From: Aric Cyr 

Signed-off-by: Aric Cyr 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index b578b2148e45..0416a17b0897 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -39,7 +39,7 @@
 #include "inc/hw/dmcu.h"
 #include "dml/display_mode_lib.h"
 
-#define DC_VER "3.2.55"
+#define DC_VER "3.2.56"
 
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
-- 
2.23.0

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[PATCH 12/37] drm/amd/display: correctly initialize dml odm variables

[sunpeng.li]

From: Dmytro Laktyushkin 

One of odm variables was not initialized in dml.

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Chris Park 
Acked-by: Leo Li 
Acked-by: Tony Cheng 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h | 6 --
 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c | 2 ++
 3 files changed, 3 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index ab1fc8c5ed10..4f9c3538fa8c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -2524,7 +2524,7 @@ bool dcn20_fast_validate_bw(
return out;
 }
 
-void dcn20_calculate_wm(
+static void dcn20_calculate_wm(
struct dc *dc, struct dc_state *context,
display_e2e_pipe_params_st *pipes,
int *out_pipe_cnt,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
index fe68669a1f0c..dccfe07832e3 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
@@ -150,12 +150,6 @@ void dcn20_calculate_dlg_params(
display_e2e_pipe_params_st *pipes,
int pipe_cnt,
int vlevel);
-void dcn20_calculate_wm(
-   struct dc *dc, struct dc_state *context,
-   display_e2e_pipe_params_st *pipes,
-   int *out_pipe_cnt,
-   int *pipe_split_from,
-   int vlevel);
 
 enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct 
dc_state *context, struct dc_stream_state *stream);
 enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state 
*new_ctx, struct dc_stream_state *dc_stream);
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c 
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
index 362dc6ea98ae..038701d7383d 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
@@ -432,6 +432,8 @@ static void fetch_pipe_params(struct display_mode_lib 
*mode_lib)
dst->recout_width; // TODO: or should this be 
full_recout_width???...maybe only when in hsplit mode?

mode_lib->vba.ODMCombineEnabled[mode_lib->vba.NumberOfActivePlanes] =
dst->odm_combine;
+   
mode_lib->vba.ODMCombineTypeEnabled[mode_lib->vba.NumberOfActivePlanes] =
+   dst->odm_combine;
mode_lib->vba.OutputFormat[mode_lib->vba.NumberOfActivePlanes] =
(enum output_format_class) 
(dout->output_format);
mode_lib->vba.OutputBpp[mode_lib->vba.NumberOfActivePlanes] =
-- 
2.23.0

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[PATCH 34/37] drm/amd/display: Do not call update bounding box on dc create

[sunpeng.li]

From: Sung Lee 

[Why]
In Hybrid Graphics, dcn2_1_soc struct stays alive through PnP.
This causes an issue on dc init where dcn2_1_soc which has been
updated by update_bw_bounding_box gets put into dml->soc.
As update_bw_bounding_box is currently incorrect for dcn2.1,
this makes dml calculations fail due to incorrect parameters,
leading to a crash on PnP.

[How]
Comment out update_bw_bounding_box call for now.

Signed-off-by: Sung Lee 
Reviewed-by: Eric Yang 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index f165f7e58da9..88f89d073061 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -1336,6 +1336,12 @@ struct display_stream_compressor *dcn21_dsc_create(
 
 static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params 
*bw_params)
 {
+   /*
+   TODO: Fix this function to calcualte correct values.
+   There are known issues with this function currently
+   that will need to be investigated. Use hardcoded known good values for 
now.
+
+
struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool);
struct clk_limit_table *clk_table = _params->clk_table;
int i;
@@ -1350,11 +1356,11 @@ static void update_bw_bounding_box(struct dc *dc, 
struct clk_bw_params *bw_param
dcn2_1_soc.clock_limits[i].dcfclk_mhz = 
clk_table->entries[i].dcfclk_mhz;
dcn2_1_soc.clock_limits[i].fabricclk_mhz = 
clk_table->entries[i].fclk_mhz;
dcn2_1_soc.clock_limits[i].socclk_mhz = 
clk_table->entries[i].socclk_mhz;
-   /* This is probably wrong, TODO: find correct calculation */
dcn2_1_soc.clock_limits[i].dram_speed_mts = 
clk_table->entries[i].memclk_mhz * 16 / 1000;
}
dcn2_1_soc.clock_limits[i] = dcn2_1_soc.clock_limits[i - i];
dcn2_1_soc.num_states = i;
+   */
 }
 
 /* Temporary Place holder until we can get them from fuse */
-- 
2.23.0

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[PATCH 36/37] drm/amd/display: fix hubbub deadline programing

[sunpeng.li]

From: Eric Yang 

[Why]
Fix the programming of DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A.
Was not filled in.

Signed-off-by: Eric Yang 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 1 +
 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 3cdb61750570..5e3738e96fdc 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -2634,6 +2634,7 @@ static void dcn20_calculate_wm(
 #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = 
get_fraction_of_urgent_bandwidth(>bw_ctx.dml, pipes, pipe_cnt) * 1000;
context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = 
get_fraction_of_urgent_bandwidth_imm_flip(>bw_ctx.dml, pipes, 
pipe_cnt) * 1000;
+   context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = 
get_urgent_latency(>bw_ctx.dml, pipes, pipe_cnt) * 1000;
 #endif
 
if (vlevel < 2) {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index 88f89d073061..12a657692d6d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -1009,6 +1009,7 @@ static void calculate_wm_set_for_vlevel(
 #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, 
pipe_cnt) * 1000;
wm_set->frac_urg_bw_flip = 
get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000;
+   wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 
1000;
 #endif
dml->soc.dram_clock_change_latency_us = 
dram_clock_change_latency_cached;
 
-- 
2.23.0

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[PATCH 35/37] drm/amd/display: fix avoid_split for dcn2+ validation

[sunpeng.li]

From: Dmytro Laktyushkin 

We are currently incorrectly processing avoid split at highest
voltage level.

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Eric Bernstein 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 11 +++
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index a1b2db8f687a..3cdb61750570 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -2357,10 +2357,11 @@ int dcn20_validate_apply_pipe_split_flags(
int vlevel,
bool *split)
 {
-   int i, pipe_idx, vlevel_unsplit;
+   int i, pipe_idx, vlevel_split;
bool force_split = false;
bool avoid_split = dc->debug.pipe_split_policy != MPC_SPLIT_DYNAMIC;
 
+   /* Single display loop, exits if there is more than one display */
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe = >res_ctx.pipe_ctx[i];
bool exit_loop = false;
@@ -2391,22 +2392,24 @@ int dcn20_validate_apply_pipe_split_flags(
if (context->stream_count > dc->res_pool->pipe_count / 2)
avoid_split = true;
 
+   /* Avoid split loop looks for lowest voltage level that allows most 
unsplit pipes possible */
if (avoid_split) {
for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
if (!context->res_ctx.pipe_ctx[i].stream)
continue;
 
-   for (vlevel_unsplit = vlevel; vlevel <= 
context->bw_ctx.dml.soc.num_states; vlevel++)
+   for (vlevel_split = vlevel; vlevel <= 
context->bw_ctx.dml.soc.num_states; vlevel++)
if 
(context->bw_ctx.dml.vba.NoOfDPP[vlevel][0][pipe_idx] == 1)
break;
/* Impossible to not split this pipe */
-   if (vlevel == context->bw_ctx.dml.soc.num_states)
-   vlevel = vlevel_unsplit;
+   if (vlevel > context->bw_ctx.dml.soc.num_states)
+   vlevel = vlevel_split;
pipe_idx++;
}
context->bw_ctx.dml.vba.maxMpcComb = 0;
}
 
+   /* Split loop sets which pipe should be split based on dml outputs and 
dc flags */
for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe = >res_ctx.pipe_ctx[i];
 
-- 
2.23.0

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[PATCH 07/37] drm/amd/display: 3.2.55

[sunpeng.li]

From: Aric Cyr 

Signed-off-by: Aric Cyr 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 2e1d34882684..a86dad3808b6 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -39,7 +39,7 @@
 #include "inc/hw/dmcu.h"
 #include "dml/display_mode_lib.h"
 
-#define DC_VER "3.2.54"
+#define DC_VER "3.2.55"
 
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
-- 
2.23.0

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[PATCH 21/37] drm/amd/display: add embedded flag to dml

[sunpeng.li]

From: Dmytro Laktyushkin 

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Eric Bernstein 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h | 1 +
 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c | 1 +
 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h | 1 +
 3 files changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h 
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
index 83f84cdd4055..cfacd6027467 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
@@ -318,6 +318,7 @@ struct _vcs_dpi_display_pipe_dest_params_st {
unsigned int vupdate_width;
unsigned int vready_offset;
unsigned char interlaced;
+   unsigned char embedded;
double pixel_rate_mhz;
unsigned char synchronized_vblank_all_planes;
unsigned char otg_inst;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c 
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
index 038701d7383d..7f9a5621922f 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
@@ -375,6 +375,7 @@ static void fetch_pipe_params(struct display_mode_lib 
*mode_lib)
 
mode_lib->vba.pipe_plane[j] = 
mode_lib->vba.NumberOfActivePlanes;
 
+   mode_lib->vba.EmbeddedPanel[mode_lib->vba.NumberOfActivePlanes] 
= dst->embedded;
mode_lib->vba.DPPPerPlane[mode_lib->vba.NumberOfActivePlanes] = 
1;
mode_lib->vba.SourceScan[mode_lib->vba.NumberOfActivePlanes] =
(enum scan_direction_class) (src->source_scan);
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h 
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index 91decac50557..1540ffbe3979 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -387,6 +387,7 @@ struct vba_vars_st {
 
/* vba mode support */
/*inputs*/
+   bool EmbeddedPanel[DC__NUM_DPP__MAX];
bool SupportGFX7CompatibleTilingIn32bppAnd64bpp;
double MaxHSCLRatio;
double MaxVSCLRatio;
-- 
2.23.0

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[PATCH 32/37] drm/amd/display: take signal type from link

[sunpeng.li]

From: Lewis Huang 

[Why]
Signal is update to EDP when driver disable first encoder. The
following encoder using SIGNAL_TYPE_EDP to handle other
device. When encoder signal is HDMI, driver will detect it is dp
and release phy. It cause hw hang.

[How]
Take signal type from link->connector_signal.

Signed-off-by: Lewis Huang 
Reviewed-by: Eric Yang 
Acked-by: Leo Li 
---
 .../drm/amd/display/dc/dce110/dce110_hw_sequencer.c   | 11 +++
 1 file changed, 3 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 9150e546dcf2..f0e837d14000 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1421,8 +1421,6 @@ static enum dc_status apply_single_controller_ctx_to_hw(
 static void power_down_encoders(struct dc *dc)
 {
int i;
-   enum connector_id connector_id;
-   enum signal_type signal = SIGNAL_TYPE_NONE;
 
/* do not know BIOS back-front mapping, simply blank all. It will not
 * hurt for non-DP
@@ -1433,15 +1431,12 @@ static void power_down_encoders(struct dc *dc)
}
 
for (i = 0; i < dc->link_count; i++) {
-   connector_id = 
dal_graphics_object_id_get_connector_id(dc->links[i]->link_id);
-   if ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
-   (connector_id == CONNECTOR_ID_EDP)) {
+   enum signal_type signal = dc->links[i]->connector_signal;
 
+   if ((signal == SIGNAL_TYPE_EDP) ||
+   (signal == SIGNAL_TYPE_DISPLAY_PORT))
if (!dc->links[i]->wa_flags.dp_keep_receiver_powered)
dp_receiver_power_ctrl(dc->links[i], false);
-   if (connector_id == CONNECTOR_ID_EDP)
-   signal = SIGNAL_TYPE_EDP;
-   }
 
dc->links[i]->link_enc->funcs->disable_output(
dc->links[i]->link_enc, signal);
-- 
2.23.0

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[PATCH 33/37] drm/amd/display: Add center mode for integer scaling in DC

[sunpeng.li]

From: Reza Amini 

[why]
We want to use maximum space on display to show source

[how]
For Centered Mode: Replicate source as many times as possible to use
maximum of display active space add borders.

Signed-off-by: Reza Amini 
Reviewed-by: Anthony Koo 
Acked-by: Leo Li 
---
 .../gpu/drm/amd/display/dc/core/dc_resource.c | 43 +++
 1 file changed, 35 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 8fe39fdefc27..70e601a975df 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -951,7 +951,7 @@ static void calculate_inits_and_adj_vp(struct pipe_ctx 
*pipe_ctx)
data->inits.v_c_bot = dc_fixpt_add(data->inits.v_c, 
data->ratios.vert_c);
 
 }
-static bool are_rect_integer_multiples(struct rect src, struct rect dest)
+static bool are_rects_integer_multiples(struct rect src, struct rect dest)
 {
if (dest.width  >= src.width  && dest.width  % src.width  == 0 &&
dest.height >= src.height && dest.height % src.height == 0)
@@ -959,6 +959,38 @@ static bool are_rect_integer_multiples(struct rect src, 
struct rect dest)
 
return false;
 }
+
+void calculate_integer_scaling(struct pipe_ctx *pipe_ctx)
+{
+   if (!pipe_ctx->plane_state->scaling_quality.integer_scaling)
+   return;
+
+   //for Centered Mode
+   if (pipe_ctx->stream->dst.width  == pipe_ctx->stream->src.width &&
+   pipe_ctx->stream->dst.height == pipe_ctx->stream->src.height) {
+   // calculate maximum # of replication of src onto addressable
+   unsigned int integer_multiple = min(
+   pipe_ctx->stream->timing.h_addressable / 
pipe_ctx->stream->src.width,
+   pipe_ctx->stream->timing.v_addressable  / 
pipe_ctx->stream->src.height);
+
+   //scale dst
+   pipe_ctx->stream->dst.width  = integer_multiple * 
pipe_ctx->stream->src.width;
+   pipe_ctx->stream->dst.height = integer_multiple * 
pipe_ctx->stream->src.height;
+
+   //center dst onto addressable
+   pipe_ctx->stream->dst.x = 
(pipe_ctx->stream->timing.h_addressable - pipe_ctx->stream->dst.width)/2;
+   pipe_ctx->stream->dst.y = 
(pipe_ctx->stream->timing.v_addressable - pipe_ctx->stream->dst.height)/2;
+   }
+
+   //disable taps if src & dst are integer ratio
+   if (are_rects_integer_multiples(pipe_ctx->stream->src, 
pipe_ctx->stream->dst)) {
+   pipe_ctx->plane_state->scaling_quality.v_taps = 1;
+   pipe_ctx->plane_state->scaling_quality.h_taps = 1;
+   pipe_ctx->plane_state->scaling_quality.v_taps_c = 1;
+   pipe_ctx->plane_state->scaling_quality.h_taps_c = 1;
+   }
+}
+
 bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
 {
const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
@@ -972,6 +1004,8 @@ bool resource_build_scaling_params(struct pipe_ctx 
*pipe_ctx)
pipe_ctx->plane_res.scl_data.format = 
convert_pixel_format_to_dalsurface(
pipe_ctx->plane_state->format);
 
+   calculate_integer_scaling(pipe_ctx);
+
calculate_scaling_ratios(pipe_ctx);
 
calculate_viewport(pipe_ctx);
@@ -1002,13 +1036,6 @@ bool resource_build_scaling_params(struct pipe_ctx 
*pipe_ctx)
res = 
pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
pipe_ctx->plane_res.dpp, 
_ctx->plane_res.scl_data, _state->scaling_quality);
 
-   if (res &&
-   plane_state->scaling_quality.integer_scaling &&
-   are_rect_integer_multiples(pipe_ctx->plane_res.scl_data.viewport,
-  pipe_ctx->plane_res.scl_data.recout)) {
-   pipe_ctx->plane_res.scl_data.taps.v_taps = 1;
-   pipe_ctx->plane_res.scl_data.taps.h_taps = 1;
-   }
 
if (!res) {
/* Try 24 bpp linebuffer */
-- 
2.23.0

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[PATCH 30/37] drm/amd/display: Make clk mgr the only dto update point

[sunpeng.li]

From: Noah Abradjian 

[Why]

* Clk Mgr DTO update point did not cover all needed updates, as it included a
  check for plane_state which does not exist yet when the updater is called on
  driver startup
* This resulted in another update path in the pipe programming sequence, based
  on a dppclk update flag
* However, this alternate path allowed for stray DTO updates, some of which 
would
  occur in the wrong order during dppclk lowering and cause underflow

[How]

* Remove plane_state check and use of plane_res.dpp->inst, getting rid
  of sequence dependencies (this results in extra dto programming for unused
  pipes but that doesn't cause issues and is a small cost)
* Allow DTOs to be updated even if global clock is equal, to account for
  edge case exposed by diags tests
* Remove update_dpp_dto call in pipe programming sequence (leave update to
  dppclk_control there, as that update is necessary and shouldn't occur in clk
  mgr)
* Remove call to optimize_bandwidth when committing state, as it is not needed
  and resulted in sporadic underflows even with other fixes in place

Signed-off-by: Noah Abradjian 
Reviewed-by: Jun Lei 
Acked-by: Leo Li 
---
 .../amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c   | 14 +-
 .../drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c  |  3 ++-
 drivers/gpu/drm/amd/display/dc/core/dc.c   |  4 
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c |  8 +---
 4 files changed, 12 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
index 607d8afc56ec..25d7b7c6681c 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
@@ -108,11 +108,12 @@ void dcn20_update_clocks_update_dpp_dto(struct 
clk_mgr_internal *clk_mgr,
for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
int dpp_inst, dppclk_khz;
 
-   if (!context->res_ctx.pipe_ctx[i].plane_state)
-   continue;
-
-   dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
+   /* Loop index will match dpp->inst if resource exists,
+* and we want to avoid dependency on dpp object
+*/
+   dpp_inst = i;
dppclk_khz = 
context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
+
clk_mgr->dccg->funcs->update_dpp_dto(
clk_mgr->dccg, dpp_inst, dppclk_khz);
}
@@ -235,6 +236,7 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,
 
update_dispclk = true;
}
+
if (dc->config.forced_clocks == false || (force_reset && 
safe_to_lower)) {
if (dpp_clock_lowered) {
// if clock is being lowered, increase DTO before 
lowering refclk
@@ -244,10 +246,12 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,
// if clock is being raised, increase refclk before 
lowering DTO
if (update_dppclk || update_dispclk)
dcn20_update_clocks_update_dentist(clk_mgr);
-   if (update_dppclk)
+   // always update dtos unless clock is lowered and not 
safe to lower
+   if (new_clocks->dppclk_khz >= 
dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
dcn20_update_clocks_update_dpp_dto(clk_mgr, 
context);
}
}
+
if (update_dispclk &&
dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
/*update dmcu for wait_loop count*/
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
index f64d221ad6f1..790a2d211bd6 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
@@ -171,7 +171,8 @@ void rn_update_clocks(struct clk_mgr *clk_mgr_base,
// if clock is being raised, increase refclk before lowering DTO
if (update_dppclk || update_dispclk)
rn_vbios_smu_set_dppclk(clk_mgr, 
clk_mgr_base->clks.dppclk_khz);
-   if (update_dppclk)
+   // always update dtos unless clock is lowered and not safe to 
lower
+   if (new_clocks->dppclk_khz >= 
dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
dcn20_update_clocks_update_dpp_dto(clk_mgr, context);
}
 
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 5e487bb82861..0a443348df10 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1241,10 +1241,6 @@ static enum dc_status dc_commit_state_no_check(struct dc 
*dc, struct dc_state *c
 
   

[PATCH 28/37] drm/amd/display: move wm ranges reporting to end of init hw

[sunpeng.li]

From: Eric Yang 

[Why]
SMU does not keep the wm table across S3, S4, need to re-send
the table. Also defer sending the cable to after DCN bave initialized

[How]
Send table at end of init hw

Signed-off-by: Eric Yang 
Reviewed-by: Yongqiang Sun 
Acked-by: Leo Li 
---
 .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 149 +-
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c |   4 +
 .../gpu/drm/amd/display/dc/inc/hw/clk_mgr.h   |   1 +
 3 files changed, 81 insertions(+), 73 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
index e8b8ee4f1b1e..f64d221ad6f1 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
@@ -396,12 +396,87 @@ void rn_init_clocks(struct clk_mgr *clk_mgr)
clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;
 }
 
+void build_watermark_ranges(struct clk_bw_params *bw_params, struct 
pp_smu_wm_range_sets *ranges)
+{
+   int i, num_valid_sets;
+
+   num_valid_sets = 0;
+
+   for (i = 0; i < WM_SET_COUNT; i++) {
+   /* skip empty entries, the smu array has no holes*/
+   if (!bw_params->wm_table.entries[i].valid)
+   continue;
+
+   ranges->reader_wm_sets[num_valid_sets].wm_inst = 
bw_params->wm_table.entries[i].wm_inst;
+   ranges->reader_wm_sets[num_valid_sets].wm_type = 
bw_params->wm_table.entries[i].wm_type;;
+   /* We will not select WM based on dcfclk, so leave it as 
unconstrained */
+   ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = 
PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
+   ranges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = 
PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
+   /* fclk wil be used to select WM*/
+
+   if (ranges->reader_wm_sets[num_valid_sets].wm_type == 
WM_TYPE_PSTATE_CHG) {
+   if (i == 0)
+   
ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = 0;
+   else {
+   /* add 1 to make it non-overlapping with next 
lvl */
+   
ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = 
bw_params->clk_table.entries[i - 1].fclk_mhz + 1;
+   }
+   ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz 
= bw_params->clk_table.entries[i].fclk_mhz;
+
+   } else {
+   /* unconstrained for memory retraining */
+   ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz 
= PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
+   ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz 
= PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
+
+   /* Modify previous watermark range to cover up to max */
+   ranges->reader_wm_sets[num_valid_sets - 
1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
+   }
+   num_valid_sets++;
+   }
+
+   ASSERT(num_valid_sets != 0); /* Must have at least one set of valid 
watermarks */
+   ranges->num_reader_wm_sets = num_valid_sets;
+
+   /* modify the min and max to make sure we cover the whole range*/
+   ranges->reader_wm_sets[0].min_drain_clk_mhz = 
PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
+   ranges->reader_wm_sets[0].min_fill_clk_mhz = 
PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
+   ranges->reader_wm_sets[ranges->num_reader_wm_sets - 
1].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
+   ranges->reader_wm_sets[ranges->num_reader_wm_sets - 1].max_fill_clk_mhz 
= PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
+
+   /* This is for writeback only, does not matter currently as no 
writeback support*/
+   ranges->num_writer_wm_sets = 1;
+   ranges->writer_wm_sets[0].wm_inst = WM_A;
+   ranges->writer_wm_sets[0].min_fill_clk_mhz = 
PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
+   ranges->writer_wm_sets[0].max_fill_clk_mhz = 
PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
+   ranges->writer_wm_sets[0].min_drain_clk_mhz = 
PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
+   ranges->writer_wm_sets[0].max_drain_clk_mhz = 
PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
+
+}
+
+static void rn_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
+{
+   struct dc_debug_options *debug = _mgr_base->ctx->dc->debug;
+   struct pp_smu_wm_range_sets ranges = {0};
+   struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+   struct pp_smu_funcs *pp_smu = clk_mgr->pp_smu;
+
+   if (!debug->disable_pplib_wm_range) {
+   build_watermark_ranges(clk_mgr_base->bw_params, );
+
+   /* Notify PP Lib/SMU which Watermarks to use for which clock 
ranges */
+   if (pp_smu && pp_smu->rn_funcs.set_wm_ranges)
+

[PATCH 25/37] drm/amd/display: Disable force_single_disp_pipe_split on DCN2+

[sunpeng.li]

From: Michael Strauss 

[WHY]
force_single_disp_pipe_split is a debug flag for use on DCN1
but isn't necessary otherwise as DCN2+ splits by default

Signed-off-by: Michael Strauss 
Reviewed-by: Tony Cheng 
Acked-by: Charlene Liu 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-
 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 88a938633d11..a1b2db8f687a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -863,7 +863,7 @@ static const struct dc_debug_options debug_defaults_drv = {
.clock_trace = true,
.disable_pplib_clock_request = true,
.pipe_split_policy = MPC_SPLIT_DYNAMIC,
-   .force_single_disp_pipe_split = true,
+   .force_single_disp_pipe_split = false,
.disable_dcc = DCC_ENABLE,
.vsr_support = true,
.performance_trace = false,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index e07f03368c97..f165f7e58da9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -836,7 +836,7 @@ static const struct dc_debug_options debug_defaults_drv = {
.clock_trace = true,
.disable_pplib_clock_request = true,
.pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
-   .force_single_disp_pipe_split = true,
+   .force_single_disp_pipe_split = false,
.disable_dcc = DCC_ENABLE,
.vsr_support = true,
.performance_trace = false,
-- 
2.23.0

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[PATCH 24/37] drm/amd/display: Passive DP->HDMI dongle detection fix

[sunpeng.li]

From: Michael Strauss 

[WHY]
i2c_read is called to differentiate passive DP->HDMI and DP->DVI-D dongles
The call is expected to fail in DVI-D case but pass in HDMI case
Some HDMI dongles have a chance to fail as well, causing misdetection as DVI-D

[HOW]
Retry i2c_read to ensure failed result is valid

Signed-off-by: Michael Strauss 
Reviewed-by: Tony Cheng 
Acked-by: Leo Li 
---
 .../gpu/drm/amd/display/dc/core/dc_link_ddc.c | 24 ++-
 1 file changed, 18 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
index 9a56f110bbd1..7f904d55c1bc 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
@@ -374,6 +374,7 @@ void dal_ddc_service_i2c_query_dp_dual_mode_adaptor(
enum display_dongle_type *dongle = _cap->dongle_type;
uint8_t type2_dongle_buf[DP_ADAPTOR_TYPE2_SIZE];
bool is_type2_dongle = false;
+   int retry_count = 2;
struct dp_hdmi_dongle_signature_data *dongle_signature;
 
/* Assume we have no valid DP passive dongle connected */
@@ -386,13 +387,24 @@ void dal_ddc_service_i2c_query_dp_dual_mode_adaptor(
DP_HDMI_DONGLE_ADDRESS,
type2_dongle_buf,
sizeof(type2_dongle_buf))) {
-   *dongle = DISPLAY_DONGLE_DP_DVI_DONGLE;
-   sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_DVI_MAX_TMDS_CLK;
+   /* Passive HDMI dongles can sometimes fail here without 
retrying*/
+   while (retry_count > 0) {
+   if (i2c_read(ddc,
+   DP_HDMI_DONGLE_ADDRESS,
+   type2_dongle_buf,
+   sizeof(type2_dongle_buf)))
+   break;
+   retry_count--;
+   }
+   if (retry_count == 0) {
+   *dongle = DISPLAY_DONGLE_DP_DVI_DONGLE;
+   sink_cap->max_hdmi_pixel_clock = 
DP_ADAPTOR_DVI_MAX_TMDS_CLK;
 
-   CONN_DATA_DETECT(ddc->link, type2_dongle_buf, 
sizeof(type2_dongle_buf),
-   "DP-DVI passive dongle %dMhz: ",
-   DP_ADAPTOR_DVI_MAX_TMDS_CLK / 1000);
-   return;
+   CONN_DATA_DETECT(ddc->link, type2_dongle_buf, 
sizeof(type2_dongle_buf),
+   "DP-DVI passive dongle %dMhz: ",
+   DP_ADAPTOR_DVI_MAX_TMDS_CLK / 1000);
+   return;
+   }
}
 
/* Check if Type 2 dongle.*/
-- 
2.23.0

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[PATCH 22/37] drm/amd/display: add flag to allow diag to force enumerate edp

[sunpeng.li]

From: Jun Lei 

[why]
SLT tests require that diag can drive eDP even if nothing is connected, this is 
not
typical production use case, so we need to add flag

[how]
add flag, and this flag supercedes "should destroy" logic

Signed-off-by: Jun Lei 
Reviewed-by: Aric Cyr 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +-
 drivers/gpu/drm/amd/display/dc/dc.h  | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 55b82ca44c3b..5e487bb82861 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -194,7 +194,7 @@ static bool create_links(
}
}
 
-   if (!should_destory_link) {
+   if (dc->config.force_enum_edp || !should_destory_link) {
dc->links[dc->link_count] = link;
link->dc = dc;
++dc->link_count;
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index a86dad3808b6..b578b2148e45 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -220,6 +220,7 @@ struct dc_config {
bool allow_seamless_boot_optimization;
bool power_down_display_on_boot;
bool edp_not_connected;
+   bool force_enum_edp;
bool forced_clocks;
bool disable_extended_timeout_support; // Used to disable extended 
timeout and lttpr feature as well
bool multi_mon_pp_mclk_switch;
-- 
2.23.0

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[PATCH 20/37] drm/amd/display: fix number of dcn21 dpm clock levels

[sunpeng.li]

From: Dmytro Laktyushkin 

These are specific to dcn21 and should not be increased for
reuse on other asics.

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Chris Park 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h 
b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
index b01db61b6181..ef7df9ef6d7e 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
@@ -251,8 +251,8 @@ struct pp_smu_funcs_nv {
 
 #define PP_SMU_NUM_SOCCLK_DPM_LEVELS  8
 #define PP_SMU_NUM_DCFCLK_DPM_LEVELS  8
-#define PP_SMU_NUM_FCLK_DPM_LEVELS8
-#define PP_SMU_NUM_MEMCLK_DPM_LEVELS  8
+#define PP_SMU_NUM_FCLK_DPM_LEVELS4
+#define PP_SMU_NUM_MEMCLK_DPM_LEVELS  4
 
 struct dpm_clock {
   uint32_t  Freq;// In MHz
-- 
2.23.0

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[PATCH 17/37] drm/amd/display: Update min dcfclk

[sunpeng.li]

From: Alvin Lee 

[Why]
NV12 has lower min dcfclk

[How]
Add update in update_bounding_box

Signed-off-by: Alvin Lee 
Reviewed-by: Jun Lei 
Acked-by: Leo Li 
---
 .../gpu/drm/amd/display/dc/dcn20/dcn20_resource.c| 12 
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 2596d4ac6263..25515c255a3d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -3084,10 +3084,14 @@ void dcn20_update_bounding_box(struct dc *dc, struct 
_vcs_dpi_soc_bounding_box_s
 
if (dc->bb_overrides.min_dcfclk_mhz > 0)
min_dcfclk = dc->bb_overrides.min_dcfclk_mhz;
-   else
-   // Accounting for SOC/DCF relationship, we can go as high as
-   // 506Mhz in Vmin.  We need to code 507 since SMU will round 
down to 506.
-   min_dcfclk = 507;
+   else {
+   if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev))
+   min_dcfclk = 310;
+   else
+   // Accounting for SOC/DCF relationship, we can go as 
high as
+   // 506Mhz in Vmin.
+   min_dcfclk = 506;
+   }
 
for (i = 0; i < num_states; i++) {
int min_fclk_required_by_uclk;
-- 
2.23.0

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[PATCH 23/37] drm/amd/display: map TRANSMITTER_UNIPHY_x to LINK_REGS_x

[sunpeng.li]

From: Yogesh Mohan Marimuthu 

[Why]
The enum value for TRANSMITTER_UNIPHY_G is 9. In resource dc_xx_resource
file structure link_enc_regs[], the TRANSMITTER_UNIPHY_G registers are
initialized at index 6. Due to this mismatch, if monitor is attached to
port using TRANSMITTER_UNIPHY_G then the monitor blanks out.

[How]
add function map_transmitter_id_to_phy_instance() and use the function
to map enum transmitter to link regs.

Signed-off-by: Yogesh Mohan Marimuthu 
Reviewed-by: Eric Yang 
Acked-by: Leo Li 
---
 .../amd/display/dc/dce100/dce100_resource.c   | 37 ++-
 .../amd/display/dc/dce110/dce110_resource.c   | 37 ++-
 .../amd/display/dc/dce112/dce112_resource.c   | 37 ++-
 .../amd/display/dc/dce120/dce120_resource.c   | 37 ++-
 .../drm/amd/display/dc/dce80/dce80_resource.c | 37 ++-
 .../drm/amd/display/dc/dcn10/dcn10_resource.c | 28 +-
 .../drm/amd/display/dc/dcn20/dcn20_resource.c | 33 -
 .../drm/amd/display/dc/dcn21/dcn21_resource.c | 31 +++-
 8 files changed, 269 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 
b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
index b5d6dff29c45..a5e122c721ec 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
@@ -399,6 +399,37 @@ static const struct dc_plane_cap plane_cap = {
 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
 #endif
 
+static int map_transmitter_id_to_phy_instance(
+   enum transmitter transmitter)
+{
+   switch (transmitter) {
+   case TRANSMITTER_UNIPHY_A:
+   return 0;
+   break;
+   case TRANSMITTER_UNIPHY_B:
+   return 1;
+   break;
+   case TRANSMITTER_UNIPHY_C:
+   return 2;
+   break;
+   case TRANSMITTER_UNIPHY_D:
+   return 3;
+   break;
+   case TRANSMITTER_UNIPHY_E:
+   return 4;
+   break;
+   case TRANSMITTER_UNIPHY_F:
+   return 5;
+   break;
+   case TRANSMITTER_UNIPHY_G:
+   return 6;
+   break;
+   default:
+   ASSERT(0);
+   return 0;
+   }
+}
+
 static void read_dce_straps(
struct dc_context *ctx,
struct resource_straps *straps)
@@ -579,14 +610,18 @@ struct link_encoder *dce100_link_encoder_create(
 {
struct dce110_link_encoder *enc110 =
kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
+   int link_regs_id;
 
if (!enc110)
return NULL;
 
+   link_regs_id =
+   map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
+
dce110_link_encoder_construct(enc110,
  enc_init_data,
  _enc_feature,
- 
_enc_regs[enc_init_data->transmitter],
+ _enc_regs[link_regs_id],
  _enc_aux_regs[enc_init_data->channel 
- 1],
  
_enc_hpd_regs[enc_init_data->hpd_source]);
return >base;
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
index c651a38e34a0..83a4dbf6d76e 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
@@ -448,6 +448,37 @@ static const struct dc_plane_cap underlay_plane_cap = {
 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
 #endif
 
+static int map_transmitter_id_to_phy_instance(
+   enum transmitter transmitter)
+{
+   switch (transmitter) {
+   case TRANSMITTER_UNIPHY_A:
+   return 0;
+   break;
+   case TRANSMITTER_UNIPHY_B:
+   return 1;
+   break;
+   case TRANSMITTER_UNIPHY_C:
+   return 2;
+   break;
+   case TRANSMITTER_UNIPHY_D:
+   return 3;
+   break;
+   case TRANSMITTER_UNIPHY_E:
+   return 4;
+   break;
+   case TRANSMITTER_UNIPHY_F:
+   return 5;
+   break;
+   case TRANSMITTER_UNIPHY_G:
+   return 6;
+   break;
+   default:
+   ASSERT(0);
+   return 0;
+   }
+}
+
 static void read_dce_straps(
struct dc_context *ctx,
struct resource_straps *straps)
@@ -625,14 +656,18 @@ static struct link_encoder *dce110_link_encoder_create(
 {
struct dce110_link_encoder *enc110 =
kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
+   int link_regs_id;
 
if (!enc110)
return NULL;
 
+   link_regs_id =
+   map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
+
dce110_link_encoder_construct(enc110,
  

[PATCH 08/37] drm/amd/display: Add debugfs entry for reading psr state

[sunpeng.li]

From: Roman Li 

[Why]
For upcoming PSR stupport it's useful to have debug entry
to verify psr state.

[How]
 - Enable psr dc api for Linux
 - Add psr_state file to eDP connector debugfs
usage e.g.: cat /sys/kernel/debug/dri/0/DP-1/psr_state

Signed-off-by: Roman Li 
Reviewed-by: Nicholas Kazlauskas 
Acked-by: Leo Li 
---
 .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c |  21 +++
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 149 ++
 2 files changed, 170 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index e29c6314f98c..bdb37e611015 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -969,6 +969,25 @@ static int force_yuv420_output_get(void *data, u64 *val)
 DEFINE_DEBUGFS_ATTRIBUTE(force_yuv420_output_fops, force_yuv420_output_get,
 force_yuv420_output_set, "%llu\n");
 
+/*
+ *  Read PSR state
+ */
+static int psr_get(void *data, u64 *val)
+{
+   struct amdgpu_dm_connector *connector = data;
+   struct dc_link *link = connector->dc_link;
+   uint32_t psr_state = 0;
+
+   dc_link_get_psr_state(link, _state);
+
+   *val = psr_state;
+
+   return 0;
+}
+
+
+DEFINE_DEBUGFS_ATTRIBUTE(psr_fops, psr_get, NULL, "%llu\n");
+
 void connector_debugfs_init(struct amdgpu_dm_connector *connector)
 {
int i;
@@ -982,6 +1001,8 @@ void connector_debugfs_init(struct amdgpu_dm_connector 
*connector)
dp_debugfs_entries[i].fops);
}
}
+   if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
+   debugfs_create_file_unsafe("psr_state", 0444, dir, connector, 
_fops);
 
debugfs_create_file_unsafe("force_yuv420_output", 0644, dir, connector,
   _yuv420_output_fops);
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 935053664160..10a04565535c 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -2436,6 +2436,155 @@ bool dc_link_set_psr_allow_active(struct dc_link *link, 
bool allow_active, bool
return true;
 }
 
+bool dc_link_get_psr_state(const struct dc_link *link, uint32_t *psr_state)
+{
+   struct dc  *core_dc = link->ctx->dc;
+   struct dmcu *dmcu = core_dc->res_pool->dmcu;
+
+   if (dmcu != NULL && link->psr_feature_enabled)
+   dmcu->funcs->get_psr_state(dmcu, psr_state);
+
+   return true;
+}
+
+bool dc_link_setup_psr(struct dc_link *link,
+   const struct dc_stream_state *stream, struct psr_config 
*psr_config,
+   struct psr_context *psr_context)
+{
+   struct dc *core_dc;
+   struct dmcu *dmcu;
+   int i;
+   /* updateSinkPsrDpcdConfig*/
+   union dpcd_psr_configuration psr_configuration;
+
+   psr_context->controllerId = CONTROLLER_ID_UNDEFINED;
+
+   if (!link)
+   return false;
+
+   core_dc = link->ctx->dc;
+   dmcu = core_dc->res_pool->dmcu;
+
+   if (!dmcu)
+   return false;
+
+
+   memset(_configuration, 0, sizeof(psr_configuration));
+
+   psr_configuration.bits.ENABLE= 1;
+   psr_configuration.bits.CRC_VERIFICATION  = 1;
+   psr_configuration.bits.FRAME_CAPTURE_INDICATION  =
+   psr_config->psr_frame_capture_indication_req;
+
+   /* Check for PSR v2*/
+   if (psr_config->psr_version == 0x2) {
+   /* For PSR v2 selective update.
+* Indicates whether sink should start capturing
+* immediately following active scan line,
+* or starting with the 2nd active scan line.
+*/
+   psr_configuration.bits.LINE_CAPTURE_INDICATION = 0;
+   /*For PSR v2, determines whether Sink should generate
+* IRQ_HPD when CRC mismatch is detected.
+*/
+   psr_configuration.bits.IRQ_HPD_WITH_CRC_ERROR= 1;
+   }
+
+   dm_helpers_dp_write_dpcd(
+   link->ctx,
+   link,
+   368,
+   _configuration.raw,
+   sizeof(psr_configuration.raw));
+
+   psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel;
+   psr_context->transmitterId = link->link_enc->transmitter;
+   psr_context->engineId = link->link_enc->preferred_engine;
+
+   for (i = 0; i < MAX_PIPES; i++) {
+   if (core_dc->current_state->res_ctx.pipe_ctx[i].stream
+   == stream) {
+   /* dmcu -1 for all controller id values,
+* therefore +1 here
+*/
+   psr_context->controllerId =
+   

[PATCH 18/37] drm/amd/display: Allow inverted gamma

[sunpeng.li]

From: Aidan Yang 

[why]
There's a use case for inverted gamma
and it's been confirmed that negative slopes are ok.

[how]
Remove code for blocking non-monotonically increasing gamma

Signed-off-by: Aidan Yang 
Reviewed-by: Krunoslav Kovac 
Acked-by: Leo Li 
Acked-by: Reza Amini 
---
 .../amd/display/dc/dcn10/dcn10_cm_common.c| 22 +++
 1 file changed, 8 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
index 01c7e30b9ce1..bbd6e01b3eca 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
@@ -393,6 +393,10 @@ bool cm_helper_translate_curve_to_hw_format(
rgb_resulted[hw_points - 1].green = 
output_tf->tf_pts.green[start_index];
rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index];
 
+   rgb_resulted[hw_points].red = rgb_resulted[hw_points - 1].red;
+   rgb_resulted[hw_points].green = rgb_resulted[hw_points - 1].green;
+   rgb_resulted[hw_points].blue = rgb_resulted[hw_points - 1].blue;
+
// All 3 color channels have same x
corner_points[0].red.x = dc_fixpt_pow(dc_fixpt_from_int(2),
 dc_fixpt_from_int(region_start));
@@ -464,13 +468,6 @@ bool cm_helper_translate_curve_to_hw_format(
 
i = 1;
while (i != hw_points + 1) {
-   if (dc_fixpt_lt(rgb_plus_1->red, rgb->red))
-   rgb_plus_1->red = rgb->red;
-   if (dc_fixpt_lt(rgb_plus_1->green, rgb->green))
-   rgb_plus_1->green = rgb->green;
-   if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue))
-   rgb_plus_1->blue = rgb->blue;
-
rgb->delta_red   = dc_fixpt_sub(rgb_plus_1->red,   rgb->red);
rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green);
rgb->delta_blue  = dc_fixpt_sub(rgb_plus_1->blue,  rgb->blue);
@@ -562,6 +559,10 @@ bool cm_helper_translate_curve_to_degamma_hw_format(
rgb_resulted[hw_points - 1].green = 
output_tf->tf_pts.green[start_index];
rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index];
 
+   rgb_resulted[hw_points].red = rgb_resulted[hw_points - 1].red;
+   rgb_resulted[hw_points].green = rgb_resulted[hw_points - 1].green;
+   rgb_resulted[hw_points].blue = rgb_resulted[hw_points - 1].blue;
+
corner_points[0].red.x = dc_fixpt_pow(dc_fixpt_from_int(2),
 dc_fixpt_from_int(region_start));
corner_points[0].green.x = corner_points[0].red.x;
@@ -624,13 +625,6 @@ bool cm_helper_translate_curve_to_degamma_hw_format(
 
i = 1;
while (i != hw_points + 1) {
-   if (dc_fixpt_lt(rgb_plus_1->red, rgb->red))
-   rgb_plus_1->red = rgb->red;
-   if (dc_fixpt_lt(rgb_plus_1->green, rgb->green))
-   rgb_plus_1->green = rgb->green;
-   if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue))
-   rgb_plus_1->blue = rgb->blue;
-
rgb->delta_red   = dc_fixpt_sub(rgb_plus_1->red,   rgb->red);
rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green);
rgb->delta_blue  = dc_fixpt_sub(rgb_plus_1->blue,  rgb->blue);
-- 
2.23.0

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[PATCH 03/37] drm/amd/display: Add unknown clk state.

[sunpeng.li]

From: Yongqiang Sun 

[Why]
System hang during S0i3 if DP only connected due to clk is disabled when
doing link training.
During S0i3, clk is disabled while the clk state is updated when ini_hw
called, and at the moment clk is still disabled which indicating a wrong
state for next time trying to enable clk.

[How]
Add an unknown state and initialize it during int_hw, make sure enable clk
command be sent to smu.

Signed-off-by: Yongqiang Sun 
Reviewed-by: Eric Yang 
Acked-by: Leo Li 
---
 .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c| 16 
 .../dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c  |  2 +-
 drivers/gpu/drm/amd/display/dc/dc.h  |  5 +++--
 3 files changed, 12 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
index b647e0320e4b..6212b407cd01 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
@@ -114,22 +114,22 @@ void rn_update_clocks(struct clk_mgr *clk_mgr_base,
 */
if (safe_to_lower) {
/* check that we're not already in lower */
-   if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_OPTIMIZED) {
+   if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
 
display_count = rn_get_active_display_cnt_wa(dc, 
context);
/* if we can go lower, go lower */
if (display_count == 0) {
-   rn_vbios_smu_set_dcn_low_power_state(clk_mgr, 
DCN_PWR_STATE_OPTIMIZED);
+   rn_vbios_smu_set_dcn_low_power_state(clk_mgr, 
DCN_PWR_STATE_LOW_POWER);
/* update power state */
-   clk_mgr_base->clks.pwr_state = 
DCN_PWR_STATE_OPTIMIZED;
+   clk_mgr_base->clks.pwr_state = 
DCN_PWR_STATE_LOW_POWER;
}
}
} else {
-   /* check that we're not already in the normal state */
-   if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_NORMAL) {
-   rn_vbios_smu_set_dcn_low_power_state(clk_mgr, 
DCN_PWR_STATE_NORMAL);
+   /* check that we're not already in D0 */
+   if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) 
{
+   rn_vbios_smu_set_dcn_low_power_state(clk_mgr, 
DCN_PWR_STATE_MISSION_MODE);
/* update power state */
-   clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_NORMAL;
+   clk_mgr_base->clks.pwr_state = 
DCN_PWR_STATE_MISSION_MODE;
}
}
 
@@ -393,7 +393,7 @@ void rn_init_clocks(struct clk_mgr *clk_mgr)
// Assumption is that boot state always supports pstate
clk_mgr->clks.p_state_change_support = true;
clk_mgr->clks.prev_p_state_change_support = true;
-   clk_mgr->clks.pwr_state = DCN_PWR_STATE_NORMAL;
+   clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;
 }
 
 static struct clk_mgr_funcs dcn21_funcs = {
diff --git 
a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
index 5647fcf10717..cb7c0e8b7e1b 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
@@ -170,7 +170,7 @@ void rn_vbios_smu_set_dcn_low_power_state(struct 
clk_mgr_internal *clk_mgr, enum
 {
int disp_count;
 
-   if (state == DCN_PWR_STATE_OPTIMIZED)
+   if (state == DCN_PWR_STATE_LOW_POWER)
disp_count = 0;
else
disp_count = 1;
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index b7e7181bad78..2e1d34882684 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -257,8 +257,9 @@ enum dtm_pstate{
 };
 
 enum dcn_pwr_state {
-   DCN_PWR_STATE_OPTIMIZED = 0,
-   DCN_PWR_STATE_NORMAL = 1
+   DCN_PWR_STATE_UNKNOWN = -1,
+   DCN_PWR_STATE_MISSION_MODE = 0,
+   DCN_PWR_STATE_LOW_POWER = 3,
 };
 
 /*
-- 
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[PATCH 10/37] drm/amd/display: correctly populate dpp refclk in fpga

[sunpeng.li]

From: Anthony Koo 

[Why]
In diags environment we are not programming the DPP DTO
correctly.

[How]
Populate the dpp refclk in dccg so it can be used to correctly
program DPP DTO.

Signed-off-by: Anthony Koo 
Reviewed-by: Tony Cheng 
Acked-by: Leo Li 
---
 .../drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c   | 10 --
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
index ecd2cb4840e3..69daddbfbf29 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
@@ -260,6 +260,8 @@ void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr,
struct dc_state *context,
bool safe_to_lower)
 {
+   struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr);
+
struct dc_clocks *new_clocks = >bw_ctx.bw.dcn.clk;
/* Min fclk = 1.2GHz since all the extra scemi logic seems to run off 
of it */
int fclk_adj = new_clocks->fclk_khz > 120 ? new_clocks->fclk_khz : 
120;
@@ -297,14 +299,18 @@ void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr,
clk_mgr->clks.dispclk_khz = new_clocks->dispclk_khz;
}
 
-   /* Both fclk and dppclk ref are run on the same scemi clock so we
-* need to keep the same value for both
+   /* Both fclk and ref_dppclk run on the same scemi clock.
+* So take the higher value since the DPP DTO is typically programmed
+* such that max dppclk is 1:1 with ref_dppclk.
 */
if (clk_mgr->clks.fclk_khz > clk_mgr->clks.dppclk_khz)
clk_mgr->clks.dppclk_khz = clk_mgr->clks.fclk_khz;
if (clk_mgr->clks.dppclk_khz > clk_mgr->clks.fclk_khz)
clk_mgr->clks.fclk_khz = clk_mgr->clks.dppclk_khz;
 
+   // Both fclk and ref_dppclk run on the same scemi clock.
+   clk_mgr_int->dccg->ref_dppclk = clk_mgr->clks.fclk_khz;
+
dm_set_dcn_clocks(clk_mgr->ctx, _mgr->clks);
 }
 
-- 
2.23.0

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[PATCH 04/37] drm/amd/display: Don't use optimized gamma22 with eetf

[sunpeng.li]

From: Aidan Yang 

[why]
Optimized gamma22 assumes fixed point distribution which is not true
for eetf true.

[how]
Use long calculation for eetf.

Signed-off-by: Aidan Yang 
Reviewed-by: Krunoslav Kovac 
Acked-by: Leo Li 
Acked-by: Reza Amini 
---
 .../amd/display/modules/color/color_gamma.c   | 45 +--
 1 file changed, 41 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c 
b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
index 2d8f14b69117..85dad356c9d5 100644
--- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
@@ -373,7 +373,42 @@ static struct fixed31_32 translate_from_linear_space(
return dc_fixpt_mul(args->arg, args->a1);
 }
 
-static struct fixed31_32 calculate_gamma22(struct fixed31_32 arg)
+
+static struct fixed31_32 translate_from_linear_space_long(
+   struct translate_from_linear_space_args *args)
+{
+   const struct fixed31_32 one = dc_fixpt_from_int(1);
+
+   if (dc_fixpt_lt(one, args->arg))
+   return one;
+
+   if (dc_fixpt_le(args->arg, dc_fixpt_neg(args->a0)))
+   return dc_fixpt_sub(
+   args->a2,
+   dc_fixpt_mul(
+   dc_fixpt_add(
+   one,
+   args->a3),
+   dc_fixpt_pow(
+   dc_fixpt_neg(args->arg),
+   dc_fixpt_recip(args->gamma;
+   else if (dc_fixpt_le(args->a0, args->arg))
+   return dc_fixpt_sub(
+   dc_fixpt_mul(
+   dc_fixpt_add(
+   one,
+   args->a3),
+   dc_fixpt_pow(
+   args->arg,
+   dc_fixpt_recip(args->gamma))),
+   args->a2);
+   else
+   return dc_fixpt_mul(
+   args->arg,
+   args->a1);
+}
+
+static struct fixed31_32 calculate_gamma22(struct fixed31_32 arg, bool 
use_eetf)
 {
struct fixed31_32 gamma = dc_fixpt_from_fraction(22, 10);
 
@@ -384,9 +419,13 @@ static struct fixed31_32 calculate_gamma22(struct 
fixed31_32 arg)
scratch_gamma_args.a3 = dc_fixpt_zero;
scratch_gamma_args.gamma = gamma;
 
+   if (use_eetf)
+   return translate_from_linear_space_long(_gamma_args);
+
return translate_from_linear_space(_gamma_args);
 }
 
+
 static struct fixed31_32 translate_to_linear_space(
struct fixed31_32 arg,
struct fixed31_32 a0,
@@ -950,7 +989,7 @@ static bool build_freesync_hdr(struct pwl_float_data_ex 
*rgb_regamma,
if (dc_fixpt_lt(scaledX, dc_fixpt_zero))
output = dc_fixpt_zero;
else
-   output = calculate_gamma22(scaledX);
+   output = calculate_gamma22(scaledX, 
use_eetf);
 
rgb->r = output;
rgb->g = output;
@@ -2173,5 +2212,3 @@ bool  mod_color_calculate_degamma_curve(enum 
dc_transfer_func_predefined trans,
 rgb_degamma_alloc_fail:
return ret;
 }
-
-
-- 
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[PATCH 13/37] drm/amd/display: move dispclk vco freq to clk mgr base

[sunpeng.li]

From: Dmytro Laktyushkin 

This value will be needed by dml and therefore should be externally
accessible.

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Nevenko Stupar 
Acked-by: Leo Li 
---
 .../amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c| 14 +++---
 .../amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c |  4 ++--
 .../drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c | 10 +-
 .../amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c   | 14 +++---
 .../drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c  | 12 ++--
 .../drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h  |  7 ---
 .../gpu/drm/amd/display/dc/dcn20/dcn20_resource.c  | 12 ++--
 .../gpu/drm/amd/display/dc/dcn20/dcn20_resource.h  |  6 ++
 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h|  2 +-
 .../drm/amd/display/dc/inc/hw/clk_mgr_internal.h   |  2 --
 10 files changed, 40 insertions(+), 43 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
index c5c8c4901eed..26db1c5d4e4d 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
@@ -147,7 +147,7 @@ int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)
 
/* Calculate the current DFS clock, in kHz.*/
dp_ref_clk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
-   * clk_mgr->dentist_vco_freq_khz) / target_div;
+   * clk_mgr->base.dentist_vco_freq_khz) / target_div;
 
return dce_adjust_dp_ref_freq_for_ss(clk_mgr, dp_ref_clk_khz);
 }
@@ -239,7 +239,7 @@ int dce_set_clock(
/* Make sure requested clock isn't lower than minimum threshold*/
if (requested_clk_khz > 0)
requested_clk_khz = max(requested_clk_khz,
-   clk_mgr_dce->dentist_vco_freq_khz / 64);
+   clk_mgr_dce->base.dentist_vco_freq_khz / 64);
 
/* Prepare to program display clock*/
pxl_clk_params.target_pixel_clock_100hz = requested_clk_khz * 10;
@@ -276,11 +276,11 @@ static void dce_clock_read_integrated_info(struct 
clk_mgr_internal *clk_mgr_dce)
int i;
 
if (bp->integrated_info)
-   clk_mgr_dce->dentist_vco_freq_khz = 
bp->integrated_info->dentist_vco_freq;
-   if (clk_mgr_dce->dentist_vco_freq_khz == 0) {
-   clk_mgr_dce->dentist_vco_freq_khz = 
bp->fw_info.smu_gpu_pll_output_freq;
-   if (clk_mgr_dce->dentist_vco_freq_khz == 0)
-   clk_mgr_dce->dentist_vco_freq_khz = 360;
+   clk_mgr_dce->base.dentist_vco_freq_khz = 
bp->integrated_info->dentist_vco_freq;
+   if (clk_mgr_dce->base.dentist_vco_freq_khz == 0) {
+   clk_mgr_dce->base.dentist_vco_freq_khz = 
bp->fw_info.smu_gpu_pll_output_freq;
+   if (clk_mgr_dce->base.dentist_vco_freq_khz == 0)
+   clk_mgr_dce->base.dentist_vco_freq_khz = 360;
}
 
/*update the maximum display clock for each power state*/
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
index 7c746ef1e32e..a6c46e903ff9 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
@@ -81,7 +81,7 @@ int dce112_set_clock(struct clk_mgr *clk_mgr_base, int 
requested_clk_khz)
/* Make sure requested clock isn't lower than minimum threshold*/
if (requested_clk_khz > 0)
requested_clk_khz = max(requested_clk_khz,
-   clk_mgr_dce->dentist_vco_freq_khz / 62);
+   clk_mgr_dce->base.dentist_vco_freq_khz / 62);
 
dce_clk_params.target_clock_frequency = requested_clk_khz;
dce_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
@@ -135,7 +135,7 @@ int dce112_set_dispclk(struct clk_mgr_internal *clk_mgr, 
int requested_clk_khz)
/* Make sure requested clock isn't lower than minimum threshold*/
if (requested_clk_khz > 0)
requested_clk_khz = max(requested_clk_khz,
-   clk_mgr->dentist_vco_freq_khz / 62);
+   clk_mgr->base.dentist_vco_freq_khz / 62);
 
dce_clk_params.target_clock_frequency = requested_clk_khz;
dce_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
index 5b3d36d41822..3fab9296918a 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
@@ -269,11 +269,11 @@ void rv1_clk_mgr_construct(struct dc_context *ctx, struct 
clk_mgr_internal *clk_
clk_mgr->base.dprefclk_khz = 60;
 
if (bp->integrated_info)
-   

[PATCH 05/37] drm/amd/display: Remove superfluous assert

[sunpeng.li]

From: Jordan Lazare 

[Why]
For loop below the assert already checks for the number of instances to
create. ASSERT is meaningless and causing spam.

[How]
dd

Signed-off-by: Jordan Lazare 
Reviewed-by: Harry Wentland 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index ee9157b673ab..c9792c47978a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -2913,8 +2913,6 @@ bool dcn20_dwbc_create(struct dc_context *ctx, struct 
resource_pool *pool)
int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
 
-   ASSERT(pipe_count > 0);
-
for (i = 0; i < pipe_count; i++) {
struct dcn20_dwbc *dwbc20 = kzalloc(sizeof(struct dcn20_dwbc),
GFP_KERNEL);
-- 
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[PATCH 19/37] drm/amd/display: enable vm by default for rn.

[sunpeng.li]

From: Yongqiang Sun 

[Why & How]
vm should be enabled by default for rn to get
right dml.

Signed-off-by: Yongqiang Sun 
Reviewed-by: Dmytro Laktyushkin 
Reviewed-by: Tony Cheng 
Acked-by: Leo Li 
---
 .../drm/amd/display/dc/dcn21/dcn21_resource.c | 29 ---
 1 file changed, 25 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index 5e3b48bb04f1..a4d9ed9f2623 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -83,8 +83,8 @@
 
 struct _vcs_dpi_ip_params_st dcn2_1_ip = {
.odm_capable = 1,
-   .gpuvm_enable = 0,
-   .hostvm_enable = 0,
+   .gpuvm_enable = 1,
+   .hostvm_enable = 1,
.gpuvm_max_page_table_levels = 1,
.hostvm_max_page_table_levels = 4,
.hostvm_cached_page_table_levels = 2,
@@ -669,6 +669,9 @@ static const struct dcn10_stream_encoder_mask se_mask = {
 
 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
 
+static int dcn21_populate_dml_pipes_from_context(
+   struct dc *dc, struct resource_context *res_ctx, 
display_e2e_pipe_params_st *pipes);
+
 static struct input_pixel_processor *dcn21_ipp_create(
struct dc_context *ctx, uint32_t inst)
 {
@@ -1083,7 +1086,7 @@ void dcn21_calculate_wm(
pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
>res_ctx, pipes);
else
-   pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
+   pipe_cnt = dcn21_populate_dml_pipes_from_context(dc,
>res_ctx, pipes);
}
 
@@ -1585,11 +1588,29 @@ static uint32_t read_pipe_fuses(struct dc_context *ctx)
return value;
 }
 
+static int dcn21_populate_dml_pipes_from_context(
+   struct dc *dc, struct resource_context *res_ctx, 
display_e2e_pipe_params_st *pipes)
+{
+   uint32_t pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, res_ctx, 
pipes);
+   int i;
+
+   for (i = 0; i < dc->res_pool->pipe_count; i++) {
+
+   if (!res_ctx->pipe_ctx[i].stream)
+   continue;
+
+   pipes[i].pipe.src.hostvm = 1;
+   pipes[i].pipe.src.gpuvm = 1;
+   }
+
+   return pipe_cnt;
+}
+
 static struct resource_funcs dcn21_res_pool_funcs = {
.destroy = dcn21_destroy_resource_pool,
.link_enc_create = dcn21_link_encoder_create,
.validate_bandwidth = dcn21_validate_bandwidth,
-   .populate_dml_pipes = dcn20_populate_dml_pipes_from_context,
+   .populate_dml_pipes = dcn21_populate_dml_pipes_from_context,
.add_stream_to_ctx = dcn20_add_stream_to_ctx,
.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
.acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
-- 
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[PATCH 14/37] drm/amd/display: remove unnecessary assert

[sunpeng.li]

From: Dmytro Laktyushkin 

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Chris Park 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index db3fb57bf244..9bc0ffad7093 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -1633,7 +1633,6 @@ bool dcn20_split_stream_for_odm(
next_odm_pipe->stream_res.dsc = NULL;
 #endif
if (prev_odm_pipe->next_odm_pipe && prev_odm_pipe->next_odm_pipe != 
next_odm_pipe) {
-   ASSERT(!next_odm_pipe->next_odm_pipe);
next_odm_pipe->next_odm_pipe = prev_odm_pipe->next_odm_pipe;
next_odm_pipe->next_odm_pipe->prev_odm_pipe = next_odm_pipe;
}
@@ -2398,8 +2397,8 @@ int dcn20_validate_apply_pipe_split_flags(
split[i] = true;

context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx] = true;
}
-   context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]
-   = 
context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx];
+   context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx] =
+   
context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx];
/* Adjust dppclk when split is forced, do not bother with 
dispclk */
if (split[i] && 
context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx]
 == 1)

context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx]
 /= 2;
-- 
2.23.0

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[PATCH 01/37] drm/amd/display: add 50us buffer as WA for pstate switch in active

[sunpeng.li]

From: Jun Lei 

Signed-off-by: Jun Lei 
Reviewed-by: Aric Cyr 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
index 649883777f62..6c6c486b774a 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
@@ -2577,7 +2577,8 @@ static void 
dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer
mode_lib->vba.MinActiveDRAMClockChangeMargin
+ mode_lib->vba.DRAMClockChangeLatency;
 
-   if (mode_lib->vba.MinActiveDRAMClockChangeMargin > 0) {
+   if (mode_lib->vba.MinActiveDRAMClockChangeMargin > 50) {
+   mode_lib->vba.DRAMClockChangeWatermark += 25;
mode_lib->vba.DRAMClockChangeSupport[0][0] = 
dm_dram_clock_change_vactive;
} else {
if (mode_lib->vba.SynchronizedVBlank || 
mode_lib->vba.NumberOfActivePlanes == 1) {
-- 
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[PATCH 02/37] drm/amd/display: add odm visual confirm

[sunpeng.li]

From: Jun Lei 

[why]
Hard to determine if pipe combine is done with MPC or ODM

[how]
Add new visual confirm type, this will mark each MPCC tree
with a different color

Signed-off-by: Jun Lei 
Reviewed-by: Yongqiang Sun 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/dc.h   |  1 +
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 25 +++
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.h|  4 ++-
 3 files changed, 29 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 5967106826ca..b7e7181bad78 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -229,6 +229,7 @@ enum visual_confirm {
VISUAL_CONFIRM_DISABLE = 0,
VISUAL_CONFIRM_SURFACE = 1,
VISUAL_CONFIRM_HDR = 2,
+   VISUAL_CONFIRM_MPCTREE = 4,
 };
 
 enum dcc_option {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 6229a8ca0013..e237ec39d193 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1996,6 +1996,28 @@ static void dcn20_reset_hw_ctx_wrap(
}
 }
 
+void dcn20_get_mpctree_visual_confirm_color(
+   struct pipe_ctx *pipe_ctx,
+   struct tg_color *color)
+{
+   const struct tg_color pipe_colors[6] = {
+   {MAX_TG_COLOR_VALUE, 0, 0}, // red
+   {MAX_TG_COLOR_VALUE, 0, MAX_TG_COLOR_VALUE}, // yellow
+   {0, MAX_TG_COLOR_VALUE, 0}, // blue
+   {MAX_TG_COLOR_VALUE / 2, 0, MAX_TG_COLOR_VALUE / 2}, // 
purple
+   {0, 0, MAX_TG_COLOR_VALUE}, // green
+   {MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE * 2 / 3, 0}, // 
orange
+   };
+
+   struct pipe_ctx *top_pipe = pipe_ctx;
+
+   while (top_pipe->top_pipe) {
+   top_pipe = top_pipe->top_pipe;
+   }
+
+   *color = pipe_colors[top_pipe->pipe_idx];
+}
+
 static void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
 {
struct hubp *hubp = pipe_ctx->plane_res.hubp;
@@ -2013,6 +2035,9 @@ static void dcn20_update_mpcc(struct dc *dc, struct 
pipe_ctx *pipe_ctx)
} else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) {
dcn10_get_surface_visual_confirm_color(
pipe_ctx, _cfg.black_color);
+   } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE) {
+   dcn20_get_mpctree_visual_confirm_color(
+   pipe_ctx, _cfg.black_color);
}
 
if (per_pixel_alpha)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
index 9dbc2effa4ea..3098f1049ed7 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
@@ -109,5 +109,7 @@ bool dcn20_set_blend_lut(
struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
 bool dcn20_set_shaper_3dlut(
struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
-
+void dcn20_get_mpctree_visual_confirm_color(
+   struct pipe_ctx *pipe_ctx,
+   struct tg_color *color);
 #endif /* __DC_HWSS_DCN20_H__ */
-- 
2.23.0

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[PATCH 00/37] DC Patches 17 Oct 2019

[sunpeng.li]

From: Leo Li 

This series has dependencies on the recent Renoir series:
https://patchwork.freedesktop.org/series/67803/#rev2

Summary of changes:
* Enable PSR on supported eDP panels
* Allow programming of negative gamma slope


Aidan Yang (2):
  drm/amd/display: Don't use optimized gamma22 with eetf
  drm/amd/display: Allow inverted gamma

Alvin Lee (1):
  drm/amd/display: Update min dcfclk

Anthony Koo (2):
  drm/amd/display: correctly populate dpp refclk in fpga
  drm/amd/display: Proper return of result when aux engine acquire fails

Aric Cyr (2):
  drm/amd/display: 3.2.55
  drm/amd/display: 3.2.56

Dmytro Laktyushkin (8):
  drm/amd/display: remove unused code
  drm/amd/display: split dcn20 fast validate into more functions
  drm/amd/display: correctly initialize dml odm variables
  drm/amd/display: move dispclk vco freq to clk mgr base
  drm/amd/display: remove unnecessary assert
  drm/amd/display: fix number of dcn21 dpm clock levels
  drm/amd/display: add embedded flag to dml
  drm/amd/display: fix avoid_split for dcn2+ validation

Eric Yang (2):
  drm/amd/display: move wm ranges reporting to end of init hw
  drm/amd/display: fix hubbub deadline programing

Jordan Lazare (1):
  drm/amd/display: Remove superfluous assert

Joshua Aberback (1):
  drm/amd/display: Apply vactive dram clock change workaround to dcn2
DMLv2

Jun Lei (4):
  drm/amd/display: add 50us buffer as WA for pstate switch in active
  drm/amd/display: add odm visual confirm
  drm/amd/display: add flag to allow diag to force enumerate edp
  drm/amd/display: do not synchronize "drr" displays

Krunoslav Kovac (1):
  drm/amd/display: Only use EETF when maxCL > max display

Lewis Huang (1):
  drm/amd/display: take signal type from link

Michael Strauss (3):
  drm/amd/display: Fix MPO & pipe split on 3-pipe dcn2x
  drm/amd/display: Passive DP->HDMI dongle detection fix
  drm/amd/display: Disable force_single_disp_pipe_split on DCN2+

Noah Abradjian (1):
  drm/amd/display: Make clk mgr the only dto update point

Paul Hsieh (1):
  drm/amd/display: audio endpoint cannot switch

Reza Amini (1):
  drm/amd/display: Add center mode for integer scaling in DC

Roman Li (2):
  drm/amd/display: Add debugfs entry for reading psr state
  drm/amd/display: Enable PSR

Sung Lee (1):
  drm/amd/display: Do not call update bounding box on dc create

Yogesh Mohan Marimuthu (1):
  drm/amd/display: map TRANSMITTER_UNIPHY_x to LINK_REGS_x

Yongqiang Sun (2):
  drm/amd/display: Add unknown clk state.
  drm/amd/display: enable vm by default for rn.

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 133 -
 .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c |  21 ++
 .../display/amdgpu_dm/amdgpu_dm_mst_types.c   |   1 +
 .../display/dc/clk_mgr/dce100/dce_clk_mgr.c   |  14 +-
 .../dc/clk_mgr/dce112/dce112_clk_mgr.c|   4 +-
 .../display/dc/clk_mgr/dcn10/rv1_clk_mgr.c|  10 +-
 .../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c  |  38 ++-
 .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 178 ++--
 .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h |   7 -
 .../dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c   |   2 +-
 drivers/gpu/drm/amd/display/dc/core/dc.c  |   8 +-
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 149 ++
 .../gpu/drm/amd/display/dc/core/dc_link_ddc.c |  24 +-
 .../gpu/drm/amd/display/dc/core/dc_resource.c |  54 +++-
 drivers/gpu/drm/amd/display/dc/dc.h   |   9 +-
 drivers/gpu/drm/amd/display/dc/dc_ddc_types.h |   3 +-
 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c  |   5 +-
 .../amd/display/dc/dce100/dce100_resource.c   |  37 ++-
 .../display/dc/dce110/dce110_hw_sequencer.c   |  11 +-
 .../amd/display/dc/dce110/dce110_resource.c   |  37 ++-
 .../amd/display/dc/dce112/dce112_resource.c   |  37 ++-
 .../amd/display/dc/dce120/dce120_resource.c   |  37 ++-
 .../drm/amd/display/dc/dce80/dce80_resource.c |  37 ++-
 .../amd/display/dc/dcn10/dcn10_cm_common.c|  22 +-
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c |   4 +
 .../drm/amd/display/dc/dcn10/dcn10_resource.c |  28 +-
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c|  33 ++-
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.h|   4 +-
 .../drm/amd/display/dc/dcn20/dcn20_resource.c | 260 +++---
 .../drm/amd/display/dc/dcn20/dcn20_resource.h |  31 +++
 .../drm/amd/display/dc/dcn21/dcn21_resource.c |  78 +-
 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h|   4 +-
 .../dc/dml/dcn20/display_mode_vba_20.c|   3 +-
 .../dc/dml/dcn20/display_mode_vba_20v2.c  |   3 +-
 .../amd/display/dc/dml/display_mode_structs.h |   1 +
 .../drm/amd/display/dc/dml/display_mode_vba.c |   3 +
 .../drm/amd/display/dc/dml/display_mode_vba.h |   1 +
 .../gpu/drm/amd/display/dc/inc/core_types.h   |   4 -
 .../gpu/drm/amd/display/dc/inc/hw/clk_mgr.h   |   3 +-
 .../amd/display/dc/inc/hw/clk_mgr_internal.h  |   2 -
 .../amd/display/modules/color/color_gamma.c   |  51 +++-
 41 files changed, 1074 insertions(+), 317 deletions(-)

-- 
2.23.0

[PATCH 00/25] DC Patches 09 Sep 2019

[sunpeng.li]

From: Leo Li 

Summary of change:

* Fix pipe split with DSC on high bandwidth timings (8k@60, 4k@144)
* Improve freesync low frame rate compensation (frame doubling) behavior
* Update ABM parameters, limit minimum adjustment
* Misc. refactors and fixes


Anthony Koo (1):
  drm/amd/display: set minimum abm backlight level

Aric Cyr (4):
  drm/amd/display: 3.2.50
  drm/amd/display: 3.4.51
  drm/amd/display: 3.4.51.1
  drm/amd/display: Improve LFC behaviour

Dmytro Laktyushkin (5):
  drm/amd/display: add additional flag consideration for surface update
  drm/amd/display: add vtg update after global sync update
  drm/amd/display: fix global sync param extraction indexing
  drm/amd/display: update odm mode validation to be in line with policy
  drm/amd/display: Add detile buffer size for DCN20

Ilya Bakoulin (1):
  drm/amd/display: Fix HUBP secondary viewport programming

Josip Pavic (1):
  drm/amd/display: define parameters for abm 2.3

Julian Parkin (1):
  drm/amd/display: Separate hardware initialization from creation

Lewis Huang (1):
  drm/amd/display: fix i2c wtire mot incorrect issue

Martin Leung (2):
  drm/amd/display: enable single dp seamless boot
  drm/amd/display: fix use of uninitialized variable

Martin Tsai (1):
  drm/amd/display: Handle virtual signal type in disable_link()

Mikita Lipski (1):
  drm/amd/display: Rebuild mapped resources after pipe split

Nikola Cornij (1):
  drm/amd/display: Set number of pipes to 1 if the second pipe was
disabled

Stylon Wang (1):
  drm/amd/display: Add debugfs entry to force YUV420 output

Wesley Chalmers (4):
  drm/amd/display: Replace for loop w/ function call
  drm/amd/display: Do not double-buffer DTO adjustments
  drm/amd/display: Revert fixup DPP programming sequence
  drm/amd/display: Optimize clocks on clock change

Zhan Liu (1):
  drm/amd/display: Add missing HBM support and raise Vega20's uclk.

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  12 +-
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |   1 +
 .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c |  31 
 .../dc/clk_mgr/dce110/dce110_clk_mgr.c|  18 ++-
 .../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c  | 132 +-
 drivers/gpu/drm/amd/display/dc/core/dc.c  |  38 ++---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c |  63 ++---
 .../gpu/drm/amd/display/dc/core/dc_link_ddc.c |   4 +-
 .../gpu/drm/amd/display/dc/core/dc_resource.c |  26 ++--
 drivers/gpu/drm/amd/display/dc/dc.h   |  12 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c |   8 ++
 .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h |  12 ++
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c |   3 +-
 .../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c |  52 +--
 .../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h |   2 +-
 .../drm/amd/display/dc/dcn20/dcn20_hubbub.c   |  12 +-
 .../drm/amd/display/dc/dcn20/dcn20_hubbub.h   |   1 +
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c|  11 +-
 .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.c |   4 +
 .../drm/amd/display/dc/dcn20/dcn20_resource.c |  29 +---
 .../dc/dml/dcn20/display_mode_vba_20v2.c  |   9 +-
 .../gpu/drm/amd/display/dc/inc/core_types.h   |   1 +
 .../amd/display/dc/inc/hw/clk_mgr_internal.h  |  10 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h  |   3 +-
 .../amd/display/modules/freesync/freesync.c   |  32 +++--
 .../amd/display/modules/inc/mod_freesync.h|   1 +
 .../amd/display/modules/power/power_helpers.c |  93 ++--
 .../amd/display/modules/power/power_helpers.h |   1 +
 28 files changed, 315 insertions(+), 306 deletions(-)

-- 
2.22.0

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[PATCH 08/25] drm/amd/display: add vtg update after global sync update

[sunpeng.li]

From: Dmytro Laktyushkin 

Global sync update was missing vtg update resulting in underflow if
vstartup decreased a significant amount.

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Jaehyun Chung 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index faaf8841c61e..4bb5ad19c4cf 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1361,7 +1361,7 @@ static void dcn20_program_pipe(
&& !pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe)
dc->hwss.blank_pixel_data(dc, pipe_ctx, 
!pipe_ctx->plane_state->visible);
 
-   if (pipe_ctx->update_flags.bits.global_sync)
+   if (pipe_ctx->update_flags.bits.global_sync) {
pipe_ctx->stream_res.tg->funcs->program_global_sync(
pipe_ctx->stream_res.tg,
pipe_ctx->pipe_dlg_param.vready_offset,
@@ -1369,6 +1369,10 @@ static void dcn20_program_pipe(
pipe_ctx->pipe_dlg_param.vupdate_offset,
pipe_ctx->pipe_dlg_param.vupdate_width);
 
+   pipe_ctx->stream_res.tg->funcs->set_vtg_params(
+   pipe_ctx->stream_res.tg, 
_ctx->stream->timing);
+   }
+
if (pipe_ctx->update_flags.bits.odm)
dc->hwss.update_odm(dc, context, pipe_ctx);
 
-- 
2.22.0

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[PATCH 20/25] drm/amd/display: 3.4.51

[sunpeng.li]

From: Aric Cyr 

Signed-off-by: Aric Cyr 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index c65f34aa2523..7c19ac71b424 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -39,7 +39,7 @@
 #include "inc/hw/dmcu.h"
 #include "dml/display_mode_lib.h"
 
-#define DC_VER "3.2.50"
+#define DC_VER "3.2.51"
 
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
-- 
2.22.0

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[PATCH 24/25] drm/amd/display: Add detile buffer size for DCN20

[sunpeng.li]

From: Dmytro Laktyushkin 

Detile buffer size affects dcc caps and therefore needs to be
corrected for each ip.

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Chris Park 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c | 7 ---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h | 1 +
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
index e0a6e30ac3e1..8b8438566101 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
@@ -186,14 +186,13 @@ static void hubbub2_get_blk256_size(unsigned int 
*blk256_width, unsigned int *bl
 }
 
 static void hubbub2_det_request_size(
+   unsigned int detile_buf_size,
unsigned int height,
unsigned int width,
unsigned int bpe,
bool *req128_horz_wc,
bool *req128_vert_wc)
 {
-   unsigned int detile_buf_size = 164 * 1024;  /* 164KB for DCN1.0 */
-
unsigned int blk256_height = 0;
unsigned int blk256_width = 0;
unsigned int swath_bytes_horz_wc, swath_bytes_vert_wc;
@@ -236,7 +235,8 @@ bool hubbub2_get_dcc_compression_cap(struct hubbub *hubbub,
_order_horz, _order_vert))
return false;
 
-   hubbub2_det_request_size(input->surface_size.height,  
input->surface_size.width,
+   hubbub2_det_request_size(TO_DCN20_HUBBUB(hubbub)->detile_buf_size,
+   input->surface_size.height,  input->surface_size.width,
bpe, _horz_wc, _vert_wc);
 
if (!req128_horz_wc && !req128_vert_wc) {
@@ -619,4 +619,5 @@ void hubbub2_construct(struct dcn20_hubbub *hubbub,
hubbub->masks = hubbub_mask;
 
hubbub->debug_test_index_pstate = 0xB;
+   hubbub->detile_buf_size = 164 * 1024; /* 164KB for DCN2.0 */
 }
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h
index 626117d3b4e9..501532dd523a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h
@@ -81,6 +81,7 @@ struct dcn20_hubbub {
unsigned int debug_test_index_pstate;
struct dcn_watermark_set watermarks;
struct dcn20_vmid vmid[16];
+   unsigned int detile_buf_size;
 };
 
 void hubbub2_construct(struct dcn20_hubbub *hubbub,
-- 
2.22.0

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[PATCH 05/25] drm/amd/display: Replace for loop w/ function call

[sunpeng.li]

From: Wesley Chalmers 

[WHY]
A function to adjust DPP clocks with DTO already exists; function code
is identical to the code replaced here

Signed-off-by: Wesley Chalmers 
Reviewed-by: Charlene Liu 
Acked-by: Leo Li 
---
 .../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c  | 25 ++-
 1 file changed, 2 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
index 3e8ac303bd52..f1df32664414 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
@@ -196,7 +196,6 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,
bool enter_display_off = false;
struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
bool force_reset = false;
-   int i;
 
if (dc->work_arounds.skip_clock_update)
return;
@@ -278,34 +277,14 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,

request_voltage_and_program_global_dpp_clk(clk_mgr_base, 
new_clocks->dppclk_khz);
 
// Then raise any dividers that need raising
-   for (i = 0; i < 
clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
-   int dpp_inst, dppclk_khz;
-
-   if (!context->res_ctx.pipe_ctx[i].plane_state)
-   continue;
-
-   dpp_inst = 
context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
-   dppclk_khz = 
context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
-
-   
clk_mgr->dccg->funcs->update_dpp_dto(clk_mgr->dccg, dpp_inst, dppclk_khz, true);
-   }
+   dcn20_update_clocks_update_dpp_dto(clk_mgr, context);
} else {
// For post-programming, we can lower ref clk if 
needed, and unconditionally set all the DTOs
 
if (new_clocks->dppclk_khz < 
clk_mgr_base->clks.dppclk_khz)

request_voltage_and_program_global_dpp_clk(clk_mgr_base, 
new_clocks->dppclk_khz);
+   dcn20_update_clocks_update_dpp_dto(clk_mgr, context);
 
-   for (i = 0; i < 
clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
-   int dpp_inst, dppclk_khz;
-
-   if (!context->res_ctx.pipe_ctx[i].plane_state)
-   continue;
-
-   dpp_inst = 
context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
-   dppclk_khz = 
context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
-
-   
clk_mgr->dccg->funcs->update_dpp_dto(clk_mgr->dccg, dpp_inst, dppclk_khz, 
false);
-   }
}
}
if (update_dispclk &&
-- 
2.22.0

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[PATCH 25/25] drm/amd/display: Improve LFC behaviour

[sunpeng.li]

From: Aric Cyr 

[Why]
There can be some unsynchronized frames when entering/exiting
LFC.  This may cause tearing or stuttering at such transitions.

[How]
Add a enter/exit margin to algorithm to smoothly transition into
and out of LFC without desynchronizing frames.

Signed-off-by: Aric Cyr 
Reviewed-by: Reza Amini 
Acked-by: Leo Li 
Acked-by: Sivapiriyan Kumarasamy 
---
 .../amd/display/modules/freesync/freesync.c   | 32 +++
 .../amd/display/modules/inc/mod_freesync.h|  1 +
 2 files changed, 20 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c 
b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index 107d81ea689b..5e5ce9e5eab7 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -35,8 +35,8 @@
 #define STATIC_SCREEN_RAMP_DELTA_REFRESH_RATE_PER_FRAME ((1000 / 60) * 65)
 /* Number of elements in the render times cache array */
 #define RENDER_TIMES_MAX_COUNT 10
-/* Threshold to exit BTR (to avoid frequent enter-exits at the lower limit) */
-#define BTR_EXIT_MARGIN 2000
+/* Threshold to exit/exit BTR (to avoid frequent enter-exits at the lower 
limit) */
+#define BTR_MAX_MARGIN 2500
 /* Threshold to change BTR multiplier (to avoid frequent changes) */
 #define BTR_DRIFT_MARGIN 2000
 /*Threshold to exit fixed refresh rate*/
@@ -248,24 +248,22 @@ static void apply_below_the_range(struct core_freesync 
*core_freesync,
unsigned int delta_from_mid_point_in_us_1 = 0x;
unsigned int delta_from_mid_point_in_us_2 = 0x;
unsigned int frames_to_insert = 0;
-   unsigned int min_frame_duration_in_ns = 0;
-   unsigned int max_render_time_in_us = in_out_vrr->max_duration_in_us;
unsigned int delta_from_mid_point_delta_in_us;
-
-   min_frame_duration_in_ns = ((unsigned int) (div64_u64(
-   (10ULL * 100),
-   in_out_vrr->max_refresh_in_uhz)));
+   unsigned int max_render_time_in_us =
+   in_out_vrr->max_duration_in_us - 
in_out_vrr->btr.margin_in_us;
 
/* Program BTR */
-   if (last_render_time_in_us + BTR_EXIT_MARGIN < max_render_time_in_us) {
+   if ((last_render_time_in_us + in_out_vrr->btr.margin_in_us / 2) < 
max_render_time_in_us) {
/* Exit Below the Range */
if (in_out_vrr->btr.btr_active) {
in_out_vrr->btr.frame_counter = 0;
in_out_vrr->btr.btr_active = false;
}
-   } else if (last_render_time_in_us > max_render_time_in_us) {
+   } else if (last_render_time_in_us > (max_render_time_in_us + 
in_out_vrr->btr.margin_in_us / 2)) {
/* Enter Below the Range */
-   in_out_vrr->btr.btr_active = true;
+   if (!in_out_vrr->btr.btr_active) {
+   in_out_vrr->btr.btr_active = true;
+   }
}
 
/* BTR set to "not active" so disengage */
@@ -321,7 +319,9 @@ static void apply_below_the_range(struct core_freesync 
*core_freesync,
/* Choose number of frames to insert based on how close it
 * can get to the mid point of the variable range.
 */
-   if (delta_from_mid_point_in_us_1 < 
delta_from_mid_point_in_us_2) {
+   if ((frame_time_in_us / mid_point_frames_ceil) > 
in_out_vrr->min_duration_in_us &&
+   (delta_from_mid_point_in_us_1 < 
delta_from_mid_point_in_us_2 ||
+   mid_point_frames_floor < 2)) {
frames_to_insert = mid_point_frames_ceil;
delta_from_mid_point_delta_in_us = 
delta_from_mid_point_in_us_2 -
delta_from_mid_point_in_us_1;
@@ -337,7 +337,7 @@ static void apply_below_the_range(struct core_freesync 
*core_freesync,
if (in_out_vrr->btr.frames_to_insert != 0 &&
delta_from_mid_point_delta_in_us < 
BTR_DRIFT_MARGIN) {
if (((last_render_time_in_us / 
in_out_vrr->btr.frames_to_insert) <
-   in_out_vrr->max_duration_in_us) &&
+   max_render_time_in_us) &&
((last_render_time_in_us / 
in_out_vrr->btr.frames_to_insert) >
in_out_vrr->min_duration_in_us))
frames_to_insert = 
in_out_vrr->btr.frames_to_insert;
@@ -786,6 +786,11 @@ void mod_freesync_build_vrr_params(struct mod_freesync 
*mod_freesync,
refresh_range = in_out_vrr->max_refresh_in_uhz -
in_out_vrr->min_refresh_in_uhz;
 
+   in_out_vrr->btr.margin_in_us = in_out_vrr->max_duration_in_us -
+   2 * in_out_vrr->min_duration_in_us;
+   

[PATCH 19/25] drm/amd/display: enable single dp seamless boot

[sunpeng.li]

From: Martin Leung 

[why]
seamless boot didn't work for non edp's before

[how]
removed edp-specific code, made dp read uefi-set link settings. Also fixed
a hubbub code line to be consistent with usage of function.

Signed-off-by: Martin Leung 
Reviewed-by: Jun Lei 
Acked-by: Anthony Koo 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c  | 30 +-
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 57 ---
 .../gpu/drm/amd/display/dc/core/dc_resource.c | 26 -
 .../drm/amd/display/dc/dcn20/dcn20_hubbub.c   |  5 +-
 4 files changed, 71 insertions(+), 47 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 0d7ef89b17a4..cadb255826be 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -971,29 +971,33 @@ bool dc_validate_seamless_boot_timing(const struct dc *dc,
 {
struct timing_generator *tg;
struct dc_link *link = sink->link;
-   unsigned int enc_inst, tg_inst;
+   unsigned int enc_inst, tg_inst, i;
+
+   // Seamless port only support single DP and EDP so far
+   if (sink->sink_signal != SIGNAL_TYPE_DISPLAY_PORT &&
+   sink->sink_signal != SIGNAL_TYPE_EDP)
+   return false;
 
/* Check for enabled DIG to identify enabled display */
if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
return false;
 
-   /* Check for which front end is used by this encoder.
-* Note the inst is 1 indexed, where 0 is undefined.
-* Note that DIG_FE can source from different OTG but our
-* current implementation always map 1-to-1, so this code makes
-* the same assumption and doesn't check OTG source.
-*/
enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
 
-   /* Instance should be within the range of the pool */
-   if (enc_inst >= dc->res_pool->pipe_count)
+   if (enc_inst == ENGINE_ID_UNKNOWN)
return false;
 
-   if (enc_inst >= dc->res_pool->stream_enc_count)
-   return false;
+   for (i = 0; i < dc->res_pool->stream_enc_count; i++) {
+   if (dc->res_pool->stream_enc[i]->id == enc_inst) {
+   tg_inst = 
dc->res_pool->stream_enc[i]->funcs->dig_source_otg(
+   dc->res_pool->stream_enc[i]);
+   break;
+   }
+   }
 
-   tg_inst = dc->res_pool->stream_enc[enc_inst]->funcs->dig_source_otg(
-   dc->res_pool->stream_enc[enc_inst]);
+   // tg_inst not found
+   if (i == dc->res_pool->stream_enc_count)
+   return false;
 
if (tg_inst >= dc->res_pool->timing_generator_count)
return false;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index de07577085ce..d6d1eca77665 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -517,7 +517,7 @@ static void link_disconnect_remap(struct dc_sink 
*prev_sink, struct dc_link *lin
 }
 
 
-static void read_edp_current_link_settings_on_detect(struct dc_link *link)
+static void read_current_link_settings_on_detect(struct dc_link *link)
 {
union lane_count_set lane_count_set = { {0} };
uint8_t link_bw_set;
@@ -552,17 +552,23 @@ static void 
read_edp_current_link_settings_on_detect(struct dc_link *link)
_bw_set, sizeof(link_bw_set));
 
if (link_bw_set == 0) {
-   /* If standard link rates are not being used,
-* Read DPCD 00115h to find the link rate set used
-*/
-   core_link_read_dpcd(link, DP_LINK_RATE_SET,
-   _rate_set, sizeof(link_rate_set));
-
-   if (link_rate_set < 
link->dpcd_caps.edp_supported_link_rates_count) {
-   link->cur_link_settings.link_rate =
-   
link->dpcd_caps.edp_supported_link_rates[link_rate_set];
-   link->cur_link_settings.link_rate_set = link_rate_set;
-   link->cur_link_settings.use_link_rate_set = true;
+   if (link->connector_signal == SIGNAL_TYPE_EDP) {
+   /* If standard link rates are not being used,
+* Read DPCD 00115h to find the edp link rate set used
+*/
+   core_link_read_dpcd(link, DP_LINK_RATE_SET,
+   _rate_set, sizeof(link_rate_set));
+
+   // edp_supported_link_rates_count = 0 for DP
+   if (link_rate_set < 
link->dpcd_caps.edp_supported_link_rates_count) {
+   link->cur_link_settings.link_rate =
+   

[PATCH 18/25] drm/amd/display: update odm mode validation to be in line with policy

[sunpeng.li]

From: Dmytro Laktyushkin 

Previously 8k30 worked with dsc and odm combine due to a workaround that ran
the formula a second time with dsc support enable should dsc validation fail.
This worked when clocks were low enough for formula to enable odm to lower
voltage, however now broke due to increased clocks.

This change updates the ODM combine policy within the formula to properly
reflect our current policy within DC, only enabling ODM when we have to, as
well as adding a check for viewport width when dsc is enabled.

As a side effect the redundant call to dml when odm is required is now
unnecessary.

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Nikola Cornij 
Acked-by: Leo Li 
---
 .../drm/amd/display/dc/dcn20/dcn20_resource.c | 22 +--
 .../dc/dml/dcn20/display_mode_vba_20v2.c  |  9 +++-
 2 files changed, 9 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index d1901ab5fb8c..8d81c65157d4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -2246,11 +2246,7 @@ bool dcn20_fast_validate_bw(
bool out = false;
 
int pipe_cnt, i, pipe_idx, vlevel, vlevel_unsplit;
-   bool odm_capable = context->bw_ctx.dml.ip.odm_capable;
bool force_split = false;
-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
-   bool failed_non_odm_dsc = false;
-#endif
int split_threshold = dc->res_pool->pipe_count / 2;
bool avoid_split = dc->debug.pipe_split_policy != MPC_SPLIT_DYNAMIC;
 
@@ -2327,24 +2323,8 @@ bool dcn20_fast_validate_bw(
goto validate_out;
}
 
-   context->bw_ctx.dml.ip.odm_capable = 0;
-
vlevel = dml_get_voltage_level(>bw_ctx.dml, pipes, pipe_cnt);
 
-   context->bw_ctx.dml.ip.odm_capable = odm_capable;
-
-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
-   /* 1 dsc per stream dsc validation */
-   if (vlevel <= context->bw_ctx.dml.soc.num_states)
-   if (!dcn20_validate_dsc(dc, context)) {
-   failed_non_odm_dsc = true;
-   vlevel = context->bw_ctx.dml.soc.num_states + 1;
-   }
-#endif
-
-   if (vlevel > context->bw_ctx.dml.soc.num_states && odm_capable)
-   vlevel = dml_get_voltage_level(>bw_ctx.dml, pipes, 
pipe_cnt);
-
if (vlevel > context->bw_ctx.dml.soc.num_states)
goto validate_fail;
 
@@ -2480,7 +2460,7 @@ bool dcn20_fast_validate_bw(
}
 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
/* Actual dsc count per stream dsc validation*/
-   if (failed_non_odm_dsc && !dcn20_validate_dsc(dc, context)) {
+   if (!dcn20_validate_dsc(dc, context)) {

context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]
 =
DML_FAIL_DSC_VALIDATION_FAILURE;
goto validate_fail;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
index 0fafd693ffb4..841ed6c23f93 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
@@ -38,6 +38,7 @@
 
 #define BPP_INVALID 0
 #define BPP_BLENDED_PIPE 0x
+#define DCN20_MAX_DSC_IMAGE_WIDTH 5184
 
 static double adjust_ReturnBW(
struct display_mode_lib *mode_lib,
@@ -3901,6 +3902,10 @@ void 
dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode
mode_lib->vba.MaximumSwathWidthInLineBuffer);
}
for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
+   double MaxMaxDispclkRoundedDown = RoundToDFSGranularityDown(
+   mode_lib->vba.MaxDispclk[mode_lib->vba.soc.num_states],
+   mode_lib->vba.DISPCLKDPPCLKVCOSpeed);
+
for (j = 0; j < 2; j++) {
mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity = 
RoundToDFSGranularityDown(
mode_lib->vba.MaxDispclk[i],
@@ -3925,7 +3930,9 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct 
display_mode_lib *mode
&& i == 
mode_lib->vba.soc.num_states)

mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] 
/ 2
* (1 + 
mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
-   if (mode_lib->vba.ODMCapability == false || 
mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine <= 
mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity) {
+   if (mode_lib->vba.ODMCapability == false ||
+   
(locals->PlaneRequiredDISPCLKWithoutODMCombine <= 

[PATCH 17/25] drm/amd/display: Optimize clocks on clock change

[sunpeng.li]

From: Wesley Chalmers 

[WHY]
Presently, there is no way for clocks to be lowered, only raised.

[HOW]
Compare clock status against previous known clock status, and optimize
if different.
This requires re-ordering the layout of the dc_clocks structure, as the
current ordering allows identical clock states to appear different.

Signed-off-by: Wesley Chalmers 
Reviewed-by: Aric Cyr 
Acked-by: Anthony Koo 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 3 +++
 drivers/gpu/drm/amd/display/dc/dc.h  | 8 
 2 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 8ec80151636d..0d7ef89b17a4 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1643,6 +1643,9 @@ enum surface_update_type 
dc_check_update_surfaces_for_stream(
updates[i].surface->update_flags.raw = 0x;
}
 
+   if (type == UPDATE_TYPE_FAST && 
memcmp(>current_state->bw_ctx.bw.dcn.clk, >clk_mgr->clks, 
offsetof(struct dc_clocks, prev_p_state_change_support)) != 0)
+   dc->optimized_required = true;
+
return type;
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 30ef31a788f8..c65f34aa2523 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -252,11 +252,7 @@ enum wm_report_mode {
  */
 struct dc_clocks {
int dispclk_khz;
-   int max_supported_dppclk_khz;
-   int max_supported_dispclk_khz;
int dppclk_khz;
-   int bw_dppclk_khz; /*a copy of dppclk_khz*/
-   int bw_dispclk_khz;
int dcfclk_khz;
int socclk_khz;
int dcfclk_deep_sleep_khz;
@@ -270,6 +266,10 @@ struct dc_clocks {
 * optimization required
 */
bool prev_p_state_change_support;
+   int max_supported_dppclk_khz;
+   int max_supported_dispclk_khz;
+   int bw_dppclk_khz; /*a copy of dppclk_khz*/
+   int bw_dispclk_khz;
 };
 
 struct dc_bw_validation_profile {
-- 
2.22.0

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[PATCH 21/25] drm/amd/display: Add missing HBM support and raise Vega20's uclk.

[sunpeng.li]

From: Zhan Liu 

[Why]
When more than 2 displays are connected to the graphics card,
only the minimum memory clock is needed. However, when more
displays are connected, the minimum memory clock is not
sufficient enough to support the overwhelming bandwidth.
System will hang under this circumstance.

Also, the old code didn't address HBM cards, which has 2
pseudo channels. We need to add the HBM part here.

[How]
When graphics card connects to 2 or more displays,
switch to high memory clock. Also, choose memory
multiplier based on whether its regular DRAM or HBM.

Signed-off-by: Zhan Liu 
Reviewed-by: Roman Li 
Acked-by: Leo Li 
---
 .../display/dc/clk_mgr/dce110/dce110_clk_mgr.c | 18 --
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
index ee32d2c19305..36277bca0326 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
@@ -174,6 +174,10 @@ void dce11_pplib_apply_display_requirements(
struct dc_state *context)
 {
struct dm_pp_display_configuration *pp_display_cfg = 
>pp_display_cfg;
+   int memory_type_multiplier = MEMORY_TYPE_MULTIPLIER_CZ;
+
+   if (dc->bw_vbios && dc->bw_vbios->memory_type == bw_def_hbm)
+   memory_type_multiplier = MEMORY_TYPE_HBM;
 
pp_display_cfg->all_displays_in_sync =
context->bw_ctx.bw.dce.all_displays_in_sync;
@@ -186,8 +190,18 @@ void dce11_pplib_apply_display_requirements(
pp_display_cfg->cpu_pstate_separation_time =
context->bw_ctx.bw.dce.blackout_recovery_time_us;
 
-   pp_display_cfg->min_memory_clock_khz = context->bw_ctx.bw.dce.yclk_khz
-   / MEMORY_TYPE_MULTIPLIER_CZ;
+   /*
+* TODO: determine whether the bandwidth has reached memory's limitation
+* , then change minimum memory clock based on real-time bandwidth
+* limitation.
+*/
+   if (ASICREV_IS_VEGA20_P(dc->ctx->asic_id.hw_internal_rev) && 
(context->stream_count >= 2)) {
+   pp_display_cfg->min_memory_clock_khz = 
max(pp_display_cfg->min_memory_clock_khz,
+   (uint32_t) (dc->bw_vbios->high_yclk.value / 
memory_type_multiplier / 1));
+   } else {
+   pp_display_cfg->min_memory_clock_khz = 
context->bw_ctx.bw.dce.yclk_khz
+   / memory_type_multiplier;
+   }
 
pp_display_cfg->min_engine_clock_khz = determine_sclk_from_bounding_box(
dc,
-- 
2.22.0

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[PATCH 23/25] drm/amd/display: fix use of uninitialized variable

[sunpeng.li]

From: Martin Leung 

tg_inst may be used uninitialized, so initialize it to 0.

Signed-off-by: Martin Leung 
Reviewed-by: Jaehyun Chung 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c  | 2 +-
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index cadb255826be..b52c457d209e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -971,7 +971,7 @@ bool dc_validate_seamless_boot_timing(const struct dc *dc,
 {
struct timing_generator *tg;
struct dc_link *link = sink->link;
-   unsigned int enc_inst, tg_inst, i;
+   unsigned int i, enc_inst, tg_inst = 0;
 
// Seamless port only support single DP and EDP so far
if (sink->sink_signal != SIGNAL_TYPE_DISPLAY_PORT &&
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index af85d6cf4427..23313c8808b3 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1845,7 +1845,7 @@ static int acquire_resource_from_hw_enabled_state(
struct dc_stream_state *stream)
 {
struct dc_link *link = stream->link;
-   unsigned int inst, tg_inst, i;
+   unsigned int i, inst, tg_inst = 0;
 
/* Check for enabled DIG to identify enabled display */
if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
-- 
2.22.0

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[PATCH 22/25] drm/amd/display: 3.4.51.1

[sunpeng.li]

From: Aric Cyr 

Signed-off-by: Aric Cyr 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 7c19ac71b424..3ecc42987b05 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -39,7 +39,7 @@
 #include "inc/hw/dmcu.h"
 #include "dml/display_mode_lib.h"
 
-#define DC_VER "3.2.51"
+#define DC_VER "3.2.51.1"
 
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
-- 
2.22.0

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[PATCH 12/25] drm/amd/display: Separate hardware initialization from creation

[sunpeng.li]

From: Julian Parkin 

[Why]
Separating the hardware initialization from the creation of the
dc structures gives greater flexibility to the dm to override
options for debugging.

[How]
Move the hardware initialization call to a new function,
dc_hardware_init. No functional change is intended.

Signed-off-by: Julian Parkin 
Reviewed-by: Tony Cheng 
Acked-by: Leo Li 
Acked-by: Nicholas Kazlauskas 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++
 drivers/gpu/drm/amd/display/dc/core/dc.c  | 8 +---
 drivers/gpu/drm/amd/display/dc/dc.h   | 2 ++
 3 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index f9c13dccfc03..c7871ddb5df4 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -711,6 +711,8 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
goto error;
}
 
+   dc_hardware_init(adev->dm.dc);
+
adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
if (!adev->dm.freesync_module) {
DRM_ERROR(
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 175275560e75..0d7ef89b17a4 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -787,9 +787,6 @@ struct dc *dc_create(const struct dc_init_data *init_params)
if (false == construct(dc, init_params))
goto construct_fail;
 
-   /*TODO: separate HW and SW initialization*/
-   dc->hwss.init_hw(dc);
-
full_pipe_count = dc->res_pool->pipe_count;
if (dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE)
full_pipe_count--;
@@ -822,6 +819,11 @@ struct dc *dc_create(const struct dc_init_data 
*init_params)
return NULL;
 }
 
+void dc_hardware_init(struct dc *dc)
+{
+   dc->hwss.init_hw(dc);
+}
+
 void dc_init_callbacks(struct dc *dc,
const struct dc_callback_init *init_params)
 {
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index d21e8fc0179e..30ef31a788f8 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -556,6 +556,8 @@ struct dc_callback_init {
 };
 
 struct dc *dc_create(const struct dc_init_data *init_params);
+void dc_hardware_init(struct dc *dc);
+
 int dc_get_vmid_use_vector(struct dc *dc);
 #ifdef CONFIG_DRM_AMD_DC_DCN2_0
 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config 
*va_config, int vmid);
-- 
2.22.0

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[PATCH 14/25] drm/amd/display: Revert fixup DPP programming sequence

[sunpeng.li]

From: Wesley Chalmers 

[WHY]
This change was made because DTO programming was double-buffered, which
is itself an issue. After deactivating the DTO double buffer, this
change becomes unnecessary.

This reverts commit 79a0feda4306a2e46872fffd1e5507b8e1785244

Signed-off-by: Wesley Chalmers 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Anthony Koo 
Acked-by: Leo Li 
---
 .../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c  | 111 ++
 drivers/gpu/drm/amd/display/dc/core/dc.c  |   3 -
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c |   3 +-
 .../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c |  31 +
 .../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h |   2 +-
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c|   3 +-
 .../drm/amd/display/dc/dcn20/dcn20_resource.c |   2 +-
 .../gpu/drm/amd/display/dc/inc/core_types.h   |   1 +
 .../amd/display/dc/inc/hw/clk_mgr_internal.h  |  10 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h  |   3 +-
 10 files changed, 48 insertions(+), 121 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
index f1df32664414..559e16983f91 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
@@ -104,6 +104,7 @@ void dcn20_update_clocks_update_dpp_dto(struct 
clk_mgr_internal *clk_mgr,
 {
int i;
 
+   clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;
for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
int dpp_inst, dppclk_khz;
 
@@ -113,75 +114,28 @@ void dcn20_update_clocks_update_dpp_dto(struct 
clk_mgr_internal *clk_mgr,
dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
dppclk_khz = 
context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
clk_mgr->dccg->funcs->update_dpp_dto(
-   clk_mgr->dccg, dpp_inst, dppclk_khz, false);
+   clk_mgr->dccg, dpp_inst, dppclk_khz);
}
 }
 
-static void update_global_dpp_clk(struct clk_mgr_internal *clk_mgr, unsigned 
int khz)
+void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr)
 {
int dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
-   * clk_mgr->dentist_vco_freq_khz / khz;
-
-   uint32_t dppclk_wdivider = dentist_get_did_from_divider(dpp_divider);
-
-   REG_UPDATE(DENTIST_DISPCLK_CNTL,
-   DENTIST_DPPCLK_WDIVIDER, dppclk_wdivider);
-   REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, 1, 5, 100);
-}
-
-static void update_display_clk(struct clk_mgr_internal *clk_mgr, unsigned int 
khz)
-{
+   * clk_mgr->dentist_vco_freq_khz / 
clk_mgr->base.clks.dppclk_khz;
int disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
-   * clk_mgr->dentist_vco_freq_khz / khz;
+   * clk_mgr->dentist_vco_freq_khz / 
clk_mgr->base.clks.dispclk_khz;
 
+   uint32_t dppclk_wdivider = dentist_get_did_from_divider(dpp_divider);
uint32_t dispclk_wdivider = dentist_get_did_from_divider(disp_divider);
 
REG_UPDATE(DENTIST_DISPCLK_CNTL,
DENTIST_DISPCLK_WDIVIDER, dispclk_wdivider);
+// REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 5, 100);
+   REG_UPDATE(DENTIST_DISPCLK_CNTL,
+   DENTIST_DPPCLK_WDIVIDER, dppclk_wdivider);
+   REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, 1, 5, 100);
 }
 
-static void request_voltage_and_program_disp_clk(struct clk_mgr *clk_mgr_base, 
unsigned int khz)
-{
-   struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
-   struct dc *dc = clk_mgr_base->ctx->dc;
-   struct pp_smu_funcs_nv *pp_smu = NULL;
-   bool going_up = clk_mgr->base.clks.dispclk_khz < khz;
-
-   if (dc->res_pool->pp_smu)
-   pp_smu = >res_pool->pp_smu->nv_funcs;
-
-   clk_mgr->base.clks.dispclk_khz = khz;
-
-   if (going_up && pp_smu && pp_smu->set_voltage_by_freq)
-   pp_smu->set_voltage_by_freq(_smu->pp_smu, PP_SMU_NV_DISPCLK, 
clk_mgr_base->clks.dispclk_khz / 1000);
-
-   update_display_clk(clk_mgr, khz);
-
-   if (!going_up && pp_smu && pp_smu->set_voltage_by_freq)
-   pp_smu->set_voltage_by_freq(_smu->pp_smu, PP_SMU_NV_DISPCLK, 
clk_mgr_base->clks.dispclk_khz / 1000);
-}
-
-static void request_voltage_and_program_global_dpp_clk(struct clk_mgr 
*clk_mgr_base, unsigned int khz)
-{
-   struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
-   struct dc *dc = clk_mgr_base->ctx->dc;
-   struct pp_smu_funcs_nv *pp_smu = NULL;
-   bool going_up = clk_mgr->base.clks.dppclk_khz < khz;
-
-   if (dc->res_pool->pp_smu)
-   pp_smu = >res_pool->pp_smu->nv_funcs;
-
-   clk_mgr->base.clks.dppclk_khz = khz;
-   clk_mgr->dccg->ref_dppclk = khz;
-
-

[PATCH 15/25] drm/amd/display: set minimum abm backlight level

[sunpeng.li]

From: Anthony Koo 

[Why]
A lot of the time, the backlight characteristic curve maps min backlight
to a non-zero value.
But there are cases where we want the curve to intersect at 0.
In this scenario even if OS never asks to set 0% backlight, the ABM
reduction can result in backlight being lowered close to 0.
This particularly can cause problems in some LED drivers, and in
general just looks like backlight is completely off.

[How]
Add default cap to disallow backlight from dropping below 1%
even after ABM reduction is applied.

Signed-off-by: Anthony Koo 
Reviewed-by: Aric Cyr 
Acked-by: Leo Li 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  5 ++
 .../amd/display/modules/power/power_helpers.c | 77 +++
 .../amd/display/modules/power/power_helpers.h |  1 +
 3 files changed, 49 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index c7871ddb5df4..7d62b4e86386 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -940,6 +940,11 @@ static int dm_late_init(void *handle)
params.backlight_lut_array_size = 16;
params.backlight_lut_array = linear_lut;
 
+   /* Min backlight level after ABM reduction,  Don't allow below 1%
+* 0x x 0.01 = 0x28F
+*/
+   params.min_abm_backlight = 0x28F;
+
/* todo will enable for navi10 */
if (adev->asic_type <= CHIP_RAVEN) {
ret = dmcu_load_iram(dmcu, params);
diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c 
b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
index cc6b794821d9..4e2f615c3566 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
+++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
@@ -115,7 +115,7 @@ static const struct abm_parameters * const abm_settings[] = 
{
 /* NOTE: iRAM is 256B in size */
 struct iram_table_v_2 {
/* flags  */
-   uint16_t flags; /* 0x00 
U16  */
+   uint16_t min_abm_backlight; /* 0x00 
U16  */
 
/* parameters for ABM2.0 algorithm */
uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL];  /* 0x02 
U0.8 */
@@ -140,10 +140,10 @@ struct iram_table_v_2 {
 
/* For reading PSR State directly from IRAM */
uint8_t psr_state;  /* 0xf0 
  */
-   uint8_t dmcu_mcp_interface_version; 
/* 0xf1   */
-   uint8_t dmcu_abm_feature_version;   
/* 0xf2   */
-   uint8_t dmcu_psr_feature_version;   
/* 0xf3   */
-   uint16_t dmcu_version;  
/* 0xf4   */
+   uint8_t dmcu_mcp_interface_version; /* 0xf1 
  */
+   uint8_t dmcu_abm_feature_version;   /* 0xf2 
  */
+   uint8_t dmcu_psr_feature_version;   /* 0xf3 
  */
+   uint16_t dmcu_version;  /* 0xf4 
  */
uint8_t dmcu_state; /* 0xf6 
  */
 
uint16_t blRampReduction;   /* 0xf7 
  */
@@ -164,42 +164,43 @@ struct iram_table_v_2_2 {
uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL];  /* 0x16 
U0.8 */
uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL];/* 0x2a 
U2.6 */
uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL];  /* 0x3e 
U2.6 */
-   uint8_t hybrid_factor[NUM_AGGR_LEVEL];  
/* 0x52 U0.8 */
-   uint8_t contrast_factor[NUM_AGGR_LEVEL];
/* 0x56 U0.8 */
-   uint8_t deviation_gain[NUM_AGGR_LEVEL]; 
/* 0x5a U0.8 */
-   uint8_t iir_curve[NUM_AMBI_LEVEL];  
/* 0x5e U0.8 */
-   uint8_t min_knee[NUM_AGGR_LEVEL];   
/* 0x63 U0.8 */
-   uint8_t max_knee[NUM_AGGR_LEVEL];   
/* 0x67 U0.8 */
-   uint8_t pad[21];
/* 0x6b U0.8 */
+   uint8_t hybrid_factor[NUM_AGGR_LEVEL];  /* 0x52 
U0.8 */
+   uint8_t contrast_factor[NUM_AGGR_LEVEL];/* 0x56 
U0.8 */
+   uint8_t deviation_gain[NUM_AGGR_LEVEL]; /* 0x5a 
U0.8 */
+   uint8_t iir_curve[NUM_AMBI_LEVEL];   

[PATCH 01/25] drm/amd/display: Fix HUBP secondary viewport programming

[sunpeng.li]

From: Ilya Bakoulin 

[Why]
Secondary viewport dimension/position registers are not programmed,
which can cause issues in some stereo configurations.

[How]
Add register definitions and register programming.

Signed-off-by: Ilya Bakoulin 
Reviewed-by: Charlene Liu 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c |  8 
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h | 12 
 2 files changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
index 001db49e4bb2..14d1be6c66e6 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
@@ -841,6 +841,14 @@ void min_set_viewport(
REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0,
  PRI_VIEWPORT_X_START_C, viewport_c->x,
  PRI_VIEWPORT_Y_START_C, viewport_c->y);
+
+   REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION_C, 0,
+ SEC_VIEWPORT_WIDTH_C, viewport_c->width,
+ SEC_VIEWPORT_HEIGHT_C, viewport_c->height);
+
+   REG_SET_2(DCSURF_SEC_VIEWPORT_START_C, 0,
+ SEC_VIEWPORT_X_START_C, viewport_c->x,
+ SEC_VIEWPORT_Y_START_C, viewport_c->y);
 }
 
 void hubp1_read_state_common(struct hubp *hubp)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
index f8e82ef24c09..ae70d9c0aa1d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
@@ -47,6 +47,8 @@
SRI(DCSURF_SEC_VIEWPORT_START, HUBP, id), \
SRI(DCSURF_PRI_VIEWPORT_DIMENSION_C, HUBP, id), \
SRI(DCSURF_PRI_VIEWPORT_START_C, HUBP, id), \
+   SRI(DCSURF_SEC_VIEWPORT_DIMENSION_C, HUBP, id), \
+   SRI(DCSURF_SEC_VIEWPORT_START_C, HUBP, id), \
SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
SRI(DCSURF_PRIMARY_SURFACE_ADDRESS, HUBPREQ, id),\
SRI(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
@@ -154,6 +156,8 @@
uint32_t DCSURF_SEC_VIEWPORT_START; \
uint32_t DCSURF_PRI_VIEWPORT_DIMENSION_C; \
uint32_t DCSURF_PRI_VIEWPORT_START_C; \
+   uint32_t DCSURF_SEC_VIEWPORT_DIMENSION_C; \
+   uint32_t DCSURF_SEC_VIEWPORT_START_C; \
uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; \
uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; \
uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH; \
@@ -287,6 +291,10 @@
HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_HEIGHT_C, 
mask_sh),\
HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_X_START_C, 
mask_sh),\
HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_Y_START_C, 
mask_sh),\
+   HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C, SEC_VIEWPORT_WIDTH_C, 
mask_sh),\
+   HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C, SEC_VIEWPORT_HEIGHT_C, 
mask_sh),\
+   HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START_C, SEC_VIEWPORT_X_START_C, 
mask_sh),\
+   HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START_C, SEC_VIEWPORT_Y_START_C, 
mask_sh),\
HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 
PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\
HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS, 
PRIMARY_SURFACE_ADDRESS, mask_sh),\
HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 
SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\
@@ -481,6 +489,10 @@
type PRI_VIEWPORT_HEIGHT_C; \
type PRI_VIEWPORT_X_START_C; \
type PRI_VIEWPORT_Y_START_C; \
+   type SEC_VIEWPORT_WIDTH_C; \
+   type SEC_VIEWPORT_HEIGHT_C; \
+   type SEC_VIEWPORT_X_START_C; \
+   type SEC_VIEWPORT_Y_START_C; \
type PRIMARY_SURFACE_ADDRESS_HIGH;\
type PRIMARY_SURFACE_ADDRESS;\
type SECONDARY_SURFACE_ADDRESS_HIGH;\
-- 
2.22.0

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[PATCH 10/25] drm/amd/display: Handle virtual signal type in disable_link()

[sunpeng.li]

From: Martin Tsai 

[Why]
The new implementation changed the behavior to allow process setMode
to DAL when DAL returns empty mode query for unplugged display.
This will trigger additional disable_link().
When unplug HDMI from MST dock, driver will update stream->signal to
"Virtual". disable_link() will call disable_output() if the signal type
is not DP and induce other displays on MST dock show black screen.

[How]
Don't need to process disable_output() if the signal type is virtual.

Signed-off-by: Martin Tsai 
Reviewed-by: Charlene Liu 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 1307b533a3f8..de07577085ce 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -2166,8 +2166,10 @@ static void disable_link(struct dc_link *link, enum 
signal_type signal)
dp_set_fec_ready(link, false);
}
 #endif
-   } else
-   link->link_enc->funcs->disable_output(link->link_enc, signal);
+   } else {
+   if (signal != SIGNAL_TYPE_VIRTUAL)
+   link->link_enc->funcs->disable_output(link->link_enc, 
signal);
+   }
 
if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
/* MST disable link only when no stream use the link */
-- 
2.22.0

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[PATCH 11/25] drm/amd/display: fix i2c wtire mot incorrect issue

[sunpeng.li]

From: Lewis Huang 

[Why]
I2C write command always send mot = true will cause sink state incorrect.

[How]
1. Remove default i2c write mot = true.
2. Deciding mot flag by is_end_of_payload flag.

Signed-off-by: Lewis Huang 
Reviewed-by: Charlene Liu 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
index f70137d67c82..588a07b525a0 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
@@ -523,7 +523,7 @@ bool dal_ddc_service_query_ddc_data(
 
if (write_size != 0) {
payload.write = true;
-   payload.mot = true;
+   payload.mot = false;
payload.length = write_size;
payload.data = write_buf;
 
@@ -592,7 +592,7 @@ bool dal_ddc_submit_aux_command(struct ddc_service *ddc,
current_payload.i2c_over_aux = payload->i2c_over_aux;
current_payload.length = is_end_of_payload ?
payload->length - retrieved : DEFAULT_AUX_MAX_DATA_SIZE;
-   current_payload.mot = payload->mot ? payload->mot : 
!is_end_of_payload;
+   current_payload.mot = !is_end_of_payload;
current_payload.reply = payload->reply;
current_payload.write = payload->write;
 
-- 
2.22.0

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[PATCH 13/25] drm/amd/display: Do not double-buffer DTO adjustments

[sunpeng.li]

From: Wesley Chalmers 

[WHY]
When changing DPP global ref clock, DTO adjustments must take effect
immediately, or else underflow may occur.
It appears the original decision to double-buffer DTO adjustments was made to
prevent underflows that occur when raising DPP ref clock (which is not
double-buffered), but that same decision causes similar issues when
lowering DPP global ref clock. The better solution is to order the
adjustments according to whether clocks are being raised or lowered.

Signed-off-by: Wesley Chalmers 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Anthony Koo 
Acked-by: Leo Li 
---
 .../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c | 21 ---
 1 file changed, 21 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c
index f9b99f8cfc31..313d3793005e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c
@@ -117,27 +117,6 @@ void dccg2_get_dccg_ref_freq(struct dccg *dccg,
 
 void dccg2_init(struct dccg *dccg)
 {
-   struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
-
-   // Fallthrough intentional to program all available dpp_dto's
-   switch (dccg_dcn->base.ctx->dc->res_pool->pipe_count) {
-   case 6:
-   REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_DB_EN[5], 1);
-   case 5:
-   REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_DB_EN[4], 1);
-   case 4:
-   REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_DB_EN[3], 1);
-   case 3:
-   REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_DB_EN[2], 1);
-   case 2:
-   REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_DB_EN[1], 1);
-   case 1:
-   REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_DB_EN[0], 1);
-   break;
-   default:
-   ASSERT(false);
-   break;
-   }
 }
 
 static const struct dccg_funcs dccg2_funcs = {
-- 
2.22.0

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[PATCH 07/25] drm/amd/display: Add debugfs entry to force YUV420 output

[sunpeng.li]

From: Stylon Wang 

[Why]
Even if YUV420 is available for video mode, YUV444 is still
automatically selected. This poses a problem for compliance tests.

[How]
Add a per-connector debugfs entry "force_yuv420_output" to force
selection of YUV420 mode.

Signed-off-by: Stylon Wang 
Reviewed-by: Nicholas Kazlauskas 
Acked-by: Leo Li 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  5 ++-
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |  1 +
 .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 31 +++
 3 files changed, 36 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index c1031121ee8a..f9c13dccfc03 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -3383,7 +3383,7 @@ static void fill_stream_properties_from_drm_display_mode(
 {
struct dc_crtc_timing *timing_out = >timing;
const struct drm_display_info *info = >display_info;
-
+   struct amdgpu_dm_connector *aconnector = 
to_amdgpu_dm_connector(connector);
memset(timing_out, 0, sizeof(struct dc_crtc_timing));
 
timing_out->h_border_left = 0;
@@ -3394,6 +3394,9 @@ static void fill_stream_properties_from_drm_display_mode(
if (drm_mode_is_420_only(info, mode_in)
&& stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
+   else if (drm_mode_is_420_also(info, mode_in)
+   && aconnector->force_yuv420_output)
+   timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
else if ((connector->display_info.color_formats & 
DRM_COLOR_FORMAT_YCRCB444)
&& stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index cbd6608f58e6..17a35b504552 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -284,6 +284,7 @@ struct amdgpu_dm_connector {
uint32_t debugfs_dpcd_address;
uint32_t debugfs_dpcd_size;
 #endif
+   bool force_yuv420_output;
 };
 
 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, 
base)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 97bbb934cc04..b99be385eea3 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -940,6 +940,33 @@ static const struct {
{"aux_dpcd_data", _dpcd_data_debugfs_fops}
 };
 
+/*
+ * Force YUV420 output if available from the given mode
+ */
+static int force_yuv420_output_set(void *data, u64 val)
+{
+   struct amdgpu_dm_connector *connector = data;
+
+   connector->force_yuv420_output = (bool)val;
+
+   return 0;
+}
+
+/*
+ * Check if YUV420 is forced when available from the given mode
+ */
+static int force_yuv420_output_get(void *data, u64 *val)
+{
+   struct amdgpu_dm_connector *connector = data;
+
+   *val = connector->force_yuv420_output;
+
+   return 0;
+}
+
+DEFINE_DEBUGFS_ATTRIBUTE(force_yuv420_output_fops, force_yuv420_output_get,
+force_yuv420_output_set, "%llu\n");
+
 void connector_debugfs_init(struct amdgpu_dm_connector *connector)
 {
int i;
@@ -953,6 +980,10 @@ void connector_debugfs_init(struct amdgpu_dm_connector 
*connector)
dp_debugfs_entries[i].fops);
}
}
+
+   debugfs_create_file_unsafe("force_yuv420_output", 0644, dir, connector,
+  _yuv420_output_fops);
+
 }
 
 /*
-- 
2.22.0

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[PATCH 16/25] drm/amd/display: Set number of pipes to 1 if the second pipe was disabled

[sunpeng.li]

From: Nikola Cornij 

[why]
Some ODM-related register settings are inconsistently updated by VBIOS, causing
the state in DC to be invalid, which would then end up crashing in certain
use-cases (such as disable/enable device).

[how]
Check the enabled status of the second pipe when determining the number of
OPTC sources. If the second pipe is disabled, set the number of sources to 1
regardless of other settings (that may not be updated correctly).

Signed-off-by: Nikola Cornij 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
index 2137e2be2140..dda90995ba93 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
@@ -287,6 +287,10 @@ void optc2_get_optc_source(struct timing_generator *optc,
*num_of_src_opp = 2;
else
*num_of_src_opp = 1;
+
+   /* Work around VBIOS not updating OPTC_NUM_OF_INPUT_SEGMENT */
+   if (*src_opp_id_1 == 0xf)
+   *num_of_src_opp = 1;
 }
 
 void optc2_set_dwb_source(struct timing_generator *optc,
-- 
2.22.0

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[PATCH 09/25] drm/amd/display: fix global sync param extraction indexing

[sunpeng.li]

From: Dmytro Laktyushkin 

dcn20_calculate_dlg_params was incorrectly indexing pipe src and
dst structs when extracting global sync params.

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Jaehyun Chung 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 9aceb159bef5..49a147661cd4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -2638,8 +2638,8 @@ void dcn20_calculate_dlg_params(
continue;
 
if (!visited[pipe_idx]) {
-   display_pipe_source_params_st *src = 
[pipe_idx_unsplit].pipe.src;
-   display_pipe_dest_params_st *dst = 
[pipe_idx_unsplit].pipe.dest;
+   display_pipe_source_params_st *src = 
[pipe_idx].pipe.src;
+   display_pipe_dest_params_st *dst = 
[pipe_idx].pipe.dest;
 
dst->vstartup_start = 
context->bw_ctx.dml.vba.VStartup[pipe_idx_unsplit];
dst->vupdate_offset = 
context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx_unsplit];
-- 
2.22.0

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[PATCH 04/25] drm/amd/display: Rebuild mapped resources after pipe split

[sunpeng.li]

From: Mikita Lipski 

[why]
The issue is specific for linux, as on timings such as 8K@60
or 4K@144 DSC should be working in combination with ODM Combine
in order to ensure that we can run those timings. The validation
for those timings was passing, but when pipe split was happening
second pipe wasn't being programmed.

[how]
Rebuild mapped resources if we split stream for ODM.

Signed-off-by: Mikita Lipski 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 62e9a9826c97..9aceb159bef5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -2466,6 +2466,7 @@ bool dcn20_fast_validate_bw(
>res_ctx, 
dc->res_pool,
pipe, hsplit_pipe))
goto validate_fail;
+   dcn20_build_mapped_resource(dc, 
context, pipe->stream);
} else
dcn20_split_stream_for_mpc(
>res_ctx, dc->res_pool,
-- 
2.22.0

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[PATCH 03/25] drm/amd/display: 3.2.50

[sunpeng.li]

From: Aric Cyr 

Signed-off-by: Aric Cyr 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 3b848d4aca8c..d21e8fc0179e 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -39,7 +39,7 @@
 #include "inc/hw/dmcu.h"
 #include "dml/display_mode_lib.h"
 
-#define DC_VER "3.2.49"
+#define DC_VER "3.2.50"
 
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
-- 
2.22.0

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[PATCH 02/25] drm/amd/display: define parameters for abm 2.3

[sunpeng.li]

From: Josip Pavic 

[Why]
Current configuration 0 is just a placeholder, and final parameters needed.
Also, configuration 1 is expected to emulate ABM 2.1 but is too aggressive.

[How]
Redefine configuration 0 with the finalized parameters, and increase the
contrast gain of configuration 1 so that it properly emulates ABM 2.1.

Signed-off-by: Josip Pavic 
Reviewed-by: Anthony Koo 
Acked-by: Leo Li 
---
 .../amd/display/modules/power/power_helpers.c| 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c 
b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
index 05e2be856037..cc6b794821d9 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
+++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
@@ -80,18 +80,18 @@ struct abm_parameters {
 
 static const struct abm_parameters abm_settings_config0[abm_defines_max_level] 
= {
 //  min_red  max_red  bright_pos  dark_pos  brightness_gain  contrast  
deviation  min_knee  max_knee
-   {0xff,   0xbf,0x20,   0x00, 0xff,0x99, 
0xb3,  0x40, 0xE0},
-   {0xff,   0x85,0x20,   0x00, 0xff,0x90, 
0xa8,  0x40, 0xE0},
-   {0xff,   0x40,0x20,   0x00, 0xff,0x90, 
0x68,  0x40, 0xE0},
-   {0x82,   0x4d,0x20,   0x00, 0x00,0x90, 
0xb3,  0x70, 0x70},
+   {0xff,   0xbf,0x20,   0x00, 0xff,0x99, 
0xb3,  0x40, 0xe0},
+   {0xde,   0x85,0x20,   0x00, 0xff,0x90, 
0xa8,  0x40, 0xdf},
+   {0xb0,   0x50,0x20,   0x00, 0xc0,0x88, 
0x78,  0x70, 0xa0},
+   {0x82,   0x40,0x20,   0x00, 0x00,0xff, 
0xb3,  0x70, 0x70},
 };
 
 static const struct abm_parameters abm_settings_config1[abm_defines_max_level] 
= {
 //  min_red  max_red  bright_pos  dark_pos  brightness_gain  contrast  
deviation  min_knee  max_knee
-   {0xf0,   0xd9,0x20,   0x00, 0x00,0xa8, 
0xb3,  0x70, 0x70},
-   {0xcd,   0xa5,0x20,   0x00, 0x00,0xa8, 
0xb3,  0x70, 0x70},
-   {0x99,   0x65,0x20,   0x00, 0x00,0xa8, 
0xb3,  0x70, 0x70},
-   {0x82,   0x4d,0x20,   0x00, 0x00,0xa8, 
0xb3,  0x70, 0x70},
+   {0xf0,   0xd9,0x20,   0x00, 0x00,0xff, 
0xb3,  0x70, 0x70},
+   {0xcd,   0xa5,0x20,   0x00, 0x00,0xff, 
0xb3,  0x70, 0x70},
+   {0x99,   0x65,0x20,   0x00, 0x00,0xff, 
0xb3,  0x70, 0x70},
+   {0x82,   0x4d,0x20,   0x00, 0x00,0xff, 
0xb3,  0x70, 0x70},
 };
 
 static const struct abm_parameters * const abm_settings[] = {
-- 
2.22.0

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[PATCH 06/25] drm/amd/display: add additional flag consideration for surface update

[sunpeng.li]

From: Dmytro Laktyushkin 

Surface dchub/dpp update would not trigger if a stream update was the
only cause. This change now allows stream flags to trigger this update.

Signed-off-by: Dmytro Laktyushkin 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 81740e0c4c4e..faaf8841c61e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1375,7 +1375,7 @@ static void dcn20_program_pipe(
if (pipe_ctx->update_flags.bits.enable)
dcn20_enable_plane(dc, pipe_ctx, context);
 
-   if (pipe_ctx->update_flags.raw || 
pipe_ctx->plane_state->update_flags.raw)
+   if (pipe_ctx->update_flags.raw || 
pipe_ctx->plane_state->update_flags.raw || pipe_ctx->stream->update_flags.raw)
dcn20_update_dchubp_dpp(dc, pipe_ctx, context);
 
if (pipe_ctx->update_flags.bits.enable
-- 
2.22.0

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[PATCH 48/49] drm/amd/display: Enable MPO with pre-blend color processing (RGB)

[sunpeng.li]

From: Michael Strauss 

[Why]
DCN10 performs color processing before MPC combination, causes color
shift in RGB colorspaces when positive brightness offset is applied
However, YCbCr is still unfixed and remains disabled

[How]
Add layerIndex to dc_plane_state and dc_plane_info structs
Re-enable MPO when brightness is adjusted and colorspace is not YCbCr
Set rear plane's brightness offset to 0 when front plane visible

Signed-off-by: Michael Strauss 
Reviewed-by: Anthony Koo 
Acked-by: Leo Li 
Acked-by: Nicholas Kazlauskas 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  3 ++
 drivers/gpu/drm/amd/display/dc/core/dc.c  |  2 +
 drivers/gpu/drm/amd/display/dc/dc.h   |  2 +
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 51 ++-
 4 files changed, 56 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 2f933f89aaef..911fe78b47c1 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -3077,6 +3077,8 @@ fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
plane_info->visible = true;
plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
 
+   plane_info->layer_index = 0;
+
ret = fill_plane_color_attributes(plane_state, plane_info->format,
  _info->color_space);
if (ret)
@@ -3142,6 +3144,7 @@ static int fill_dc_plane_attributes(struct amdgpu_device 
*adev,
dc_plane_state->global_alpha = plane_info.global_alpha;
dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
dc_plane_state->dcc = plane_info.dcc;
+   dc_plane_state->layer_index = plane_info.layer_index; // Always returns 0
 
/*
 * Always set input transfer function, since plane state is refreshed
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 7408df05d3e5..0b624db17e63 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1689,6 +1689,8 @@ static void copy_surface_update_to_plane(
srf_update->plane_info->dcc;
surface->sdr_white_level =
srf_update->plane_info->sdr_white_level;
+   surface->layer_index =
+   srf_update->plane_info->layer_index;
}
 
if (srf_update->gamma &&
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 87be02a8a958..3ef269f82478 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -750,6 +750,7 @@ struct dc_plane_state {
bool visible;
bool flip_immediate;
bool horizontal_mirror;
+   int layer_index;
 
union surface_update_flags update_flags;
/* private to DC core */
@@ -779,6 +780,7 @@ struct dc_plane_info {
bool global_alpha;
int  global_alpha_value;
bool input_csc_enabled;
+   int layer_index;
 };
 
 struct dc_scaling_info {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 0045b698fb68..9fe2fff67dc5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1904,6 +1904,36 @@ static void dcn10_program_gamut_remap(struct pipe_ctx 
*pipe_ctx)

pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp, 
);
 }
 
+
+static bool dcn10_is_rear_mpo_fix_required(struct pipe_ctx *pipe_ctx, enum 
dc_color_space colorspace)
+{
+   if (pipe_ctx->plane_state && pipe_ctx->plane_state->layer_index > 0 && 
is_rgb_cspace(colorspace)) {
+   if (pipe_ctx->top_pipe) {
+   struct pipe_ctx *top = pipe_ctx->top_pipe;
+
+   while (top->top_pipe)
+   top = top->top_pipe; // Traverse to top pipe_ctx
+   if (top->plane_state && top->plane_state->layer_index 
== 0)
+   return true; // Front MPO plane not hidden
+   }
+   }
+   return false;
+}
+
+static void dcn10_set_csc_adjustment_rgb_mpo_fix(struct pipe_ctx *pipe_ctx, 
uint16_t *matrix)
+{
+   // Override rear plane RGB bias to fix MPO brightness
+   uint16_t rgb_bias = matrix[3];
+
+   matrix[3] = 0;
+   matrix[7] = 0;
+   matrix[11] = 0;
+   
pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, 
matrix);
+   matrix[3] = rgb_bias;
+   matrix[7] = rgb_bias;
+   matrix[11] = rgb_bias;
+}
+
 static void dcn10_program_output_csc(struct dc *dc,
struct pipe_ctx *pipe_ctx,
enum dc_color_space colorspace,
@@ -1911,8 +1941,25 @@ static void 

[PATCH 37/49] drm/amd/display: Register VUPDATE_NO_LOCK interrupts for DCN2

[sunpeng.li]

From: Nicholas Kazlauskas 

[Why]
These are needed to send back DRM vblank events in the case where VRR
is on. Without the interrupt enabled we're deferring the events into the
vblank queue and userspace is left waiting forever to get back the
events they need.

Found using igt@kms_vrr - the test fails immediately due to vblank
timeout.

[How]
Register them the same way we're handling it for DCN1.

This fixes igt@kms_vrr for DCN2.

Signed-off-by: Nicholas Kazlauskas 
Reviewed-by: David Francis 
Acked-by: Leo Li 
---
 .../display/dc/irq/dcn20/irq_service_dcn20.c  | 28 ---
 1 file changed, 18 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c 
b/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
index 65866d620759..1fdbc9e5f7bc 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
@@ -165,6 +165,11 @@ static const struct irq_source_info_funcs 
vblank_irq_info_funcs = {
.ack = NULL
 };
 
+static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
+   .set = NULL,
+   .ack = NULL
+};
+
 #undef BASE_INNER
 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
 
@@ -219,12 +224,15 @@ static const struct irq_source_info_funcs 
vblank_irq_info_funcs = {
.funcs = _irq_info_funcs\
}
 
-#define vupdate_int_entry(reg_num)\
+/* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
+ * of DCE's DC_IRQ_SOURCE_VUPDATEx.
+ */
+#define vupdate_no_lock_int_entry(reg_num)\
[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
IRQ_REG_ENTRY(OTG, reg_num,\
-   OTG_GLOBAL_SYNC_STATUS, VUPDATE_INT_EN,\
-   OTG_GLOBAL_SYNC_STATUS, VUPDATE_EVENT_CLEAR),\
-   .funcs = _irq_info_funcs\
+   OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
+   OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
+   .funcs = _no_lock_irq_info_funcs\
}
 
 #define vblank_int_entry(reg_num)\
@@ -331,12 +339,12 @@ irq_source_info_dcn20[DAL_IRQ_SOURCES_NUMBER] = {
dc_underflow_int_entry(6),
[DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
[DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
-   vupdate_int_entry(0),
-   vupdate_int_entry(1),
-   vupdate_int_entry(2),
-   vupdate_int_entry(3),
-   vupdate_int_entry(4),
-   vupdate_int_entry(5),
+   vupdate_no_lock_int_entry(0),
+   vupdate_no_lock_int_entry(1),
+   vupdate_no_lock_int_entry(2),
+   vupdate_no_lock_int_entry(3),
+   vupdate_no_lock_int_entry(4),
+   vupdate_no_lock_int_entry(5),
vblank_int_entry(0),
vblank_int_entry(1),
vblank_int_entry(2),
-- 
2.22.0

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[PATCH 34/49] drm/amd/display: Check if set_blank_data_double_buffer exists before call

[sunpeng.li]

From: Vitaly Prosyak 

Not all ASIC types have this function implemented - check before
calling.

Signed-off-by: Vitaly Prosyak 
Reviewed-by: Julian Parkin 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index b08632ba6211..0a5c75e737a5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -720,7 +720,8 @@ static void false_optc_underflow_wa(
dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, 
old_pipe_ctx);
}
 
-   tg->funcs->set_blank_data_double_buffer(tg, true);
+   if (tg->funcs->set_blank_data_double_buffer)
+   tg->funcs->set_blank_data_double_buffer(tg, true);
 
if (tg->funcs->is_optc_underflow_occurred(tg) && !underflow)
tg->funcs->clear_optc_underflow(tg);
-- 
2.22.0

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[PATCH 36/49] drm/amd/display: wake up ogam mem pwr before programming ocsc

[sunpeng.li]

From: Charlene Liu 

[Description]
OGAM_MEM_PWR could stay in light up when driver woke up to update gamma.
either disable MEM_LOW power feature or set to OGAM_bypass could make 
artificial color distortion goes away.
Easy reproduce after LOW_MEM Power feature enables and resume from S3.

Signed-off-by: Charlene Liu 
Reviewed-by: Julian Parkin 
Acked-by: Leo Li 
---
 .../gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c  | 16 
 .../gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h  | 19 +++
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c|  6 ++
 .../gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c  |  5 +++--
 .../gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h  |  6 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h   |  4 
 6 files changed, 49 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
index 9bc5dd23d297..db311574f42f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
@@ -72,6 +72,21 @@ void dpp20_read_state(struct dpp *dpp_base,
}
 }
 
+void dpp2_power_on_obuf(
+   struct dpp *dpp_base,
+   bool power_on)
+{
+   struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
+
+   REG_UPDATE(CM_MEM_PWR_CTRL, SHARED_MEM_PWR_DIS, power_on == true ? 1:0);
+
+   REG_UPDATE(OBUF_MEM_PWR_CTRL,
+   OBUF_MEM_PWR_FORCE, power_on == true ? 0:1);
+
+   REG_UPDATE(DSCL_MEM_PWR_CTRL,
+   LUT_MEM_PWR_FORCE, power_on == true ? 0:1);
+}
+
 void dpp2_dummy_program_input_lut(
struct dpp *dpp_base,
const struct dc_gamma *gamma)
@@ -227,6 +242,7 @@ static void dpp2_cnv_setup (
CUR0_ENABLE, 0);
 
}
+   dpp2_power_on_obuf(dpp_base, true);
 
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h
index 59b67ed57c19..1f5d99a6d240 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h
@@ -162,7 +162,9 @@
SRI(COLOR_KEYER_GREEN, CNVC_CFG, id), \
SRI(COLOR_KEYER_BLUE, CNVC_CFG, id), \
SRI(CM_SHAPER_LUT_DATA, CM, id), \
-   SRI(CURSOR_CONTROL, CURSOR0_, id)
+   SRI(CURSOR_CONTROL, CURSOR0_, id),\
+   SRI(OBUF_MEM_PWR_CTRL, DSCL, id),\
+   SRI(DSCL_MEM_PWR_CTRL, DSCL, id)
 
 #define TF_REG_LIST_SH_MASK_DCN20(mask_sh)\
TF_REG_LIST_SH_MASK_DCN(mask_sh), \
@@ -554,7 +556,9 @@
TF_SF(CNVC_CFG0_COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_HIGH, mask_sh), \
TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_PIX_INV_MODE, mask_sh), \
TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_PIXEL_ALPHA_MOD_EN, mask_sh), \
-   TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ROM_EN, mask_sh)
+   TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ROM_EN, mask_sh),\
+   TF_SF(DSCL0_OBUF_MEM_PWR_CTRL, OBUF_MEM_PWR_FORCE, mask_sh),\
+   TF_SF(DSCL0_DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, mask_sh)
 
 #define TF_REG_FIELD_LIST_DCN2_0(type) \
TF_REG_FIELD_LIST(type) \
@@ -585,7 +589,9 @@
type COLOR_KEYER_BLUE_HIGH; \
type CUR0_PIX_INV_MODE; \
type CUR0_PIXEL_ALPHA_MOD_EN; \
-   type CUR0_ROM_EN
+   type CUR0_ROM_EN;\
+   type OBUF_MEM_PWR_FORCE;\
+   type LUT_MEM_PWR_FORCE
 
 struct dcn2_dpp_shift {
TF_REG_FIELD_LIST_DCN2_0(uint8_t);
@@ -609,7 +615,9 @@ struct dcn2_dpp_mask {
uint32_t COLOR_KEYER_ALPHA; \
uint32_t COLOR_KEYER_RED; \
uint32_t COLOR_KEYER_GREEN; \
-   uint32_t COLOR_KEYER_BLUE
+   uint32_t COLOR_KEYER_BLUE; \
+   uint32_t OBUF_MEM_PWR_CTRL;\
+   uint32_t DSCL_MEM_PWR_CTRL
 
 struct dcn2_dpp_registers {
DPP_DCN2_REG_VARIABLE_LIST;
@@ -695,4 +703,7 @@ bool dpp2_construct(struct dcn20_dpp *dpp2,
const struct dcn2_dpp_shift *tf_shift,
const struct dcn2_dpp_mask *tf_mask);
 
+void dpp2_power_on_obuf(
+   struct dpp *dpp_base,
+   bool power_on);
 #endif /* __DC_HWSS_DCN20_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 5904d4d329df..4e9ac051d3d8 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -631,6 +631,10 @@ void dcn20_program_output_csc(struct dc *dc,
 {
struct mpc *mpc = dc->res_pool->mpc;
enum mpc_output_csc_mode ocsc_mode = MPC_OUTPUT_CSC_COEF_A;
+   int mpcc_id = pipe_ctx->plane_res.hubp->inst;
+
+   if (mpc->funcs->power_on_mpc_mem_pwr)
+   mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true);
 
if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
if (mpc->funcs->set_output_csc != NULL)
@@ -660,6 +664,8 @@ bool dcn20_set_output_transfer_func(struct pipe_ctx 
*pipe_ctx,
 * if programming for all pipes is 

[PATCH 39/49] drm/amd/display: Remove redundant definition of dwb_source enums

[sunpeng.li]

From: Julian Parkin 

There are repeated (but guarded) definitions of dwb_src enums. There are
also unused entires. Clean them up.

Signed-off-by: Julian Parkin 
Reviewed-by: Charlene Liu 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h | 12 
 1 file changed, 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h 
b/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
index a3409294ae0c..ff1a07b35c85 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
@@ -45,22 +45,10 @@ enum dwb_source {
dwb_src_scl = 0,/* for DCE7x/9x, DCN won't support. */
dwb_src_blnd,   /* for DCE7x/9x */
dwb_src_fmt,/* for DCE7x/9x */
-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
dwb_src_otg0 = 0x100,   /* for DCN1.x/DCN2.x, register: 
mmDWB_SOURCE_SELECT */
dwb_src_otg1,   /* for DCN1.x/DCN2.x */
dwb_src_otg2,   /* for DCN1.x/DCN2.x */
dwb_src_otg3,   /* for DCN1.x/DCN2.x */
-#else
-   dwb_src_otg0 = 0x100,   /* for DCN1.x, register: mmDWB_SOURCE_SELECT */
-   dwb_src_otg1,   /* for DCN1.x */
-   dwb_src_otg2,   /* for DCN1.x */
-   dwb_src_otg3,   /* for DCN1.x */
-#endif
-   dwb_src_mpc0 = 0x200,   /* for DCN2, register: mmMPC_DWB0_MUX, 
mmMPC_DWB1_MUX, mmMPC_DWB2_MUX */
-   dwb_src_mpc1,   /* for DCN2 */
-   dwb_src_mpc2,   /* for DCN2 */
-   dwb_src_mpc3,   /* for DCN2 */
-   dwb_src_mpc4,   /* for DCN2 */
 };
 
 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
-- 
2.22.0

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[PATCH 42/49] drm/amd/display: 3.2.45

[sunpeng.li]

From: Anthony Koo 

Signed-off-by: Anthony Koo 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 5e53a9eabb34..7bc16eaf8b01 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -39,7 +39,7 @@
 #include "inc/hw/dmcu.h"
 #include "dml/display_mode_lib.h"
 
-#define DC_VER "3.2.44"
+#define DC_VER "3.2.45"
 
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
-- 
2.22.0

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