subject:"\[PATCH\] amd\/include\: Move register declarations from display to include\/asic

Re: [PATCH] amd/include: Move register declarations from display to include/asic_reg

2018-05-31 Thread Harry Wentland



On 2018-05-31 09:19 AM, David Francis wrote:
> A few register addresses were declared in
> amd/display/dc/dce*/dce*_resource.c.
> 
> They have been consolidated with the appropriate
> master list of registers in
> amd/include/asic_reg/dce/...
> 
> This will make them accessible to external tools that
> need direct asic register access
> 
> Signed-off-by: David Francis 
> ---
>  .../amd/display/dc/dce100/dce100_resource.c   | 35 ---
>  .../amd/display/dc/dce110/dce110_resource.c   | 35 ---
>  .../amd/display/dc/dce112/dce112_resource.c   | 35 ---
>  .../drm/amd/display/dc/dce80/dce80_resource.c | 34 --
>  .../drm/amd/include/asic_reg/dce/dce_10_0_d.h | 18 ++
>  .../drm/amd/include/asic_reg/dce/dce_11_0_d.h | 10 ++
>  .../drm/amd/include/asic_reg/dce/dce_11_2_d.h | 10 ++
>  .../drm/amd/include/asic_reg/dce/dce_8_0_d.h  | 15 
>  8 files changed, 53 insertions(+), 139 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 
> b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
> index 38ec0d609297..7615668a78e9 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
> @@ -59,46 +59,11 @@
>  #include "gmc/gmc_8_2_sh_mask.h"
>  #endif
>  
> -#ifndef mmDP_DPHY_INTERNAL_CTRL
> - #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
> - #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
> - #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7
> - #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7
> - #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7
> - #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7
> - #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7
> - #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7
> - #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7
> - #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
> -#endif
> -
>  #ifndef mmBIOS_SCRATCH_2
>   #define mmBIOS_SCRATCH_2 0x05CB
>   #define mmBIOS_SCRATCH_6 0x05CF
>  #endif
>  
> -#ifndef mmDP_DPHY_BS_SR_SWAP_CNTL
> - #define mmDP_DPHY_BS_SR_SWAP_CNTL   0x4ADC
> - #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL   0x4ADC
> - #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL   0x4BDC
> - #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL   0x4CDC
> - #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL   0x4DDC
> - #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL   0x4EDC
> - #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL   0x4FDC
> - #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL   0x54DC
> -#endif
> -
> -#ifndef mmDP_DPHY_FAST_TRAINING
> - #define mmDP_DPHY_FAST_TRAINING 0x4ABC
> - #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC
> - #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC
> - #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC
> - #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC
> - #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC
> - #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC
> - #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC
> -#endif
> -
>  static const struct dce110_timing_generator_offsets dce100_tg_offsets[] = {
>   {
>   .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
> diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 
> b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
> index ee33786bdef6..648187a28671 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
> @@ -68,46 +68,11 @@
>  #include "gmc/gmc_8_2_sh_mask.h"
>  #endif
>  
> -#ifndef mmDP_DPHY_INTERNAL_CTRL
> - #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
> - #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
> - #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7
> - #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7
> - #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7
> - #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7
> - #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7
> - #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7
> - #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7
> - #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
> -#endif
> -
>  #ifndef mmBIOS_SCRATCH_2
>   #define mmBIOS_SCRATCH_2 0x05CB
>   #define mmBIOS_SCRATCH_6 0x05CF
>  #endif
>  
> -#ifndef mmDP_DPHY_BS_SR_SWAP_CNTL
> - #define mmDP_DPHY_BS_SR_SWAP_CNTL   0x4ADC
> - #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL   0x4ADC
> - #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL   0x4BDC
> - #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL   0x4CDC
> - #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL   0x4DDC
> - #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL   0x4EDC
> - #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL

[PATCH] amd/include: Move register declarations from display to include/asic_reg

2018-05-31 Thread David Francis

A few register addresses were declared in
amd/display/dc/dce*/dce*_resource.c.

They have been consolidated with the appropriate
master list of registers in
amd/include/asic_reg/dce/...

This will make them accessible to external tools that
need direct asic register access

Signed-off-by: David Francis 
---
 .../amd/display/dc/dce100/dce100_resource.c   | 35 ---
 .../amd/display/dc/dce110/dce110_resource.c   | 35 ---
 .../amd/display/dc/dce112/dce112_resource.c   | 35 ---
 .../drm/amd/display/dc/dce80/dce80_resource.c | 34 --
 .../drm/amd/include/asic_reg/dce/dce_10_0_d.h | 18 ++
 .../drm/amd/include/asic_reg/dce/dce_11_0_d.h | 10 ++
 .../drm/amd/include/asic_reg/dce/dce_11_2_d.h | 10 ++
 .../drm/amd/include/asic_reg/dce/dce_8_0_d.h  | 15 
 8 files changed, 53 insertions(+), 139 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 
b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
index 38ec0d609297..7615668a78e9 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
@@ -59,46 +59,11 @@
 #include "gmc/gmc_8_2_sh_mask.h"
 #endif
 
-#ifndef mmDP_DPHY_INTERNAL_CTRL
-   #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
-   #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
-   #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7
-   #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7
-   #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7
-   #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7
-   #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7
-   #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7
-   #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7
-   #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
-#endif
-
 #ifndef mmBIOS_SCRATCH_2
#define mmBIOS_SCRATCH_2 0x05CB
#define mmBIOS_SCRATCH_6 0x05CF
 #endif
 
-#ifndef mmDP_DPHY_BS_SR_SWAP_CNTL
-   #define mmDP_DPHY_BS_SR_SWAP_CNTL   0x4ADC
-   #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL   0x4ADC
-   #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL   0x4BDC
-   #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL   0x4CDC
-   #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL   0x4DDC
-   #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL   0x4EDC
-   #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL   0x4FDC
-   #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL   0x54DC
-#endif
-
-#ifndef mmDP_DPHY_FAST_TRAINING
-   #define mmDP_DPHY_FAST_TRAINING 0x4ABC
-   #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC
-   #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC
-   #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC
-   #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC
-   #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC
-   #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC
-   #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC
-#endif
-
 static const struct dce110_timing_generator_offsets dce100_tg_offsets[] = {
{
.crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
index ee33786bdef6..648187a28671 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
@@ -68,46 +68,11 @@
 #include "gmc/gmc_8_2_sh_mask.h"
 #endif
 
-#ifndef mmDP_DPHY_INTERNAL_CTRL
-   #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
-   #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
-   #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7
-   #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7
-   #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7
-   #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7
-   #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7
-   #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7
-   #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7
-   #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
-#endif
-
 #ifndef mmBIOS_SCRATCH_2
#define mmBIOS_SCRATCH_2 0x05CB
#define mmBIOS_SCRATCH_6 0x05CF
 #endif
 
-#ifndef mmDP_DPHY_BS_SR_SWAP_CNTL
-   #define mmDP_DPHY_BS_SR_SWAP_CNTL   0x4ADC
-   #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL   0x4ADC
-   #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL   0x4BDC
-   #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL   0x4CDC
-   #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL   0x4DDC
-   #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL   0x4EDC
-   #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL   0x4FDC
-   #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL   0x54DC
-#endif
-
-#ifndef mmDP_DPHY_FAST_TRAINING
-   #define mmDP_DPHY_FAST_TRAINING

Re: [PATCH] amd/include: Move register declarations from display to include/asic_reg

[PATCH] amd/include: Move register declarations from display to include/asic_reg

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