Re: [PATCH] drm/amd/display: Use DCN30 watermark calc for DCN301
On Mon, Aug 16, 2021 at 4:25 PM Leo Li wrote:
>
>
>
> On 2021-08-16 9:59 a.m., Leo Li wrote:
> >
> >
> >
> > On 2021-08-13 3:21 p.m., Liu, Zhan wrote:
> >> [AMD Official Use Only]
> >>
> >> [AMD Official Use Only]
> >>
> >> [why]
> >> dcn301_calculate_wm_and_dl() causes flickering when external monitor is
> >> connected.
> >>
> >> This issue has been fixed before by commit 0e4c0ae59d7e
> >> ("drm/amdgpu/display: drop dcn301_calculate_wm_and_dl for now"), however
> >> part of the fix was gone after commit 2cbcb78c9ee5 ("Merge tag
> >> 'amd-drm-next-5.13-2021-03-23' of
> >> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitlab.freedesktop.org%2Fagd5f%2Flinuxdata=04%7C01%7Csunpeng.li%40amd.com%7C723f9131e57b4bd99db508d960be2441%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637647192045690562%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata=f2gL9TVAvdXlCbsZCDa2prF1J4l2ZDbpY8L2f6vK7as%3Dreserved=0
> >> into drm-next").
> >>
> >> [how]
> >> Use dcn30_calculate_wm_and_dlg() instead as in the original fix.
> >>
> >> Fixes: 2cbcb78c9ee5 ("Merge tag 'amd-drm-next-5.13-2021-03-23' of
> >> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitlab.freedesktop.org%2Fagd5f%2Flinuxdata=04%7C01%7Csunpeng.li%40amd.com%7C723f9131e57b4bd99db508d960be2441%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637647192045690562%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata=f2gL9TVAvdXlCbsZCDa2prF1J4l2ZDbpY8L2f6vK7as%3Dreserved=0
> >> into drm-next")
> >> Signed-off-by: Nikola Cornij mailto:nikola.cor...@amd.com
> >> ---
> >> .../amd/display/dc/dcn301/dcn301_resource.c | 96 +--
> >> 1 file changed, 1 insertion(+), 95 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
> >> b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
> >> index 9776d1737818..912285fdce18 100644
> >> --- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
> >> +++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
> >> @@ -1622,106 +1622,12 @@ static void
> >> dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *b
> >> dml_init_instance(>dml, _01_soc, _01_ip,
> >> DML_PROJECT_DCN30);
> >> }
> >>
> >> -static void calculate_wm_set_for_vlevel(
> >> - int vlevel,
> >> - struct wm_range_table_entry *table_entry,
> >> - struct dcn_watermarks *wm_set,
> >> - struct display_mode_lib *dml,
> >> - display_e2e_pipe_params_st *pipes,
> >> - int pipe_cnt)
> >> -{
> >> - double dram_clock_change_latency_cached =
> >> dml->soc.dram_clock_change_latency_us;
> >> -
> >> - ASSERT(vlevel < dml->soc.num_states);
> >> - /* only pipe 0 is read for voltage and dcf/soc clocks */
> >> - pipes[0].clks_cfg.voltage = vlevel;
> >> - pipes[0].clks_cfg.dcfclk_mhz =
> >> dml->soc.clock_limits[vlevel].dcfclk_mhz;
> >> - pipes[0].clks_cfg.socclk_mhz =
> >> dml->soc.clock_limits[vlevel].socclk_mhz;
> >> -
> >> - dml->soc.dram_clock_change_latency_us =
> >> table_entry->pstate_latency_us;
> >> - dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us;
> >> - dml->soc.sr_enter_plus_exit_time_us =
> >> table_entry->sr_enter_plus_exit_time_us;
> >> -
> >> - wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000;
> >> - wm_set->cstate_pstate.cstate_enter_plus_exit_ns =
> >> get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000;
> >> - wm_set->cstate_pstate.cstate_exit_ns =
> >> get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000;
> >> - wm_set->cstate_pstate.pstate_change_ns =
> >> get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000;
> >> - wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes,
> >> pipe_cnt) * 1000;
> >> - wm_set->frac_urg_bw_nom =
> >> get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000;
> >> - wm_set->frac_urg_bw_flip =
> >> get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000;
> >> - wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes,
> >> pipe_cnt) * 1000;
> >> - dml->soc.dram_clock_change_latency_us =
> >> dram_clock_change_latency_cached;
> >> -
> >> -}
> >> -
> >> -static void dcn301_calculate_wm_and_dlg(
> >> - struct dc *dc, struct dc_state *context,
> >> - display_e2e_pipe_params_st *pipes,
> >> - int pipe_cnt,
> >> - int vlevel_req)
> >> -{
> >> - int i, pipe_idx;
> >> - int vlevel, vlevel_max;
> >> - struct wm_range_table_entry *table_entry;
> >> - struct clk_bw_params *bw_params = dc->clk_mgr->bw_params;
> >> -
> >> - ASSERT(bw_params);
> >> -
> >> - vlevel_max = bw_params->clk_table.num_entries - 1;
> >> -
> >> - /* WM Set D */
> >> - table_entry = _params->wm_table.entries[WM_D];
> >> -
Re: [PATCH] drm/amd/display: Use DCN30 watermark calc for DCN301
On 2021-08-16 9:59 a.m., Leo Li wrote:
On 2021-08-13 3:21 p.m., Liu, Zhan wrote:
[AMD Official Use Only]
[AMD Official Use Only]
[why]
dcn301_calculate_wm_and_dl() causes flickering when external monitor is
connected.
This issue has been fixed before by commit 0e4c0ae59d7e
("drm/amdgpu/display: drop dcn301_calculate_wm_and_dl for now"), however
part of the fix was gone after commit 2cbcb78c9ee5 ("Merge tag
'amd-drm-next-5.13-2021-03-23' of
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitlab.freedesktop.org%2Fagd5f%2Flinuxdata=04%7C01%7Csunpeng.li%40amd.com%7C723f9131e57b4bd99db508d960be2441%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637647192045690562%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata=f2gL9TVAvdXlCbsZCDa2prF1J4l2ZDbpY8L2f6vK7as%3Dreserved=0
into drm-next").
[how]
Use dcn30_calculate_wm_and_dlg() instead as in the original fix.
Fixes: 2cbcb78c9ee5 ("Merge tag 'amd-drm-next-5.13-2021-03-23' of
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitlab.freedesktop.org%2Fagd5f%2Flinuxdata=04%7C01%7Csunpeng.li%40amd.com%7C723f9131e57b4bd99db508d960be2441%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637647192045690562%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata=f2gL9TVAvdXlCbsZCDa2prF1J4l2ZDbpY8L2f6vK7as%3Dreserved=0
into drm-next")
Signed-off-by: Nikola Cornij mailto:nikola.cor...@amd.com
---
.../amd/display/dc/dcn301/dcn301_resource.c | 96 +--
1 file changed, 1 insertion(+), 95 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
index 9776d1737818..912285fdce18 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
@@ -1622,106 +1622,12 @@ static void
dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *b
dml_init_instance(>dml, _01_soc, _01_ip,
DML_PROJECT_DCN30);
}
-static void calculate_wm_set_for_vlevel(
- int vlevel,
- struct wm_range_table_entry *table_entry,
- struct dcn_watermarks *wm_set,
- struct display_mode_lib *dml,
- display_e2e_pipe_params_st *pipes,
- int pipe_cnt)
-{
- double dram_clock_change_latency_cached =
dml->soc.dram_clock_change_latency_us;
-
- ASSERT(vlevel < dml->soc.num_states);
- /* only pipe 0 is read for voltage and dcf/soc clocks */
- pipes[0].clks_cfg.voltage = vlevel;
- pipes[0].clks_cfg.dcfclk_mhz =
dml->soc.clock_limits[vlevel].dcfclk_mhz;
- pipes[0].clks_cfg.socclk_mhz =
dml->soc.clock_limits[vlevel].socclk_mhz;
-
- dml->soc.dram_clock_change_latency_us =
table_entry->pstate_latency_us;
- dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us;
- dml->soc.sr_enter_plus_exit_time_us =
table_entry->sr_enter_plus_exit_time_us;
-
- wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000;
- wm_set->cstate_pstate.cstate_enter_plus_exit_ns =
get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000;
- wm_set->cstate_pstate.cstate_exit_ns =
get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000;
- wm_set->cstate_pstate.pstate_change_ns =
get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000;
- wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes,
pipe_cnt) * 1000;
- wm_set->frac_urg_bw_nom =
get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000;
- wm_set->frac_urg_bw_flip =
get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000;
- wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes,
pipe_cnt) * 1000;
- dml->soc.dram_clock_change_latency_us =
dram_clock_change_latency_cached;
-
-}
-
-static void dcn301_calculate_wm_and_dlg(
- struct dc *dc, struct dc_state *context,
- display_e2e_pipe_params_st *pipes,
- int pipe_cnt,
- int vlevel_req)
-{
- int i, pipe_idx;
- int vlevel, vlevel_max;
- struct wm_range_table_entry *table_entry;
- struct clk_bw_params *bw_params = dc->clk_mgr->bw_params;
-
- ASSERT(bw_params);
-
- vlevel_max = bw_params->clk_table.num_entries - 1;
-
- /* WM Set D */
- table_entry = _params->wm_table.entries[WM_D];
- if (table_entry->wm_type == WM_TYPE_RETRAINING)
- vlevel = 0;
- else
- vlevel = vlevel_max;
- calculate_wm_set_for_vlevel(vlevel, table_entry,
>bw_ctx.bw.dcn.watermarks.d,
- >bw_ctx.dml,
pipes, pipe_cnt);
- /* WM Set C */
- table_entry = _params->wm_table.entries[WM_C];
- vlevel = min(max(vlevel_req, 2), vlevel_max);
- calculate_wm_set_for_vlevel(vlevel, table_entry,
>bw_ctx.bw.dcn.watermarks.c,
-
Re: [PATCH] drm/amd/display: Use DCN30 watermark calc for DCN301
On 2021-08-13 3:21 p.m., Liu, Zhan wrote:
[AMD Official Use Only]
[AMD Official Use Only]
[why]
dcn301_calculate_wm_and_dl() causes flickering when external monitor is
connected.
This issue has been fixed before by commit 0e4c0ae59d7e
("drm/amdgpu/display: drop dcn301_calculate_wm_and_dl for now"), however
part of the fix was gone after commit 2cbcb78c9ee5 ("Merge tag
'amd-drm-next-5.13-2021-03-23' of
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitlab.freedesktop.org%2Fagd5f%2Flinuxdata=04%7C01%7Csunpeng.li%40amd.com%7C5f101c8bf2594f79890508d95e8f8f98%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637644792952782170%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata=VDcz5SuZ0guBGRKKOlOWdWI%2FDLuIIwYAIs%2F8geu4JLU%3Dreserved=0
into drm-next").
[how]
Use dcn30_calculate_wm_and_dlg() instead as in the original fix.
Fixes: 2cbcb78c9ee5 ("Merge tag 'amd-drm-next-5.13-2021-03-23' of
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitlab.freedesktop.org%2Fagd5f%2Flinuxdata=04%7C01%7Csunpeng.li%40amd.com%7C5f101c8bf2594f79890508d95e8f8f98%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637644792952782170%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata=VDcz5SuZ0guBGRKKOlOWdWI%2FDLuIIwYAIs%2F8geu4JLU%3Dreserved=0
into drm-next")
Signed-off-by: Nikola Cornij mailto:nikola.cor...@amd.com
---
.../amd/display/dc/dcn301/dcn301_resource.c | 96 +--
1 file changed, 1 insertion(+), 95 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
index 9776d1737818..912285fdce18 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
@@ -1622,106 +1622,12 @@ static void dcn301_update_bw_bounding_box(struct dc
*dc, struct clk_bw_params *b
dml_init_instance(>dml, _01_soc, _01_ip,
DML_PROJECT_DCN30);
}
-static void calculate_wm_set_for_vlevel(
- int vlevel,
- struct wm_range_table_entry *table_entry,
- struct dcn_watermarks *wm_set,
- struct display_mode_lib *dml,
- display_e2e_pipe_params_st *pipes,
- int pipe_cnt)
-{
- double dram_clock_change_latency_cached =
dml->soc.dram_clock_change_latency_us;
-
- ASSERT(vlevel < dml->soc.num_states);
- /* only pipe 0 is read for voltage and dcf/soc clocks */
- pipes[0].clks_cfg.voltage = vlevel;
- pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz;
- pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz;
-
- dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us;
- dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us;
- dml->soc.sr_enter_plus_exit_time_us =
table_entry->sr_enter_plus_exit_time_us;
-
- wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000;
- wm_set->cstate_pstate.cstate_enter_plus_exit_ns =
get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000;
- wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes,
pipe_cnt) * 1000;
- wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml,
pipes, pipe_cnt) * 1000;
- wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) *
1000;
- wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes,
pipe_cnt) * 1000;
- wm_set->frac_urg_bw_flip =
get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000;
- wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) *
1000;
- dml->soc.dram_clock_change_latency_us =
dram_clock_change_latency_cached;
-
-}
-
-static void dcn301_calculate_wm_and_dlg(
- struct dc *dc, struct dc_state *context,
- display_e2e_pipe_params_st *pipes,
- int pipe_cnt,
- int vlevel_req)
-{
- int i, pipe_idx;
- int vlevel, vlevel_max;
- struct wm_range_table_entry *table_entry;
- struct clk_bw_params *bw_params = dc->clk_mgr->bw_params;
-
- ASSERT(bw_params);
-
- vlevel_max = bw_params->clk_table.num_entries - 1;
-
- /* WM Set D */
- table_entry = _params->wm_table.entries[WM_D];
- if (table_entry->wm_type == WM_TYPE_RETRAINING)
- vlevel = 0;
- else
- vlevel = vlevel_max;
- calculate_wm_set_for_vlevel(vlevel, table_entry,
>bw_ctx.bw.dcn.watermarks.d,
- >bw_ctx.dml, pipes,
pipe_cnt);
- /* WM Set C */
- table_entry = _params->wm_table.entries[WM_C];
- vlevel = min(max(vlevel_req, 2), vlevel_max);
- calculate_wm_set_for_vlevel(vlevel, table_entry,
>bw_ctx.bw.dcn.watermarks.c,
-
RE: [PATCH] drm/amd/display: Use DCN30 watermark calc for DCN301
[Public]
> -Original Message-
> From: Liu, Zhan
> Sent: 2021/August/13, Friday 3:21 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Cornij, Nikola ; Liu, Zhan
> ; Logush, Oliver
> Subject: [PATCH] drm/amd/display: Use DCN30 watermark calc for DCN301
>
>
> [why]
> dcn301_calculate_wm_and_dl() causes flickering when external monitor is
> connected.
>
> This issue has been fixed before by commit 0e4c0ae59d7e
> ("drm/amdgpu/display: drop dcn301_calculate_wm_and_dl for now"),
> however part of the fix was gone after commit 2cbcb78c9ee5 ("Merge tag
> 'amd-drm-next-5.13-2021-03-23' of
> https://gitlab.freedesktop.org/agd5f/linux into drm-next").
>
> [how]
> Use dcn30_calculate_wm_and_dlg() instead as in the original fix.
>
> Fixes: 2cbcb78c9ee5 ("Merge tag 'amd-drm-next-5.13-2021-03-23' of
> https://gitlab.freedesktop.org/agd5f/linux into drm-next")
> Signed-off-by: Nikola Cornij
Reviewed-by: Zhan Liu
Tested-by: Zhan Liu
Tested-by: Oliver Logush
> ---
> .../amd/display/dc/dcn301/dcn301_resource.c | 96 +--
> 1 file changed, 1 insertion(+), 95 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
> b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
> index 9776d1737818..912285fdce18 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
> @@ -1622,106 +1622,12 @@ static void
> dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *b
> dml_init_instance(>dml, _01_soc, _01_ip,
> DML_PROJECT_DCN30); }
>
> -static void calculate_wm_set_for_vlevel(
> - int vlevel,
> - struct wm_range_table_entry *table_entry,
> - struct dcn_watermarks *wm_set,
> - struct display_mode_lib *dml,
> - display_e2e_pipe_params_st *pipes,
> - int pipe_cnt)
> -{
> - double dram_clock_change_latency_cached = dml-
> >soc.dram_clock_change_latency_us;
> -
> - ASSERT(vlevel < dml->soc.num_states);
> - /* only pipe 0 is read for voltage and dcf/soc clocks */
> - pipes[0].clks_cfg.voltage = vlevel;
> - pipes[0].clks_cfg.dcfclk_mhz =
> dml->soc.clock_limits[vlevel].dcfclk_mhz;
> - pipes[0].clks_cfg.socclk_mhz =
> dml->soc.clock_limits[vlevel].socclk_mhz;
> -
> - dml->soc.dram_clock_change_latency_us = table_entry-
> >pstate_latency_us;
> - dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us;
> - dml->soc.sr_enter_plus_exit_time_us = table_entry-
> >sr_enter_plus_exit_time_us;
> -
> - wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000;
> - wm_set->cstate_pstate.cstate_enter_plus_exit_ns =
> get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000;
> - wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes,
> pipe_cnt) * 1000;
> - wm_set->cstate_pstate.pstate_change_ns =
> get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000;
> - wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes,
> pipe_cnt) * 1000;
> - wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml,
> pipes, pipe_cnt) * 1000;
> - wm_set->frac_urg_bw_flip =
> get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000;
> - wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt)
> * 1000;
> - dml->soc.dram_clock_change_latency_us =
> dram_clock_change_latency_cached;
> -
> -}
> -
> -static void dcn301_calculate_wm_and_dlg(
> - struct dc *dc, struct dc_state *context,
> - display_e2e_pipe_params_st *pipes,
> - int pipe_cnt,
> - int vlevel_req)
> -{
> - int i, pipe_idx;
> - int vlevel, vlevel_max;
> - struct wm_range_table_entry *table_entry;
> - struct clk_bw_params *bw_params = dc->clk_mgr->bw_params;
> -
> - ASSERT(bw_params);
> -
> - vlevel_max = bw_params->clk_table.num_entries - 1;
> -
> - /* WM Set D */
> - table_entry = _params->wm_table.entries[WM_D];
> - if (table_entry->wm_type == WM_TYPE_RETRAINING)
> - vlevel = 0;
> - else
> - vlevel = vlevel_max;
> - calculate_wm_set_for_vlevel(vlevel, table_entry,
> >bw_ctx.bw.dcn.watermarks.d,
> - >bw_ctx.dml, pipes,
> pipe_cnt);
> - /* WM Set C */
> - table_entry = _params->wm_table.entries[WM_C];
> - vlevel = min(max(vlevel_req, 2), vlevel_max);
> -
[PATCH] drm/amd/display: Use DCN30 watermark calc for DCN301
[AMD Official Use Only]
[why]
dcn301_calculate_wm_and_dl() causes flickering when external monitor is
connected.
This issue has been fixed before by commit 0e4c0ae59d7e
("drm/amdgpu/display: drop dcn301_calculate_wm_and_dl for now"), however
part of the fix was gone after commit 2cbcb78c9ee5 ("Merge tag
'amd-drm-next-5.13-2021-03-23' of
https://gitlab.freedesktop.org/agd5f/linux into drm-next").
[how]
Use dcn30_calculate_wm_and_dlg() instead as in the original fix.
Fixes: 2cbcb78c9ee5 ("Merge tag 'amd-drm-next-5.13-2021-03-23' of
https://gitlab.freedesktop.org/agd5f/linux into drm-next")
Signed-off-by: Nikola Cornij mailto:nikola.cor...@amd.com
---
.../amd/display/dc/dcn301/dcn301_resource.c | 96 +--
1 file changed, 1 insertion(+), 95 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
index 9776d1737818..912285fdce18 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
@@ -1622,106 +1622,12 @@ static void dcn301_update_bw_bounding_box(struct dc
*dc, struct clk_bw_params *b
dml_init_instance(>dml, _01_soc, _01_ip,
DML_PROJECT_DCN30);
}
-static void calculate_wm_set_for_vlevel(
- int vlevel,
- struct wm_range_table_entry *table_entry,
- struct dcn_watermarks *wm_set,
- struct display_mode_lib *dml,
- display_e2e_pipe_params_st *pipes,
- int pipe_cnt)
-{
- double dram_clock_change_latency_cached =
dml->soc.dram_clock_change_latency_us;
-
- ASSERT(vlevel < dml->soc.num_states);
- /* only pipe 0 is read for voltage and dcf/soc clocks */
- pipes[0].clks_cfg.voltage = vlevel;
- pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz;
- pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz;
-
- dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us;
- dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us;
- dml->soc.sr_enter_plus_exit_time_us =
table_entry->sr_enter_plus_exit_time_us;
-
- wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000;
- wm_set->cstate_pstate.cstate_enter_plus_exit_ns =
get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000;
- wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes,
pipe_cnt) * 1000;
- wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml,
pipes, pipe_cnt) * 1000;
- wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) *
1000;
- wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes,
pipe_cnt) * 1000;
- wm_set->frac_urg_bw_flip =
get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000;
- wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) *
1000;
- dml->soc.dram_clock_change_latency_us =
dram_clock_change_latency_cached;
-
-}
-
-static void dcn301_calculate_wm_and_dlg(
- struct dc *dc, struct dc_state *context,
- display_e2e_pipe_params_st *pipes,
- int pipe_cnt,
- int vlevel_req)
-{
- int i, pipe_idx;
- int vlevel, vlevel_max;
- struct wm_range_table_entry *table_entry;
- struct clk_bw_params *bw_params = dc->clk_mgr->bw_params;
-
- ASSERT(bw_params);
-
- vlevel_max = bw_params->clk_table.num_entries - 1;
-
- /* WM Set D */
- table_entry = _params->wm_table.entries[WM_D];
- if (table_entry->wm_type == WM_TYPE_RETRAINING)
- vlevel = 0;
- else
- vlevel = vlevel_max;
- calculate_wm_set_for_vlevel(vlevel, table_entry,
>bw_ctx.bw.dcn.watermarks.d,
- >bw_ctx.dml, pipes,
pipe_cnt);
- /* WM Set C */
- table_entry = _params->wm_table.entries[WM_C];
- vlevel = min(max(vlevel_req, 2), vlevel_max);
- calculate_wm_set_for_vlevel(vlevel, table_entry,
>bw_ctx.bw.dcn.watermarks.c,
- >bw_ctx.dml, pipes,
pipe_cnt);
- /* WM Set B */
- table_entry = _params->wm_table.entries[WM_B];
- vlevel = min(max(vlevel_req, 1), vlevel_max);
- calculate_wm_set_for_vlevel(vlevel, table_entry,
>bw_ctx.bw.dcn.watermarks.b,
- >bw_ctx.dml, pipes,
pipe_cnt);
-
- /* WM Set A */
- table_entry = _params->wm_table.entries[WM_A];
- vlevel = min(vlevel_req, vlevel_max);
- calculate_wm_set_for_vlevel(vlevel, table_entry,
>bw_ctx.bw.dcn.watermarks.a,
- >bw_ctx.dml, pipes,
pipe_cnt);
-
- for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
- if (!context->res_ctx.pipe_ctx[i].stream)
- continue;
-
-
