[Public]
-Original Message-
From: Liu, Zhan
Sent: Wednesday, January 19, 2022 5:22 PM
To: amd-gfx@lists.freedesktop.org
Cc: Liu, Charlene ; Cornij, Nikola
; Gutierrez, Agustin ;
Kotarac, Pavle ; Pierre-Loup Griffais
Subject: [PATCH] drm/amd/display: change FIFO reset condition to embedded
display only
[Public]
[Why]
FIFO reset is only necessary for fast boot sequence, where otg is disabled and
dig fe is enabled when changing dispclk. Fast boot is only enabled on embedded
displays.
[How]
Change FIFO reset condition to "embedded display only".
Signed-off-by: Zhan Liu
Reviewed-by: Charlene Liu
---
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index f1593186e964..f3ff141b706a 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1608,7 +1608,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(
pipe_ctx->stream_res.stream_enc,
pipe_ctx->stream_res.tg->inst);
- if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
+ if (dc_is_embedded_signal(pipe_ctx->stream->signal) &&
pipe_ctx->stream_res.stream_enc->funcs->reset_fifo)
pipe_ctx->stream_res.stream_enc->funcs->reset_fifo(
pipe_ctx->stream_res.stream_enc);
--
2.25.1
