RE: [PATCH] drm/amd/powerplay: read pcie speed/width info
> -Original Message-
> From: amd-gfx On Behalf Of
> Kenneth Feng
> Sent: Tuesday, November 12, 2019 4:40 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Feng, Kenneth
> Subject: [PATCH] drm/amd/powerplay: read pcie speed/width info
>
> sysfs interface to read pcie speed info on navi1x.
>
> Signed-off-by: Kenneth Feng
> ---
> drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 10 +++---
> drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 8 +
> drivers/gpu/drm/amd/powerplay/navi10_ppt.c| 50
> ++-
> drivers/gpu/drm/amd/powerplay/navi10_ppt.h| 3 ++
> 4 files changed, 66 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index 57459a6..69243a8 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -1068,10 +1068,6 @@ static int smu_smc_table_hw_init(struct
> smu_context *smu,
> return ret;
>
> if (adev->asic_type != CHIP_ARCTURUS) {
> - ret = smu_override_pcie_parameters(smu);
> - if (ret)
> - return ret;
> -
> ret = smu_notify_display_change(smu);
> if (ret)
> return ret;
> @@ -1100,6 +1096,12 @@ static int smu_smc_table_hw_init(struct
> smu_context *smu,
> return ret;
> }
>
> + if (adev->asic_type != CHIP_ARCTURUS) {
> + ret = smu_override_pcie_parameters(smu);
> + if (ret)
> + return ret;
> + }
> +
> ret = smu_set_default_od_settings(smu, initialize);
> if (ret)
> return ret;
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
> b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
> index 0ba7a72..6061490 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
> @@ -48,6 +48,8 @@
>
> #define SMU11_TOOL_SIZE 0x19000
>
> +#define MAX_PCIE_CONF 2
> +
> #define CLK_MAP(clk, index) \
> [SMU_##clk] = {1, (index)}
>
> @@ -88,6 +90,11 @@ struct smu_11_0_dpm_table {
> uint32_tmax;/* MHz */
> };
>
> +struct smu_11_0_pcie_table {
> +uint8_t pcie_gen[MAX_PCIE_CONF];
> +uint8_t pcie_lane[MAX_PCIE_CONF];
> +};
> +
> struct smu_11_0_dpm_tables {
> struct smu_11_0_dpm_tablesoc_table;
> struct smu_11_0_dpm_tablegfx_table;
> @@ -100,6 +107,7 @@ struct smu_11_0_dpm_tables {
> struct smu_11_0_dpm_tabledisplay_table;
> struct smu_11_0_dpm_tablephy_table;
> struct smu_11_0_dpm_tablefclk_table;
> + struct smu_11_0_pcie_table pcie_table;
> };
>
> struct smu_11_0_dpm_context {
> diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> index 36cf313..8855bcc 100644
> --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> @@ -36,6 +36,7 @@
> #include "navi10_ppt.h"
> #include "smu_v11_0_pptable.h"
> #include "smu_v11_0_ppsmc.h"
> +#include "nbio/nbio_7_4_sh_mask.h"
>
> #include "asic_reg/mp/mp_11_0_sh_mask.h"
>
> @@ -599,6 +600,7 @@ static int navi10_set_default_dpm_table(struct
> smu_context *smu)
> struct smu_table_context *table_context = >smu_table;
> struct smu_11_0_dpm_context *dpm_context = smu_dpm-
> >dpm_context;
> PPTable_t *driver_ppt = NULL;
> + int i;
>
> driver_ppt = table_context->driver_pptable;
>
> @@ -629,6 +631,11 @@ static int navi10_set_default_dpm_table(struct
> smu_context *smu)
> dpm_context->dpm_tables.phy_table.min = driver_ppt-
> >FreqTablePhyclk[0];
> dpm_context->dpm_tables.phy_table.max = driver_ppt-
> >FreqTablePhyclk[NUM_PHYCLK_DPM_LEVELS - 1];
>
> + for (i = 0; i < MAX_PCIE_CONF; i++) {
> + dpm_context->dpm_tables.pcie_table.pcie_gen[i] = driver_ppt-
> >PcieGenSpeed[i];
> + dpm_context->dpm_tables.pcie_table.pcie_lane[i] =
> driver_ppt->PcieLaneCount[i];
> + }
> +
> return 0;
> }
>
> @@ -710,6 +717,11 @@ static int navi10_print_clk_levels(struct smu_context
> *smu,
> struct smu_table_context *table_context = >smu_table;
> od_table = (OverDriveTable_t *)table_context->overdrive_table;
> od_settings = smu->od_settings;
> + uint32_t gen_speed, lane_width;
> + struct smu_dpm_co
[PATCH] drm/amd/powerplay: read pcie speed/width info
sysfs interface to read pcie speed info on navi1x.
Signed-off-by: Kenneth Feng
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 10 +++---
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 8 +
drivers/gpu/drm/amd/powerplay/navi10_ppt.c| 50 ++-
drivers/gpu/drm/amd/powerplay/navi10_ppt.h| 3 ++
4 files changed, 66 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 57459a6..69243a8 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1068,10 +1068,6 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
return ret;
if (adev->asic_type != CHIP_ARCTURUS) {
- ret = smu_override_pcie_parameters(smu);
- if (ret)
- return ret;
-
ret = smu_notify_display_change(smu);
if (ret)
return ret;
@@ -1100,6 +1096,12 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
return ret;
}
+ if (adev->asic_type != CHIP_ARCTURUS) {
+ ret = smu_override_pcie_parameters(smu);
+ if (ret)
+ return ret;
+ }
+
ret = smu_set_default_od_settings(smu, initialize);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index 0ba7a72..6061490 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -48,6 +48,8 @@
#define SMU11_TOOL_SIZE0x19000
+#define MAX_PCIE_CONF 2
+
#define CLK_MAP(clk, index) \
[SMU_##clk] = {1, (index)}
@@ -88,6 +90,11 @@ struct smu_11_0_dpm_table {
uint32_tmax;/* MHz */
};
+struct smu_11_0_pcie_table {
+uint8_t pcie_gen[MAX_PCIE_CONF];
+uint8_t pcie_lane[MAX_PCIE_CONF];
+};
+
struct smu_11_0_dpm_tables {
struct smu_11_0_dpm_tablesoc_table;
struct smu_11_0_dpm_tablegfx_table;
@@ -100,6 +107,7 @@ struct smu_11_0_dpm_tables {
struct smu_11_0_dpm_tabledisplay_table;
struct smu_11_0_dpm_tablephy_table;
struct smu_11_0_dpm_tablefclk_table;
+ struct smu_11_0_pcie_table pcie_table;
};
struct smu_11_0_dpm_context {
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 36cf313..8855bcc 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -36,6 +36,7 @@
#include "navi10_ppt.h"
#include "smu_v11_0_pptable.h"
#include "smu_v11_0_ppsmc.h"
+#include "nbio/nbio_7_4_sh_mask.h"
#include "asic_reg/mp/mp_11_0_sh_mask.h"
@@ -599,6 +600,7 @@ static int navi10_set_default_dpm_table(struct smu_context
*smu)
struct smu_table_context *table_context = >smu_table;
struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
PPTable_t *driver_ppt = NULL;
+ int i;
driver_ppt = table_context->driver_pptable;
@@ -629,6 +631,11 @@ static int navi10_set_default_dpm_table(struct smu_context
*smu)
dpm_context->dpm_tables.phy_table.min = driver_ppt->FreqTablePhyclk[0];
dpm_context->dpm_tables.phy_table.max =
driver_ppt->FreqTablePhyclk[NUM_PHYCLK_DPM_LEVELS - 1];
+ for (i = 0; i < MAX_PCIE_CONF; i++) {
+ dpm_context->dpm_tables.pcie_table.pcie_gen[i] =
driver_ppt->PcieGenSpeed[i];
+ dpm_context->dpm_tables.pcie_table.pcie_lane[i] =
driver_ppt->PcieLaneCount[i];
+ }
+
return 0;
}
@@ -710,6 +717,11 @@ static int navi10_print_clk_levels(struct smu_context *smu,
struct smu_table_context *table_context = >smu_table;
od_table = (OverDriveTable_t *)table_context->overdrive_table;
od_settings = smu->od_settings;
+ uint32_t gen_speed, lane_width;
+ struct smu_dpm_context *smu_dpm = >smu_dpm;
+ struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
+ struct amdgpu_device *adev = smu->adev;
+ PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
switch (clk_type) {
case SMU_GFXCLK:
@@ -760,6 +772,30 @@ static int navi10_print_clk_levels(struct smu_context *smu,
}
break;
+ case SMU_PCIE:
+ gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
+
PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
+ >>
PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
+ lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
+ PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
+ >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
+
