Re: [PATCH] drm/amd/pp: Fix truncated clock value when set watermark

2018-11-13 Thread Wentland, Harry 
On 2018-11-12 10:32 p.m., Rex Zhu wrote:
> the clk value should be tranferred to MHz first and
> then transfer to uint16. otherwise, the clock value
> will be truncated.
> 
> Reported-by: Hersen Wu 
> Signed-off-by: Rex Zhu 

Reviewed-by: Harry Wentland 

Harry

> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c | 32 
> 
>  1 file changed, 16 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
> index 99a33c3..101c09b 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
> @@ -713,20 +713,20 @@ int smu_set_watermarks_for_clocks_ranges(void *wt_table,
>   for (i = 0; i < wm_with_clock_ranges->num_wm_dmif_sets; i++) {
>   table->WatermarkRow[1][i].MinClock =
>   cpu_to_le16((uint16_t)
> - 
> (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz) /
> - 1000);
> + 
> (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
> + 1000));
>   table->WatermarkRow[1][i].MaxClock =
>   cpu_to_le16((uint16_t)
> - 
> (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz) /
> - 1000);
> + 
> (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
> + 1000));
>   table->WatermarkRow[1][i].MinUclk =
>   cpu_to_le16((uint16_t)
> - 
> (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz) /
> - 1000);
> + 
> (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
> + 1000));
>   table->WatermarkRow[1][i].MaxUclk =
>   cpu_to_le16((uint16_t)
> - 
> (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz) /
> - 1000);
> + 
> (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
> + 1000));
>   table->WatermarkRow[1][i].WmSetting = (uint8_t)
>   
> wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
>   }
> @@ -734,20 +734,20 @@ int smu_set_watermarks_for_clocks_ranges(void *wt_table,
>   for (i = 0; i < wm_with_clock_ranges->num_wm_mcif_sets; i++) {
>   table->WatermarkRow[0][i].MinClock =
>   cpu_to_le16((uint16_t)
> - 
> (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz) /
> - 1000);
> + 
> (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
> + 1000));
>   table->WatermarkRow[0][i].MaxClock =
>   cpu_to_le16((uint16_t)
> - 
> (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz) /
> - 1000);
> + 
> (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
> + 1000));
>   table->WatermarkRow[0][i].MinUclk =
>   cpu_to_le16((uint16_t)
> - 
> (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz) /
> - 1000);
> + 
> (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
> + 1000));
>   table->WatermarkRow[0][i].MaxUclk =
>   cpu_to_le16((uint16_t)
> - 
> (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz) /
> - 1000);
> + 
> (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
> + 1000));
>   table->WatermarkRow[0][i].WmSetting = (uint8_t)
>   
> wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
>   }
> 
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Re: [PATCH] drm/amd/pp: Fix truncated clock value when set watermark

2018-11-12 Thread Alex Deucher 
On Mon, Nov 12, 2018 at 10:34 PM Rex Zhu  wrote:
>
> the clk value should be tranferred to MHz first and
> then transfer to uint16. otherwise, the clock value
> will be truncated.
>
> Reported-by: Hersen Wu 
> Signed-off-by: Rex Zhu 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c | 32 
> 
>  1 file changed, 16 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
> index 99a33c3..101c09b 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
> @@ -713,20 +713,20 @@ int smu_set_watermarks_for_clocks_ranges(void *wt_table,
> for (i = 0; i < wm_with_clock_ranges->num_wm_dmif_sets; i++) {
> table->WatermarkRow[1][i].MinClock =
> cpu_to_le16((uint16_t)
> -   
> (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz) /
> -   1000);
> +   
> (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
> +   1000));
> table->WatermarkRow[1][i].MaxClock =
> cpu_to_le16((uint16_t)
> -   
> (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz) /
> -   1000);
> +   
> (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
> +   1000));
> table->WatermarkRow[1][i].MinUclk =
> cpu_to_le16((uint16_t)
> -   
> (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz) /
> -   1000);
> +   
> (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
> +   1000));
> table->WatermarkRow[1][i].MaxUclk =
> cpu_to_le16((uint16_t)
> -   
> (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz) /
> -   1000);
> +   
> (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
> +   1000));
> table->WatermarkRow[1][i].WmSetting = (uint8_t)
> 
> wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
> }
> @@ -734,20 +734,20 @@ int smu_set_watermarks_for_clocks_ranges(void *wt_table,
> for (i = 0; i < wm_with_clock_ranges->num_wm_mcif_sets; i++) {
> table->WatermarkRow[0][i].MinClock =
> cpu_to_le16((uint16_t)
> -   
> (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz) /
> -   1000);
> +   
> (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
> +   1000));
> table->WatermarkRow[0][i].MaxClock =
> cpu_to_le16((uint16_t)
> -   
> (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz) /
> -   1000);
> +   
> (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
> +   1000));
> table->WatermarkRow[0][i].MinUclk =
> cpu_to_le16((uint16_t)
> -   
> (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz) /
> -   1000);
> +   
> (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
> +   1000));
> table->WatermarkRow[0][i].MaxUclk =
> cpu_to_le16((uint16_t)
> -   
> (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz) /
> -   1000);
> +   
> (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
> +   1000));
> table->WatermarkRow[0][i].WmSetting = (uint8_t)
> 
> wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
> }
> --
> 1.9.1
>
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[PATCH] drm/amd/pp: Fix truncated clock value when set watermark

2018-11-12 Thread Rex Zhu 
the clk value should be tranferred to MHz first and
then transfer to uint16. otherwise, the clock value
will be truncated.

Reported-by: Hersen Wu 
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c | 32 
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
index 99a33c3..101c09b 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
@@ -713,20 +713,20 @@ int smu_set_watermarks_for_clocks_ranges(void *wt_table,
for (i = 0; i < wm_with_clock_ranges->num_wm_dmif_sets; i++) {
table->WatermarkRow[1][i].MinClock =
cpu_to_le16((uint16_t)
-   
(wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz) /
-   1000);
+   
(wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
+   1000));
table->WatermarkRow[1][i].MaxClock =
cpu_to_le16((uint16_t)
-   
(wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz) /
-   1000);
+   
(wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
+   1000));
table->WatermarkRow[1][i].MinUclk =
cpu_to_le16((uint16_t)
-   
(wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz) /
-   1000);
+   
(wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
+   1000));
table->WatermarkRow[1][i].MaxUclk =
cpu_to_le16((uint16_t)
-   
(wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz) /
-   1000);
+   
(wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
+   1000));
table->WatermarkRow[1][i].WmSetting = (uint8_t)

wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
}
@@ -734,20 +734,20 @@ int smu_set_watermarks_for_clocks_ranges(void *wt_table,
for (i = 0; i < wm_with_clock_ranges->num_wm_mcif_sets; i++) {
table->WatermarkRow[0][i].MinClock =
cpu_to_le16((uint16_t)
-   
(wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz) /
-   1000);
+   
(wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
+   1000));
table->WatermarkRow[0][i].MaxClock =
cpu_to_le16((uint16_t)
-   
(wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz) /
-   1000);
+   
(wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
+   1000));
table->WatermarkRow[0][i].MinUclk =
cpu_to_le16((uint16_t)
-   
(wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz) /
-   1000);
+   
(wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
+   1000));
table->WatermarkRow[0][i].MaxUclk =
cpu_to_le16((uint16_t)
-   
(wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz) /
-   1000);
+   
(wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
+   1000));
table->WatermarkRow[0][i].WmSetting = (uint8_t)

wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
}
-- 
1.9.1

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