Re: [PATCH] drm/amdgpu/display: re-add surface size calculation in dcn30_hwseq.c

2020-10-27 Thread Abramov, Slava 
[AMD Official Use Only - Internal Distribution Only]

Looks sane to me.

Acked-by: Slava Abramov 

From: amd-gfx  on behalf of Alex Deucher 

Sent: Tuesday, October 27, 2020 11:20 AM
To: amd-gfx list 
Cc: Deucher, Alexander 
Subject: Re: [PATCH] drm/amdgpu/display: re-add surface size calculation in 
dcn30_hwseq.c

Ping?

On Mon, Oct 26, 2020 at 12:14 PM Alex Deucher  wrote:
>
> This is required for MALL.  Was accidently removed in PRS update.
>
> Fixes: 48e48e598478 ("drm/amd/display: Disable idle optimization when PSR is 
> enabled")
> Fixes: 52f2e83e2fe5 ("drm/amdgpu/display: add MALL support (v2)")
> Signed-off-by: Alex Deucher 
> ---
>  .../gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c| 15 +++
>  1 file changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c 
> b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> index f3ae208850b0..cc2eca8c9a62 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> @@ -715,6 +715,21 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, 
> bool enable)
> break;
> }
>
> +   if (dc->current_state->stream_count == 1 // single 
> display only
> +   && 
> dc->current_state->stream_status[0].plane_count == 1 // single surface only
> +   && 
> dc->current_state->stream_status[0].plane_states[0]->address.page_table_base.quad_part
>  == 0 // no VM
> +   // Only 8 and 16 bit formats
> +   && 
> dc->current_state->stream_status[0].plane_states[0]->format <= 
> SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F
> +   && 
> dc->current_state->stream_status[0].plane_states[0]->format >= 
> SURFACE_PIXEL_FORMAT_GRPH_ARGB) {
> +   surface_size = 
> dc->current_state->stream_status[0].plane_states[0]->plane_size.surface_pitch 
> *
> +   
> dc->current_state->stream_status[0].plane_states[0]->plane_size.surface_size.height
>  *
> +   
> (dc->current_state->stream_status[0].plane_states[0]->format >= 
> SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ?
> +8 : 4);
> +   } else {
> +   // TODO: remove hard code size
> +   surface_size = 128 * 1024 * 1024;
> +   }
> +
> // TODO: remove hard code size
> if (surface_size < 128 * 1024 * 1024) {
> refresh_hz = div_u64((unsigned long long) 
> dc->current_state->streams[0]->timing.pix_clk_100hz *
> --
> 2.25.4
>
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfxdata=04%7C01%7Cslava.abramov%40amd.com%7Ce1c9b8c00a2e4a54ca2608d87a8bd178%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637394088245930973%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata=kRMXUEm5Y%2BkYhwBNWUrH6mm8dRYARwXjgXy%2BET4%2BaPk%3Dreserved=0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amdgpu/display: re-add surface size calculation in dcn30_hwseq.c

2020-10-27 Thread Alex Deucher 
Ping?

On Mon, Oct 26, 2020 at 12:14 PM Alex Deucher  wrote:
>
> This is required for MALL.  Was accidently removed in PRS update.
>
> Fixes: 48e48e598478 ("drm/amd/display: Disable idle optimization when PSR is 
> enabled")
> Fixes: 52f2e83e2fe5 ("drm/amdgpu/display: add MALL support (v2)")
> Signed-off-by: Alex Deucher 
> ---
>  .../gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c| 15 +++
>  1 file changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c 
> b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> index f3ae208850b0..cc2eca8c9a62 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> @@ -715,6 +715,21 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, 
> bool enable)
> break;
> }
>
> +   if (dc->current_state->stream_count == 1 // single 
> display only
> +   && 
> dc->current_state->stream_status[0].plane_count == 1 // single surface only
> +   && 
> dc->current_state->stream_status[0].plane_states[0]->address.page_table_base.quad_part
>  == 0 // no VM
> +   // Only 8 and 16 bit formats
> +   && 
> dc->current_state->stream_status[0].plane_states[0]->format <= 
> SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F
> +   && 
> dc->current_state->stream_status[0].plane_states[0]->format >= 
> SURFACE_PIXEL_FORMAT_GRPH_ARGB) {
> +   surface_size = 
> dc->current_state->stream_status[0].plane_states[0]->plane_size.surface_pitch 
> *
> +   
> dc->current_state->stream_status[0].plane_states[0]->plane_size.surface_size.height
>  *
> +   
> (dc->current_state->stream_status[0].plane_states[0]->format >= 
> SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ?
> +8 : 4);
> +   } else {
> +   // TODO: remove hard code size
> +   surface_size = 128 * 1024 * 1024;
> +   }
> +
> // TODO: remove hard code size
> if (surface_size < 128 * 1024 * 1024) {
> refresh_hz = div_u64((unsigned long long) 
> dc->current_state->streams[0]->timing.pix_clk_100hz *
> --
> 2.25.4
>
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH] drm/amdgpu/display: re-add surface size calculation in dcn30_hwseq.c

2020-10-26 Thread Alex Deucher 
This is required for MALL.  Was accidently removed in PRS update.

Fixes: 48e48e598478 ("drm/amd/display: Disable idle optimization when PSR is 
enabled")
Fixes: 52f2e83e2fe5 ("drm/amdgpu/display: add MALL support (v2)")
Signed-off-by: Alex Deucher 
---
 .../gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c| 15 +++
 1 file changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
index f3ae208850b0..cc2eca8c9a62 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
@@ -715,6 +715,21 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, 
bool enable)
break;
}
 
+   if (dc->current_state->stream_count == 1 // single 
display only
+   && dc->current_state->stream_status[0].plane_count 
== 1 // single surface only
+   && 
dc->current_state->stream_status[0].plane_states[0]->address.page_table_base.quad_part
 == 0 // no VM
+   // Only 8 and 16 bit formats
+   && 
dc->current_state->stream_status[0].plane_states[0]->format <= 
SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F
+   && 
dc->current_state->stream_status[0].plane_states[0]->format >= 
SURFACE_PIXEL_FORMAT_GRPH_ARGB) {
+   surface_size = 
dc->current_state->stream_status[0].plane_states[0]->plane_size.surface_pitch *
+   
dc->current_state->stream_status[0].plane_states[0]->plane_size.surface_size.height
 *
+   
(dc->current_state->stream_status[0].plane_states[0]->format >= 
SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ?
+8 : 4);
+   } else {
+   // TODO: remove hard code size
+   surface_size = 128 * 1024 * 1024;
+   }
+
// TODO: remove hard code size
if (surface_size < 128 * 1024 * 1024) {
refresh_hz = div_u64((unsigned long long) 
dc->current_state->streams[0]->timing.pix_clk_100hz *
-- 
2.25.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx