From: Wesley Chalmers <wchal...@amd.com>
[WHY]
Disabling DPG should happen after setting watermarks and clocks
Signed-off-by: Wesley Chalmers <wchal...@amd.com>
Reviewed-by: Tony Cheng <tony.ch...@amd.com>
Acked-by: Qingqing Zhuo <qingqing.z...@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 5b7466a243b2..49dd310ed588 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1248,7 +1248,6 @@ static enum dc_status dc_commit_state_no_check(struct dc
*dc, struct dc_state *c
int i, k, l;
struct dc_stream_state *dc_streams[MAX_STREAMS] = {0};
- disable_dangling_plane(dc, context);
for (i = 0; i < context->stream_count; i++)
dc_streams[i] = context->streams[i];
@@ -1264,6 +1263,7 @@ static enum dc_status dc_commit_state_no_check(struct dc
*dc, struct dc_state *c
if (dc->optimize_seamless_boot_streams == 0)
dc->hwss.prepare_bandwidth(dc, context);
+ disable_dangling_plane(dc, context);
/* re-program planes for existing stream, in case we need to
* free up plane resource for later use
*/
--
2.17.1
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