On Tue, Sep 5, 2023 at 3:50 PM Mario Limonciello
wrote:
>
> This will allow base driver to dictate whether seamless should be
> enabled. No intended functional changes.
>
> Signed-off-by: Mario Limonciello
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 21 +
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 23 +--
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 2 --
> 4 files changed, 23 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 1f846650cc8b..7fb282574fa3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1306,6 +1306,7 @@ void amdgpu_device_pci_config_reset(struct
> amdgpu_device *adev);
> int amdgpu_device_pci_reset(struct amdgpu_device *adev);
> bool amdgpu_device_need_post(struct amdgpu_device *adev);
> bool amdgpu_sg_display_supported(struct amdgpu_device *adev);
> +bool amdgpu_seamless_boot_supported(struct amdgpu_device *adev);
> bool amdgpu_device_pcie_dynamic_switching_supported(void);
> bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev);
> bool amdgpu_device_aspm_support_quirk(void);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index d45f5ea57583..72a5f77fc7b4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -1271,6 +1271,27 @@ bool amdgpu_sg_display_supported(struct amdgpu_device
> *adev)
> return true;
> }
>
> +/*
> + * Check whether seamless boot is supported.
> + *
> + * So far we only support seamless boot on select ASICs.
> + * If everything goes well, we may consider expanding
> + * seamless boot to other ASICs.
> + */
> +bool amdgpu_seamless_boot_supported(struct amdgpu_device *adev)
amdgpu_device_seamless_boot_supported() for consistency with the rest
of the file.
Alex
> +{
> + switch (adev->ip_versions[DCE_HWIP][0]) {
> + case IP_VERSION(3, 0, 1):
> + if (!adev->mman.keep_stolen_vga_memory)
> + return true;
> + break;
> + default:
> + break;
> + }
> +
> + return false;
> +}
> +
> /*
> * Intel hosts such as Raptor Lake and Sapphire Rapids don't support dynamic
> * speed switching. Until we have confirmation from Intel that a specific
> host
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 1bb1a394f55f..8961e2ec3b51 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -1675,7 +1675,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
>
> init_data.flags.seamless_boot_edp_requested = false;
>
> - if (check_seamless_boot_capability(adev)) {
> + if (amdgpu_seamless_boot_supported(adev)) {
> init_data.flags.seamless_boot_edp_requested = true;
> init_data.flags.allow_seamless_boot_optimization = true;
> DRM_INFO("Seamless boot condition check passed\n");
> @@ -10924,27 +10924,6 @@ int amdgpu_dm_process_dmub_set_config_sync(
> return ret;
> }
>
> -/*
> - * Check whether seamless boot is supported.
> - *
> - * So far we only support seamless boot on CHIP_VANGOGH.
> - * If everything goes well, we may consider expanding
> - * seamless boot to other ASICs.
> - */
> -bool check_seamless_boot_capability(struct amdgpu_device *adev)
> -{
> - switch (adev->ip_versions[DCE_HWIP][0]) {
> - case IP_VERSION(3, 0, 1):
> - if (!adev->mman.keep_stolen_vga_memory)
> - return true;
> - break;
> - default:
> - break;
> - }
> -
> - return false;
> -}
> -
> bool dm_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd
> *cmd, enum dm_dmub_wait_type wait_type)
> {
> return dc_dmub_srv_cmd_run(ctx->dmub_srv, cmd, wait_type);
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
> index a2d34be82613..4c74245add90 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
> @@ -825,8 +825,6 @@ int amdgpu_dm_process_dmub_aux_transfer_sync(struct
> dc_context *ctx, unsigned in
> int amdgpu_dm_process_dmub_set_config_sync(struct dc_context *ctx, unsigned
> int link_index,
> struct set_config_cmd_payload
> *payload, enum set_config_status *operation_result);
>
> -bool check_seamless_boot_capability(struct amdgpu_device *adev);
> -
> struct dc_stream_state *
> create_validate_stream_for_sink(struct amdgpu_dm_connector
> *aconnector,
> const struct
