Re: [PATCH 3/8] drm/amdgpu: Vega10 doorbell index initialization
On Mon, Nov 26, 2018 at 5:51 PM Oak Zeng wrote:
>
> v2: Use enum definition instead of hardcoded value
> v3: Remove unused enum definition
>
> Change-Id: Ib72058337f0aa53adfc6c6aae5341a7cd665111a
> Signed-off-by: Oak Zeng
> Suggested-by: Felix Kuehling
> Suggested-by: Alex Deucher
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 14 --
> drivers/gpu/drm/amd/amdgpu/soc15.c | 1 +
> drivers/gpu/drm/amd/amdgpu/soc15.h | 1 +
> drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c | 28
>
> 4 files changed, 34 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 686652d..ea4dbcf 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -434,20 +434,14 @@ typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
> * default non-graphics QWORD index is 0xe0 - 0xFF inclusive
> */
>
> - /* sDMA engines reserved from 0xe0 -0xef */
> - AMDGPU_DOORBELL64_sDMA_ENGINE0= 0xE0,
> - AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xE1,
> - AMDGPU_DOORBELL64_sDMA_ENGINE1= 0xE8,
> - AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xE9,
> -
> /* For vega10 sriov, the sdma doorbell must be fixed as follow
> * to keep the same setting with host driver, or it will
> * happen conflicts
> */
> - AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0= 0xF0,
> - AMDGPU_VEGA10_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1,
> - AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1= 0xF2,
> - AMDGPU_VEGA10_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3,
> + AMDGPU_DOORBELL64_sDMA_ENGINE0= 0xF0,
> + AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1,
> + AMDGPU_DOORBELL64_sDMA_ENGINE1= 0xF2,
> + AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3,
>
> /* Interrupt handler */
> AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy
> interrupt ring buffer */
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
> b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index 4cc0dcb..cae25dd 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -613,6 +613,7 @@ static const struct amdgpu_asic_funcs soc15_asic_funcs =
> .flush_hdp = _flush_hdp,
> .invalidate_hdp = _invalidate_hdp,
> .need_full_reset = _need_full_reset,
> + .init_doorbell_index = _doorbell_index_init,
> };
>
> static int soc15_common_early_init(void *handle)
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h
> b/drivers/gpu/drm/amd/amdgpu/soc15.h
> index f8ad780..d37c57d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.h
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.h
> @@ -58,4 +58,5 @@ void soc15_program_register_sequence(struct amdgpu_device
> *adev,
> int vega10_reg_base_init(struct amdgpu_device *adev);
> int vega20_reg_base_init(struct amdgpu_device *adev);
>
> +void vega10_doorbell_index_init(struct amdgpu_device *adev);
> #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
> b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
> index c5c9b2b..422674b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
> @@ -56,4 +56,32 @@ int vega10_reg_base_init(struct amdgpu_device *adev)
> return 0;
> }
>
> +void vega10_doorbell_index_init(struct amdgpu_device *adev)
> +{
> + adev->doorbell_index.kiq = AMDGPU_DOORBELL64_KIQ;
> + adev->doorbell_index.mec_ring0 = AMDGPU_DOORBELL64_MEC_RING0;
> + adev->doorbell_index.mec_ring1 = AMDGPU_DOORBELL64_MEC_RING1;
> + adev->doorbell_index.mec_ring2 = AMDGPU_DOORBELL64_MEC_RING2;
> + adev->doorbell_index.mec_ring3 = AMDGPU_DOORBELL64_MEC_RING3;
> + adev->doorbell_index.mec_ring4 = AMDGPU_DOORBELL64_MEC_RING4;
> + adev->doorbell_index.mec_ring5 = AMDGPU_DOORBELL64_MEC_RING5;
> + adev->doorbell_index.mec_ring6 = AMDGPU_DOORBELL64_MEC_RING6;
> + adev->doorbell_index.mec_ring7 = AMDGPU_DOORBELL64_MEC_RING7;
> + adev->doorbell_index.userqueue_start =
> AMDGPU_DOORBELL64_USERQUEUE_START;
> + adev->doorbell_index.userqueue_end = AMDGPU_DOORBELL64_USERQUEUE_END;
> + adev->doorbell_index.gfx_ring0 = AMDGPU_DOORBELL64_GFX_RING0;
> + adev->doorbell_index.sdma_engine0 = AMDGPU_DOORBELL64_sDMA_ENGINE0;
> + adev->doorbell_index.sdma_engine1 = AMDGPU_DOORBELL64_sDMA_ENGINE1;
> + adev->doorbell_index.ih = AMDGPU_DOORBELL64_IH;
> + adev->doorbell_index.uvd_vce.uvd_ring0_1 =
> AMDGPU_DOORBELL64_UVD_RING0_1;
> + adev->doorbell_index.uvd_vce.uvd_ring2_3 =
> AMDGPU_DOORBELL64_UVD_RING2_3;
> + adev->doorbell_index.uvd_vce.uvd_ring4_5 =
> AMDGPU_DOORBELL64_UVD_RING4_5;
> + adev->doorbell_index.uvd_vce.uvd_ring6_7 =
>
[PATCH 3/8] drm/amdgpu: Vega10 doorbell index initialization
v2: Use enum definition instead of hardcoded value
v3: Remove unused enum definition
Change-Id: Ib72058337f0aa53adfc6c6aae5341a7cd665111a
Signed-off-by: Oak Zeng
Suggested-by: Felix Kuehling
Suggested-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 14 --
drivers/gpu/drm/amd/amdgpu/soc15.c | 1 +
drivers/gpu/drm/amd/amdgpu/soc15.h | 1 +
drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c | 28
4 files changed, 34 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 686652d..ea4dbcf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -434,20 +434,14 @@ typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
* default non-graphics QWORD index is 0xe0 - 0xFF inclusive
*/
- /* sDMA engines reserved from 0xe0 -0xef */
- AMDGPU_DOORBELL64_sDMA_ENGINE0= 0xE0,
- AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xE1,
- AMDGPU_DOORBELL64_sDMA_ENGINE1= 0xE8,
- AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xE9,
-
/* For vega10 sriov, the sdma doorbell must be fixed as follow
* to keep the same setting with host driver, or it will
* happen conflicts
*/
- AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0= 0xF0,
- AMDGPU_VEGA10_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1,
- AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1= 0xF2,
- AMDGPU_VEGA10_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3,
+ AMDGPU_DOORBELL64_sDMA_ENGINE0= 0xF0,
+ AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1,
+ AMDGPU_DOORBELL64_sDMA_ENGINE1= 0xF2,
+ AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3,
/* Interrupt handler */
AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy
interrupt ring buffer */
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 4cc0dcb..cae25dd 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -613,6 +613,7 @@ static const struct amdgpu_asic_funcs soc15_asic_funcs =
.flush_hdp = _flush_hdp,
.invalidate_hdp = _invalidate_hdp,
.need_full_reset = _need_full_reset,
+ .init_doorbell_index = _doorbell_index_init,
};
static int soc15_common_early_init(void *handle)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h
b/drivers/gpu/drm/amd/amdgpu/soc15.h
index f8ad780..d37c57d 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.h
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.h
@@ -58,4 +58,5 @@ void soc15_program_register_sequence(struct amdgpu_device
*adev,
int vega10_reg_base_init(struct amdgpu_device *adev);
int vega20_reg_base_init(struct amdgpu_device *adev);
+void vega10_doorbell_index_init(struct amdgpu_device *adev);
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
index c5c9b2b..422674b 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
@@ -56,4 +56,32 @@ int vega10_reg_base_init(struct amdgpu_device *adev)
return 0;
}
+void vega10_doorbell_index_init(struct amdgpu_device *adev)
+{
+ adev->doorbell_index.kiq = AMDGPU_DOORBELL64_KIQ;
+ adev->doorbell_index.mec_ring0 = AMDGPU_DOORBELL64_MEC_RING0;
+ adev->doorbell_index.mec_ring1 = AMDGPU_DOORBELL64_MEC_RING1;
+ adev->doorbell_index.mec_ring2 = AMDGPU_DOORBELL64_MEC_RING2;
+ adev->doorbell_index.mec_ring3 = AMDGPU_DOORBELL64_MEC_RING3;
+ adev->doorbell_index.mec_ring4 = AMDGPU_DOORBELL64_MEC_RING4;
+ adev->doorbell_index.mec_ring5 = AMDGPU_DOORBELL64_MEC_RING5;
+ adev->doorbell_index.mec_ring6 = AMDGPU_DOORBELL64_MEC_RING6;
+ adev->doorbell_index.mec_ring7 = AMDGPU_DOORBELL64_MEC_RING7;
+ adev->doorbell_index.userqueue_start =
AMDGPU_DOORBELL64_USERQUEUE_START;
+ adev->doorbell_index.userqueue_end = AMDGPU_DOORBELL64_USERQUEUE_END;
+ adev->doorbell_index.gfx_ring0 = AMDGPU_DOORBELL64_GFX_RING0;
+ adev->doorbell_index.sdma_engine0 = AMDGPU_DOORBELL64_sDMA_ENGINE0;
+ adev->doorbell_index.sdma_engine1 = AMDGPU_DOORBELL64_sDMA_ENGINE1;
+ adev->doorbell_index.ih = AMDGPU_DOORBELL64_IH;
+ adev->doorbell_index.uvd_vce.uvd_ring0_1 =
AMDGPU_DOORBELL64_UVD_RING0_1;
+ adev->doorbell_index.uvd_vce.uvd_ring2_3 =
AMDGPU_DOORBELL64_UVD_RING2_3;
+ adev->doorbell_index.uvd_vce.uvd_ring4_5 =
AMDGPU_DOORBELL64_UVD_RING4_5;
+ adev->doorbell_index.uvd_vce.uvd_ring6_7 =
AMDGPU_DOORBELL64_UVD_RING6_7;
+ adev->doorbell_index.uvd_vce.vce_ring0_1 =
AMDGPU_DOORBELL64_VCE_RING0_1;
+ adev->doorbell_index.uvd_vce.vce_ring2_3 =
AMDGPU_DOORBELL64_VCE_RING2_3;
+ adev->doorbell_index.uvd_vce.vce_ring4_5 =
AMDGPU_DOORBELL64_VCE_RING4_5;
+
[PATCH 3/8] drm/amdgpu: Vega10 doorbell index initialization
v2: Use enum definition instead of hardcoded value
Change-Id: Ib72058337f0aa53adfc6c6aae5341a7cd665111a
Signed-off-by: Oak Zeng
Suggested-by: Felix Kuehling
Suggested-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 1 +
drivers/gpu/drm/amd/amdgpu/soc15.h | 1 +
drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c | 28
3 files changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 4cc0dcb..cae25dd 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -613,6 +613,7 @@ static const struct amdgpu_asic_funcs soc15_asic_funcs =
.flush_hdp = _flush_hdp,
.invalidate_hdp = _invalidate_hdp,
.need_full_reset = _need_full_reset,
+ .init_doorbell_index = _doorbell_index_init,
};
static int soc15_common_early_init(void *handle)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h
b/drivers/gpu/drm/amd/amdgpu/soc15.h
index f8ad780..d37c57d 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.h
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.h
@@ -58,4 +58,5 @@ void soc15_program_register_sequence(struct amdgpu_device
*adev,
int vega10_reg_base_init(struct amdgpu_device *adev);
int vega20_reg_base_init(struct amdgpu_device *adev);
+void vega10_doorbell_index_init(struct amdgpu_device *adev);
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
index c5c9b2b..9ba8e02 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
@@ -56,4 +56,32 @@ int vega10_reg_base_init(struct amdgpu_device *adev)
return 0;
}
+void vega10_doorbell_index_init(struct amdgpu_device *adev)
+{
+ adev->doorbell_index.kiq = AMDGPU_DOORBELL64_KIQ;
+ adev->doorbell_index.mec_ring0 = AMDGPU_DOORBELL64_MEC_RING0;
+ adev->doorbell_index.mec_ring1 = AMDGPU_DOORBELL64_MEC_RING1;
+ adev->doorbell_index.mec_ring2 = AMDGPU_DOORBELL64_MEC_RING2;
+ adev->doorbell_index.mec_ring3 = AMDGPU_DOORBELL64_MEC_RING3;
+ adev->doorbell_index.mec_ring4 = AMDGPU_DOORBELL64_MEC_RING4;
+ adev->doorbell_index.mec_ring5 = AMDGPU_DOORBELL64_MEC_RING5;
+ adev->doorbell_index.mec_ring6 = AMDGPU_DOORBELL64_MEC_RING6;
+ adev->doorbell_index.mec_ring7 = AMDGPU_DOORBELL64_MEC_RING7;
+ adev->doorbell_index.userqueue_start =
AMDGPU_DOORBELL64_USERQUEUE_START;
+ adev->doorbell_index.userqueue_end = AMDGPU_DOORBELL64_USERQUEUE_END;
+ adev->doorbell_index.gfx_ring0 = AMDGPU_DOORBELL64_GFX_RING0;
+ adev->doorbell_index.sdma_engine0 =
AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0;
+ adev->doorbell_index.sdma_engine1 =
AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1;
+ adev->doorbell_index.ih = AMDGPU_DOORBELL64_IH;
+ adev->doorbell_index.uvd_vce.uvd_ring0_1 =
AMDGPU_DOORBELL64_UVD_RING0_1;
+ adev->doorbell_index.uvd_vce.uvd_ring2_3 =
AMDGPU_DOORBELL64_UVD_RING2_3;
+ adev->doorbell_index.uvd_vce.uvd_ring4_5 =
AMDGPU_DOORBELL64_UVD_RING4_5;
+ adev->doorbell_index.uvd_vce.uvd_ring6_7 =
AMDGPU_DOORBELL64_UVD_RING6_7;
+ adev->doorbell_index.uvd_vce.vce_ring0_1 =
AMDGPU_DOORBELL64_VCE_RING0_1;
+ adev->doorbell_index.uvd_vce.vce_ring2_3 =
AMDGPU_DOORBELL64_VCE_RING2_3;
+ adev->doorbell_index.uvd_vce.vce_ring4_5 =
AMDGPU_DOORBELL64_VCE_RING4_5;
+ adev->doorbell_index.uvd_vce.vce_ring6_7 =
AMDGPU_DOORBELL64_VCE_RING6_7;
+ /* In unit of dword doorbell */
+ adev->doorbell_index.max_assignment = AMDGPU_DOORBELL64_MAX_ASSIGNMENT
<< 1;
+}
--
2.7.4
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