Re: [PATCH 7/7] drm/amdgpu: tlbs invalidate replaced by kiq_pm4_funcs
The end result looks good, but you should consider re-ordering this
patch set.
That would clean things up and make review much easier.
Adding code first and then removing it later on in the same patch set is
not a good practice.
Regards,
Christian.
Am 10.01.20 um 01:04 schrieb Alex Sierra:
TLBs invalidation was removed from gmc_v9 and gmc_v10 files.
This implementation has been moved to kiq_pm4_funcs calls.
Change-Id: I66463e2e5fdf7611ef4a802eb517ae0d269987c3
Signed-off-by: Alex Sierra
---
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 32 ++
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 32 ++
2 files changed, 4 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index 8cf34c7bd416..09408b8b390f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -250,35 +250,6 @@ static bool gmc_v10_0_get_atc_vmid_pasid_mapping_info(
return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
}
-static int gmc_v10_0_invalidate_tlbs_with_kiq(struct amdgpu_device *adev,
- uint16_t pasid, uint32_t flush_type,
- bool all_hub)
-{
- signed long r;
- uint32_t seq;
- struct amdgpu_ring *ring = >gfx.kiq.ring;
-
- spin_lock(>gfx.kiq.ring_lock);
- amdgpu_ring_alloc(ring, 12); /* fence + invalidate_tlbs package*/
- amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
- amdgpu_ring_write(ring,
- PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
- PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
- PACKET3_INVALIDATE_TLBS_PASID(pasid) |
- PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
- amdgpu_fence_emit_polling(ring, );
- amdgpu_ring_commit(ring);
- spin_unlock(>gfx.kiq.ring_lock);
-
- r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout);
- if (r < 1) {
- DRM_ERROR("wait for kiq fence error: %ld.\n", r);
- return -ETIME;
- }
-
- return 0;
-}
-
/*
* GART
* VMID 0 is the physical GPU addresses as used by the kernel.
@@ -441,9 +412,10 @@ static int gmc_v10_0_flush_gpu_tlb_pasid(struct
amdgpu_device *adev,
uint16_t queried_pasid;
bool ret;
struct amdgpu_ring *ring = >gfx.kiq.ring;
+ struct amdgpu_kiq *kiq = >gfx.kiq;
if (amdgpu_emu_mode == 0 && ring->sched.ready)
- return gmc_v10_0_invalidate_tlbs_with_kiq(adev,
+ return kiq->pmf->kiq_invalidate_tlbs(ring,
pasid, flush_type, all_hub);
for (vmid = 1; vmid < 16; vmid++) {
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 7cc6f305bfa8..670b2b62789b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -455,35 +455,6 @@ static bool
gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev,
return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
}
-static int gmc_v9_0_invalidate_tlbs_with_kiq(struct amdgpu_device *adev,
- uint16_t pasid, uint32_t flush_type,
- bool all_hub)
-{
- signed long r;
- uint32_t seq;
- struct amdgpu_ring *ring = >gfx.kiq.ring;
-
- spin_lock(>gfx.kiq.ring_lock);
- amdgpu_ring_alloc(ring, 12); /* fence + invalidate_tlbs package*/
- amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
- amdgpu_ring_write(ring,
- PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
- PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
- PACKET3_INVALIDATE_TLBS_PASID(pasid) |
- PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
- amdgpu_fence_emit_polling(ring, );
- amdgpu_ring_commit(ring);
- spin_unlock(>gfx.kiq.ring_lock);
-
- r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout);
- if (r < 1) {
- DRM_ERROR("wait for kiq fence error: %ld.\n", r);
- return -ETIME;
- }
-
- return 0;
-}
-
/*
* GART
* VMID 0 is the physical GPU addresses as used by the kernel.
@@ -598,12 +569,13 @@ static int gmc_v9_0_flush_gpu_tlb_pasid(struct
amdgpu_device *adev,
uint16_t queried_pasid;
bool ret;
struct amdgpu_ring *ring = >gfx.kiq.ring;
+ struct amdgpu_kiq *kiq = >gfx.kiq;
if (adev->in_gpu_reset)
return -EIO;
if (ring->sched.ready)
- return gmc_v9_0_invalidate_tlbs_with_kiq(adev,
+ return kiq->pmf->kiq_invalidate_tlbs(ring,
pasid, flush_type, all_hub);
for (vmid = 1; vmid < 16; vmid++) {
[PATCH 7/7] drm/amdgpu: tlbs invalidate replaced by kiq_pm4_funcs
TLBs invalidation was removed from gmc_v9 and gmc_v10 files.
This implementation has been moved to kiq_pm4_funcs calls.
Change-Id: I66463e2e5fdf7611ef4a802eb517ae0d269987c3
Signed-off-by: Alex Sierra
---
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 32 ++
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 32 ++
2 files changed, 4 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index 8cf34c7bd416..09408b8b390f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -250,35 +250,6 @@ static bool gmc_v10_0_get_atc_vmid_pasid_mapping_info(
return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
}
-static int gmc_v10_0_invalidate_tlbs_with_kiq(struct amdgpu_device *adev,
- uint16_t pasid, uint32_t flush_type,
- bool all_hub)
-{
- signed long r;
- uint32_t seq;
- struct amdgpu_ring *ring = >gfx.kiq.ring;
-
- spin_lock(>gfx.kiq.ring_lock);
- amdgpu_ring_alloc(ring, 12); /* fence + invalidate_tlbs package*/
- amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
- amdgpu_ring_write(ring,
- PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
- PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
- PACKET3_INVALIDATE_TLBS_PASID(pasid) |
- PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
- amdgpu_fence_emit_polling(ring, );
- amdgpu_ring_commit(ring);
- spin_unlock(>gfx.kiq.ring_lock);
-
- r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout);
- if (r < 1) {
- DRM_ERROR("wait for kiq fence error: %ld.\n", r);
- return -ETIME;
- }
-
- return 0;
-}
-
/*
* GART
* VMID 0 is the physical GPU addresses as used by the kernel.
@@ -441,9 +412,10 @@ static int gmc_v10_0_flush_gpu_tlb_pasid(struct
amdgpu_device *adev,
uint16_t queried_pasid;
bool ret;
struct amdgpu_ring *ring = >gfx.kiq.ring;
+ struct amdgpu_kiq *kiq = >gfx.kiq;
if (amdgpu_emu_mode == 0 && ring->sched.ready)
- return gmc_v10_0_invalidate_tlbs_with_kiq(adev,
+ return kiq->pmf->kiq_invalidate_tlbs(ring,
pasid, flush_type, all_hub);
for (vmid = 1; vmid < 16; vmid++) {
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 7cc6f305bfa8..670b2b62789b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -455,35 +455,6 @@ static bool
gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev,
return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
}
-static int gmc_v9_0_invalidate_tlbs_with_kiq(struct amdgpu_device *adev,
- uint16_t pasid, uint32_t flush_type,
- bool all_hub)
-{
- signed long r;
- uint32_t seq;
- struct amdgpu_ring *ring = >gfx.kiq.ring;
-
- spin_lock(>gfx.kiq.ring_lock);
- amdgpu_ring_alloc(ring, 12); /* fence + invalidate_tlbs package*/
- amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
- amdgpu_ring_write(ring,
- PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
- PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
- PACKET3_INVALIDATE_TLBS_PASID(pasid) |
- PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
- amdgpu_fence_emit_polling(ring, );
- amdgpu_ring_commit(ring);
- spin_unlock(>gfx.kiq.ring_lock);
-
- r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout);
- if (r < 1) {
- DRM_ERROR("wait for kiq fence error: %ld.\n", r);
- return -ETIME;
- }
-
- return 0;
-}
-
/*
* GART
* VMID 0 is the physical GPU addresses as used by the kernel.
@@ -598,12 +569,13 @@ static int gmc_v9_0_flush_gpu_tlb_pasid(struct
amdgpu_device *adev,
uint16_t queried_pasid;
bool ret;
struct amdgpu_ring *ring = >gfx.kiq.ring;
+ struct amdgpu_kiq *kiq = >gfx.kiq;
if (adev->in_gpu_reset)
return -EIO;
if (ring->sched.ready)
- return gmc_v9_0_invalidate_tlbs_with_kiq(adev,
+ return kiq->pmf->kiq_invalidate_tlbs(ring,
pasid, flush_type, all_hub);
for (vmid = 1; vmid < 16; vmid++) {
--
2.17.1
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