RE: [PATCH v3 3/7] drm/amdgpu/vcn: sriov support for vcn_v4_0_3
[AMD Official Use Only - General] Thanks Leo. I'll restore the check for sriov before calling amdgpu_virt_alloc_mm_table(). That will make it consistent with other vcn ip versions. I'll retain the check for sriov inside amdgpu_virt_alloc_mm_table() as well, as a conservative check. Thanks, Samir -Original Message- From: Liu, Leo Sent: Tuesday, August 8, 2023 8:29 AM To: Dhume, Samir ; amd-gfx@lists.freedesktop.org Cc: Luo, Zhigang ; Chen, Guchun ; Wan, Gavin ; Lazar, Lijo ; Min, Frank ; Zhang, Hawking Subject: Re: [PATCH v3 3/7] drm/amdgpu/vcn: sriov support for vcn_v4_0_3 On 2023-07-28 15:15, Samir Dhume wrote: > initialization table handshake with mmsch > > Signed-off-by: Samir Dhume > --- > drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 257 +--- > 1 file changed, 233 insertions(+), 24 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c > b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c > index 411c1d802823..b978265b2d77 100644 > --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c > +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c > @@ -31,6 +31,7 @@ > #include "soc15d.h" > #include "soc15_hw_ip.h" > #include "vcn_v2_0.h" > +#include "mmsch_v4_0_3.h" > > #include "vcn/vcn_4_0_3_offset.h" > #include "vcn/vcn_4_0_3_sh_mask.h" > @@ -44,6 +45,7 @@ > #define VCN_VID_SOC_ADDRESS_2_0 0x1fb00 > #define VCN1_VID_SOC_ADDRESS_3_00x48300 > > +static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev); > static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev); > static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev); > static int vcn_v4_0_3_set_powergating_state(void *handle, @@ -130,6 > +132,10 @@ static int vcn_v4_0_3_sw_init(void *handle) > amdgpu_vcn_fwlog_init(>vcn.inst[i]); > } > > + r = amdgpu_virt_alloc_mm_table(adev); Since this function is not for bare-metal, please move amdgpu_sriov_vf() check from inside of the function to here, to avoid confusion. > + if (r) > + return r; > + > if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) > adev->vcn.pause_dpg_mode = vcn_v4_0_3_pause_dpg_mode; > > @@ -167,6 +173,8 @@ static int vcn_v4_0_3_sw_fini(void *handle) > drm_dev_exit(idx); > } > > + amdgpu_virt_free_mm_table(adev); Same as above. Regards, Leo > + > r = amdgpu_vcn_suspend(adev); > if (r) > return r; > @@ -189,33 +197,47 @@ static int vcn_v4_0_3_hw_init(void *handle) > struct amdgpu_ring *ring; > int i, r, vcn_inst; > > - for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { > - vcn_inst = GET_INST(VCN, i); > - ring = >vcn.inst[i].ring_enc[0]; > + if (amdgpu_sriov_vf(adev)) { > + r = vcn_v4_0_3_start_sriov(adev); > + if (r) > + goto done; > > - if (ring->use_doorbell) { > - adev->nbio.funcs->vcn_doorbell_range( > - adev, ring->use_doorbell, > - (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + > - 9 * vcn_inst, > - adev->vcn.inst[i].aid_id); > - > - WREG32_SOC15( > - VCN, GET_INST(VCN, ring->me), > - regVCN_RB1_DB_CTRL, > - ring->doorbell_index > - << > VCN_RB1_DB_CTRL__OFFSET__SHIFT | > - VCN_RB1_DB_CTRL__EN_MASK); > - > - /* Read DB_CTRL to flush the write DB_CTRL command. */ > - RREG32_SOC15( > - VCN, GET_INST(VCN, ring->me), > - regVCN_RB1_DB_CTRL); > + for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { > + ring = >vcn.inst[i].ring_enc[0]; > + ring->wptr = 0; > + ring->wptr_old = 0; > + vcn_v4_0_3_unified_ring_set_wptr(ring); > + ring->sched.ready = true; > } > + } else { > + for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { > + vcn_inst = GET_INST(VCN, i); > + ring = >vcn.inst[i].ring_enc[0]; > + > + if (ring->use_doorbell) { > + adev->nbio.funcs->vcn_doorbell_range( > +
Re: [PATCH v3 3/7] drm/amdgpu/vcn: sriov support for vcn_v4_0_3
On 2023-07-28 15:15, Samir Dhume wrote: initialization table handshake with mmsch Signed-off-by: Samir Dhume --- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 257 +--- 1 file changed, 233 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c index 411c1d802823..b978265b2d77 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c @@ -31,6 +31,7 @@ #include "soc15d.h" #include "soc15_hw_ip.h" #include "vcn_v2_0.h" +#include "mmsch_v4_0_3.h" #include "vcn/vcn_4_0_3_offset.h" #include "vcn/vcn_4_0_3_sh_mask.h" @@ -44,6 +45,7 @@ #define VCN_VID_SOC_ADDRESS_2_0 0x1fb00 #define VCN1_VID_SOC_ADDRESS_3_0 0x48300 +static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev); static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev); static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev); static int vcn_v4_0_3_set_powergating_state(void *handle, @@ -130,6 +132,10 @@ static int vcn_v4_0_3_sw_init(void *handle) amdgpu_vcn_fwlog_init(>vcn.inst[i]); } + r = amdgpu_virt_alloc_mm_table(adev); Since this function is not for bare-metal, please move amdgpu_sriov_vf() check from inside of the function to here, to avoid confusion. + if (r) + return r; + if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) adev->vcn.pause_dpg_mode = vcn_v4_0_3_pause_dpg_mode; @@ -167,6 +173,8 @@ static int vcn_v4_0_3_sw_fini(void *handle) drm_dev_exit(idx); } + amdgpu_virt_free_mm_table(adev); Same as above. Regards, Leo + r = amdgpu_vcn_suspend(adev); if (r) return r; @@ -189,33 +197,47 @@ static int vcn_v4_0_3_hw_init(void *handle) struct amdgpu_ring *ring; int i, r, vcn_inst; - for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { - vcn_inst = GET_INST(VCN, i); - ring = >vcn.inst[i].ring_enc[0]; + if (amdgpu_sriov_vf(adev)) { + r = vcn_v4_0_3_start_sriov(adev); + if (r) + goto done; - if (ring->use_doorbell) { - adev->nbio.funcs->vcn_doorbell_range( - adev, ring->use_doorbell, - (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + - 9 * vcn_inst, - adev->vcn.inst[i].aid_id); - - WREG32_SOC15( - VCN, GET_INST(VCN, ring->me), - regVCN_RB1_DB_CTRL, - ring->doorbell_index - << VCN_RB1_DB_CTRL__OFFSET__SHIFT | - VCN_RB1_DB_CTRL__EN_MASK); - - /* Read DB_CTRL to flush the write DB_CTRL command. */ - RREG32_SOC15( - VCN, GET_INST(VCN, ring->me), - regVCN_RB1_DB_CTRL); + for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { + ring = >vcn.inst[i].ring_enc[0]; + ring->wptr = 0; + ring->wptr_old = 0; + vcn_v4_0_3_unified_ring_set_wptr(ring); + ring->sched.ready = true; } + } else { + for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { + vcn_inst = GET_INST(VCN, i); + ring = >vcn.inst[i].ring_enc[0]; + + if (ring->use_doorbell) { + adev->nbio.funcs->vcn_doorbell_range( + adev, ring->use_doorbell, + (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + + 9 * vcn_inst, + adev->vcn.inst[i].aid_id); + + WREG32_SOC15( + VCN, GET_INST(VCN, ring->me), + regVCN_RB1_DB_CTRL, + ring->doorbell_index + << VCN_RB1_DB_CTRL__OFFSET__SHIFT | + VCN_RB1_DB_CTRL__EN_MASK); + + /* Read DB_CTRL to flush the write DB_CTRL command. */ + RREG32_SOC15( + VCN, GET_INST(VCN, ring->me), + regVCN_RB1_DB_CTRL); + } - r = amdgpu_ring_test_helper(ring); - if (r) - goto done; + r = amdgpu_ring_test_helper(ring); + if (r)
[PATCH v3 3/7] drm/amdgpu/vcn: sriov support for vcn_v4_0_3
initialization table handshake with mmsch Signed-off-by: Samir Dhume --- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 257 +--- 1 file changed, 233 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c index 411c1d802823..b978265b2d77 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c @@ -31,6 +31,7 @@ #include "soc15d.h" #include "soc15_hw_ip.h" #include "vcn_v2_0.h" +#include "mmsch_v4_0_3.h" #include "vcn/vcn_4_0_3_offset.h" #include "vcn/vcn_4_0_3_sh_mask.h" @@ -44,6 +45,7 @@ #define VCN_VID_SOC_ADDRESS_2_00x1fb00 #define VCN1_VID_SOC_ADDRESS_3_0 0x48300 +static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev); static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev); static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev); static int vcn_v4_0_3_set_powergating_state(void *handle, @@ -130,6 +132,10 @@ static int vcn_v4_0_3_sw_init(void *handle) amdgpu_vcn_fwlog_init(>vcn.inst[i]); } + r = amdgpu_virt_alloc_mm_table(adev); + if (r) + return r; + if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) adev->vcn.pause_dpg_mode = vcn_v4_0_3_pause_dpg_mode; @@ -167,6 +173,8 @@ static int vcn_v4_0_3_sw_fini(void *handle) drm_dev_exit(idx); } + amdgpu_virt_free_mm_table(adev); + r = amdgpu_vcn_suspend(adev); if (r) return r; @@ -189,33 +197,47 @@ static int vcn_v4_0_3_hw_init(void *handle) struct amdgpu_ring *ring; int i, r, vcn_inst; - for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { - vcn_inst = GET_INST(VCN, i); - ring = >vcn.inst[i].ring_enc[0]; + if (amdgpu_sriov_vf(adev)) { + r = vcn_v4_0_3_start_sriov(adev); + if (r) + goto done; - if (ring->use_doorbell) { - adev->nbio.funcs->vcn_doorbell_range( - adev, ring->use_doorbell, - (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + - 9 * vcn_inst, - adev->vcn.inst[i].aid_id); - - WREG32_SOC15( - VCN, GET_INST(VCN, ring->me), - regVCN_RB1_DB_CTRL, - ring->doorbell_index - << VCN_RB1_DB_CTRL__OFFSET__SHIFT | - VCN_RB1_DB_CTRL__EN_MASK); - - /* Read DB_CTRL to flush the write DB_CTRL command. */ - RREG32_SOC15( - VCN, GET_INST(VCN, ring->me), - regVCN_RB1_DB_CTRL); + for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { + ring = >vcn.inst[i].ring_enc[0]; + ring->wptr = 0; + ring->wptr_old = 0; + vcn_v4_0_3_unified_ring_set_wptr(ring); + ring->sched.ready = true; } + } else { + for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { + vcn_inst = GET_INST(VCN, i); + ring = >vcn.inst[i].ring_enc[0]; + + if (ring->use_doorbell) { + adev->nbio.funcs->vcn_doorbell_range( + adev, ring->use_doorbell, + (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + + 9 * vcn_inst, + adev->vcn.inst[i].aid_id); + + WREG32_SOC15( + VCN, GET_INST(VCN, ring->me), + regVCN_RB1_DB_CTRL, + ring->doorbell_index + << VCN_RB1_DB_CTRL__OFFSET__SHIFT | + VCN_RB1_DB_CTRL__EN_MASK); + + /* Read DB_CTRL to flush the write DB_CTRL command. */ + RREG32_SOC15( + VCN, GET_INST(VCN, ring->me), + regVCN_RB1_DB_CTRL); + } - r = amdgpu_ring_test_helper(ring); - if (r) - goto done; + r = amdgpu_ring_test_helper(ring); + if (r) + goto done; + } } done: @@ -813,6 +835,193 @@ static int vcn_v4_0_3_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, b return 0; }