[AMD Official Use Only - General]
OK, will do
-
Best Regards,
Thomas
-Original Message-
From: Zhang, Hawking
Sent: Tuesday, August 8, 2023 5:50 PM
To: Chai, Thomas ; amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao ; Chai, Thomas ; Yang,
Stanley ; Chai, Thomas ; Li, Candice
Subject: RE: [PATCH] drm/amdgpu: mode1 reset needs to recover mp1 for mp0
v13_0_10
[AMD Official Use Only - General]
Like other psp callback helper defined in amdgpu_psp.h, let's define a macro
called psp_fatal_error_recovery_quirk to wrap the psp function
(psp_v13_0_fatal_error_recovery_quirk)
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of YiPeng Chai
Sent: Tuesday, August 8, 2023 16:02
To: amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao ; Chai, Thomas ; Yang,
Stanley ; Chai, Thomas ; Li, Candice
; Zhang, Hawking
Subject: [PATCH] drm/amdgpu: mode1 reset needs to recover mp1 for mp0 v13_0_10
Mode1 reset needs to recover mp1 in fatal error case for mp0 v13_0_10.
Signed-off-by: YiPeng Chai
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 3 +++
drivers/gpu/drm/amd/amdgpu/psp_v13_0.c | 24 +++-
3 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index e8cbfacb5ac1..763242d702c2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -127,6 +127,7 @@ struct psp_funcs
int (*ring_destroy)(struct psp_context *psp,
enum psp_ring_type ring_type);
bool (*smu_reload_quirk)(struct psp_context *psp);
+ int (*pre_mode1_reset)(struct psp_context *psp);
int (*mode1_reset)(struct psp_context *psp);
int (*mem_training)(struct psp_context *psp, uint32_t ops);
uint32_t (*ring_get_wptr)(struct psp_context *psp); diff --git
a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 50c38f75769c..f59f0cc2ab5a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -2066,6 +2066,9 @@ static void amdgpu_ras_do_recovery(struct work_struct
*work)
if (ras->gpu_reset_flags &
AMDGPU_RAS_GPU_RESET_MODE1_RESET) {
ras->gpu_reset_flags &=
~AMDGPU_RAS_GPU_RESET_MODE1_RESET;
set_bit(AMDGPU_NEED_FULL_RESET,
_context.flags);
+
+ if (adev->psp.funcs &&
adev->psp.funcs->pre_mode1_reset)
+
adev->psp.funcs->pre_mode1_reset(>psp);
}
}
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
index 58db1ee631b3..65c44c7d2b12 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
@@ -691,6 +691,27 @@ static int psp_v13_0_vbflash_status(struct psp_context
*psp)
return RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115); }
+static int psp_v13_0_pre_mode1_reset(struct psp_context *psp) {
+ struct amdgpu_device *adev = psp->adev;
+
+ if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 10)) {
+ uint32_t reg_data;
+ /* MP1 fatal error: trigger PSP dram read to unhalt PSP
+* during MP1 triggered sync flood.
+*/
+ reg_data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67);
+ WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, reg_data + 0x10);
+
+ /* delay 1000ms for the mode1 reset for fatal error
+* to be recovered back.
+*/
+ msleep(1000);
+ }
+
+ return 0;
+}
+
static const struct psp_funcs psp_v13_0_funcs = {
.init_microcode = psp_v13_0_init_microcode,
.bootloader_load_kdb = psp_v13_0_bootloader_load_kdb, @@ -710,7 +731,8
@@ static const struct psp_funcs psp_v13_0_funcs = {
.load_usbc_pd_fw = psp_v13_0_load_usbc_pd_fw,
.read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw,
.update_spirom = psp_v13_0_update_spirom,
- .vbflash_stat = psp_v13_0_vbflash_status
+ .vbflash_stat = psp_v13_0_vbflash_status,
+ .pre_mode1_reset = psp_v13_0_pre_mode1_reset,
};
void psp_v13_0_set_psp_funcs(struct psp_context *psp)
--
2.34.1
