RE: CZ EDC param and support

2017-05-01 Thread Panariti, David 
Thanks.
I’ve been using my Windwoes box way too much.  I need to set up email on my 
linux boxen.

davep

From: Christian König [mailto:deathsim...@vodafone.de]
Sent: Monday, May 01, 2017 10:40 AM
To: Panariti, David <david.panar...@amd.com>; Koenig, Christian 
<christian.koe...@amd.com>; gpudriverdevsupport <gpudriverdevsupp...@amd.com>; 
amd-gfx@lists.freedesktop.org
Subject: Re: CZ EDC param and support

I’ve gotten a comment that inline patches are preferred.
Well, they are. But you should send them with "git send-email" and not squashed 
together all in one mail :)

Otherwise I can't see how we should be able to apply them.

Additional to that at least I'm perfectly fine with attached patches as well.

Christian.

Am 28.04.2017 um 16:18 schrieb Panariti, David:
Actually, the attachment was an oversight.
It’s easier for me to attach, open the attachment and then delete the 
attachment.
I got only 2/3 this time.
I’ve gotten a comment that inline patches are preferred.

Sorry for the inconvenience.

davep

From: Koenig, Christian
Sent: Friday, April 28, 2017 4:06 AM
To: Panariti, David <david.panar...@amd.com><mailto:david.panar...@amd.com>; 
gpudriverdevsupport 
<gpudriverdevsupp...@amd.com><mailto:gpudriverdevsupp...@amd.com>; 
amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org>
Subject: Re: CZ EDC param and support

You somehow messed up the attachment.

Instead of individual files everything is squashed together as all-edc.patch.

Please fix that otherwise proper review won't be possible.

Christian.

Am 28.04.2017 um 00:13 schrieb Panariti, David:
The changes in the workarounds function use DRM_INFO rather than DRM_DEBUG 
because CZs with EDC are often used in embedded environments and any info can 
be useful especially in the case of an intermittent problem.

From e1ce383592c275b58ad95bd80b5479af8c1f9dae Mon Sep 17 00:00:00 2001
From: David Panariti <david.panar...@amd.com><mailto:david.panar...@amd.com>
Date: Fri, 14 Apr 2017 13:41:52 -0400
Subject: [PATCH 1/3] drm/amdgpu: Moved gfx_v8_0_select_se_sh() in lieu of
re-redundant prototype.

Will be needed for the rest of the EDC workarounds patch.

Change-Id: Ie586ab38a69e98a91c6cb5747e285ce8bfdd1c86
Signed-off-by: David Panariti 
<david.panar...@amd.com><mailto:david.panar...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 46 +--
1 file changed, 23 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 2ff5f19..27b57cb 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -1500,6 +1500,29 @@ static int gfx_v8_0_kiq_init(struct amdgpu_device *adev)
   return 0;
}
+static void gfx_v8_0_select_se_sh(struct amdgpu_device *adev,
+   u32 se_num, u32 
sh_num, u32 instance)
+{
+ u32 data;
+
+ if (instance == 0x)
+ data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 
INSTANCE_BROADCAST_WRITES, 1);
+ else
+ data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 
INSTANCE_INDEX, instance);
+
+ if (se_num == 0x)
+ data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 
SE_BROADCAST_WRITES, 1);
+ else
+ data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 
SE_INDEX, se_num);
+
+ if (sh_num == 0x)
+ data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 
SH_BROADCAST_WRITES, 1);
+ else
+ data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 
SH_INDEX, sh_num);
+
+ WREG32(mmGRBM_GFX_INDEX, data);
+}
+
static const u32 vgpr_init_compute_shader[] =
{
   0x7e000209, 0x7e020208,
@@ -3556,29 +3579,6 @@ static void gfx_v8_0_tiling_mode_table_init(struct 
amdgpu_device *adev)
   }
}
-static void gfx_v8_0_select_se_sh(struct amdgpu_device *adev,
-u32 se_num, 
u32 sh_num, u32 instance)
-{
-  u32 data;
-
-  if (instance == 0x)
-  data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 
INSTANCE_BROADCAST_WRITES, 1);
-  else
-  data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 
INSTANCE_INDEX, instance);
-
-  if (se_num == 0x)
-  data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 
SE_BROADCAST_WRITES, 1);
-  else
-  data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 
SE_INDEX, se_num);
-
-  if (sh_num == 0x)
-  data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 
SH_BROADCAST_WRITES, 1);
-  else
-  data = REG_SET_FIELD(data,

Re: CZ EDC param and support

2017-05-01 Thread Christian König 

I’ve gotten a comment that inline patches are preferred.

Well, they are. But you should send them with "git send-email" and not 
squashed together all in one mail :)


Otherwise I can't see how we should be able to apply them.

Additional to that at least I'm perfectly fine with attached patches as 
well.


Christian.

Am 28.04.2017 um 16:18 schrieb Panariti, David:


Actually, the attachment was an oversight.

It’s easier for me to attach, open the attachment and then delete the 
attachment.


I got only 2/3 this time.

I’ve gotten a comment that inline patches are preferred.

Sorry for the inconvenience.

davep

*From:*Koenig, Christian
*Sent:* Friday, April 28, 2017 4:06 AM
*To:* Panariti, David <david.panar...@amd.com>; gpudriverdevsupport 
<gpudriverdevsupp...@amd.com>; amd-gfx@lists.freedesktop.org

*Subject:* Re: CZ EDC param and support

You somehow messed up the attachment.

Instead of individual files everything is squashed together as 
all-edc.patch.


Please fix that otherwise proper review won't be possible.

Christian.

Am 28.04.2017 um 00:13 schrieb Panariti, David:

The changes in the workarounds function use DRM_INFO rather than
DRM_DEBUG because CZs with EDC are often used in embedded
environments and any info can be useful especially in the case of
an intermittent problem.

From e1ce383592c275b58ad95bd80b5479af8c1f9dae Mon Sep 17 00:00:00 2001

From: David Panariti <david.panar...@amd.com>
<mailto:david.panar...@amd.com>

Date: Fri, 14 Apr 2017 13:41:52 -0400

Subject: [PATCH 1/3] drm/amdgpu: Moved gfx_v8_0_select_se_sh() in
lieu of

re-redundant prototype.

Will be needed for the rest of the EDC workarounds patch.

Change-Id: Ie586ab38a69e98a91c6cb5747e285ce8bfdd1c86

Signed-off-by: David Panariti <david.panar...@amd.com>
<mailto:david.panar...@amd.com>

---

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 46
+--

1 file changed, 23 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

index 2ff5f19..27b57cb 100644

--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

@@ -1500,6 +1500,29 @@ static int gfx_v8_0_kiq_init(struct
amdgpu_device *adev)

   return 0;

}

+static void gfx_v8_0_select_se_sh(struct amdgpu_device *adev,

+   u32 se_num, u32 sh_num, u32 instance)

+{

+ u32 data;

+

+ if (instance == 0x)

+ data = REG_SET_FIELD(0,
GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);

+ else

+ data = REG_SET_FIELD(0,
GRBM_GFX_INDEX, INSTANCE_INDEX, instance);

+

+ if (se_num == 0x)

+ data = REG_SET_FIELD(data,
GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);

+ else

+ data = REG_SET_FIELD(data,
GRBM_GFX_INDEX, SE_INDEX, se_num);

+

+ if (sh_num == 0x)

+ data = REG_SET_FIELD(data,
GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);

+ else

+ data = REG_SET_FIELD(data,
GRBM_GFX_INDEX, SH_INDEX, sh_num);

+

+ WREG32(mmGRBM_GFX_INDEX, data);

+}

+

static const u32 vgpr_init_compute_shader[] =

{

   0x7e000209, 0x7e020208,

@@ -3556,29 +3579,6 @@ static void
gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)

   }

}

-static void gfx_v8_0_select_se_sh(struct amdgpu_device *adev,

-   u32 se_num, u32 sh_num, u32 instance)

-{

-  u32 data;

-

-  if (instance == 0x)

-  data = REG_SET_FIELD(0,
GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);

-  else

-  data = REG_SET_FIELD(0,
GRBM_GFX_INDEX, INSTANCE_INDEX, instance);

-

-  if (se_num == 0x)

-  data = REG_SET_FIELD(data,
GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);

-  else

-  data = REG_SET_FIELD(data,
GRBM_GFX_INDEX, SE_INDEX, se_num);

-

-  if (sh_num == 0x)

-  data = REG_SET_FIELD(data,
GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);

-  else

-  data = REG_SET_FIELD(data,
GRBM_GFX_INDEX, SH_INDEX, sh_num);

-

-  WREG32(mmGRBM_GFX_INDEX, data);

-}

-

static u32 gfx_v8_0_create_bitmask(u32 bit_width)

{

   return (u32)((1ULL << bit_width) - 1);

-- 


2.7.4

RE: CZ EDC param and support

2017-04-28 Thread Panariti, David 
Actually, the attachment was an oversight.
It's easier for me to attach, open the attachment and then delete the 
attachment.
I got only 2/3 this time.
I've gotten a comment that inline patches are preferred.

Sorry for the inconvenience.

davep

From: Koenig, Christian
Sent: Friday, April 28, 2017 4:06 AM
To: Panariti, David <david.panar...@amd.com>; gpudriverdevsupport 
<gpudriverdevsupp...@amd.com>; amd-gfx@lists.freedesktop.org
Subject: Re: CZ EDC param and support

You somehow messed up the attachment.

Instead of individual files everything is squashed together as all-edc.patch.

Please fix that otherwise proper review won't be possible.

Christian.

Am 28.04.2017 um 00:13 schrieb Panariti, David:
The changes in the workarounds function use DRM_INFO rather than DRM_DEBUG 
because CZs with EDC are often used in embedded environments and any info can 
be useful especially in the case of an intermittent problem.

>From e1ce383592c275b58ad95bd80b5479af8c1f9dae Mon Sep 17 00:00:00 2001
From: David Panariti <david.panar...@amd.com><mailto:david.panar...@amd.com>
Date: Fri, 14 Apr 2017 13:41:52 -0400
Subject: [PATCH 1/3] drm/amdgpu: Moved gfx_v8_0_select_se_sh() in lieu of
re-redundant prototype.

Will be needed for the rest of the EDC workarounds patch.

Change-Id: Ie586ab38a69e98a91c6cb5747e285ce8bfdd1c86
Signed-off-by: David Panariti 
<david.panar...@amd.com><mailto:david.panar...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 46 +--
1 file changed, 23 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 2ff5f19..27b57cb 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -1500,6 +1500,29 @@ static int gfx_v8_0_kiq_init(struct amdgpu_device *adev)
   return 0;
}
+static void gfx_v8_0_select_se_sh(struct amdgpu_device *adev,
+   u32 se_num, u32 
sh_num, u32 instance)
+{
+ u32 data;
+
+ if (instance == 0x)
+ data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 
INSTANCE_BROADCAST_WRITES, 1);
+ else
+ data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 
INSTANCE_INDEX, instance);
+
+ if (se_num == 0x)
+ data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 
SE_BROADCAST_WRITES, 1);
+ else
+ data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 
SE_INDEX, se_num);
+
+ if (sh_num == 0x)
+ data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 
SH_BROADCAST_WRITES, 1);
+ else
+ data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 
SH_INDEX, sh_num);
+
+ WREG32(mmGRBM_GFX_INDEX, data);
+}
+
static const u32 vgpr_init_compute_shader[] =
{
   0x7e000209, 0x7e020208,
@@ -3556,29 +3579,6 @@ static void gfx_v8_0_tiling_mode_table_init(struct 
amdgpu_device *adev)
   }
}
-static void gfx_v8_0_select_se_sh(struct amdgpu_device *adev,
-u32 se_num, 
u32 sh_num, u32 instance)
-{
-  u32 data;
-
-  if (instance == 0x)
-  data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 
INSTANCE_BROADCAST_WRITES, 1);
-  else
-  data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 
INSTANCE_INDEX, instance);
-
-  if (se_num == 0x)
-  data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 
SE_BROADCAST_WRITES, 1);
-  else
-  data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 
SE_INDEX, se_num);
-
-  if (sh_num == 0x)
-  data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 
SH_BROADCAST_WRITES, 1);
-  else
-  data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 
SH_INDEX, sh_num);
-
-  WREG32(mmGRBM_GFX_INDEX, data);
-}
-
static u32 gfx_v8_0_create_bitmask(u32 bit_width)
{
   return (u32)((1ULL << bit_width) - 1);
--
2.7.4


>From 38fac8cab73dbc07e0ee7599b52106bc09dd32ea Mon Sep 17 00:00:00 2001
From: David Panariti <david.panar...@amd.com><mailto:david.panar...@amd.com>
Date: Mon, 24 Apr 2017 11:05:45 -0400
Subject: [PATCH 2/3] drm/amdgpu: Complete Carrizo EDC (Error Detection and
Correction) workarounds.

The workarounds are unconditionally performed on CZs with EDC enabled.
EDC detects uncorrected ECC errors and uses data poisoning to prevent
corrupted compute results from being used (read).
EDC enabled CZs are often used in embedded environments.

Change-Id: I84c261785329beeb797f11efbe0ec35790f2996c
Signed-off-by: David Panariti 
<david.panar...@amd.com><mailto:david.panar...@amd.com>
---
drivers/gpu/d

Re: CZ EDC param and support

2017-04-28 Thread Christian König 

You somehow messed up the attachment.

Instead of individual files everything is squashed together as 
all-edc.patch.


Please fix that otherwise proper review won't be possible.

Christian.

Am 28.04.2017 um 00:13 schrieb Panariti, David:


The changes in the workarounds function use DRM_INFO rather than 
DRM_DEBUG because CZs with EDC are often used in embedded environments 
and any info can be useful especially in the case of an intermittent 
problem.


From e1ce383592c275b58ad95bd80b5479af8c1f9dae Mon Sep 17 00:00:00 2001

From: David Panariti 

Date: Fri, 14 Apr 2017 13:41:52 -0400

Subject: [PATCH 1/3] drm/amdgpu: Moved gfx_v8_0_select_se_sh() in lieu of

re-redundant prototype.

Will be needed for the rest of the EDC workarounds patch.

Change-Id: Ie586ab38a69e98a91c6cb5747e285ce8bfdd1c86

Signed-off-by: David Panariti 

---

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 46 
+--


1 file changed, 23 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c


index 2ff5f19..27b57cb 100644

--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

@@ -1500,6 +1500,29 @@ static int gfx_v8_0_kiq_init(struct 
amdgpu_device *adev)


   return 0;

}

+static void gfx_v8_0_select_se_sh(struct amdgpu_device *adev,

+   u32 se_num, u32 sh_num, u32 instance)

+{

+ u32 data;

+

+ if (instance == 0x)

+ data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 
INSTANCE_BROADCAST_WRITES, 1);


+ else

+ data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 
INSTANCE_INDEX, instance);


+

+ if (se_num == 0x)

+ data = REG_SET_FIELD(data, 
GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);


+ else

+ data = REG_SET_FIELD(data, 
GRBM_GFX_INDEX, SE_INDEX, se_num);


+

+ if (sh_num == 0x)

+ data = REG_SET_FIELD(data, 
GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);


+ else

+ data = REG_SET_FIELD(data, 
GRBM_GFX_INDEX, SH_INDEX, sh_num);


+

+ WREG32(mmGRBM_GFX_INDEX, data);

+}

+

static const u32 vgpr_init_compute_shader[] =

{

   0x7e000209, 0x7e020208,

@@ -3556,29 +3579,6 @@ static void 
gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)


   }

}

-static void gfx_v8_0_select_se_sh(struct amdgpu_device *adev,

-   u32 se_num, u32 sh_num, u32 instance)

-{

-  u32 data;

-

-  if (instance == 0x)

-  data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 
INSTANCE_BROADCAST_WRITES, 1);


-  else

-  data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 
INSTANCE_INDEX, instance);


-

-  if (se_num == 0x)

-  data = REG_SET_FIELD(data, 
GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);


-  else

-  data = REG_SET_FIELD(data, 
GRBM_GFX_INDEX, SE_INDEX, se_num);


-

-  if (sh_num == 0x)

-  data = REG_SET_FIELD(data, 
GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);


-  else

-  data = REG_SET_FIELD(data, 
GRBM_GFX_INDEX, SH_INDEX, sh_num);


-

-  WREG32(mmGRBM_GFX_INDEX, data);

-}

-

static u32 gfx_v8_0_create_bitmask(u32 bit_width)

{

   return (u32)((1ULL << bit_width) - 1);

--

2.7.4

From 38fac8cab73dbc07e0ee7599b52106bc09dd32ea Mon Sep 17 00:00:00 2001

From: David Panariti 

Date: Mon, 24 Apr 2017 11:05:45 -0400

Subject: [PATCH 2/3] drm/amdgpu: Complete Carrizo EDC (Error Detection and

Correction) workarounds.

The workarounds are unconditionally performed on CZs with EDC enabled.

EDC detects uncorrected ECC errors and uses data poisoning to prevent

corrupted compute results from being used (read).

EDC enabled CZs are often used in embedded environments.

Change-Id: I84c261785329beeb797f11efbe0ec35790f2996c

Signed-off-by: David Panariti 

---

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 148 
--


1 file changed, 106 insertions(+), 42 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c


index 27b57cb..2f5bf5f 100644

--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

@@ -1645,35 +1645,92 @@ static const u32 sgpr2_init_regs[] =

   mmCOMPUTE_USER_DATA_9, 0xedcedc09,

};

-static const u32 sec_ded_counter_registers[] =

-{

-  mmCPC_EDC_ATC_CNT,

-  mmCPC_EDC_SCRATCH_CNT,

-  mmCPC_EDC_UCODE_CNT,

-  mmCPF_EDC_ATC_CNT,

-  mmCPF_EDC_ROQ_CNT,

-