Re: [PATCH 01/26] drm/amdgpu: refactor MQD/HQD initialization v2

2017-04-12 Thread Andres Rodriguez 



On 2017-04-11 06:18 PM, Alex Deucher wrote:

On Thu, Apr 6, 2017 at 2:21 AM, Andres Rodriguez  wrote:

The MQD programming sequence currently exists in 3 different places.
Refactor it to absorb all the duplicates.

The success path remains mostly identical except for a slightly
different order in the non-kiq case. This shouldn't matter if the HQD
is disabled.

The error handling paths have been updated to deal with the new code
structure.

v2: the non-kiq path for gfxv8 was dropped in the rebase

Reviewed-by: Edward O'Callaghan 
Acked-by: Christian König 
Signed-off-by: Andres Rodriguez 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 447 ++
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 110 +
 2 files changed, 309 insertions(+), 248 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 185cb31..f67ef58 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -42,20 +42,22 @@
 #include "gca/gfx_7_2_sh_mask.h"

 #include "gmc/gmc_7_0_d.h"
 #include "gmc/gmc_7_0_sh_mask.h"

 #include "oss/oss_2_0_d.h"
 #include "oss/oss_2_0_sh_mask.h"

 #define GFX7_NUM_GFX_RINGS 1
 #define GFX7_NUM_COMPUTE_RINGS 8
+#define GFX7_MEC_HPD_SIZE  2048
+

 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev);
 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev);
 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev);

 MODULE_FIRMWARE("radeon/bonaire_pfp.bin");
 MODULE_FIRMWARE("radeon/bonaire_me.bin");
 MODULE_FIRMWARE("radeon/bonaire_ce.bin");
 MODULE_FIRMWARE("radeon/bonaire_rlc.bin");
 MODULE_FIRMWARE("radeon/bonaire_mec.bin");
@@ -2814,40 +2816,38 @@ static void gfx_v7_0_mec_fini(struct amdgpu_device 
*adev)
if (unlikely(r != 0))
dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", 
r);
amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);

amdgpu_bo_unref(>gfx.mec.hpd_eop_obj);
adev->gfx.mec.hpd_eop_obj = NULL;
}
 }

-#define MEC_HPD_SIZE 2048
-
 static int gfx_v7_0_mec_init(struct amdgpu_device *adev)
 {
int r;
u32 *hpd;

/*
 * KV:2 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 64 Queues total
 * CI/KB: 1 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 32 Queues total
 * Nonetheless, we assign only 1 pipe because all other pipes will
 * be handled by KFD
 */
adev->gfx.mec.num_mec = 1;
adev->gfx.mec.num_pipe = 1;
adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * 
adev->gfx.mec.num_pipe * 8;

if (adev->gfx.mec.hpd_eop_obj == NULL) {
r = amdgpu_bo_create(adev,
-adev->gfx.mec.num_mec 
*adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2,
+adev->gfx.mec.num_mec * 
adev->gfx.mec.num_pipe * GFX7_MEC_HPD_SIZE * 2,
 PAGE_SIZE, true,
 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
 >gfx.mec.hpd_eop_obj);
if (r) {
dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", 
r);
return r;
}
}

r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
@@ -2863,21 +2863,21 @@ static int gfx_v7_0_mec_init(struct amdgpu_device *adev)
return r;
}
r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **));
if (r) {
dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
gfx_v7_0_mec_fini(adev);
return r;
}

/* clear memory.  Not sure if this is required or not */
-   memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * 
MEC_HPD_SIZE * 2);
+   memset(hpd, 0, adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 
GFX7_MEC_HPD_SIZE * 2);

amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);

return 0;
 }

 struct hqd_registers
 {
u32 cp_mqd_base_addr;
@@ -2938,261 +2938,296 @@ struct bonaire_mqd
u32 restart[3];
u32 thread_trace_enable;
u32 reserved1;
u32 user_data[16];
u32 vgtcs_invoke_count[2];
struct hqd_registers queue_state;
u32 dequeue_cntr;
u32 interrupt_queue[64];
 };

-/**
- * gfx_v7_0_cp_compute_resume - setup the compute queue registers
- *
- * @adev: amdgpu_device pointer
- *
- * Program the compute queues and test them to make sure they
- * are working.
- * Returns 0 for success, error for failure.
- */
-static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev)
+static void gfx_v7_0_compute_pipe_init(struct amdgpu_device *adev, int

Re: [PATCH 01/26] drm/amdgpu: refactor MQD/HQD initialization v2

2017-04-12 Thread Andres Rodriguez 



On 2017-04-11 06:08 PM, Alex Deucher wrote:

On Thu, Apr 6, 2017 at 2:21 AM, Andres Rodriguez  wrote:

The MQD programming sequence currently exists in 3 different places.
Refactor it to absorb all the duplicates.

The success path remains mostly identical except for a slightly
different order in the non-kiq case. This shouldn't matter if the HQD
is disabled.

The error handling paths have been updated to deal with the new code
structure.

v2: the non-kiq path for gfxv8 was dropped in the rebase

Reviewed-by: Edward O'Callaghan 
Acked-by: Christian König 
Signed-off-by: Andres Rodriguez 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 447 ++
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 110 +
 2 files changed, 309 insertions(+), 248 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 185cb31..f67ef58 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -42,20 +42,22 @@
 #include "gca/gfx_7_2_sh_mask.h"

 #include "gmc/gmc_7_0_d.h"
 #include "gmc/gmc_7_0_sh_mask.h"

 #include "oss/oss_2_0_d.h"
 #include "oss/oss_2_0_sh_mask.h"

 #define GFX7_NUM_GFX_RINGS 1
 #define GFX7_NUM_COMPUTE_RINGS 8
+#define GFX7_MEC_HPD_SIZE  2048
+


Might want to split out that the rename of this define into a separate
patch so it can be applied early.  Could probably also split the gfx7
and gfx8 changes into two patches so they can be applied separately
separately so gfx7 doesn't have to be beholden to the flux in gfx8 at
the moment.



Done



 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev);
 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev);
 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev);

 MODULE_FIRMWARE("radeon/bonaire_pfp.bin");
 MODULE_FIRMWARE("radeon/bonaire_me.bin");
 MODULE_FIRMWARE("radeon/bonaire_ce.bin");
 MODULE_FIRMWARE("radeon/bonaire_rlc.bin");
 MODULE_FIRMWARE("radeon/bonaire_mec.bin");
@@ -2814,40 +2816,38 @@ static void gfx_v7_0_mec_fini(struct amdgpu_device 
*adev)
if (unlikely(r != 0))
dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", 
r);
amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);

amdgpu_bo_unref(>gfx.mec.hpd_eop_obj);
adev->gfx.mec.hpd_eop_obj = NULL;
}
 }

-#define MEC_HPD_SIZE 2048
-
 static int gfx_v7_0_mec_init(struct amdgpu_device *adev)
 {
int r;
u32 *hpd;

/*
 * KV:2 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 64 Queues total
 * CI/KB: 1 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 32 Queues total
 * Nonetheless, we assign only 1 pipe because all other pipes will
 * be handled by KFD
 */
adev->gfx.mec.num_mec = 1;
adev->gfx.mec.num_pipe = 1;
adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * 
adev->gfx.mec.num_pipe * 8;

if (adev->gfx.mec.hpd_eop_obj == NULL) {
r = amdgpu_bo_create(adev,
-adev->gfx.mec.num_mec 
*adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2,
+adev->gfx.mec.num_mec * 
adev->gfx.mec.num_pipe * GFX7_MEC_HPD_SIZE * 2,
 PAGE_SIZE, true,
 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
 >gfx.mec.hpd_eop_obj);
if (r) {
dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", 
r);
return r;
}
}

r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
@@ -2863,21 +2863,21 @@ static int gfx_v7_0_mec_init(struct amdgpu_device *adev)
return r;
}
r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **));
if (r) {
dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
gfx_v7_0_mec_fini(adev);
return r;
}

/* clear memory.  Not sure if this is required or not */
-   memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * 
MEC_HPD_SIZE * 2);
+   memset(hpd, 0, adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 
GFX7_MEC_HPD_SIZE * 2);

amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);

return 0;
 }

 struct hqd_registers
 {
u32 cp_mqd_base_addr;
@@ -2938,261 +2938,296 @@ struct bonaire_mqd
u32 restart[3];
u32 thread_trace_enable;
u32 reserved1;
u32 user_data[16];
u32 vgtcs_invoke_count[2];
struct hqd_registers queue_state;
u32 dequeue_cntr;
u32 interrupt_queue[64];
 };

-/**
- * gfx_v7_0_cp_compute_resume - setup the compute queue registers
- *
- *

Re: [PATCH 01/26] drm/amdgpu: refactor MQD/HQD initialization v2

2017-04-12 Thread Andres Rodriguez 

Your proposed patch looks good to me. You can add a:

Reviewed-by: Andres Rodriguez 

On 2017-04-11 06:18 PM, Alex Deucher wrote:

On Thu, Apr 6, 2017 at 2:21 AM, Andres Rodriguez  wrote:

The MQD programming sequence currently exists in 3 different places.
Refactor it to absorb all the duplicates.

The success path remains mostly identical except for a slightly
different order in the non-kiq case. This shouldn't matter if the HQD
is disabled.

The error handling paths have been updated to deal with the new code
structure.

v2: the non-kiq path for gfxv8 was dropped in the rebase

Reviewed-by: Edward O'Callaghan 
Acked-by: Christian König 
Signed-off-by: Andres Rodriguez 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 447 ++
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 110 +
 2 files changed, 309 insertions(+), 248 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 185cb31..f67ef58 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -42,20 +42,22 @@
 #include "gca/gfx_7_2_sh_mask.h"

 #include "gmc/gmc_7_0_d.h"
 #include "gmc/gmc_7_0_sh_mask.h"

 #include "oss/oss_2_0_d.h"
 #include "oss/oss_2_0_sh_mask.h"

 #define GFX7_NUM_GFX_RINGS 1
 #define GFX7_NUM_COMPUTE_RINGS 8
+#define GFX7_MEC_HPD_SIZE  2048
+

 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev);
 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev);
 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev);

 MODULE_FIRMWARE("radeon/bonaire_pfp.bin");
 MODULE_FIRMWARE("radeon/bonaire_me.bin");
 MODULE_FIRMWARE("radeon/bonaire_ce.bin");
 MODULE_FIRMWARE("radeon/bonaire_rlc.bin");
 MODULE_FIRMWARE("radeon/bonaire_mec.bin");
@@ -2814,40 +2816,38 @@ static void gfx_v7_0_mec_fini(struct amdgpu_device 
*adev)
if (unlikely(r != 0))
dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", 
r);
amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);

amdgpu_bo_unref(>gfx.mec.hpd_eop_obj);
adev->gfx.mec.hpd_eop_obj = NULL;
}
 }

-#define MEC_HPD_SIZE 2048
-
 static int gfx_v7_0_mec_init(struct amdgpu_device *adev)
 {
int r;
u32 *hpd;

/*
 * KV:2 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 64 Queues total
 * CI/KB: 1 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 32 Queues total
 * Nonetheless, we assign only 1 pipe because all other pipes will
 * be handled by KFD
 */
adev->gfx.mec.num_mec = 1;
adev->gfx.mec.num_pipe = 1;
adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * 
adev->gfx.mec.num_pipe * 8;

if (adev->gfx.mec.hpd_eop_obj == NULL) {
r = amdgpu_bo_create(adev,
-adev->gfx.mec.num_mec 
*adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2,
+adev->gfx.mec.num_mec * 
adev->gfx.mec.num_pipe * GFX7_MEC_HPD_SIZE * 2,
 PAGE_SIZE, true,
 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
 >gfx.mec.hpd_eop_obj);
if (r) {
dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", 
r);
return r;
}
}

r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
@@ -2863,21 +2863,21 @@ static int gfx_v7_0_mec_init(struct amdgpu_device *adev)
return r;
}
r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **));
if (r) {
dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
gfx_v7_0_mec_fini(adev);
return r;
}

/* clear memory.  Not sure if this is required or not */
-   memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * 
MEC_HPD_SIZE * 2);
+   memset(hpd, 0, adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 
GFX7_MEC_HPD_SIZE * 2);

amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);

return 0;
 }

 struct hqd_registers
 {
u32 cp_mqd_base_addr;
@@ -2938,261 +2938,296 @@ struct bonaire_mqd
u32 restart[3];
u32 thread_trace_enable;
u32 reserved1;
u32 user_data[16];
u32 vgtcs_invoke_count[2];
struct hqd_registers queue_state;
u32 dequeue_cntr;
u32 interrupt_queue[64];
 };

-/**
- * gfx_v7_0_cp_compute_resume - setup the compute queue registers
- *
- * @adev: amdgpu_device pointer
- *
- * Program the compute queues and test them to make sure they
- * are working.
- * Returns 0 for success, error for failure.
- */
-static int

Re: [PATCH 01/26] drm/amdgpu: refactor MQD/HQD initialization v2

2017-04-11 Thread Alex Deucher 
On Thu, Apr 6, 2017 at 2:21 AM, Andres Rodriguez  wrote:
> The MQD programming sequence currently exists in 3 different places.
> Refactor it to absorb all the duplicates.
>
> The success path remains mostly identical except for a slightly
> different order in the non-kiq case. This shouldn't matter if the HQD
> is disabled.
>
> The error handling paths have been updated to deal with the new code
> structure.
>
> v2: the non-kiq path for gfxv8 was dropped in the rebase
>
> Reviewed-by: Edward O'Callaghan 
> Acked-by: Christian König 
> Signed-off-by: Andres Rodriguez 
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 447 
> ++
>  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 110 +
>  2 files changed, 309 insertions(+), 248 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> index 185cb31..f67ef58 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> @@ -42,20 +42,22 @@
>  #include "gca/gfx_7_2_sh_mask.h"
>
>  #include "gmc/gmc_7_0_d.h"
>  #include "gmc/gmc_7_0_sh_mask.h"
>
>  #include "oss/oss_2_0_d.h"
>  #include "oss/oss_2_0_sh_mask.h"
>
>  #define GFX7_NUM_GFX_RINGS 1
>  #define GFX7_NUM_COMPUTE_RINGS 8
> +#define GFX7_MEC_HPD_SIZE  2048
> +
>
>  static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev);
>  static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev);
>  static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev);
>
>  MODULE_FIRMWARE("radeon/bonaire_pfp.bin");
>  MODULE_FIRMWARE("radeon/bonaire_me.bin");
>  MODULE_FIRMWARE("radeon/bonaire_ce.bin");
>  MODULE_FIRMWARE("radeon/bonaire_rlc.bin");
>  MODULE_FIRMWARE("radeon/bonaire_mec.bin");
> @@ -2814,40 +2816,38 @@ static void gfx_v7_0_mec_fini(struct amdgpu_device 
> *adev)
> if (unlikely(r != 0))
> dev_warn(adev->dev, "(%d) reserve HPD EOP bo 
> failed\n", r);
> amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
> amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
>
> amdgpu_bo_unref(>gfx.mec.hpd_eop_obj);
> adev->gfx.mec.hpd_eop_obj = NULL;
> }
>  }
>
> -#define MEC_HPD_SIZE 2048
> -
>  static int gfx_v7_0_mec_init(struct amdgpu_device *adev)
>  {
> int r;
> u32 *hpd;
>
> /*
>  * KV:2 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 64 Queues total
>  * CI/KB: 1 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 32 Queues total
>  * Nonetheless, we assign only 1 pipe because all other pipes will
>  * be handled by KFD
>  */
> adev->gfx.mec.num_mec = 1;
> adev->gfx.mec.num_pipe = 1;
> adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * 
> adev->gfx.mec.num_pipe * 8;
>
> if (adev->gfx.mec.hpd_eop_obj == NULL) {
> r = amdgpu_bo_create(adev,
> -adev->gfx.mec.num_mec 
> *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2,
> +adev->gfx.mec.num_mec * 
> adev->gfx.mec.num_pipe * GFX7_MEC_HPD_SIZE * 2,
>  PAGE_SIZE, true,
>  AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
>  >gfx.mec.hpd_eop_obj);
> if (r) {
> dev_warn(adev->dev, "(%d) create HDP EOP bo 
> failed\n", r);
> return r;
> }
> }
>
> r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
> @@ -2863,21 +2863,21 @@ static int gfx_v7_0_mec_init(struct amdgpu_device 
> *adev)
> return r;
> }
> r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **));
> if (r) {
> dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
> gfx_v7_0_mec_fini(adev);
> return r;
> }
>
> /* clear memory.  Not sure if this is required or not */
> -   memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * 
> MEC_HPD_SIZE * 2);
> +   memset(hpd, 0, adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 
> GFX7_MEC_HPD_SIZE * 2);
>
> amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
> amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
>
> return 0;
>  }
>
>  struct hqd_registers
>  {
> u32 cp_mqd_base_addr;
> @@ -2938,261 +2938,296 @@ struct bonaire_mqd
> u32 restart[3];
> u32 thread_trace_enable;
> u32 reserved1;
> u32 user_data[16];
> u32 vgtcs_invoke_count[2];
> struct hqd_registers queue_state;
> u32 dequeue_cntr;
> u32 interrupt_queue[64];
>  };
>
> -/**
> - * gfx_v7_0_cp_compute_resume - setup the compute queue registers
> - *
> - * @adev: amdgpu_device pointer
> - *
> - * Program the compute queues and test them to make

Re: [PATCH 01/26] drm/amdgpu: refactor MQD/HQD initialization v2

2017-04-11 Thread Alex Deucher 
On Thu, Apr 6, 2017 at 2:21 AM, Andres Rodriguez  wrote:
> The MQD programming sequence currently exists in 3 different places.
> Refactor it to absorb all the duplicates.
>
> The success path remains mostly identical except for a slightly
> different order in the non-kiq case. This shouldn't matter if the HQD
> is disabled.
>
> The error handling paths have been updated to deal with the new code
> structure.
>
> v2: the non-kiq path for gfxv8 was dropped in the rebase
>
> Reviewed-by: Edward O'Callaghan 
> Acked-by: Christian König 
> Signed-off-by: Andres Rodriguez 
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 447 
> ++
>  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 110 +
>  2 files changed, 309 insertions(+), 248 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> index 185cb31..f67ef58 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> @@ -42,20 +42,22 @@
>  #include "gca/gfx_7_2_sh_mask.h"
>
>  #include "gmc/gmc_7_0_d.h"
>  #include "gmc/gmc_7_0_sh_mask.h"
>
>  #include "oss/oss_2_0_d.h"
>  #include "oss/oss_2_0_sh_mask.h"
>
>  #define GFX7_NUM_GFX_RINGS 1
>  #define GFX7_NUM_COMPUTE_RINGS 8
> +#define GFX7_MEC_HPD_SIZE  2048
> +

Might want to split out that the rename of this define into a separate
patch so it can be applied early.  Could probably also split the gfx7
and gfx8 changes into two patches so they can be applied separately
separately so gfx7 doesn't have to be beholden to the flux in gfx8 at
the moment.

>
>  static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev);
>  static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev);
>  static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev);
>
>  MODULE_FIRMWARE("radeon/bonaire_pfp.bin");
>  MODULE_FIRMWARE("radeon/bonaire_me.bin");
>  MODULE_FIRMWARE("radeon/bonaire_ce.bin");
>  MODULE_FIRMWARE("radeon/bonaire_rlc.bin");
>  MODULE_FIRMWARE("radeon/bonaire_mec.bin");
> @@ -2814,40 +2816,38 @@ static void gfx_v7_0_mec_fini(struct amdgpu_device 
> *adev)
> if (unlikely(r != 0))
> dev_warn(adev->dev, "(%d) reserve HPD EOP bo 
> failed\n", r);
> amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
> amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
>
> amdgpu_bo_unref(>gfx.mec.hpd_eop_obj);
> adev->gfx.mec.hpd_eop_obj = NULL;
> }
>  }
>
> -#define MEC_HPD_SIZE 2048
> -
>  static int gfx_v7_0_mec_init(struct amdgpu_device *adev)
>  {
> int r;
> u32 *hpd;
>
> /*
>  * KV:2 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 64 Queues total
>  * CI/KB: 1 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 32 Queues total
>  * Nonetheless, we assign only 1 pipe because all other pipes will
>  * be handled by KFD
>  */
> adev->gfx.mec.num_mec = 1;
> adev->gfx.mec.num_pipe = 1;
> adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * 
> adev->gfx.mec.num_pipe * 8;
>
> if (adev->gfx.mec.hpd_eop_obj == NULL) {
> r = amdgpu_bo_create(adev,
> -adev->gfx.mec.num_mec 
> *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2,
> +adev->gfx.mec.num_mec * 
> adev->gfx.mec.num_pipe * GFX7_MEC_HPD_SIZE * 2,
>  PAGE_SIZE, true,
>  AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
>  >gfx.mec.hpd_eop_obj);
> if (r) {
> dev_warn(adev->dev, "(%d) create HDP EOP bo 
> failed\n", r);
> return r;
> }
> }
>
> r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
> @@ -2863,21 +2863,21 @@ static int gfx_v7_0_mec_init(struct amdgpu_device 
> *adev)
> return r;
> }
> r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **));
> if (r) {
> dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
> gfx_v7_0_mec_fini(adev);
> return r;
> }
>
> /* clear memory.  Not sure if this is required or not */
> -   memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * 
> MEC_HPD_SIZE * 2);
> +   memset(hpd, 0, adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 
> GFX7_MEC_HPD_SIZE * 2);
>
> amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
> amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
>
> return 0;
>  }
>
>  struct hqd_registers
>  {
> u32 cp_mqd_base_addr;
> @@ -2938,261 +2938,296 @@ struct bonaire_mqd
> u32 restart[3];
> u32 thread_trace_enable;
> u32 reserved1;
> u32 user_data[16];
> u32 vgtcs_invoke_count[2];
>