RE: [PATCH 07/14] drm/amdgpu/si: fix the dce6 for si macro

2016-08-30 Thread Deucher, Alexander 
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Huang Rui
> Sent: Tuesday, August 30, 2016 7:50 AM
> To: amd-gfx@lists.freedesktop.org; Deucher, Alexander
> Cc: Wang, Ken; Yu, Hui; Huang, Ray; Huan, Alvin
> Subject: [PATCH 07/14] drm/amdgpu/si: fix the dce6 for si macro
> 
> Change-Id: I3e5f42158c57d1ec722f713b129189bc5f802b11
> Signed-off-by: Huang Rui 
> ---
>  drivers/gpu/drm/amd/include/asic_reg/si/sid.h | 6 +-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/si/sid.h
> b/drivers/gpu/drm/amd/include/asic_reg/si/sid.h
> index 9609199..ced0390 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/si/sid.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/si/sid.h
> @@ -1968,7 +1968,11 @@
>  #define AMDGPU_MM_INDEX  0x
>  #define AMDGPU_MM_DATA   0x0001
> 
> -#define ASIC_IS_DCE6(adev) ((adev->asic_type == CHIP_VERDE))
> +#define ASIC_IS_DCE6(adev) ((adev->asic_type == CHIP_VERDE)|| \
> + (adev->asic_type == CHIP_TAHITI)   || \
> + (adev->asic_type == CHIP_PITCAIRN) || \
> + (adev->asic_type == CHIP_OLAND))
> +

Let's just drop this macro and check the asic types explicitly.

Alex

>  #define VERDE_NUM_CRTC 6
>  #define  BLACKOUT_MODE_MASK  0x0007
>  #define  VGA_RENDER_CONTROL  0xC0
> --
> 2.7.4
> 
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Re: [PATCH 07/14] drm/amdgpu/si: fix the dce6 for si macro

2016-08-30 Thread Huang Rui 
On Tue, Aug 30, 2016 at 10:17:58PM +0800, Deucher, Alexander wrote:
> > -Original Message-
> > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> > Of Huang Rui
> > Sent: Tuesday, August 30, 2016 7:50 AM
> > To: amd-gfx@lists.freedesktop.org; Deucher, Alexander
> > Cc: Wang, Ken; Yu, Hui; Huang, Ray; Huan, Alvin
> > Subject: [PATCH 07/14] drm/amdgpu/si: fix the dce6 for si macro
> > 
> > Change-Id: I3e5f42158c57d1ec722f713b129189bc5f802b11
> > Signed-off-by: Huang Rui 
> > ---
> >  drivers/gpu/drm/amd/include/asic_reg/si/sid.h | 6 +-
> >  1 file changed, 5 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/amd/include/asic_reg/si/sid.h
> > b/drivers/gpu/drm/amd/include/asic_reg/si/sid.h
> > index 9609199..ced0390 100644
> > --- a/drivers/gpu/drm/amd/include/asic_reg/si/sid.h
> > +++ b/drivers/gpu/drm/amd/include/asic_reg/si/sid.h
> > @@ -1968,7 +1968,11 @@
> >  #define AMDGPU_MM_INDEX0x
> >  #define AMDGPU_MM_DATA 0x0001
> > 
> > -#define ASIC_IS_DCE6(adev) ((adev->asic_type == CHIP_VERDE))
> > +#define ASIC_IS_DCE6(adev) ((adev->asic_type == CHIP_VERDE)|| \
> > +   (adev->asic_type == CHIP_TAHITI)   || \
> > +   (adev->asic_type == CHIP_PITCAIRN) || \
> > +   (adev->asic_type == CHIP_OLAND))
> > +
> 
> Let's just drop this macro and check the asic types explicitly.
> 

OK, will remove this macro in V2.

Thanks,
Rui
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Re: [PATCH] drm/amdgpu: record error code when ring test failed

2016-08-30 Thread Alex Deucher 
On Tue, Aug 30, 2016 at 11:04 AM, Christian König
 wrote:
> Am 30.08.2016 um 16:24 schrieb Deucher, Alexander:
>>>
>>> -Original Message-
>>> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
>>> Of Chunming Zhou
>>> Sent: Tuesday, August 30, 2016 5:59 AM
>>> To: amd-gfx@lists.freedesktop.org
>>> Cc: Zhou, David(ChunMing)
>>> Subject: [PATCH] drm/amdgpu: record error code when ring test failed
>>>
>>> Change-Id: I3a59f602a4d5ec42c8c184daa14eb8194b0dab9e
>>> Signed-off-by: Chunming Zhou 
>>> ---
>>>   drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 5 +++--
>>>   1 file changed, 3 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
>>> index f5810f7..8c17888 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
>>> @@ -280,7 +280,7 @@ void amdgpu_ib_pool_fini(struct amdgpu_device
>>> *adev)
>>>   int amdgpu_ib_ring_tests(struct amdgpu_device *adev)
>>>   {
>>> unsigned i;
>>> -   int r;
>>> +   int r, ret = 0;
>>>
>>> for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
>>> struct amdgpu_ring *ring = adev->rings[i];
>>> @@ -301,10 +301,11 @@ int amdgpu_ib_ring_tests(struct amdgpu_device
>>> *adev)
>>> } else {
>>> /* still not good, but we can live with
>>> it */
>>> DRM_ERROR("amdgpu: failed testing IB on
>>> ring %d (%d).\n", i, r);
>>> +   ret = r;
>>
>> Hmm, I think that was intentional so as not to fail completely even if
>> some of the engines aren't working.
>
>
> Yeah, I've had the same concern so I double checked it. The driver just
> prints an additional error message and continuous with the startup.
>
> In general I think it makes sense to return an error here, cause then we can
> easily identify cases where we need to fallback to a full engine reset.
>

Thanks for checking.

Reviewed-by: Alex Deucher 

> Christian.
>
>
>> Alex
>>
>>> }
>>> }
>>> }
>>> -   return 0;
>>> +   return ret;
>>>   }
>>>
>>>   /*
>>> --
>>> 1.9.1
>>>
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>
>
>
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Re: [PATCH 00/14] drm/amdgpu/si: Make SI DPM workable

2016-08-30 Thread Huang Rui 
On Tue, Aug 30, 2016 at 08:30:57PM +0800, Christian König wrote:
> For patch #4:
> > drm/amdgpu: remove useless functions of si dpm
> Maybe call that "remove unused function forward define".
> 
> And in general patches should at least have a commit message and not 
> just subject. A simple one liner like "The functions don't exists any 
> more." should be sufficient in this case.
> 

I see, you're right. "unused function" is better, I will update it at V2.

> Patch #10:
> 
> Well we probably shouldn't call those functions rv770_* any more.
> 

Yep, I would like to remove that function. Use "adev->mc.vram_type ==
AMDGPU_VRAM_TYPE_GDDR5" instead of mem_gddr5 flag.

> Apart from that the patches look good to me, but since I'm clearly not 
> the DPM expert they are Acked-by: Christian König 
> .
> 

Thank you,
Rui
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RE: [PATCH 10/14] drm/amdgpu: add rv770_get_memory_type to set the GDDR5 flag

2016-08-30 Thread Deucher, Alexander 
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Huang Rui
> Sent: Tuesday, August 30, 2016 7:50 AM
> To: amd-gfx@lists.freedesktop.org; Deucher, Alexander
> Cc: Wang, Ken; Yu, Hui; Huang, Ray; Huan, Alvin
> Subject: [PATCH 10/14] drm/amdgpu: add rv770_get_memory_type to set
> the GDDR5 flag
> 
> Add rv770_get_memory_type to set mem_gddr5 flag, because it will be
> used on the whole si dpm part.
> 
> Change-Id: I60f7ef38775c3b27e475f38f939905483fbb56f5
> Signed-off-by: Huang Rui 
> ---
>  drivers/gpu/drm/amd/amdgpu/si_dpm.c | 16 
>  1 file changed, 16 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
> b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
> index 5f1e5fe..563aeea 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
> @@ -6433,8 +6433,24 @@ static void si_set_pcie_lane_width_in_smc(struct
> amdgpu_device *adev,
>   }
>  }
> 
> +void rv770_get_memory_type(struct amdgpu_device *adev)

adev->mc.vram_type should be set in the gmc module.  Use that instead of 
pi->mem_gddr5.  See ci_dpm.c for example.

Alex

> +{
> + struct rv7xx_power_info *pi = rv770_get_pi(adev);
> + u32 tmp;
> +
> + tmp = RREG32(MC_SEQ_MISC0);
> +
> + if (((tmp & MC_SEQ_MISC0_GDDR5_MASK) >>
> MC_SEQ_MISC0_GDDR5_SHIFT) ==
> + MC_SEQ_MISC0_GDDR5_VALUE)
> + pi->mem_gddr5 = true;
> + else
> + pi->mem_gddr5 = false;
> +
> +}
> +
>  static void si_dpm_setup_asic(struct amdgpu_device *adev)
>  {
> + rv770_get_memory_type(adev);
>   si_read_clock_registers(adev);
>   si_enable_acpi_power_management(adev);
>  }
> --
> 2.7.4
> 
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RE: [PATCH 00/14] drm/amdgpu/si: Make SI DPM workable

2016-08-30 Thread Deucher, Alexander 
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Huang Rui
> Sent: Tuesday, August 30, 2016 7:50 AM
> To: amd-gfx@lists.freedesktop.org; Deucher, Alexander
> Cc: Wang, Ken; Yu, Hui; Huang, Ray; Huan, Alvin
> Subject: [PATCH 00/14] drm/amdgpu/si: Make SI DPM workable
> 
> Hi all,
> 
> These patchest resolve the DPM issues of SI.
> SI DPM doesn't work since it implemented, the following patches fixes
> serival issues to make SI DPM workable now.
> 
> Patch 1 -> 3: Add firmware version for checking firmware loading via
> sysfs.
> 
> Patch 4 -> 5: Refine the codes for si dpm.
> 
> Patch 6 -> 13: Fix the issues which impact DPM functionality.
> 
> Patch 14: Enable SI DPM by default.

A few comments on patches 7 and 10.  The rest are:
Reviewed-by: Alex Deucher 

> 
> Thanks,
> Rui
> 
> Huang Rui (14):
>   drm/amdgpu: add gfx v6 firmware versions for sysfs dump
>   drm/amdgpu: add gmc v6 firmware versions for sysfs dump
>   drm/amdgpu/si: add SI smc firmware versions for sysfs dump
>   drm/amdgpu: remove useless functions of si dpm
>   drm/amdgpu: use DRM print instead of printk
>   drm/amdgpu: fix oland and hainan asic specific handle at
> si_program_aspm
>   drm/amdgpu/si: fix the dce6 for si macro
>   drm/amdgpu: fix the tahiti specific value of DEEP_SLEEP_CLK_SEL field
>   drm/amdgpu: fix to miss adding thermal controller
>   drm/amdgpu: add rv770_get_memory_type to set the GDDR5 flag
>   drm/amdgpu: fix incorrect index of CG_FFCT_0 register
>   drm/amdgpu: introduce pcie port read/write entry
>   drm/amdgpu: fix incorrect reading method at si_get_current_pcie_speed
>   drm/amdgpu/si: enable SI DPM by default
> 
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h   |   4 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c|   2 +
>  drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c |  14 
>  drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c |   2 +
>  drivers/gpu/drm/amd/amdgpu/si.c   | 112 
> ++
>  drivers/gpu/drm/amd/amdgpu/si_dpm.c   |  54 +
>  drivers/gpu/drm/amd/amdgpu/si_smc.c   |   1 +
>  drivers/gpu/drm/amd/include/asic_reg/si/sid.h |   6 +-
>  8 files changed, 124 insertions(+), 71 deletions(-)
> 
> --
> 2.7.4
> 
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RE: [PATCH] drm/amdgpu: record error code when ring test failed

2016-08-30 Thread Deucher, Alexander 
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Chunming Zhou
> Sent: Tuesday, August 30, 2016 5:59 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhou, David(ChunMing)
> Subject: [PATCH] drm/amdgpu: record error code when ring test failed
> 
> Change-Id: I3a59f602a4d5ec42c8c184daa14eb8194b0dab9e
> Signed-off-by: Chunming Zhou 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> index f5810f7..8c17888 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> @@ -280,7 +280,7 @@ void amdgpu_ib_pool_fini(struct amdgpu_device
> *adev)
>  int amdgpu_ib_ring_tests(struct amdgpu_device *adev)
>  {
>   unsigned i;
> - int r;
> + int r, ret = 0;
> 
>   for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
>   struct amdgpu_ring *ring = adev->rings[i];
> @@ -301,10 +301,11 @@ int amdgpu_ib_ring_tests(struct amdgpu_device
> *adev)
>   } else {
>   /* still not good, but we can live with it */
>   DRM_ERROR("amdgpu: failed testing IB on
> ring %d (%d).\n", i, r);
> + ret = r;

Hmm, I think that was intentional so as not to fail completely even if some of 
the engines aren't working.

Alex

>   }
>   }
>   }
> - return 0;
> + return ret;
>  }
> 
>  /*
> --
> 1.9.1
> 
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RE: [PATCH 10/14] drm/amdgpu: add rv770_get_memory_type to set the GDDR5 flag

2016-08-30 Thread Deucher, Alexander 
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Huang Rui
> Sent: Tuesday, August 30, 2016 12:07 PM
> To: Deucher, Alexander
> Cc: Huan, Alvin; Wang, Ken; amd-gfx@lists.freedesktop.org; Yu, Hui
> Subject: Re: [PATCH 10/14] drm/amdgpu: add rv770_get_memory_type to
> set the GDDR5 flag
> 
> On Tue, Aug 30, 2016 at 10:21:21PM +0800, Deucher, Alexander wrote:
> > > -Original Message-
> > > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On
> Behalf
> > > Of Huang Rui
> > > Sent: Tuesday, August 30, 2016 7:50 AM
> > > To: amd-gfx@lists.freedesktop.org; Deucher, Alexander
> > > Cc: Wang, Ken; Yu, Hui; Huang, Ray; Huan, Alvin
> > > Subject: [PATCH 10/14] drm/amdgpu: add rv770_get_memory_type to
> set
> > > the GDDR5 flag
> > >
> > > Add rv770_get_memory_type to set mem_gddr5 flag, because it will be
> > > used on the whole si dpm part.
> > >
> > > Change-Id: I60f7ef38775c3b27e475f38f939905483fbb56f5
> > > Signed-off-by: Huang Rui 
> > > ---
> > >  drivers/gpu/drm/amd/amdgpu/si_dpm.c | 16 
> > >  1 file changed, 16 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
> > > b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
> > > index 5f1e5fe..563aeea 100644
> > > --- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
> > > +++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
> > > @@ -6433,8 +6433,24 @@ static void
> si_set_pcie_lane_width_in_smc(struct
> > > amdgpu_device *adev,
> > >   }
> > >  }
> > >
> > > +void rv770_get_memory_type(struct amdgpu_device *adev)
> >
> > adev->mc.vram_type should be set in the gmc module.  Use that instead of
> pi->mem_gddr5.  See ci_dpm.c for example.
> >
> 
> So should I use "adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5"
> check
> instead? I will update it in V2.

Sure.  Either that or set pi->mem_gddr5 = adev->mc.vram_type == 
AMDGPU_VRAM_TYPE_GDDR5;

Also, double check that the gmc6 module properly sets vram_type.  See the gmc 7 
module for reference.

Alex

> 
> Thanks,
> Rui
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Re: [PATCH 10/14] drm/amdgpu: add rv770_get_memory_type to set the GDDR5 flag

2016-08-30 Thread Huang Rui 
On Tue, Aug 30, 2016 at 10:21:21PM +0800, Deucher, Alexander wrote:
> > -Original Message-
> > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> > Of Huang Rui
> > Sent: Tuesday, August 30, 2016 7:50 AM
> > To: amd-gfx@lists.freedesktop.org; Deucher, Alexander
> > Cc: Wang, Ken; Yu, Hui; Huang, Ray; Huan, Alvin
> > Subject: [PATCH 10/14] drm/amdgpu: add rv770_get_memory_type to set
> > the GDDR5 flag
> > 
> > Add rv770_get_memory_type to set mem_gddr5 flag, because it will be
> > used on the whole si dpm part.
> > 
> > Change-Id: I60f7ef38775c3b27e475f38f939905483fbb56f5
> > Signed-off-by: Huang Rui 
> > ---
> >  drivers/gpu/drm/amd/amdgpu/si_dpm.c | 16 
> >  1 file changed, 16 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
> > b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
> > index 5f1e5fe..563aeea 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
> > @@ -6433,8 +6433,24 @@ static void si_set_pcie_lane_width_in_smc(struct
> > amdgpu_device *adev,
> > }
> >  }
> > 
> > +void rv770_get_memory_type(struct amdgpu_device *adev)
> 
> adev->mc.vram_type should be set in the gmc module.  Use that instead of 
> pi->mem_gddr5.  See ci_dpm.c for example.
> 

So should I use "adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5" check
instead? I will update it in V2.

Thanks,
Rui
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[PATCH v2 07/15] drm/amdgpu: fix oland and hainan asic specific handle at si_program_aspm

2016-08-30 Thread Huang Rui 
Acked-by: Christian König 
Reviewed-by: Alex Deucher 
Signed-off-by: Huang Rui 
---
 drivers/gpu/drm/amd/amdgpu/si.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index d2309b7..d5fc197 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -1602,7 +1602,7 @@ static void si_program_aspm(struct amdgpu_device *adev)
if (orig != data)
si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_1, data);
 
-   {
+   if ((adev->family != CHIP_OLAND) && (adev->family != 
CHIP_HAINAN)) {
orig = data = 
si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_0);
data &= ~PLL_RAMP_UP_TIME_0_MASK;
if (orig != data)
@@ -1651,11 +1651,15 @@ static void si_program_aspm(struct amdgpu_device *adev)
 
orig = data = si_pif_phy0_rreg(adev,PB0_PIF_CNTL);
data &= ~LS2_EXIT_TIME_MASK;
+   if ((adev->family == CHIP_OLAND) || (adev->family == 
CHIP_HAINAN))
+   data |= LS2_EXIT_TIME(5);
if (orig != data)
si_pif_phy0_wreg(adev,PB0_PIF_CNTL, data);
 
orig = data = si_pif_phy1_rreg(adev,PB1_PIF_CNTL);
data &= ~LS2_EXIT_TIME_MASK;
+   if ((adev->family == CHIP_OLAND) || (adev->family == 
CHIP_HAINAN))
+   data |= LS2_EXIT_TIME(5);
if (orig != data)
si_pif_phy1_wreg(adev,PB1_PIF_CNTL, data);
 
-- 
2.7.4

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[PATCH v2 08/15] drm/amdgpu/si: drop ASIC_IS_DCE6 macro on SI

2016-08-30 Thread Huang Rui 
Drop ASIC_IS_DCE6 macro, because it will check the asic types
explicitly in future.

Acked-by: Christian König 
Signed-off-by: Huang Rui 
---
 drivers/gpu/drm/amd/include/asic_reg/si/sid.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/include/asic_reg/si/sid.h 
b/drivers/gpu/drm/amd/include/asic_reg/si/sid.h
index 9609199..8c5608a 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/si/sid.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/si/sid.h
@@ -1968,7 +1968,6 @@
 #define AMDGPU_MM_INDEX0x
 #define AMDGPU_MM_DATA 0x0001
 
-#define ASIC_IS_DCE6(adev) ((adev->asic_type == CHIP_VERDE))
 #define VERDE_NUM_CRTC 6
 #defineBLACKOUT_MODE_MASK  0x0007
 #defineVGA_RENDER_CONTROL  0xC0
-- 
2.7.4

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[PATCH v2 05/15] drm/amdgpu: remove unused function forward define

2016-08-30 Thread Huang Rui 
The functions don't exists any more.

Reviewed-by: Alex Deucher 
Signed-off-by: Huang Rui 
---
 drivers/gpu/drm/amd/amdgpu/si_dpm.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c 
b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index d66435d..fa56184 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -1828,9 +1828,6 @@ struct evergreen_power_info *evergreen_get_pi(struct 
amdgpu_device *adev);
 struct ni_power_info *ni_get_pi(struct amdgpu_device *adev);
 struct  si_ps *si_get_ps(struct amdgpu_ps *rps);
 
-extern int si_mc_load_microcode(struct amdgpu_device *adev);
-extern void vce_v1_0_enable_mgcg(struct amdgpu_device *adev, bool enable);
-
 static int si_populate_voltage_value(struct amdgpu_device *adev,
 const struct atom_voltage_table *table,
 u16 value, SISLANDS_SMC_VOLTAGE_VALUE 
*voltage);
-- 
2.7.4

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[PATCH v2 06/15] drm/amdgpu: use DRM print instead of printk

2016-08-30 Thread Huang Rui 
Acked-by: Christian König 
Reviewed-by: Alex Deucher 
Signed-off-by: Huang Rui 
---
 drivers/gpu/drm/amd/amdgpu/si_dpm.c | 15 +++
 1 file changed, 7 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c 
b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index fa56184..c9b0989 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -7720,9 +7720,8 @@ static int si_dpm_init_microcode(struct amdgpu_device 
*adev)
 
 out:
if (err) {
-   printk(KERN_ERR
-  "si_smc: Failed to load firmware. err = %d\"%s\"\n",
-  err, fw_name);
+   DRM_ERROR("si_smc: Failed to load firmware. err = %d\"%s\"\n",
+ err, fw_name);
release_firmware(adev->pm.fw);
adev->pm.fw = NULL;
}
@@ -7941,15 +7940,15 @@ static void si_dpm_print_power_state(struct 
amdgpu_device *adev,

 amdgpu_dpm_print_class_info(rps->class, rps->class2);
 amdgpu_dpm_print_cap_info(rps->caps);
-printk("\tuvdvclk: %d dclk: %d\n", rps->vclk, rps->dclk);
+DRM_INFO("\tuvdvclk: %d dclk: %d\n", rps->vclk, rps->dclk);
 for (i = 0; i < ps->performance_level_count; i++) {
 pl = >performance_levels[i];
 if (adev->asic_type >= CHIP_TAHITI)
-printk("\t\tpower level %dsclk: %u mclk: %u vddc: 
%u vddci: %u pcie gen: %u\n",
-   i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, 
pl->pcie_gen + 1);
+DRM_INFO("\t\tpower level %dsclk: %u mclk: %u 
vddc: %u vddci: %u pcie gen: %u\n",
+i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, 
pl->pcie_gen + 1);
 else
-printk("\t\tpower level %dsclk: %u mclk: %u vddc: 
%u vddci: %u\n",
-   i, pl->sclk, pl->mclk, pl->vddc, pl->vddci);
+DRM_INFO("\t\tpower level %dsclk: %u mclk: %u 
vddc: %u vddci: %u\n",
+i, pl->sclk, pl->mclk, pl->vddc, pl->vddci);
 }
 amdgpu_dpm_print_ps_status(adev, rps);
 }
-- 
2.7.4

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[PATCH v2 11/15] drm/amdgpu: use vram_type instead of checking mem_gddr5 flag

2016-08-30 Thread Huang Rui 
For current design, it would better use vram_type member to check if
current vram is GDDR5. So remove the old mem_gddr5 flag.

Signed-off-by: Huang Rui 
---
 drivers/gpu/drm/amd/amdgpu/si_dpm.c | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c 
b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index ece2527..e1b2ab5 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -4375,7 +4375,7 @@ static u8 si_get_strobe_mode_settings(struct 
amdgpu_device *adev, u32 mclk)
if (mclk <= pi->mclk_strobe_mode_threshold)
strobe_mode = true;
 
-   if (pi->mem_gddr5)
+   if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
else
result = si_get_ddr3_mclk_frequency_ratio(mclk);
@@ -4965,7 +4965,7 @@ static int si_populate_smc_initial_state(struct 
amdgpu_device *adev,
 
table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
 
-   if (pi->mem_gddr5) {
+   if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
table->initialState.levels[0].strobeMode =
si_get_strobe_mode_settings(adev,

initial_state->performance_levels[0].mclk);
@@ -5237,7 +5237,7 @@ static int si_init_smc_table(struct amdgpu_device *adev)
if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
 
-   if (pi->mem_gddr5)
+   if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
 
if (adev->pm.dpm.platform_caps & 
ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
@@ -5414,7 +5414,7 @@ static int si_populate_mclk_value(struct amdgpu_device 
*adev,
mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
 
-   if (pi->mem_gddr5) {
+   if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
YCLK_POST_DIV(mpll_param.post_div);
@@ -5426,7 +5426,7 @@ static int si_populate_mclk_value(struct amdgpu_device 
*adev,
u32 tmp;
u32 reference_clock = adev->clock.mpll.reference_freq;
 
-   if (pi->mem_gddr5)
+   if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
freq_nom = memory_clock * 4;
else
freq_nom = memory_clock * 2;
@@ -5518,7 +5518,7 @@ static int si_convert_power_level_to_smc(struct 
amdgpu_device *adev,
level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
}
 
-   if (pi->mem_gddr5) {
+   if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
if (pl->mclk > pi->mclk_edc_enable_threshold)
level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
 
-- 
2.7.4

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[PATCH v2 10/15] drm/amdgpu: fix to miss adding thermal controller

2016-08-30 Thread Huang Rui 
Thermal controller isn't inited during si dpm sw_init phase.

Acked-by: Christian König 
Reviewed-by: Alex Deucher 
Signed-off-by: Huang Rui 
---
 drivers/gpu/drm/amd/amdgpu/si_dpm.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c 
b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index 5269c33..ece2527 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -7281,6 +7281,8 @@ static int si_parse_power_table(struct amdgpu_device 
*adev)
return -EINVAL;
power_info = (union power_info *)(mode_info->atom_context->bios + 
data_offset);
 
+   amdgpu_add_thermal_controller(adev);
+
state_array = (struct _StateArray *)
(mode_info->atom_context->bios + data_offset +
 le16_to_cpu(power_info->pplib.usStateArrayOffset));
-- 
2.7.4

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[PATCH v2 00/15] drm/amdgpu/si: Make SI DPM workable

2016-08-30 Thread Huang Rui 
Hi all,

These patchest resolve the DPM issues of SI.
SI DPM doesn't work since it implemented, the following patches fix
several issues to make SI DPM workable now.

Patch 1: Update SI firmware path to share it with radeon

Patch 2 -> 4: Add firmware version for checking firmware loading via
sysfs.

Patch 5 -> 6: Refine the codes for si dpm.

Patch 7 -> 14: Fix the issues which impact DPM functionality.

Patch 15: Enable SI DPM by default.


Changes from V1 -> V2:
- Add a patch to update SI dpm path to firmware/radeon
- Reword patch 5 to "unused function" according to Christian's comments 
- Drop ASIC_IS_DCE6 macro
- Modify patch 11 to use "adev->mc.vram_type" instead of pi->mem_gddr5


Thanks,
Rui

Huang Rui (15):
  drm/amdgpu/si: update si firmware path
  drm/amdgpu: add gfx v6 firmware versions for sysfs dump
  drm/amdgpu: add gmc v6 firmware versions for sysfs dump
  drm/amdgpu/si: add SI smc firmware versions for sysfs dump
  drm/amdgpu: remove unused function forward define
  drm/amdgpu: use DRM print instead of printk
  drm/amdgpu: fix oland and hainan asic specific handle at
si_program_aspm
  drm/amdgpu/si: drop ASIC_IS_DCE6 macro on SI
  drm/amdgpu: fix the tahiti specific value of DEEP_SLEEP_CLK_SEL field
  drm/amdgpu: fix to miss adding thermal controller
  drm/amdgpu: use vram_type instead of checking mem_gddr5 flag
  drm/amdgpu: fix incorrect index of CG_FFCT_0 register
  drm/amdgpu: introduce pcie port read/write entry
  drm/amdgpu: fix incorrect reading method at si_get_current_pcie_speed
  drm/amdgpu/si: enable SI DPM by default

 drivers/gpu/drm/amd/amdgpu/amdgpu.h   |   4 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c|   2 +
 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c |  14 
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c |   2 +
 drivers/gpu/drm/amd/amdgpu/si.c   | 112 ++
 drivers/gpu/drm/amd/amdgpu/si_dpm.c   |  60 +++---
 drivers/gpu/drm/amd/amdgpu/si_smc.c   |   1 +
 drivers/gpu/drm/amd/include/asic_reg/si/sid.h |   1 -
 8 files changed, 114 insertions(+), 82 deletions(-)

-- 
2.7.4

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[PATCH v2 01/15] drm/amdgpu/si: update si firmware path

2016-08-30 Thread Huang Rui 
SI firmware is shared with radeon for now, so update path with this
patch.

Signed-off-by: Huang Rui 
---
 drivers/gpu/drm/amd/amdgpu/si_dpm.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c 
b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index 076f6cd..d66435d 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -55,15 +55,15 @@
 
 #define BIOS_SCRATCH_40x5cd
 
-MODULE_FIRMWARE("amdgpu/tahiti_smc.bin");
+MODULE_FIRMWARE("radeon/tahiti_smc.bin");
 MODULE_FIRMWARE("radeon/tahiti_k_smc.bin");
-MODULE_FIRMWARE("amdgpu/pitcairn_smc.bin");
+MODULE_FIRMWARE("radeon/pitcairn_smc.bin");
 MODULE_FIRMWARE("radeon/pitcairn_k_smc.bin");
-MODULE_FIRMWARE("amdgpu/verde_smc.bin");
+MODULE_FIRMWARE("radeon/verde_smc.bin");
 MODULE_FIRMWARE("radeon/verde_k_smc.bin");
-MODULE_FIRMWARE("amdgpu/oland_smc.bin");
+MODULE_FIRMWARE("radeon/oland_smc.bin");
 MODULE_FIRMWARE("radeon/oland_k_smc.bin");
-MODULE_FIRMWARE("amdgpu/hainan_smc.bin");
+MODULE_FIRMWARE("radeon/hainan_smc.bin");
 MODULE_FIRMWARE("radeon/hainan_k_smc.bin");
 
 union power_info {
-- 
2.7.4

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[PATCH v2 02/15] drm/amdgpu: add gfx v6 firmware versions for sysfs dump

2016-08-30 Thread Huang Rui 
Acked-by: Christian König 
Reviewed-by: Alex Deucher 
Signed-off-by: Huang Rui 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index f3ad4aa..17a560c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -298,6 +298,8 @@ static int gfx_v6_0_init_microcode(struct amdgpu_device 
*adev)
const char *chip_name;
char fw_name[30];
int err;
+   const struct gfx_firmware_header_v1_0 *cp_hdr;
+   const struct rlc_firmware_header_v1_0 *rlc_hdr;
 
DRM_DEBUG("\n");
 
@@ -327,6 +329,9 @@ static int gfx_v6_0_init_microcode(struct amdgpu_device 
*adev)
err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
if (err)
goto out;
+   cp_hdr = (const struct gfx_firmware_header_v1_0 
*)adev->gfx.pfp_fw->data;
+   adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
+   adev->gfx.pfp_feature_version = 
le32_to_cpu(cp_hdr->ucode_feature_version);
 
snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
err = request_firmware(>gfx.me_fw, fw_name, adev->dev);
@@ -335,6 +340,9 @@ static int gfx_v6_0_init_microcode(struct amdgpu_device 
*adev)
err = amdgpu_ucode_validate(adev->gfx.me_fw);
if (err)
goto out;
+   cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
+   adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
+   adev->gfx.me_feature_version = 
le32_to_cpu(cp_hdr->ucode_feature_version);
 
snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
err = request_firmware(>gfx.ce_fw, fw_name, adev->dev);
@@ -343,12 +351,18 @@ static int gfx_v6_0_init_microcode(struct amdgpu_device 
*adev)
err = amdgpu_ucode_validate(adev->gfx.ce_fw);
if (err)
goto out;
+   cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
+   adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
+   adev->gfx.ce_feature_version = 
le32_to_cpu(cp_hdr->ucode_feature_version);
 
snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
err = request_firmware(>gfx.rlc_fw, fw_name, adev->dev);
if (err)
goto out;
err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
+   rlc_hdr = (const struct rlc_firmware_header_v1_0 
*)adev->gfx.rlc_fw->data;
+   adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
+   adev->gfx.rlc_feature_version = 
le32_to_cpu(rlc_hdr->ucode_feature_version);
 
 out:
if (err) {
-- 
2.7.4

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[PATCH v2 03/15] drm/amdgpu: add gmc v6 firmware versions for sysfs dump

2016-08-30 Thread Huang Rui 
Acked-by: Christian König 
Reviewed-by: Alex Deucher 
Signed-off-by: Huang Rui 
---
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index c18a4ef..1d2952b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -149,6 +149,8 @@ static int gmc_v6_0_mc_load_microcode(struct amdgpu_device 
*adev)
hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
 
amdgpu_ucode_print_mc_hdr(>header);
+
+   adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
new_io_mc_regs = (const __le32 *)
(adev->mc.fw->data + 
le32_to_cpu(hdr->io_debug_array_offset_bytes));
-- 
2.7.4

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Re: [PATCH] drm/amdgpu: record error code when ring test failed

2016-08-30 Thread zhoucm1 



On 2016年08月30日 22:24, Deucher, Alexander wrote:

-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
Of Chunming Zhou
Sent: Tuesday, August 30, 2016 5:59 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhou, David(ChunMing)
Subject: [PATCH] drm/amdgpu: record error code when ring test failed

Change-Id: I3a59f602a4d5ec42c8c184daa14eb8194b0dab9e
Signed-off-by: Chunming Zhou 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 5 +++--
  1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index f5810f7..8c17888 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -280,7 +280,7 @@ void amdgpu_ib_pool_fini(struct amdgpu_device
*adev)
  int amdgpu_ib_ring_tests(struct amdgpu_device *adev)
  {
unsigned i;
-   int r;
+   int r, ret = 0;

for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
struct amdgpu_ring *ring = adev->rings[i];
@@ -301,10 +301,11 @@ int amdgpu_ib_ring_tests(struct amdgpu_device
*adev)
} else {
/* still not good, but we can live with it */
DRM_ERROR("amdgpu: failed testing IB on
ring %d (%d).\n", i, r);
+   ret = r;

Hmm, I think that was intentional so as not to fail completely even if some of 
the engines aren't working.
After gpu reset, sometimes this case will happen, then gpu could hang if 
ignoring error.


Regards,
David Zhou


Alex


}
}
}
-   return 0;
+   return ret;
  }

  /*
--
1.9.1

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Re: [PATCH 2/2] drm/amdgpu: add gart recovery by gtt list

2016-08-30 Thread Christian König 

Am 30.08.2016 um 10:54 schrieb Chunming Zhou:

Change-Id: I8daf687d43b51d69f9be36cae8b265deb88e5754
Signed-off-by: Chunming Zhou 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu.h| 15 +++
  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  3 +++
  drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c   | 20 
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c| 14 +-
  4 files changed, 39 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 18bbfea..6ee9987 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -607,6 +607,20 @@ struct amdgpu_gart {
const struct amdgpu_gart_funcs *gart_funcs;
  };
  
+struct amdgpu_ttm_tt {

+   struct ttm_dma_tt   ttm;
+   struct amdgpu_device*adev;
+   u64 offset;
+   uint32_tpte_flags;
+   uint64_tuserptr;
+   struct mm_struct*usermm;
+   uint32_tuserflags;
+   spinlock_t  guptasklock;
+   struct list_headguptasks;
+   atomic_tmmu_invalidations;
+   struct list_headlist;
+};
+
  int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
  void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
  int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
@@ -620,6 +634,7 @@ void amdgpu_gart_unbind(struct amdgpu_device *adev, 
unsigned offset,
  int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset,
 int pages, struct page **pagelist,
 dma_addr_t *dma_addr, uint32_t flags);
+int amdgpu_gart_recovery(struct amdgpu_device *adev);
  
  /*

   * GPU MC structures, functions & helpers
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 6cd485a..0e475ed 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2247,6 +2247,9 @@ retry:
struct fence *fence = NULL, *next = NULL;
  
  			DRM_INFO("recover vram bo from shadow\n");

+   r = amdgpu_gart_recovery(adev);
+   if (r)
+   DRM_ERROR("gart recovery failed!!!\n");
mutex_lock(>shadow_list_lock);
list_for_each_entry_safe(bo, tmp, >shadow_list, 
shadow_list) {
amdgpu_recover_vram_from_shadow(adev, ring, bo, 
);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
index 921bce2..02695a6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
@@ -302,6 +302,26 @@ int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned 
offset,
return 0;
  }
  
+int amdgpu_gart_recovery(struct amdgpu_device *adev)

+{
+   struct amdgpu_ttm_tt *gtt, *tmp;
+   int r;
+
+   mutex_lock(>gtt_list_lock);
+   list_for_each_entry_safe(gtt, tmp, >gtt_list, list) {
+   r = amdgpu_gart_bind(adev, gtt->offset, gtt->ttm.ttm.num_pages,
+gtt->ttm.ttm.pages, gtt->ttm.dma_address,
+gtt->pte_flags);
+   if (r) {
+   mutex_unlock(>gtt_list_lock);
+   DRM_ERROR("failed to bind %lu pages at 0x%08X\n",
+ gtt->ttm.ttm.num_pages, 
(unsigned)gtt->offset);
+   return r;
+   }
+   }
+   mutex_unlock(>gtt_list_lock);
+   return 0;
+}


This function would better be in amdgpu_ttm.c, cause it uses the TTM 
handling internal structures for the recovery.


Call it something like amdgpu_ttm_recover_gart(), this way you also 
don't need to move the structure.



  /**
   * amdgpu_gart_init - init the driver info for managing the gart
   *
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index efeb9a5..431fe62 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -511,19 +511,6 @@ struct amdgpu_ttm_gup_task_list {
struct task_struct  *task;
  };
  
-struct amdgpu_ttm_tt {

-   struct ttm_dma_tt   ttm;
-   struct amdgpu_device*adev;
-   u64 offset;
-   uint64_tuserptr;
-   struct mm_struct*usermm;
-   uint32_tuserflags;
-   spinlock_t  guptasklock;
-   struct list_headguptasks;
-   atomic_tmmu_invalidations;
-   struct list_headlist;
-};
-
  int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
  {
struct amdgpu_ttm_tt *gtt = (void *)ttm;
@@ -668,6 +655,7 @@ static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,

[PATCH 10/14] drm/amdgpu: add rv770_get_memory_type to set the GDDR5 flag

2016-08-30 Thread Huang Rui 
Add rv770_get_memory_type to set mem_gddr5 flag, because it will be
used on the whole si dpm part.

Change-Id: I60f7ef38775c3b27e475f38f939905483fbb56f5
Signed-off-by: Huang Rui 
---
 drivers/gpu/drm/amd/amdgpu/si_dpm.c | 16 
 1 file changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c 
b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index 5f1e5fe..563aeea 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -6433,8 +6433,24 @@ static void si_set_pcie_lane_width_in_smc(struct 
amdgpu_device *adev,
}
 }
 
+void rv770_get_memory_type(struct amdgpu_device *adev)
+{
+   struct rv7xx_power_info *pi = rv770_get_pi(adev);
+   u32 tmp;
+
+   tmp = RREG32(MC_SEQ_MISC0);
+
+   if (((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT) ==
+   MC_SEQ_MISC0_GDDR5_VALUE)
+   pi->mem_gddr5 = true;
+   else
+   pi->mem_gddr5 = false;
+
+}
+
 static void si_dpm_setup_asic(struct amdgpu_device *adev)
 {
+   rv770_get_memory_type(adev);
si_read_clock_registers(adev);
si_enable_acpi_power_management(adev);
 }
-- 
2.7.4

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[PATCH 08/14] drm/amdgpu: fix the tahiti specific value of DEEP_SLEEP_CLK_SEL field

2016-08-30 Thread Huang Rui 
Change-Id: Ib5b6146fa712192dec120702831252d9221335bb
Signed-off-by: Huang Rui 
---
 drivers/gpu/drm/amd/amdgpu/si_dpm.c | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c 
b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index 1764c0b..90842c0 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -4173,7 +4173,13 @@ static void si_program_response_times(struct 
amdgpu_device *adev)
 static void si_program_ds_registers(struct amdgpu_device *adev)
 {
struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
-   u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */
+   u32 tmp;
+
+   /* DEEP_SLEEP_CLK_SEL field should be 0x10 on tahiti A0 */
+   if (adev->asic_type == CHIP_TAHITI && adev->rev_id == 0x0)
+   tmp = 0x10;
+   else
+   tmp = 0x1;
 
if (eg_pi->sclk_deep_sleep) {
WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), 
~DEEP_SLEEP_CLK_SEL_MASK);
-- 
2.7.4

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[PATCH 13/14] drm/amdgpu: fix incorrect reading method at si_get_current_pcie_speed

2016-08-30 Thread Huang Rui 
Change-Id: I7379d073c0e8123444deed9a91564de17b3fb722
Signed-off-by: Huang Rui 
---
 drivers/gpu/drm/amd/amdgpu/si_dpm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c 
b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index ce563cb..9b7d4bf 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -6242,7 +6242,7 @@ static u16 si_get_current_pcie_speed(struct amdgpu_device 
*adev)
 {
u32 speed_cntl;
 
-   speed_cntl = RREG32_PCIE(PCIE_LC_SPEED_CNTL) & 
LC_CURRENT_DATA_RATE_MASK;
+   speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & 
LC_CURRENT_DATA_RATE_MASK;
speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
 
return (u16)speed_cntl;
-- 
2.7.4

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[PATCH 11/14] drm/amdgpu: fix incorrect index of CG_FFCT_0 register

2016-08-30 Thread Huang Rui 
Change-Id: I8b1c7618b3043595c1f6d369dca693d4eaac412e
Signed-off-by: Huang Rui 
---
 drivers/gpu/drm/amd/amdgpu/si_dpm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c 
b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index 563aeea..ce563cb 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -4281,7 +4281,7 @@ static void si_program_tp(struct amdgpu_device *adev)
enum r600_td td = R600_TD_DFLT;
 
for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
-   WREG32(CG_FFCT_0 + (i * 10), (UTC_0(r600_utc[i]) | 
DTC_0(r600_dtc[i])));
+   WREG32(CG_FFCT_0 + i, (UTC_0(r600_utc[i]) | 
DTC_0(r600_dtc[i])));
 
if (td == R600_TD_AUTO)
WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
-- 
2.7.4

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Re: [PATCH] drm/amdgpu: record error code when ring test failed

2016-08-30 Thread Christian König 

Am 30.08.2016 um 11:59 schrieb Chunming Zhou:

Change-Id: I3a59f602a4d5ec42c8c184daa14eb8194b0dab9e
Signed-off-by: Chunming Zhou 


Reviewed-by: Christian König .


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 5 +++--
  1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index f5810f7..8c17888 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -280,7 +280,7 @@ void amdgpu_ib_pool_fini(struct amdgpu_device *adev)
  int amdgpu_ib_ring_tests(struct amdgpu_device *adev)
  {
unsigned i;
-   int r;
+   int r, ret = 0;
  
  	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {

struct amdgpu_ring *ring = adev->rings[i];
@@ -301,10 +301,11 @@ int amdgpu_ib_ring_tests(struct amdgpu_device *adev)
} else {
/* still not good, but we can live with it */
DRM_ERROR("amdgpu: failed testing IB on ring %d 
(%d).\n", i, r);
+   ret = r;
}
}
}
-   return 0;
+   return ret;
  }
  
  /*



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[PATCH 01/14] drm/amdgpu: add gfx v6 firmware versions for sysfs dump

2016-08-30 Thread Huang Rui 
Change-Id: I4af15bca9b20190803411afcd8711c10ec25ac56
Signed-off-by: Huang Rui 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index f3ad4aa..17a560c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -298,6 +298,8 @@ static int gfx_v6_0_init_microcode(struct amdgpu_device 
*adev)
const char *chip_name;
char fw_name[30];
int err;
+   const struct gfx_firmware_header_v1_0 *cp_hdr;
+   const struct rlc_firmware_header_v1_0 *rlc_hdr;
 
DRM_DEBUG("\n");
 
@@ -327,6 +329,9 @@ static int gfx_v6_0_init_microcode(struct amdgpu_device 
*adev)
err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
if (err)
goto out;
+   cp_hdr = (const struct gfx_firmware_header_v1_0 
*)adev->gfx.pfp_fw->data;
+   adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
+   adev->gfx.pfp_feature_version = 
le32_to_cpu(cp_hdr->ucode_feature_version);
 
snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
err = request_firmware(>gfx.me_fw, fw_name, adev->dev);
@@ -335,6 +340,9 @@ static int gfx_v6_0_init_microcode(struct amdgpu_device 
*adev)
err = amdgpu_ucode_validate(adev->gfx.me_fw);
if (err)
goto out;
+   cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
+   adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
+   adev->gfx.me_feature_version = 
le32_to_cpu(cp_hdr->ucode_feature_version);
 
snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
err = request_firmware(>gfx.ce_fw, fw_name, adev->dev);
@@ -343,12 +351,18 @@ static int gfx_v6_0_init_microcode(struct amdgpu_device 
*adev)
err = amdgpu_ucode_validate(adev->gfx.ce_fw);
if (err)
goto out;
+   cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
+   adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
+   adev->gfx.ce_feature_version = 
le32_to_cpu(cp_hdr->ucode_feature_version);
 
snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
err = request_firmware(>gfx.rlc_fw, fw_name, adev->dev);
if (err)
goto out;
err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
+   rlc_hdr = (const struct rlc_firmware_header_v1_0 
*)adev->gfx.rlc_fw->data;
+   adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
+   adev->gfx.rlc_feature_version = 
le32_to_cpu(rlc_hdr->ucode_feature_version);
 
 out:
if (err) {
-- 
2.7.4

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[PATCH 09/14] drm/amdgpu: fix to miss adding thermal controller

2016-08-30 Thread Huang Rui 
Thermal controller isn't inited during si dpm sw_init phase.

Change-Id: Ie9ddcd7026067e19bb0e300cf85c79948e7275a9
Signed-off-by: Huang Rui 
---
 drivers/gpu/drm/amd/amdgpu/si_dpm.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c 
b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index 90842c0..5f1e5fe 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -7281,6 +7281,8 @@ static int si_parse_power_table(struct amdgpu_device 
*adev)
return -EINVAL;
power_info = (union power_info *)(mode_info->atom_context->bios + 
data_offset);
 
+   amdgpu_add_thermal_controller(adev);
+
state_array = (struct _StateArray *)
(mode_info->atom_context->bios + data_offset +
 le16_to_cpu(power_info->pplib.usStateArrayOffset));
-- 
2.7.4

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[PATCH 12/14] drm/amdgpu: introduce pcie port read/write entry

2016-08-30 Thread Huang Rui 
This patch adds pcie port read/write entry, because it will be also
used on si dpm part.

Change-Id: Id8a3cf57233ac807c2e5a37fe1d310e2874b0814
Signed-off-by: Huang Rui 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h|   4 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |   2 +
 drivers/gpu/drm/amd/amdgpu/si.c| 106 +++--
 3 files changed, 60 insertions(+), 52 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 19c9a2e..6eb1d3d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -2043,6 +2043,8 @@ struct amdgpu_device {
spinlock_t pcie_idx_lock;
amdgpu_rreg_t   pcie_rreg;
amdgpu_wreg_t   pcie_wreg;
+   amdgpu_rreg_t   pciep_rreg;
+   amdgpu_wreg_t   pciep_wreg;
/* protects concurrent UVD register access */
spinlock_t uvd_ctx_idx_lock;
amdgpu_rreg_t   uvd_ctx_rreg;
@@ -2183,6 +2185,8 @@ bool amdgpu_device_has_dal_support(struct amdgpu_device 
*adev);
 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
+#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
+#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 8eb5396..a20a2b2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1544,6 +1544,8 @@ int amdgpu_device_init(struct amdgpu_device *adev,
adev->smc_wreg = _invalid_wreg;
adev->pcie_rreg = _invalid_rreg;
adev->pcie_wreg = _invalid_wreg;
+   adev->pciep_rreg = _invalid_rreg;
+   adev->pciep_wreg = _invalid_wreg;
adev->uvd_ctx_rreg = _invalid_rreg;
adev->uvd_ctx_wreg = _invalid_wreg;
adev->didt_rreg = _invalid_rreg;
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index d5fc197..fee76b8 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -905,6 +905,31 @@ static void si_pcie_wreg(struct amdgpu_device *adev, u32 
reg, u32 v)
spin_unlock_irqrestore(>pcie_idx_lock, flags);
 }
 
+u32 si_pciep_rreg(struct amdgpu_device *adev, u32 reg)
+{
+   unsigned long flags;
+   u32 r;
+
+   spin_lock_irqsave(>pcie_idx_lock, flags);
+   WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
+   (void)RREG32(PCIE_PORT_INDEX);
+   r = RREG32(PCIE_PORT_DATA);
+   spin_unlock_irqrestore(>pcie_idx_lock, flags);
+   return r;
+}
+
+void si_pciep_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
+{
+   unsigned long flags;
+
+   spin_lock_irqsave(>pcie_idx_lock, flags);
+   WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
+   (void)RREG32(PCIE_PORT_INDEX);
+   WREG32(PCIE_PORT_DATA, (v));
+   (void)RREG32(PCIE_PORT_DATA);
+   spin_unlock_irqrestore(>pcie_idx_lock, flags);
+}
+
 static u32 si_smc_rreg(struct amdgpu_device *adev, u32 reg)
 {
unsigned long flags;
@@ -1125,6 +1150,8 @@ static int si_common_early_init(void *handle)
adev->smc_wreg = _smc_wreg;
adev->pcie_rreg = _pcie_rreg;
adev->pcie_wreg = _pcie_wreg;
+   adev->pciep_rreg = _pciep_rreg;
+   adev->pciep_wreg = _pciep_wreg;
adev->uvd_ctx_rreg = NULL;
adev->uvd_ctx_wreg = NULL;
adev->didt_rreg = NULL;
@@ -1316,31 +1343,6 @@ static void si_init_golden_registers(struct 
amdgpu_device *adev)
}
 }
 
-u32 si_pciep_rreg(struct amdgpu_device *adev, u32 reg)
-{
-   unsigned long flags;
-   u32 r;
-
-   spin_lock_irqsave(>pcie_idx_lock, flags);
-   WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
-   (void)RREG32(PCIE_PORT_INDEX);
-   r = RREG32(PCIE_PORT_DATA);
-   spin_unlock_irqrestore(>pcie_idx_lock, flags);
-   return r;
-}
-
-void si_pciep_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
-{
-   unsigned long flags;
-
-   spin_lock_irqsave(>pcie_idx_lock, flags);
-   WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
-   (void)RREG32(PCIE_PORT_INDEX);
-   WREG32(PCIE_PORT_DATA, (v));
-   (void)RREG32(PCIE_PORT_DATA);
-   spin_unlock_irqrestore(>pcie_idx_lock, flags);
-}
-
 static void si_pcie_gen3_enable(struct amdgpu_device *adev)
 {
struct pci_dev *root = adev->pdev->bus->self;
@@ -1365,7 +1367,7 @@ static void si_pcie_gen3_enable(struct amdgpu_device 
*adev)
if (!(mask & (DRM_PCIE_SPEED_50 | DRM_PCIE_SPEED_80)))
return;
 
-   speed_cntl = si_pciep_rreg(adev,PCIE_LC_SPEED_CNTL);
+   speed_cntl

[PATCH] drm/amd/powerplay: fix issue vce dpm can't be enabled on tonga.

2016-08-30 Thread Rex Zhu 
Signed-off-by: Rex Zhu 

Change-Id: If7fa45cf3e81c31a8828f208ee9ba02bb9f18a1c
---
 .../amd/powerplay/hwmgr/tonga_clockpowergating.c   | 60 +-
 drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c  | 34 ++--
 drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h  |  2 +-
 3 files changed, 31 insertions(+), 65 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_clockpowergating.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_clockpowergating.c
index e58d038..6f2ac10 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_clockpowergating.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_clockpowergating.c
@@ -137,55 +137,23 @@ int tonga_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool 
bgate)
 int tonga_phm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
 {
struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
-   struct phm_set_power_state_input states;
-   const struct pp_power_state  *pcurrent;
-   struct pp_power_state  *requested;
-
-   pcurrent = hwmgr->current_ps;
-   requested = hwmgr->request_ps;
-
-   states.pcurrent_state = &(pcurrent->hardware);
-   states.pnew_state = &(requested->hardware);
-
-   if (phm_cf_want_vce_power_gating(hwmgr)) {
-   if (data->vce_power_gated != bgate) {
-   if (bgate) {
-   cgs_set_clockgating_state(
-   hwmgr->device,
-   AMD_IP_BLOCK_TYPE_VCE,
-   AMD_CG_STATE_UNGATE);
-   cgs_set_powergating_state(
-   hwmgr->device,
-   AMD_IP_BLOCK_TYPE_VCE,
-   AMD_PG_STATE_GATE);
-   tonga_enable_disable_vce_dpm(hwmgr, false);
-   data->vce_power_gated = true;
-   } else {
-   tonga_phm_powerup_vce(hwmgr);
-   data->vce_power_gated = false;
-   cgs_set_powergating_state(
-   hwmgr->device,
-   AMD_IP_BLOCK_TYPE_VCE,
-   AMD_PG_STATE_UNGATE);
-   cgs_set_clockgating_state(
-   hwmgr->device,
-   AMD_IP_BLOCK_TYPE_VCE,
-   AMD_PG_STATE_GATE);
-
-   tonga_update_vce_dpm(hwmgr, );
-   tonga_enable_disable_vce_dpm(hwmgr, true);
-   return 0;
-   }
-   }
-   } else {
-   tonga_update_vce_dpm(hwmgr, );
-   tonga_enable_disable_vce_dpm(hwmgr, true);
+
+   if (data->vce_power_gated == bgate)
return 0;
-   }
 
-   if (!data->vce_power_gated)
-   tonga_update_vce_dpm(hwmgr, );
+   data->vce_power_gated = bgate;
 
+   if (bgate) {
+   cgs_set_clockgating_state(hwmgr->device,
+   AMD_IP_BLOCK_TYPE_VCE,
+   AMD_CG_STATE_GATE);
+   tonga_update_vce_dpm(hwmgr, true);
+   } else {
+   tonga_update_vce_dpm(hwmgr, false);
+   cgs_set_clockgating_state(hwmgr->device,
+   AMD_IP_BLOCK_TYPE_VCE,
+   AMD_CG_STATE_UNGATE);
+   }
return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
index e09847d..2c1c4f8 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
@@ -5567,35 +5567,36 @@ int tonga_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool 
bgate)
return tonga_enable_disable_uvd_dpm(hwmgr, !bgate);
 }
 
-int tonga_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
+int tonga_update_vce_dpm(struct pp_hwmgr *hwmgr, bool bgate)
 {
-   const struct phm_set_power_state_input *states = (const struct 
phm_set_power_state_input *)input;
struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
-   const struct tonga_power_state *tonga_nps = 
cast_const_phw_tonga_power_state(states->pnew_state);
-   const struct tonga_power_state *tonga_cps = 
cast_const_phw_tonga_power_state(states->pcurrent_state);
-
uint32_t mm_boot_level_offset, mm_boot_level_value;
-   struct phm_ppt_v1_information *pptable_info = (struct 
phm_ppt_v1_information *)(hwmgr->pptable);
+   struct

Re: [PATCH 1/5] drm/amdgpu: add AMDGPU_GEM_CREATE_VRAM_LINEAR flag v2

2016-08-30 Thread Christian König 

Am 30.08.2016 um 03:49 schrieb Flora Cui:

On Tue, Aug 30, 2016 at 09:57:56AM +0900, Michel Dänzer wrote:

On 29/08/16 10:47 PM, Deucher, Alexander wrote:

From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
Of Christian König
Sent: Monday, August 29, 2016 5:20 AM

I still think this should be renamed AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS
or the anti-flag AMDGPU_GEM_CREATE_VRAM_SCATTER_GATHER to avoid
confusion with linear in the tiling sense.

Seconded.


and this could be the default option unless
AMDGPU_GEM_CREATE_VRAM_SCATTER_GATHER is specified.


Yeah, but then we won't correctly use it with existing userspace.

I will just rename it to AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS.

Christian.


--
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer
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[PATCH 1/2] drm/amdgpu: link all gtt when binding them

2016-08-30 Thread Chunming Zhou 
Change-Id: I5dc3f9003e706d3a142aadb559bd85f6e0f2a03f
Signed-off-by: Chunming Zhou 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h| 4 
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c| 9 +
 3 files changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index b17916d..18bbfea 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -2117,6 +2117,10 @@ struct amdgpu_device {
/* link all shadow bo */
struct list_headshadow_list;
struct mutexshadow_list_lock;
+   /* link all gtt */
+   struct mutexgtt_list_lock;
+   struct list_headgtt_list;
+
 };
 
 bool amdgpu_device_is_px(struct drm_device *dev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 9a6a1a9..6cd485a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1591,6 +1591,9 @@ int amdgpu_device_init(struct amdgpu_device *adev,
INIT_LIST_HEAD(>shadow_list);
mutex_init(>shadow_list_lock);
 
+   INIT_LIST_HEAD(>gtt_list);
+   mutex_init(>gtt_list_lock);
+
adev->rmmio_base = pci_resource_start(adev->pdev, 5);
adev->rmmio_size = pci_resource_len(adev->pdev, 5);
adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 2ba3c8d..efeb9a5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -521,6 +521,7 @@ struct amdgpu_ttm_tt {
spinlock_t  guptasklock;
struct list_headguptasks;
atomic_tmmu_invalidations;
+   struct list_headlist;
 };
 
 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
@@ -667,6 +668,9 @@ static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
  ttm->num_pages, (unsigned)gtt->offset);
return r;
}
+   mutex_lock(>adev->gtt_list_lock);
+   list_add_tail(>list, >adev->gtt_list);
+   mutex_unlock(>adev->gtt_list_lock);
return 0;
 }
 
@@ -681,6 +685,10 @@ static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
if (gtt->userptr)
amdgpu_ttm_tt_unpin_userptr(ttm);
 
+   mutex_lock(>adev->gtt_list_lock);
+   list_del_init(>list);
+   mutex_unlock(>adev->gtt_list_lock);
+
return 0;
 }
 
@@ -717,6 +725,7 @@ static struct ttm_tt *amdgpu_ttm_tt_create(struct 
ttm_bo_device *bdev,
kfree(gtt);
return NULL;
}
+   INIT_LIST_HEAD(>list);
return >ttm.ttm;
 }
 
-- 
1.9.1

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Re: [PATCH 1/3] drm/amd/amdgpu: VCE ring test fail during S4 on CI

2016-08-30 Thread Christian König 

Am 30.08.2016 um 03:21 schrieb jimqu:

Set up the VCE clock no matter dpm is enabled or not.


NAK, if DPM or powerplay is enabled you are totally confusing it by 
messing with the clocks manually.


Christian.



Change-Id: I68e315f8b62c6e3a8636bc5e14036ecc11d980b4
Signed-off-by: JimQu 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 7 ++-
  1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
index 9b71d6c..50993df 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
@@ -812,11 +812,13 @@ int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring)
unsigned i;
int r;
  
+	amdgpu_asic_set_vce_clocks(adev, 53300, 4);

+
r = amdgpu_ring_alloc(ring, 16);
if (r) {
DRM_ERROR("amdgpu: vce failed to lock ring %d (%d).\n",
  ring->idx, r);
-   return r;
+   goto done;
}
amdgpu_ring_write(ring, VCE_CMD_END);
amdgpu_ring_commit(ring);
@@ -836,6 +838,9 @@ int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring)
r = -ETIMEDOUT;
}
  
+done:

+   amdgpu_asic_set_vce_clocks(adev, 0, 0);
+
return r;
  }
  



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gart table recovery V2

2016-08-30 Thread Chunming Zhou 
save gtt info by list, re-bind gtt after gpu reset.
V2:
spinlock instead of mutex.
rename function name.
recover gart table ahead of ring test.

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[PATCH] drm/amdgpu: record error code when ring test failed

2016-08-30 Thread Chunming Zhou 
Change-Id: I3a59f602a4d5ec42c8c184daa14eb8194b0dab9e
Signed-off-by: Chunming Zhou 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index f5810f7..8c17888 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -280,7 +280,7 @@ void amdgpu_ib_pool_fini(struct amdgpu_device *adev)
 int amdgpu_ib_ring_tests(struct amdgpu_device *adev)
 {
unsigned i;
-   int r;
+   int r, ret = 0;
 
for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
struct amdgpu_ring *ring = adev->rings[i];
@@ -301,10 +301,11 @@ int amdgpu_ib_ring_tests(struct amdgpu_device *adev)
} else {
/* still not good, but we can live with it */
DRM_ERROR("amdgpu: failed testing IB on ring %d 
(%d).\n", i, r);
+   ret = r;
}
}
}
-   return 0;
+   return ret;
 }
 
 /*
-- 
1.9.1

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Re: [PATCH 1/2] drm/amdgpu: link all gtt when binding them

2016-08-30 Thread Christian König 

Am 30.08.2016 um 10:54 schrieb Chunming Zhou:

Change-Id: I5dc3f9003e706d3a142aadb559bd85f6e0f2a03f
Signed-off-by: Chunming Zhou 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu.h| 4 
  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +++
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c| 9 +
  3 files changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index b17916d..18bbfea 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -2117,6 +2117,10 @@ struct amdgpu_device {
/* link all shadow bo */
struct list_headshadow_list;
struct mutexshadow_list_lock;
+   /* link all gtt */
+   struct mutexgtt_list_lock;


I think this time a spin lock should clearly be sufficient here. Or do 
we block somewhere in the GART code path?


Apart from that the patch looks good to me.

Christian.


+   struct list_headgtt_list;
+
  };
  
  bool amdgpu_device_is_px(struct drm_device *dev);

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 9a6a1a9..6cd485a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1591,6 +1591,9 @@ int amdgpu_device_init(struct amdgpu_device *adev,
INIT_LIST_HEAD(>shadow_list);
mutex_init(>shadow_list_lock);
  
+	INIT_LIST_HEAD(>gtt_list);

+   mutex_init(>gtt_list_lock);
+
adev->rmmio_base = pci_resource_start(adev->pdev, 5);
adev->rmmio_size = pci_resource_len(adev->pdev, 5);
adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 2ba3c8d..efeb9a5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -521,6 +521,7 @@ struct amdgpu_ttm_tt {
spinlock_t  guptasklock;
struct list_headguptasks;
atomic_tmmu_invalidations;
+   struct list_headlist;
  };
  
  int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)

@@ -667,6 +668,9 @@ static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
  ttm->num_pages, (unsigned)gtt->offset);
return r;
}
+   mutex_lock(>adev->gtt_list_lock);
+   list_add_tail(>list, >adev->gtt_list);
+   mutex_unlock(>adev->gtt_list_lock);
return 0;
  }
  
@@ -681,6 +685,10 @@ static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)

if (gtt->userptr)
amdgpu_ttm_tt_unpin_userptr(ttm);
  
+	mutex_lock(>adev->gtt_list_lock);

+   list_del_init(>list);
+   mutex_unlock(>adev->gtt_list_lock);
+
return 0;
  }
  
@@ -717,6 +725,7 @@ static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_bo_device *bdev,

kfree(gtt);
return NULL;
}
+   INIT_LIST_HEAD(>list);
return >ttm.ttm;
  }
  



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[PATCH 1/2] drm/amdgpu: link all gtt when binding them V2

2016-08-30 Thread Chunming Zhou 
V2:
spin lock instead of mutex for gtt list

Change-Id: I5dc3f9003e706d3a142aadb559bd85f6e0f2a03f
Signed-off-by: Chunming Zhou 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h| 4 
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c| 9 +
 3 files changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index b17916d..6f0af25 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -2117,6 +2117,10 @@ struct amdgpu_device {
/* link all shadow bo */
struct list_headshadow_list;
struct mutexshadow_list_lock;
+   /* link all gtt */
+   spinlock_t  gtt_list_lock;
+   struct list_headgtt_list;
+
 };
 
 bool amdgpu_device_is_px(struct drm_device *dev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 9a6a1a9..a968fc6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1591,6 +1591,9 @@ int amdgpu_device_init(struct amdgpu_device *adev,
INIT_LIST_HEAD(>shadow_list);
mutex_init(>shadow_list_lock);
 
+   INIT_LIST_HEAD(>gtt_list);
+   spin_lock_init(>gtt_list_lock);
+
adev->rmmio_base = pci_resource_start(adev->pdev, 5);
adev->rmmio_size = pci_resource_len(adev->pdev, 5);
adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 2ba3c8d..0c561c6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -521,6 +521,7 @@ struct amdgpu_ttm_tt {
spinlock_t  guptasklock;
struct list_headguptasks;
atomic_tmmu_invalidations;
+   struct list_headlist;
 };
 
 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
@@ -667,6 +668,9 @@ static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
  ttm->num_pages, (unsigned)gtt->offset);
return r;
}
+   spin_lock(>adev->gtt_list_lock);
+   list_add_tail(>list, >adev->gtt_list);
+   spin_unlock(>adev->gtt_list_lock);
return 0;
 }
 
@@ -681,6 +685,10 @@ static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
if (gtt->userptr)
amdgpu_ttm_tt_unpin_userptr(ttm);
 
+   spin_lock(>adev->gtt_list_lock);
+   list_del_init(>list);
+   spin_unlock(>adev->gtt_list_lock);
+
return 0;
 }
 
@@ -717,6 +725,7 @@ static struct ttm_tt *amdgpu_ttm_tt_create(struct 
ttm_bo_device *bdev,
kfree(gtt);
return NULL;
}
+   INIT_LIST_HEAD(>list);
return >ttm.ttm;
 }
 
-- 
1.9.1

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