Re: [PATCH 2/2] drm/atomic: Create and use __drm_atomic_helper_crtc_reset() everywhere
For the nouveau and drm core changes
Reviewed-by: Lyude Paul
On Mon, 2018-11-12 at 16:01 +0100, Maarten Lankhorst wrote:
> We already have __drm_atomic_helper_connector_reset() and
> __drm_atomic_helper_plane_reset(), extend this to crtc as well.
>
> Most drivers already have a gpu reset hook, correct it.
> Nouveau already implemented its own __drm_atomic_helper_crtc_reset(),
> convert it to the common one.
>
> Signed-off-by: Maarten Lankhorst
> Cc: Harry Wentland
> Cc: Leo Li
> Cc: Alex Deucher
> Cc: "Christian König"
> Cc: "David (ChunMing) Zhou"
> Cc: David Airlie
> Cc: Liviu Dudau
> Cc: Brian Starkey
> Cc: Mali DP Maintainers
> Cc: Boris Brezillon
> Cc: Nicolas Ferre
> Cc: Alexandre Belloni
> Cc: Ludovic Desroches
> Cc: Maarten Lankhorst
> Cc: Maxime Ripard
> Cc: Sean Paul
> Cc: Jani Nikula
> Cc: Joonas Lahtinen
> Cc: Rodrigo Vivi
> Cc: Philipp Zabel
> Cc: CK Hu
> Cc: Matthias Brugger
> Cc: Rob Clark
> Cc: Ben Skeggs
> Cc: Tomi Valkeinen
> Cc: Laurent Pinchart
> Cc: Kieran Bingham
> Cc: Sandy Huang
> Cc: "Heiko Stübner"
> Cc: Thierry Reding
> Cc: Jonathan Hunter
> Cc: Eric Anholt
> Cc: VMware Graphics
> Cc: Sinclair Yeh
> Cc: Thomas Hellstrom
> Cc: Tony Cheng
> Cc: Shirish S
> Cc: Mikita Lipski
> Cc: Bhawanpreet Lakha
> Cc: David Francis
> Cc: Anthony Koo
> Cc: Jeykumar Sankaran
> Cc: Jordan Crouse
> Cc: Bruce Wang
> Cc: Sravanthi Kollukuduru
> Cc: Archit Taneja
> Cc: Steve Kowalik
> Cc: Carsten Behling
> Cc: Haneen Mohammed
> Cc: Daniel Vetter
> Cc: Rodrigo Siqueira
> Cc: Mahesh Kumar
> Cc: amd-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org
> Cc: linux-ker...@vger.kernel.org
> Cc: linux-arm-ker...@lists.infradead.org
> Cc: intel-...@lists.freedesktop.org
> Cc: linux-media...@lists.infradead.org
> Cc: linux-arm-...@vger.kernel.org
> Cc: freedr...@lists.freedesktop.org
> Cc: nouv...@lists.freedesktop.org
> Cc: linux-renesas-...@vger.kernel.org
> Cc: linux-rockc...@lists.infradead.org
> Cc: linux-te...@vger.kernel.org
> ---
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +--
> drivers/gpu/drm/arm/malidp_crtc.c | 5 +--
> .../gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c| 5 +--
> drivers/gpu/drm/drm_atomic_state_helper.c | 31 ---
> drivers/gpu/drm/i915/intel_display.c | 2 +-
> drivers/gpu/drm/imx/ipuv3-crtc.c | 5 +--
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 5 +--
> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 12 ++-
> drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 6 +---
> drivers/gpu/drm/nouveau/dispnv50/head.c | 13 ++--
> drivers/gpu/drm/omapdrm/omap_crtc.c | 7 ++---
> drivers/gpu/drm/rcar-du/rcar_du_crtc.c| 4 +--
> drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 7 +++--
> drivers/gpu/drm/tegra/dc.c| 5 +--
> drivers/gpu/drm/vc4/vc4_crtc.c| 8 ++---
> drivers/gpu/drm/vkms/vkms_crtc.c | 7 +
> drivers/gpu/drm/vmwgfx/vmwgfx_kms.c | 9 +-
> include/drm/drm_atomic_state_helper.h | 2 ++
> 18 files changed, 56 insertions(+), 81 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 5064768642f3..770a71726cd1 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -2802,9 +2802,7 @@ static void dm_crtc_reset_state(struct drm_crtc *crtc)
> if (WARN_ON(!state))
> return;
>
> - crtc->state = >base;
> - crtc->state->crtc = crtc;
> -
> + __drm_atomic_helper_crtc_reset(crtc, >base);
> }
>
> static struct drm_crtc_state *
> diff --git a/drivers/gpu/drm/arm/malidp_crtc.c
> b/drivers/gpu/drm/arm/malidp_crtc.c
> index e1b72782848c..9a924ff27148 100644
> --- a/drivers/gpu/drm/arm/malidp_crtc.c
> +++ b/drivers/gpu/drm/arm/malidp_crtc.c
> @@ -474,10 +474,7 @@ static void malidp_crtc_reset(struct drm_crtc *crtc)
>
> kfree(state);
> state = kzalloc(sizeof(*state), GFP_KERNEL);
> - if (state) {
> - crtc->state = >base;
> - crtc->state->crtc = crtc;
> - }
> + __drm_atomic_helper_crtc_reset(crtc, >base);
> }
>
> static void malidp_crtc_destroy_state(struct drm_crtc *crtc,
> diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
> b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
> index 96f4082671fe..8084d549c7d1 100644
> --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
> +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
> @@ -412,10 +412,7 @@ static void atmel_hlcdc_crtc_reset(struct drm_crtc
> *crtc)
> }
>
> state = kzalloc(sizeof(*state), GFP_KERNEL);
> - if (state) {
> - crtc->state = >base;
> - crtc->state->crtc = crtc;
> - }
> + __drm_atomic_helper_crtc_reset(crtc, >base);
> }
>
> static struct drm_crtc_state *
> diff --git
Re: [PATCH 4/5] drm/amdgpu: Expose hive adev list and xgmi_mutex
On Wed, Nov 21, 2018 at 1:11 PM Andrey Grodzovsky
wrote:
>
> It's needed for device reset of entire hive.
>
> Signed-off-by: Andrey Grodzovsky
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++
> drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 7 ++-
> 2 files changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 3e5bede..4ef5f7a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1227,8 +1227,10 @@ long amdgpu_kms_compat_ioctl(struct file *filp,
> unsigned int cmd,
> * functions used by amdgpu_xgmi.c
> */
>
> +extern struct mutex xgmi_mutex;
> struct amdgpu_hive_info;
>
> +struct list_head *amdgpu_xgmi_get_adev_list_handle(struct amdgpu_hive_info
> *hive);
> struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev);
> int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive);
> int amdgpu_xgmi_add_device(struct amdgpu_device *adev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
> index 23e4e16..e483e60 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
> @@ -26,7 +26,7 @@
> #include "amdgpu_psp.h"
>
>
> -static DEFINE_MUTEX(xgmi_mutex);
> +DEFINE_MUTEX(xgmi_mutex);
>
> #define AMDGPU_MAX_XGMI_HIVE 8
> #define AMDGPU_MAX_XGMI_DEVICE_PER_HIVE4
> @@ -41,6 +41,11 @@ struct amdgpu_hive_info {
> static struct amdgpu_hive_info xgmi_hives[AMDGPU_MAX_XGMI_HIVE];
> static unsigned hive_count = 0;
>
> +struct list_head *amdgpu_xgmi_get_adev_list_handle(struct amdgpu_hive_info
> *hive)
> +{
> + return >device_list;
> +}
> +
> struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev)
> {
> int i;
> --
> 2.7.4
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
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Re: [PATCH 5/5] drm/amdgpu: Refactor GPU reset for XGMI hive case.
Depends what was the reason for triggering the reset for that node how
do we know ?
If the reason was RAS error that probably not hard to check all errors
are cleared, but
if the reason was job timeout on that specific node I will need to
recheck that no jobs are left in incomplete state
state. And if the reason is manual gpu reset trigger from sysfs, then
what's the policy ?
Sounds to me it's just easier to go ahead and allow all the pending
resets to proceed unless there is
a clear and quick criteria you can check after you grab the mutex then
sure - but I don't know what it would be.
Andrey
On 11/21/2018 03:49 PM, Liu, Shaoyun wrote:
> I saw you use the global xgmi_mutex to prevent concurrent reset to be
> triggered by different nodes , but after the mutex been released ,
> current node may grap the mutex and continue to do another reset .
> Maybe we should check the GPU status and skip the reset in this case
> since the GPU may already be in good state .
>
> Regards
>
> shaoyun.liu
>
> On 2018-11-21 1:10 p.m., Andrey Grodzovsky wrote:
>> For XGMI hive case do reset in steps where each step iterates over
>> all devs in hive. This especially important for asic reset
>> since all PSP FW in hive must come up within a limited time
>> (around 1 sec) to properply negotiate the link.
>> Do this by refactoring amdgpu_device_gpu_recover and amdgpu_device_reset
>> into pre_asic_reset, asic_reset and post_asic_reset functions where is part
>> is exectued for all the GPUs in the hive before going to the next step.
>>
>> Signed-off-by: Andrey Grodzovsky
>> ---
>>drivers/gpu/drm/amd/amdgpu/amdgpu.h| 5 +-
>>drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 375
>> -
>>2 files changed, 264 insertions(+), 116 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> index 4ef5f7a..bd06d45 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> @@ -1026,6 +1026,9 @@ struct amdgpu_device {
>> unsigned long last_mm_index;
>> boolin_gpu_reset;
>> struct mutex lock_reset;
>> +
>> +int asic_reset_res;
>> +int resched;
>>};
>>
>>static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device
>> *bdev)
>> @@ -1232,7 +1235,7 @@ struct amdgpu_hive_info;
>>
>>struct list_head *amdgpu_xgmi_get_adev_list_handle(struct
>> amdgpu_hive_info *hive);
>>struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev);
>> -int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive);
>> +int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive, struct
>> amdgpu_device *adev);
>>int amdgpu_xgmi_add_device(struct amdgpu_device *adev);
>>
>>/*
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> index cb06e68..8e94d7f 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> @@ -3157,86 +3157,6 @@ static int amdgpu_device_recover_vram(struct
>> amdgpu_device *adev)
>> return 0;
>>}
>>
>> -/**
>> - * amdgpu_device_reset - reset ASIC/GPU for bare-metal or passthrough
>> - *
>> - * @adev: amdgpu device pointer
>> - *
>> - * attempt to do soft-reset or full-reset and reinitialize Asic
>> - * return 0 means succeeded otherwise failed
>> - */
>> -static int amdgpu_device_reset(struct amdgpu_device *adev)
>> -{
>> -bool need_full_reset, vram_lost = 0;
>> -int r;
>> -
>> -need_full_reset = amdgpu_device_ip_need_full_reset(adev);
>> -
>> -if (!need_full_reset) {
>> -amdgpu_device_ip_pre_soft_reset(adev);
>> -r = amdgpu_device_ip_soft_reset(adev);
>> -amdgpu_device_ip_post_soft_reset(adev);
>> -if (r || amdgpu_device_ip_check_soft_reset(adev)) {
>> -DRM_INFO("soft reset failed, will fallback to full
>> reset!\n");
>> -need_full_reset = true;
>> -}
>> -}
>> -
>> -if (need_full_reset) {
>> -r = amdgpu_device_ip_suspend(adev);
>> -
>> -retry:
>> -r = amdgpu_asic_reset(adev);
>> -/* post card */
>> -amdgpu_atom_asic_init(adev->mode_info.atom_context);
>> -
>> -if (!r) {
>> -dev_info(adev->dev, "GPU reset succeeded, trying to
>> resume\n");
>> -r = amdgpu_device_ip_resume_phase1(adev);
>> -if (r)
>> -goto out;
>> -
>> -vram_lost = amdgpu_device_check_vram_lost(adev);
>> -if (vram_lost) {
>> -DRM_ERROR("VRAM is lost!\n");
>> -atomic_inc(>vram_lost_counter);
>> -}
>> -
>> -r = amdgpu_gtt_mgr_recover(
>> -
Re: [PATCH 3/7] drm/amdgpu: Vega12 doorbell index initialization
On Wed, Nov 21, 2018 at 5:00 PM Oak Zeng wrote:
>
> v2: Changed file name for consistency
>
> Change-Id: Ib2c570224321bb7002d2ed01f43ac70203e86f88
> Signed-off-by: Oak Zeng
> Suggested-by: Felix Kuehling
> Suggested-by: Alex Deucher
Just drop this patch and use the vega10 definition for vega12 and raven.
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/Makefile | 2 +-
> drivers/gpu/drm/amd/amdgpu/soc15.h | 1 +
> drivers/gpu/drm/amd/amdgpu/vega12_reg_init.c | 54
>
> 3 files changed, 56 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/amd/amdgpu/vega12_reg_init.c
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
> b/drivers/gpu/drm/amd/amdgpu/Makefile
> index f76bcb9..1cef9e1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/Makefile
> +++ b/drivers/gpu/drm/amd/amdgpu/Makefile
> @@ -63,7 +63,7 @@ amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o
> si_ih.o si_dma.o dce
>
> amdgpu-y += \
> vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o
> vega10_reg_init.o \
> - vega20_reg_init.o nbio_v7_4.o
> + vega20_reg_init.o nbio_v7_4.o vega12_reg_init.o
>
> # add DF block
> amdgpu-y += \
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h
> b/drivers/gpu/drm/amd/amdgpu/soc15.h
> index d37c57d..939c0e8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.h
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.h
> @@ -59,4 +59,5 @@ int vega10_reg_base_init(struct amdgpu_device *adev);
> int vega20_reg_base_init(struct amdgpu_device *adev);
>
> void vega10_doorbell_index_init(struct amdgpu_device *adev);
> +void vega12_doorbell_index_init(struct amdgpu_device *adev);
> #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/vega12_reg_init.c
> b/drivers/gpu/drm/amd/amdgpu/vega12_reg_init.c
> new file mode 100644
> index 000..71622b5
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/amdgpu/vega12_reg_init.c
> @@ -0,0 +1,54 @@
> +/*
> + * Copyright 2018 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + */
> +
> +#include "amdgpu.h"
> +
> +void vega12_doorbell_index_init(struct amdgpu_device *adev)
> +{
> + adev->doorbell_index.kiq = AMDGPU_DOORBELL64_KIQ;
> + adev->doorbell_index.mec_ring0 = AMDGPU_DOORBELL64_MEC_RING0;
> + adev->doorbell_index.mec_ring1 = AMDGPU_DOORBELL64_MEC_RING1;
> + adev->doorbell_index.mec_ring2 = AMDGPU_DOORBELL64_MEC_RING2;
> + adev->doorbell_index.mec_ring3 = AMDGPU_DOORBELL64_MEC_RING3;
> + adev->doorbell_index.mec_ring4 = AMDGPU_DOORBELL64_MEC_RING4;
> + adev->doorbell_index.mec_ring5 = AMDGPU_DOORBELL64_MEC_RING5;
> + adev->doorbell_index.mec_ring6 = AMDGPU_DOORBELL64_MEC_RING6;
> + adev->doorbell_index.mec_ring7 = AMDGPU_DOORBELL64_MEC_RING7;
> + adev->doorbell_index.userqueue_start =
> AMDGPU_DOORBELL64_USERQUEUE_START;
> + adev->doorbell_index.userqueue_end = AMDGPU_DOORBELL64_USERQUEUE_END;
> + adev->doorbell_index.gfx_ring0 = AMDGPU_DOORBELL64_GFX_RING0;
> + adev->doorbell_index.sdma_engine0 = AMDGPU_DOORBELL64_sDMA_ENGINE0;
> + adev->doorbell_index.sdma_engine1 = AMDGPU_DOORBELL64_sDMA_ENGINE1;
> + adev->doorbell_index.ih = AMDGPU_DOORBELL64_IH;
> + adev->doorbell_index.uvd_vce.uvd_ring0_1 =
> AMDGPU_DOORBELL64_UVD_RING0_1;
> + adev->doorbell_index.uvd_vce.uvd_ring2_3 =
> AMDGPU_DOORBELL64_UVD_RING2_3;
> + adev->doorbell_index.uvd_vce.uvd_ring4_5 =
> AMDGPU_DOORBELL64_UVD_RING4_5;
> + adev->doorbell_index.uvd_vce.uvd_ring6_7 =
> AMDGPU_DOORBELL64_UVD_RING6_7;
> + adev->doorbell_index.uvd_vce.vce_ring0_1 =
> AMDGPU_DOORBELL64_VCE_RING0_1;
> + adev->doorbell_index.uvd_vce.vce_ring2_3 =
> AMDGPU_DOORBELL64_VCE_RING2_3;
> + adev->doorbell_index.uvd_vce.vce_ring4_5 =
> AMDGPU_DOORBELL64_VCE_RING4_5;
> + adev->doorbell_index.uvd_vce.vce_ring6_7 =
>
Re: [PATCH 3/5] drm/amdgpu: Refactor amdgpu_xgmi_add_device
On Wed, Nov 21, 2018 at 1:11 PM Andrey Grodzovsky
wrote:
>
> This is prep work for updating each PSP FW in hive after
> GPU reset.
> Split into build topology SW state and update each PSP FW in the hive.
> Save topology and count of XGMI devices for reuse.
>
> Signed-off-by: Andrey Grodzovsky
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5 +++
> drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 55
> +++-
> 2 files changed, 38 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 2c80453..3e5bede 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1226,6 +1226,11 @@ long amdgpu_kms_compat_ioctl(struct file *filp,
> unsigned int cmd,
> /*
> * functions used by amdgpu_xgmi.c
> */
> +
> +struct amdgpu_hive_info;
> +
> +struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev);
> +int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive);
> int amdgpu_xgmi_add_device(struct amdgpu_device *adev);
We should move these to their own header, amdgpu_xgmi.h, rather than
dumping them in amdgpu.h
>
> /*
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
> index 909216a..23e4e16 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
> @@ -34,12 +34,14 @@ static DEFINE_MUTEX(xgmi_mutex);
> struct amdgpu_hive_info {
> uint64_thive_id;
> struct list_headdevice_list;
> + struct psp_xgmi_topology_info topology_info;
> + int number_devices;
> };
>
> static struct amdgpu_hive_info xgmi_hives[AMDGPU_MAX_XGMI_HIVE];
> static unsigned hive_count = 0;
>
> -static struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device
> *adev)
> +struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev)
Any reason to make this public?
> {
> int i;
> struct amdgpu_hive_info *tmp;
> @@ -61,12 +63,33 @@ static struct amdgpu_hive_info
> *amdgpu_get_xgmi_hive(struct amdgpu_device *adev)
> return tmp;
> }
>
> +int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive, struct
> amdgpu_device *adev)
> +{
> + int ret = -EINVAL;
> +
> + /* Each psp need to set the latest topology */
> + ret = psp_xgmi_set_topology_info(>psp,
> +hive->number_devices,
> +>topology_info);
> + if (ret)
> + dev_err(adev->dev,
> + "XGMI: Set topology failure on device %llx,
> hive %llx, ret %d",
> + adev->gmc.xgmi.node_id,
> + adev->gmc.xgmi.hive_id, ret);
> + else
> + dev_info(adev->dev, "XGMI: Add node %d to hive
> 0x%llx.\n",
> +adev->gmc.xgmi.physical_node_id,
> +adev->gmc.xgmi.hive_id);
> +
> + return ret;
> +}
Indentation in this function looks wrong.
> +
> int amdgpu_xgmi_add_device(struct amdgpu_device *adev)
> {
> - struct psp_xgmi_topology_info *tmp_topology;
> + struct psp_xgmi_topology_info *hive_topology;
> struct amdgpu_hive_info *hive;
> struct amdgpu_xgmi *entry;
> - struct amdgpu_device*tmp_adev;
> + struct amdgpu_device *tmp_adev = NULL;
>
> int count = 0, ret = -EINVAL;
>
> @@ -76,21 +99,21 @@ int amdgpu_xgmi_add_device(struct amdgpu_device *adev)
> adev->gmc.xgmi.node_id = psp_xgmi_get_node_id(>psp);
> adev->gmc.xgmi.hive_id = psp_xgmi_get_hive_id(>psp);
>
> - tmp_topology = kzalloc(sizeof(struct psp_xgmi_topology_info),
> GFP_KERNEL);
> - if (!tmp_topology)
> - return -ENOMEM;
> mutex_lock(_mutex);
> hive = amdgpu_get_xgmi_hive(adev);
> if (!hive)
> goto exit;
>
> + hive_topology = >topology_info;
> +
> list_add_tail(>gmc.xgmi.head, >device_list);
> list_for_each_entry(entry, >device_list, head)
> - tmp_topology->nodes[count++].node_id = entry->node_id;
> + hive_topology->nodes[count++].node_id = entry->node_id;
> + hive->number_devices = count;
>
> /* Each psp need to get the latest topology */
> list_for_each_entry(tmp_adev, >device_list, gmc.xgmi.head) {
> - ret = psp_xgmi_get_topology_info(_adev->psp, count,
> tmp_topology);
> + ret = psp_xgmi_get_topology_info(_adev->psp, count,
> hive_topology);
> if (ret) {
> dev_err(tmp_adev->dev,
> "XGMI: Get topology failure on device %llx,
> hive %llx, ret %d",
> @@ -101,25 +124,13 @@ int amdgpu_xgmi_add_device(struct amdgpu_device *adev)
>
Re: [PATCH 3/5] drm/amdgpu: Refactor amdgpu_xgmi_add_device
On 11/21/2018 02:29 PM, Alex Deucher wrote:
> On Wed, Nov 21, 2018 at 1:11 PM Andrey Grodzovsky
> wrote:
>> This is prep work for updating each PSP FW in hive after
>> GPU reset.
>> Split into build topology SW state and update each PSP FW in the hive.
>> Save topology and count of XGMI devices for reuse.
>>
>> Signed-off-by: Andrey Grodzovsky
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5 +++
>> drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 55
>> +++-
>> 2 files changed, 38 insertions(+), 22 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> index 2c80453..3e5bede 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> @@ -1226,6 +1226,11 @@ long amdgpu_kms_compat_ioctl(struct file *filp,
>> unsigned int cmd,
>> /*
>>* functions used by amdgpu_xgmi.c
>>*/
>> +
>> +struct amdgpu_hive_info;
>> +
>> +struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev);
>> +int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive);
>> int amdgpu_xgmi_add_device(struct amdgpu_device *adev);
> We should move these to their own header, amdgpu_xgmi.h, rather than
> dumping them in amdgpu.h
>
>> /*
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
>> index 909216a..23e4e16 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
>> @@ -34,12 +34,14 @@ static DEFINE_MUTEX(xgmi_mutex);
>> struct amdgpu_hive_info {
>> uint64_thive_id;
>> struct list_headdevice_list;
>> + struct psp_xgmi_topology_info topology_info;
>> + int number_devices;
>> };
>>
>> static struct amdgpu_hive_info xgmi_hives[AMDGPU_MAX_XGMI_HIVE];
>> static unsigned hive_count = 0;
>>
>> -static struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device
>> *adev)
>> +struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev)
> Any reason to make this public?
It is used in Patch 5.
Andrey
>
>> {
>> int i;
>> struct amdgpu_hive_info *tmp;
>> @@ -61,12 +63,33 @@ static struct amdgpu_hive_info
>> *amdgpu_get_xgmi_hive(struct amdgpu_device *adev)
>> return tmp;
>> }
>>
>> +int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive, struct
>> amdgpu_device *adev)
>> +{
>> + int ret = -EINVAL;
>> +
>> + /* Each psp need to set the latest topology */
>> + ret = psp_xgmi_set_topology_info(>psp,
>> +hive->number_devices,
>> +>topology_info);
>> + if (ret)
>> + dev_err(adev->dev,
>> + "XGMI: Set topology failure on device %llx,
>> hive %llx, ret %d",
>> + adev->gmc.xgmi.node_id,
>> + adev->gmc.xgmi.hive_id, ret);
>> + else
>> + dev_info(adev->dev, "XGMI: Add node %d to hive
>> 0x%llx.\n",
>> +adev->gmc.xgmi.physical_node_id,
>> +adev->gmc.xgmi.hive_id);
>> +
>> + return ret;
>> +}
> Indentation in this function looks wrong.
>
>> +
>> int amdgpu_xgmi_add_device(struct amdgpu_device *adev)
>> {
>> - struct psp_xgmi_topology_info *tmp_topology;
>> + struct psp_xgmi_topology_info *hive_topology;
>> struct amdgpu_hive_info *hive;
>> struct amdgpu_xgmi *entry;
>> - struct amdgpu_device*tmp_adev;
>> + struct amdgpu_device *tmp_adev = NULL;
>>
>> int count = 0, ret = -EINVAL;
>>
>> @@ -76,21 +99,21 @@ int amdgpu_xgmi_add_device(struct amdgpu_device *adev)
>> adev->gmc.xgmi.node_id = psp_xgmi_get_node_id(>psp);
>> adev->gmc.xgmi.hive_id = psp_xgmi_get_hive_id(>psp);
>>
>> - tmp_topology = kzalloc(sizeof(struct psp_xgmi_topology_info),
>> GFP_KERNEL);
>> - if (!tmp_topology)
>> - return -ENOMEM;
>> mutex_lock(_mutex);
>> hive = amdgpu_get_xgmi_hive(adev);
>> if (!hive)
>> goto exit;
>>
>> + hive_topology = >topology_info;
>> +
>> list_add_tail(>gmc.xgmi.head, >device_list);
>> list_for_each_entry(entry, >device_list, head)
>> - tmp_topology->nodes[count++].node_id = entry->node_id;
>> + hive_topology->nodes[count++].node_id = entry->node_id;
>> + hive->number_devices = count;
>>
>> /* Each psp need to get the latest topology */
>> list_for_each_entry(tmp_adev, >device_list, gmc.xgmi.head) {
>> - ret = psp_xgmi_get_topology_info(_adev->psp, count,
>> tmp_topology);
>> + ret = psp_xgmi_get_topology_info(_adev->psp, count,
>> hive_topology);
>> if (ret)
[PATCH 4/7] drm/amdgpu: Doorbell index initialization for ASICs before vega10
v2: Use enum definition instead of hardcoded number
Change-Id: Id64eb98f5b1c24b51eb2fd5a083086fc3515813d
Signed-off-by: Oak Zeng
Suggested-by: Felix Kuehling
Suggested-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/Makefile | 2 +-
drivers/gpu/drm/amd/amdgpu/vi.h | 2 +-
drivers/gpu/drm/amd/amdgpu/vi_reg_init.c | 43
3 files changed, 45 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/vi_reg_init.c
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 1cef9e1..ae29bf5 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -63,7 +63,7 @@ amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o
si_ih.o si_dma.o dce
amdgpu-y += \
vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o
vega10_reg_init.o \
- vega20_reg_init.o nbio_v7_4.o vega12_reg_init.o
+ vega20_reg_init.o nbio_v7_4.o vega12_reg_init.o vi_reg_init.o
# add DF block
amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.h b/drivers/gpu/drm/amd/amdgpu/vi.h
index 0429fe3..abcb52e 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.h
+++ b/drivers/gpu/drm/amd/amdgpu/vi.h
@@ -29,5 +29,5 @@
void vi_srbm_select(struct amdgpu_device *adev,
u32 me, u32 pipe, u32 queue, u32 vmid);
int vi_set_ip_blocks(struct amdgpu_device *adev);
-
+void vi_doorbell_index_init(struct amdgpu_device *adev);
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/vi_reg_init.c
b/drivers/gpu/drm/amd/amdgpu/vi_reg_init.c
new file mode 100644
index 000..cdeb88d
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/vi_reg_init.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "amdgpu.h"
+
+void vi_doorbell_index_init(struct amdgpu_device *adev)
+{
+ adev->doorbell_index.kiq = AMDGPU_DOORBELL_KIQ;
+ adev->doorbell_index.mec_ring0 = AMDGPU_DOORBELL_MEC_RING0;
+ adev->doorbell_index.mec_ring1 = AMDGPU_DOORBELL_MEC_RING1;
+ adev->doorbell_index.mec_ring2 = AMDGPU_DOORBELL_MEC_RING2;
+ adev->doorbell_index.mec_ring3 = AMDGPU_DOORBELL_MEC_RING3;
+ adev->doorbell_index.mec_ring4 = AMDGPU_DOORBELL_MEC_RING4;
+ adev->doorbell_index.mec_ring5 = AMDGPU_DOORBELL_MEC_RING5;
+ adev->doorbell_index.mec_ring6 = AMDGPU_DOORBELL_MEC_RING6;
+ adev->doorbell_index.mec_ring7 = AMDGPU_DOORBELL_MEC_RING7;
+ adev->doorbell_index.gfx_ring0 = AMDGPU_DOORBELL_GFX_RING0;
+ adev->doorbell_index.sdma_engine0 = AMDGPU_DOORBELL_sDMA_ENGINE0;
+ adev->doorbell_index.sdma_engine1 = AMDGPU_DOORBELL_sDMA_ENGINE1;
+ adev->doorbell_index.ih = AMDGPU_DOORBELL_IH;
+ adev->doorbell_index.max_assignment = AMDGPU_DOORBELL_MAX_ASSIGNMENT;
+}
+
--
2.7.4
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 7/7] drm/amdgpu: Use new doorbell layout for vega20 and future asic
v2: Use enum definition instead of hardcoded value
Change-Id: I04d22fb717ac50483c0835f160a2e860e344f358
Signed-off-by: Oak Zeng
Suggested-by: Felix Kuehling
Suggested-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 50
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++-
drivers/gpu/drm/amd/amdgpu/soc15.h | 1 +
drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c | 33 ++
4 files changed, 87 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index b7ee4ef..e4101b1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -392,6 +392,56 @@ struct amdgpu_doorbell {
u32 num_doorbells; /* Number of doorbells actually
reserved for amdgpu. */
};
+typedef enum _AMDGPU_VEGA20_DOORBELL_ASSIGNMENT
+{
+ /* Compute + GFX: 0~255 */
+ AMDGPU_VEGA20_DOORBELL_KIQ = 0x000,
+ AMDGPU_VEGA20_DOORBELL_HIQ = 0x001,
+ AMDGPU_VEGA20_DOORBELL_DIQ = 0x002,
+ AMDGPU_VEGA20_DOORBELL_MEC_RING0 = 0x003,
+ AMDGPU_VEGA20_DOORBELL_MEC_RING1 = 0x004,
+ AMDGPU_VEGA20_DOORBELL_MEC_RING2 = 0x005,
+ AMDGPU_VEGA20_DOORBELL_MEC_RING3 = 0x006,
+ AMDGPU_VEGA20_DOORBELL_MEC_RING4 = 0x007,
+ AMDGPU_VEGA20_DOORBELL_MEC_RING5 = 0x008,
+ AMDGPU_VEGA20_DOORBELL_MEC_RING6 = 0x009,
+ AMDGPU_VEGA20_DOORBELL_MEC_RING7 = 0x00A,
+ AMDGPU_VEGA20_DOORBELL_USERQUEUE_START = 0x00B,
+ AMDGPU_VEGA20_DOORBELL_USERQUEUE_END = 0x08A,
+ AMDGPU_VEGA20_DOORBELL_GFX_RING0 = 0x08B,
+ /* SDMA:256~335*/
+ AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0= 0x100,
+ AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE1= 0x10A,
+ AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE2= 0x114,
+ AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE3= 0x11E,
+ AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE4= 0x128,
+ AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE5= 0x132,
+ AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE6= 0x13C,
+ AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE7= 0x146,
+ /* IH: 376~391 */
+ AMDGPU_VEGA20_DOORBELL_IH = 0x178,
+ /* MMSCH: 392~407
+* overlap the doorbell assignment with VCN as they are mutually
exclusive
+* VCE engine's doorbell is 32 bit and two VCE ring share one QWORD
+*/
+ AMDGPU_VEGA20_DOORBELL64_VCN0_1 = 0x188, /* lower 32
bits for VNC0 and upper 32 bits for VNC1 */
+ AMDGPU_VEGA20_DOORBELL64_VCN2_3 = 0x189,
+ AMDGPU_VEGA20_DOORBELL64_VCN4_5 = 0x18A,
+ AMDGPU_VEGA20_DOORBELL64_VCN6_7 = 0x18B,
+
+ AMDGPU_VEGA20_DOORBELL64_UVD_RING0_1 = 0x188,
+ AMDGPU_VEGA20_DOORBELL64_UVD_RING2_3 = 0x189,
+ AMDGPU_VEGA20_DOORBELL64_UVD_RING4_5 = 0x18A,
+ AMDGPU_VEGA20_DOORBELL64_UVD_RING6_7 = 0x18B,
+
+ AMDGPU_VEGA20_DOORBELL64_VCE_RING0_1 = 0x18C,
+ AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3 = 0x18D,
+ AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5 = 0x18E,
+ AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7 = 0x18F,
+ AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT= 0x18F,
+ AMDGPU_VEGA20_DOORBELL_INVALID = 0x
+} AMDGPU_VEGA20_DOORBELL_ASSIGNMENT;
+
/*
* 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space
*/
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 3ffd8f5..19f2149 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -517,8 +517,10 @@ static int amdgpu_device_doorbell_init(struct
amdgpu_device *adev)
vi_doorbell_index_init(adev);
else if (adev->asic_type == CHIP_VEGA10)
vega10_doorbell_index_init(adev);
- else
+ else if (adev->asic_type == CHIP_VEGA12 || adev->asic_type ==
CHIP_RAVEN)
vega12_doorbell_index_init(adev);
+ else
+ vega20_doorbell_index_init(adev);
/* No doorbell on SI hardware generation */
if (adev->asic_type < CHIP_BONAIRE) {
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h
b/drivers/gpu/drm/amd/amdgpu/soc15.h
index 939c0e8..6ba0d26 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.h
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.h
@@ -60,4 +60,5 @@ int vega20_reg_base_init(struct amdgpu_device *adev);
void vega10_doorbell_index_init(struct amdgpu_device *adev);
void vega12_doorbell_index_init(struct amdgpu_device *adev);
+void vega20_doorbell_index_init(struct amdgpu_device
[PATCH 6/7] drm/amdgpu: Use asic specific doorbell index instead of macro definition
Change-Id: I84475efcfb482c474fccb133010abb5df5f4
Signed-off-by: Oak Zeng
Suggested-by: Felix Kuehling
Suggested-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 27 ---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c| 2 +-
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 10 +-
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 8
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 25 +
drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 2 +-
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 2 +-
12 files changed, 36 insertions(+), 54 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index 1c1fed6..d693b804 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -181,25 +181,14 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
* process in case of 64-bit doorbells so we
* can use each doorbell assignment twice.
*/
- if (adev->asic_type == CHIP_VEGA10) {
- gpu_resources.sdma_doorbell[0][i] =
- AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 +
(i >> 1);
- gpu_resources.sdma_doorbell[0][i+1] =
- AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 +
0x200 + (i >> 1);
- gpu_resources.sdma_doorbell[1][i] =
- AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 +
(i >> 1);
- gpu_resources.sdma_doorbell[1][i+1] =
- AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 +
0x200 + (i >> 1);
- } else {
- gpu_resources.sdma_doorbell[0][i] =
- AMDGPU_DOORBELL64_sDMA_ENGINE0 + (i >>
1);
- gpu_resources.sdma_doorbell[0][i+1] =
- AMDGPU_DOORBELL64_sDMA_ENGINE0 + 0x200
+ (i >> 1);
- gpu_resources.sdma_doorbell[1][i] =
- AMDGPU_DOORBELL64_sDMA_ENGINE1 + (i >>
1);
- gpu_resources.sdma_doorbell[1][i+1] =
- AMDGPU_DOORBELL64_sDMA_ENGINE1 + 0x200
+ (i >> 1);
- }
+ gpu_resources.sdma_doorbell[0][i] =
+ adev->doorbell_index.sdma_engine0 + (i >> 1);
+ gpu_resources.sdma_doorbell[0][i+1] =
+ adev->doorbell_index.sdma_engine0 + 0x200 + (i
>> 1);
+ gpu_resources.sdma_doorbell[1][i] =
+ adev->doorbell_index.sdma_engine1 + (i >> 1);
+ gpu_resources.sdma_doorbell[1][i+1] =
+ adev->doorbell_index.sdma_engine1 + 0x200 + (i
>> 1);
}
/* Doorbells 0x0e0-0ff and 0x2e0-2ff are reserved for
* SDMA, IH and VCN. So don't use them for the CP.
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index a942a88..3ffd8f5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -537,7 +537,7 @@ static int amdgpu_device_doorbell_init(struct amdgpu_device
*adev)
adev->doorbell.size = pci_resource_len(adev->pdev, 2);
adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size /
sizeof(u32),
-AMDGPU_DOORBELL_MAX_ASSIGNMENT+1);
+
adev->doorbell_index.max_assignment+1);
if (adev->doorbell.num_doorbells == 0)
return -EINVAL;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 6a70c0b..97a60da 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -250,7 +250,7 @@ int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
ring->adev = NULL;
ring->ring_obj = NULL;
ring->use_doorbell = true;
- ring->doorbell_index = AMDGPU_DOORBELL_KIQ;
+ ring->doorbell_index = adev->doorbell_index.kiq;
r = amdgpu_gfx_kiq_acquire(adev, ring);
if (r)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index f467b9b..3a9fb60 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -4363,7
[PATCH 5/7] drm/amdgpu: Call doorbell index init on device initialization
Change-Id: I2f004bbbe2565035460686f4fc16e86b77a2a9b5
Signed-off-by: Oak Zeng
Suggested-by: Felix Kuehling
Suggested-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index cb06e68..a942a88 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -513,6 +513,13 @@ void amdgpu_device_pci_config_reset(struct amdgpu_device
*adev)
*/
static int amdgpu_device_doorbell_init(struct amdgpu_device *adev)
{
+ if (adev->asic_type < CHIP_VEGA10)
+ vi_doorbell_index_init(adev);
+ else if (adev->asic_type == CHIP_VEGA10)
+ vega10_doorbell_index_init(adev);
+ else
+ vega12_doorbell_index_init(adev);
+
/* No doorbell on SI hardware generation */
if (adev->asic_type < CHIP_BONAIRE) {
adev->doorbell.base = 0;
--
2.7.4
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[PATCH 1/7] drm/amdgpu: Add field in amdgpu_dev to hold reserved doorbell index
This is a preparation work to make reserved doorbell index per device,
instead of using a global macro definition. By doing this, we can easily
change doorbell layout for future ASICs while not affecting ASICs in
production.
Change-Id: If08e2bc9d0749748ed4083ba4eb32a4698763085
Signed-off-by: Oak Zeng
Suggested-by: Felix Kuehling
Suggested-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 50 +
1 file changed, 50 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 2c80453..b7ee4ef 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -813,6 +813,55 @@ struct amd_powerplay {
uint32_t pp_feature;
};
+/* Reserved doorbells for amdgpu (including multimedia).
+ * KFD can use all the rest in the 2M doorbell bar.
+ * For asic before vega10, doorbell is 32-bit, so the
+ * index/offset is in dword. For vega10 and after, doorbell
+ * can be 64-bit, so the index defined is in qword.
+ */
+struct amdgpu_doorbell_index {
+ uint32_t kiq;
+ uint32_t mec_ring0;
+ uint32_t mec_ring1;
+ uint32_t mec_ring2;
+ uint32_t mec_ring3;
+ uint32_t mec_ring4;
+ uint32_t mec_ring5;
+ uint32_t mec_ring6;
+ uint32_t mec_ring7;
+ uint32_t userqueue_start;
+ uint32_t userqueue_end;
+ uint32_t gfx_ring0;
+ uint32_t sdma_engine0;
+ uint32_t sdma_engine1;
+ uint32_t sdma_engine2;
+ uint32_t sdma_engine3;
+ uint32_t sdma_engine4;
+ uint32_t sdma_engine5;
+ uint32_t sdma_engine6;
+ uint32_t sdma_engine7;
+ uint32_t ih;
+ union {
+ struct {
+ uint32_t vcn_ring0_1;
+ uint32_t vcn_ring2_3;
+ uint32_t vcn_ring4_5;
+ uint32_t vcn_ring6_7;
+ } vcn;
+ struct {
+ uint32_t uvd_ring0_1;
+ uint32_t uvd_ring2_3;
+ uint32_t uvd_ring4_5;
+ uint32_t uvd_ring6_7;
+ uint32_t vce_ring0_1;
+ uint32_t vce_ring2_3;
+ uint32_t vce_ring4_5;
+ uint32_t vce_ring6_7;
+ } uvd_vce;
+ };
+ uint32_t max_assignment;
+};
+
#define AMDGPU_RESET_MAGIC_NUM 64
struct amdgpu_device {
struct device *dev;
@@ -1026,6 +1075,7 @@ struct amdgpu_device {
unsigned long last_mm_index;
boolin_gpu_reset;
struct mutex lock_reset;
+ struct amdgpu_doorbell_index doorbell_index;
};
static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
--
2.7.4
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[PATCH 3/7] drm/amdgpu: Vega12 doorbell index initialization
v2: Changed file name for consistency
Change-Id: Ib2c570224321bb7002d2ed01f43ac70203e86f88
Signed-off-by: Oak Zeng
Suggested-by: Felix Kuehling
Suggested-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/Makefile | 2 +-
drivers/gpu/drm/amd/amdgpu/soc15.h | 1 +
drivers/gpu/drm/amd/amdgpu/vega12_reg_init.c | 54
3 files changed, 56 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/vega12_reg_init.c
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
b/drivers/gpu/drm/amd/amdgpu/Makefile
index f76bcb9..1cef9e1 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -63,7 +63,7 @@ amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o
si_ih.o si_dma.o dce
amdgpu-y += \
vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o
vega10_reg_init.o \
- vega20_reg_init.o nbio_v7_4.o
+ vega20_reg_init.o nbio_v7_4.o vega12_reg_init.o
# add DF block
amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h
b/drivers/gpu/drm/amd/amdgpu/soc15.h
index d37c57d..939c0e8 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.h
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.h
@@ -59,4 +59,5 @@ int vega10_reg_base_init(struct amdgpu_device *adev);
int vega20_reg_base_init(struct amdgpu_device *adev);
void vega10_doorbell_index_init(struct amdgpu_device *adev);
+void vega12_doorbell_index_init(struct amdgpu_device *adev);
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/vega12_reg_init.c
b/drivers/gpu/drm/amd/amdgpu/vega12_reg_init.c
new file mode 100644
index 000..71622b5
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/vega12_reg_init.c
@@ -0,0 +1,54 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "amdgpu.h"
+
+void vega12_doorbell_index_init(struct amdgpu_device *adev)
+{
+ adev->doorbell_index.kiq = AMDGPU_DOORBELL64_KIQ;
+ adev->doorbell_index.mec_ring0 = AMDGPU_DOORBELL64_MEC_RING0;
+ adev->doorbell_index.mec_ring1 = AMDGPU_DOORBELL64_MEC_RING1;
+ adev->doorbell_index.mec_ring2 = AMDGPU_DOORBELL64_MEC_RING2;
+ adev->doorbell_index.mec_ring3 = AMDGPU_DOORBELL64_MEC_RING3;
+ adev->doorbell_index.mec_ring4 = AMDGPU_DOORBELL64_MEC_RING4;
+ adev->doorbell_index.mec_ring5 = AMDGPU_DOORBELL64_MEC_RING5;
+ adev->doorbell_index.mec_ring6 = AMDGPU_DOORBELL64_MEC_RING6;
+ adev->doorbell_index.mec_ring7 = AMDGPU_DOORBELL64_MEC_RING7;
+ adev->doorbell_index.userqueue_start =
AMDGPU_DOORBELL64_USERQUEUE_START;
+ adev->doorbell_index.userqueue_end = AMDGPU_DOORBELL64_USERQUEUE_END;
+ adev->doorbell_index.gfx_ring0 = AMDGPU_DOORBELL64_GFX_RING0;
+ adev->doorbell_index.sdma_engine0 = AMDGPU_DOORBELL64_sDMA_ENGINE0;
+ adev->doorbell_index.sdma_engine1 = AMDGPU_DOORBELL64_sDMA_ENGINE1;
+ adev->doorbell_index.ih = AMDGPU_DOORBELL64_IH;
+ adev->doorbell_index.uvd_vce.uvd_ring0_1 =
AMDGPU_DOORBELL64_UVD_RING0_1;
+ adev->doorbell_index.uvd_vce.uvd_ring2_3 =
AMDGPU_DOORBELL64_UVD_RING2_3;
+ adev->doorbell_index.uvd_vce.uvd_ring4_5 =
AMDGPU_DOORBELL64_UVD_RING4_5;
+ adev->doorbell_index.uvd_vce.uvd_ring6_7 =
AMDGPU_DOORBELL64_UVD_RING6_7;
+ adev->doorbell_index.uvd_vce.vce_ring0_1 =
AMDGPU_DOORBELL64_VCE_RING0_1;
+ adev->doorbell_index.uvd_vce.vce_ring2_3 =
AMDGPU_DOORBELL64_VCE_RING2_3;
+ adev->doorbell_index.uvd_vce.vce_ring4_5 =
AMDGPU_DOORBELL64_VCE_RING4_5;
+ adev->doorbell_index.uvd_vce.vce_ring6_7 =
AMDGPU_DOORBELL64_VCE_RING6_7;
+ /* In unit of dword doorbell */
+ adev->doorbell_index.max_assignment = AMDGPU_DOORBELL64_MAX_ASSIGNMENT
<< 1;
+}
+
--
2.7.4
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Re: [PATCH 3/5] drm/amdgpu: Refactor amdgpu_xgmi_add_device
On Wed, Nov 21, 2018 at 2:36 PM Grodzovsky, Andrey
wrote:
>
>
>
> On 11/21/2018 02:29 PM, Alex Deucher wrote:
> > On Wed, Nov 21, 2018 at 1:11 PM Andrey Grodzovsky
> > wrote:
> >> This is prep work for updating each PSP FW in hive after
> >> GPU reset.
> >> Split into build topology SW state and update each PSP FW in the hive.
> >> Save topology and count of XGMI devices for reuse.
> >>
> >> Signed-off-by: Andrey Grodzovsky
> >> ---
> >> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5 +++
> >> drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 55
> >> +++-
> >> 2 files changed, 38 insertions(+), 22 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >> index 2c80453..3e5bede 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >> @@ -1226,6 +1226,11 @@ long amdgpu_kms_compat_ioctl(struct file *filp,
> >> unsigned int cmd,
> >> /*
> >>* functions used by amdgpu_xgmi.c
> >>*/
> >> +
> >> +struct amdgpu_hive_info;
> >> +
> >> +struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev);
> >> +int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive);
> >> int amdgpu_xgmi_add_device(struct amdgpu_device *adev);
> > We should move these to their own header, amdgpu_xgmi.h, rather than
> > dumping them in amdgpu.h
> >
> >> /*
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
> >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
> >> index 909216a..23e4e16 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
> >> @@ -34,12 +34,14 @@ static DEFINE_MUTEX(xgmi_mutex);
> >> struct amdgpu_hive_info {
> >> uint64_thive_id;
> >> struct list_headdevice_list;
> >> + struct psp_xgmi_topology_info topology_info;
> >> + int number_devices;
> >> };
> >>
> >> static struct amdgpu_hive_info xgmi_hives[AMDGPU_MAX_XGMI_HIVE];
> >> static unsigned hive_count = 0;
> >>
> >> -static struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device
> >> *adev)
> >> +struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev)
> > Any reason to make this public?
>
> It is used in Patch 5.
Ok. thanks.
Alex
>
> Andrey
>
> >
> >> {
> >> int i;
> >> struct amdgpu_hive_info *tmp;
> >> @@ -61,12 +63,33 @@ static struct amdgpu_hive_info
> >> *amdgpu_get_xgmi_hive(struct amdgpu_device *adev)
> >> return tmp;
> >> }
> >>
> >> +int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive, struct
> >> amdgpu_device *adev)
> >> +{
> >> + int ret = -EINVAL;
> >> +
> >> + /* Each psp need to set the latest topology */
> >> + ret = psp_xgmi_set_topology_info(>psp,
> >> +hive->number_devices,
> >> +>topology_info);
> >> + if (ret)
> >> + dev_err(adev->dev,
> >> + "XGMI: Set topology failure on device
> >> %llx, hive %llx, ret %d",
> >> + adev->gmc.xgmi.node_id,
> >> + adev->gmc.xgmi.hive_id, ret);
> >> + else
> >> + dev_info(adev->dev, "XGMI: Add node %d to hive
> >> 0x%llx.\n",
> >> +adev->gmc.xgmi.physical_node_id,
> >> +adev->gmc.xgmi.hive_id);
> >> +
> >> + return ret;
> >> +}
> > Indentation in this function looks wrong.
> >
> >> +
> >> int amdgpu_xgmi_add_device(struct amdgpu_device *adev)
> >> {
> >> - struct psp_xgmi_topology_info *tmp_topology;
> >> + struct psp_xgmi_topology_info *hive_topology;
> >> struct amdgpu_hive_info *hive;
> >> struct amdgpu_xgmi *entry;
> >> - struct amdgpu_device*tmp_adev;
> >> + struct amdgpu_device *tmp_adev = NULL;
> >>
> >> int count = 0, ret = -EINVAL;
> >>
> >> @@ -76,21 +99,21 @@ int amdgpu_xgmi_add_device(struct amdgpu_device *adev)
> >> adev->gmc.xgmi.node_id = psp_xgmi_get_node_id(>psp);
> >> adev->gmc.xgmi.hive_id = psp_xgmi_get_hive_id(>psp);
> >>
> >> - tmp_topology = kzalloc(sizeof(struct psp_xgmi_topology_info),
> >> GFP_KERNEL);
> >> - if (!tmp_topology)
> >> - return -ENOMEM;
> >> mutex_lock(_mutex);
> >> hive = amdgpu_get_xgmi_hive(adev);
> >> if (!hive)
> >> goto exit;
> >>
> >> + hive_topology = >topology_info;
> >> +
> >> list_add_tail(>gmc.xgmi.head, >device_list);
> >> list_for_each_entry(entry, >device_list, head)
> >> - tmp_topology->nodes[count++].node_id = entry->node_id;
> >> + hive_topology->nodes[count++].node_id = entry->node_id;
> >> + hive->number_devices = count;
> >>
> >>
Re: [PATCH 7/7] drm/amdgpu: Use new doorbell layout for vega20 and future asic
On Wed, Nov 21, 2018 at 5:00 PM Oak Zeng wrote:
>
> v2: Use enum definition instead of hardcoded value
>
> Change-Id: I04d22fb717ac50483c0835f160a2e860e344f358
> Signed-off-by: Oak Zeng
> Suggested-by: Felix Kuehling
> Suggested-by: Alex Deucher
This patch should come before patch 5 so we update all of the asics
before we switch to using the new interface.
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 50
>
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++-
> drivers/gpu/drm/amd/amdgpu/soc15.h | 1 +
> drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c | 33 ++
> 4 files changed, 87 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index b7ee4ef..e4101b1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -392,6 +392,56 @@ struct amdgpu_doorbell {
> u32 num_doorbells; /* Number of doorbells
> actually reserved for amdgpu. */
> };
>
> +typedef enum _AMDGPU_VEGA20_DOORBELL_ASSIGNMENT
> +{
> + /* Compute + GFX: 0~255 */
> + AMDGPU_VEGA20_DOORBELL_KIQ = 0x000,
> + AMDGPU_VEGA20_DOORBELL_HIQ = 0x001,
> + AMDGPU_VEGA20_DOORBELL_DIQ = 0x002,
> + AMDGPU_VEGA20_DOORBELL_MEC_RING0 = 0x003,
> + AMDGPU_VEGA20_DOORBELL_MEC_RING1 = 0x004,
> + AMDGPU_VEGA20_DOORBELL_MEC_RING2 = 0x005,
> + AMDGPU_VEGA20_DOORBELL_MEC_RING3 = 0x006,
> + AMDGPU_VEGA20_DOORBELL_MEC_RING4 = 0x007,
> + AMDGPU_VEGA20_DOORBELL_MEC_RING5 = 0x008,
> + AMDGPU_VEGA20_DOORBELL_MEC_RING6 = 0x009,
> + AMDGPU_VEGA20_DOORBELL_MEC_RING7 = 0x00A,
> + AMDGPU_VEGA20_DOORBELL_USERQUEUE_START = 0x00B,
> + AMDGPU_VEGA20_DOORBELL_USERQUEUE_END = 0x08A,
> + AMDGPU_VEGA20_DOORBELL_GFX_RING0 = 0x08B,
> + /* SDMA:256~335*/
> + AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0= 0x100,
> + AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE1= 0x10A,
> + AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE2= 0x114,
> + AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE3= 0x11E,
> + AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE4= 0x128,
> + AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE5= 0x132,
> + AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE6= 0x13C,
> + AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE7= 0x146,
> + /* IH: 376~391 */
> + AMDGPU_VEGA20_DOORBELL_IH = 0x178,
> + /* MMSCH: 392~407
> +* overlap the doorbell assignment with VCN as they are mutually
> exclusive
> +* VCE engine's doorbell is 32 bit and two VCE ring share one QWORD
> +*/
> + AMDGPU_VEGA20_DOORBELL64_VCN0_1 = 0x188, /* lower 32
> bits for VNC0 and upper 32 bits for VNC1 */
> + AMDGPU_VEGA20_DOORBELL64_VCN2_3 = 0x189,
> + AMDGPU_VEGA20_DOORBELL64_VCN4_5 = 0x18A,
> + AMDGPU_VEGA20_DOORBELL64_VCN6_7 = 0x18B,
> +
> + AMDGPU_VEGA20_DOORBELL64_UVD_RING0_1 = 0x188,
> + AMDGPU_VEGA20_DOORBELL64_UVD_RING2_3 = 0x189,
> + AMDGPU_VEGA20_DOORBELL64_UVD_RING4_5 = 0x18A,
> + AMDGPU_VEGA20_DOORBELL64_UVD_RING6_7 = 0x18B,
> +
> + AMDGPU_VEGA20_DOORBELL64_VCE_RING0_1 = 0x18C,
> + AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3 = 0x18D,
> + AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5 = 0x18E,
> + AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7 = 0x18F,
> + AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT= 0x18F,
> + AMDGPU_VEGA20_DOORBELL_INVALID = 0x
> +} AMDGPU_VEGA20_DOORBELL_ASSIGNMENT;
> +
> /*
> * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space
> */
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 3ffd8f5..19f2149 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -517,8 +517,10 @@ static int amdgpu_device_doorbell_init(struct
> amdgpu_device *adev)
> vi_doorbell_index_init(adev);
> else if (adev->asic_type == CHIP_VEGA10)
> vega10_doorbell_index_init(adev);
> - else
> + else if (adev->asic_type == CHIP_VEGA12 || adev->asic_type ==
> CHIP_RAVEN)
> vega12_doorbell_index_init(adev);
> + else
> + vega20_doorbell_index_init(adev);
>
> /* No doorbell on SI hardware generation */
> if (adev->asic_type < CHIP_BONAIRE) {
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h
> b/drivers/gpu/drm/amd/amdgpu/soc15.h
>
Re: [PATCH] drm/amd/amdgpu/vce_v3_0.c: Remove duplicate header
Applied. thanks! On Wed, Nov 21, 2018 at 3:16 AM Zhang, Jerry(Junwei) wrote: > > On 11/21/18 3:11 PM, Brajeswar Ghosh wrote: > > Remove gca/gfx_8_0_d.h which is included more than once > > > > Signed-off-by: Brajeswar Ghosh > Reviewed-by: Junwei Zhang > > > --- > > drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 1 - > > 1 file changed, 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c > > b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c > > index 6dbd39730070..4e4289a06a53 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c > > +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c > > @@ -37,7 +37,6 @@ > > #include "gca/gfx_8_0_d.h" > > #include "smu/smu_7_1_2_d.h" > > #include "smu/smu_7_1_2_sh_mask.h" > > -#include "gca/gfx_8_0_d.h" > > #include "gca/gfx_8_0_sh_mask.h" > > #include "ivsrcid/ivsrcid_vislands30.h" > > > > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amd/display/amdgpu_dm/amdgpu_dm.c: Remove duplicate header
Applied. thanks! On Wed, Nov 21, 2018 at 9:25 AM Brajeswar Ghosh wrote: > > Remove dm_services_types.h which is included more than once > > Signed-off-by: Brajeswar Ghosh > --- > drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > index e224f23e2215..62a96c683584 100644 > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > @@ -38,7 +38,6 @@ > #include "amd_shared.h" > #include "amdgpu_dm_irq.h" > #include "dm_helpers.h" > -#include "dm_services_types.h" > #include "amdgpu_dm_mst_types.h" > #if defined(CONFIG_DEBUG_FS) > #include "amdgpu_dm_debugfs.h" > -- > 2.17.1 > > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amd/amdgpu: Remove duplicate header
Applied. thanks! On Wed, Nov 21, 2018 at 9:24 AM Brajeswar Ghosh wrote: > > Remove gca/gfx_8_0_sh_mask.h which is included more than once > > Signed-off-by: Brajeswar Ghosh > --- > drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c > b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c > index 64e875d528dd..6a0fcd67662a 100644 > --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c > +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c > @@ -37,7 +37,6 @@ > #include "gmc/gmc_8_2_sh_mask.h" > #include "oss/oss_3_0_d.h" > #include "oss/oss_3_0_sh_mask.h" > -#include "gca/gfx_8_0_sh_mask.h" > #include "dce/dce_10_0_d.h" > #include "dce/dce_10_0_sh_mask.h" > #include "smu/smu_7_1_3_d.h" > -- > 2.17.1 > > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amd: Query and use ACPI backlight caps
On 2018-11-20 10:16 a.m., David Francis wrote:
> ACPI ATIF has a function called query
> backlight transfer characteristics. Among the
> information returned by this function is
> the minimum and maximum input signals for the
> backlight
>
> Call that function on ACPI init. When DM
> backlight device is updated, copy over the
> backlight caps into DM, but only once. Use
> the backlight caps in the backlight-to-dc
> calculation.
>
> Signed-off-by: David Francis
Reviewed-by: Harry Wentland
Harry
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 83 +++
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 59 ++---
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 13 +++
> drivers/gpu/drm/amd/include/amd_acpi.h| 24 ++
> 5 files changed, 170 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 2c80453ca350..adbad0e2d4ea 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1255,6 +1255,9 @@ bool
> amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *ade
> int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
> u8 perf_req, bool advertise);
> int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
> +
> +void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev,
> + struct amdgpu_dm_backlight_caps *caps);
> #else
> static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
> static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> index 471266901d1b..47db65926d71 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> @@ -65,6 +65,7 @@ struct amdgpu_atif {
> struct amdgpu_atif_functions functions;
> struct amdgpu_atif_notification_cfg notification_cfg;
> struct amdgpu_encoder *encoder_for_bl;
> + struct amdgpu_dm_backlight_caps backlight_caps;
> };
>
> /* Call the ATIF method
> @@ -297,6 +298,65 @@ static int amdgpu_atif_get_notification_params(struct
> amdgpu_atif *atif)
> return err;
> }
>
> +/**
> + * amdgpu_atif_query_backlight_caps - get min and max backlight input signal
> + *
> + * @handle: acpi handle
> + *
> + * Execute the QUERY_BRIGHTNESS_TRANSFER_CHARACTERISTICS ATIF function
> + * to determine the acceptable range of backlight values
> + *
> + * Backlight_caps.caps_valid will be set to true if the query is successful
> + *
> + * The input signals are in range 0-255
> + *
> + * This function assumes the display with backlight is the first LCD
> + *
> + * Returns 0 on success, error on failure.
> + */
> +static int amdgpu_atif_query_backlight_caps(struct amdgpu_atif *atif)
> +{
> + union acpi_object *info;
> + struct atif_qbtc_output characteristics;
> + struct atif_qbtc_arguments arguments;
> + struct acpi_buffer params;
> + size_t size;
> + int err = 0;
> +
> + arguments.size = sizeof(arguments);
> + arguments.requested_display = ATIF_QBTC_REQUEST_LCD1;
> +
> + params.length = sizeof(arguments);
> + params.pointer = (void *)
> +
> + info = amdgpu_atif_call(atif,
> + ATIF_FUNCTION_QUERY_BRIGHTNESS_TRANSFER_CHARACTERISTICS,
> + );
> + if (!info) {
> + err = -EIO;
> + goto out;
> + }
> +
> + size = *(u16 *) info->buffer.pointer;
> + if (size < 10) {
> + err = -EINVAL;
> + goto out;
> + }
> +
> + memset(, 0, sizeof(characteristics));
> + size = min(sizeof(characteristics), size);
> + memcpy(, info->buffer.pointer, size);
> +
> + atif->backlight_caps.caps_valid = true;
> + atif->backlight_caps.min_input_signal =
> + characteristics.min_input_signal;
> + atif->backlight_caps.max_input_signal =
> + characteristics.max_input_signal;
> +out:
> + kfree(info);
> + return err;
> +}
> +
> /**
> * amdgpu_atif_get_sbios_requests - get requested sbios event
> *
> @@ -786,6 +846,17 @@ int amdgpu_acpi_init(struct amdgpu_device *adev)
> }
> }
>
> + if (atif->functions.query_backlight_transfer_characteristics) {
> + ret = amdgpu_atif_query_backlight_caps(atif);
> + if (ret) {
> + DRM_DEBUG_DRIVER("Call to
> QUERY_BACKLIGHT_TRANSFER_CHARACTERISTICS failed: %d\n",
> + ret);
> + atif->backlight_caps.caps_valid = false;
> + }
> + } else {
> + atif->backlight_caps.caps_valid = false;
> + }
> +
> out:
> adev->acpi_nb.notifier_call = amdgpu_acpi_event;
>
Re: [PATCH 5/5] drm/amdgpu: Refactor GPU reset for XGMI hive case.
I saw you use the global xgmi_mutex to prevent concurrent reset to be
triggered by different nodes , but after the mutex been released ,
current node may grap the mutex and continue to do another reset .
Maybe we should check the GPU status and skip the reset in this case
since the GPU may already be in good state .
Regards
shaoyun.liu
On 2018-11-21 1:10 p.m., Andrey Grodzovsky wrote:
> For XGMI hive case do reset in steps where each step iterates over
> all devs in hive. This especially important for asic reset
> since all PSP FW in hive must come up within a limited time
> (around 1 sec) to properply negotiate the link.
> Do this by refactoring amdgpu_device_gpu_recover and amdgpu_device_reset
> into pre_asic_reset, asic_reset and post_asic_reset functions where is part
> is exectued for all the GPUs in the hive before going to the next step.
>
> Signed-off-by: Andrey Grodzovsky
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h| 5 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 375
> -
> 2 files changed, 264 insertions(+), 116 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 4ef5f7a..bd06d45 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1026,6 +1026,9 @@ struct amdgpu_device {
> unsigned long last_mm_index;
> boolin_gpu_reset;
> struct mutex lock_reset;
> +
> + int asic_reset_res;
> + int resched;
> };
>
> static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device
> *bdev)
> @@ -1232,7 +1235,7 @@ struct amdgpu_hive_info;
>
> struct list_head *amdgpu_xgmi_get_adev_list_handle(struct amdgpu_hive_info
> *hive);
> struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev);
> -int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive);
> +int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive, struct
> amdgpu_device *adev);
> int amdgpu_xgmi_add_device(struct amdgpu_device *adev);
>
> /*
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index cb06e68..8e94d7f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -3157,86 +3157,6 @@ static int amdgpu_device_recover_vram(struct
> amdgpu_device *adev)
> return 0;
> }
>
> -/**
> - * amdgpu_device_reset - reset ASIC/GPU for bare-metal or passthrough
> - *
> - * @adev: amdgpu device pointer
> - *
> - * attempt to do soft-reset or full-reset and reinitialize Asic
> - * return 0 means succeeded otherwise failed
> - */
> -static int amdgpu_device_reset(struct amdgpu_device *adev)
> -{
> - bool need_full_reset, vram_lost = 0;
> - int r;
> -
> - need_full_reset = amdgpu_device_ip_need_full_reset(adev);
> -
> - if (!need_full_reset) {
> - amdgpu_device_ip_pre_soft_reset(adev);
> - r = amdgpu_device_ip_soft_reset(adev);
> - amdgpu_device_ip_post_soft_reset(adev);
> - if (r || amdgpu_device_ip_check_soft_reset(adev)) {
> - DRM_INFO("soft reset failed, will fallback to full
> reset!\n");
> - need_full_reset = true;
> - }
> - }
> -
> - if (need_full_reset) {
> - r = amdgpu_device_ip_suspend(adev);
> -
> -retry:
> - r = amdgpu_asic_reset(adev);
> - /* post card */
> - amdgpu_atom_asic_init(adev->mode_info.atom_context);
> -
> - if (!r) {
> - dev_info(adev->dev, "GPU reset succeeded, trying to
> resume\n");
> - r = amdgpu_device_ip_resume_phase1(adev);
> - if (r)
> - goto out;
> -
> - vram_lost = amdgpu_device_check_vram_lost(adev);
> - if (vram_lost) {
> - DRM_ERROR("VRAM is lost!\n");
> - atomic_inc(>vram_lost_counter);
> - }
> -
> - r = amdgpu_gtt_mgr_recover(
> - >mman.bdev.man[TTM_PL_TT]);
> - if (r)
> - goto out;
> -
> - r = amdgpu_device_fw_loading(adev);
> - if (r)
> - return r;
> -
> - r = amdgpu_device_ip_resume_phase2(adev);
> - if (r)
> - goto out;
> -
> - if (vram_lost)
> - amdgpu_device_fill_reset_magic(adev);
> - }
> - }
> -
> -out:
> - if (!r) {
> - amdgpu_irq_gpu_reset_resume_helper(adev);
> - r = amdgpu_ib_ring_tests(adev);
> - if (r) {
> - dev_err(adev->dev, "ib ring test failed (%d).\n", r);
> -
Re: [PATCH 4/7] drm/amdgpu: Doorbell index initialization for ASICs before vega10
On Wed, Nov 21, 2018 at 5:00 PM Oak Zeng wrote:
>
> v2: Use enum definition instead of hardcoded number
>
> Change-Id: Id64eb98f5b1c24b51eb2fd5a083086fc3515813d
> Signed-off-by: Oak Zeng
> Suggested-by: Felix Kuehling
> Suggested-by: Alex Deucher
Since this covers cik and vi, maybe call it cik_doorbell_index_init()
or legacy_doorbell_index_init()?
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/Makefile | 2 +-
> drivers/gpu/drm/amd/amdgpu/vi.h | 2 +-
> drivers/gpu/drm/amd/amdgpu/vi_reg_init.c | 43
>
> 3 files changed, 45 insertions(+), 2 deletions(-)
> create mode 100644 drivers/gpu/drm/amd/amdgpu/vi_reg_init.c
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
> b/drivers/gpu/drm/amd/amdgpu/Makefile
> index 1cef9e1..ae29bf5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/Makefile
> +++ b/drivers/gpu/drm/amd/amdgpu/Makefile
> @@ -63,7 +63,7 @@ amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o
> si_ih.o si_dma.o dce
>
> amdgpu-y += \
> vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o
> vega10_reg_init.o \
> - vega20_reg_init.o nbio_v7_4.o vega12_reg_init.o
> + vega20_reg_init.o nbio_v7_4.o vega12_reg_init.o vi_reg_init.o
>
> # add DF block
> amdgpu-y += \
> diff --git a/drivers/gpu/drm/amd/amdgpu/vi.h b/drivers/gpu/drm/amd/amdgpu/vi.h
> index 0429fe3..abcb52e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vi.h
> +++ b/drivers/gpu/drm/amd/amdgpu/vi.h
> @@ -29,5 +29,5 @@
> void vi_srbm_select(struct amdgpu_device *adev,
> u32 me, u32 pipe, u32 queue, u32 vmid);
> int vi_set_ip_blocks(struct amdgpu_device *adev);
> -
> +void vi_doorbell_index_init(struct amdgpu_device *adev);
> #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/vi_reg_init.c
> b/drivers/gpu/drm/amd/amdgpu/vi_reg_init.c
> new file mode 100644
> index 000..cdeb88d
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/amdgpu/vi_reg_init.c
> @@ -0,0 +1,43 @@
> +/*
> + * Copyright 2018 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + */
> +
> +#include "amdgpu.h"
> +
> +void vi_doorbell_index_init(struct amdgpu_device *adev)
> +{
> + adev->doorbell_index.kiq = AMDGPU_DOORBELL_KIQ;
> + adev->doorbell_index.mec_ring0 = AMDGPU_DOORBELL_MEC_RING0;
> + adev->doorbell_index.mec_ring1 = AMDGPU_DOORBELL_MEC_RING1;
> + adev->doorbell_index.mec_ring2 = AMDGPU_DOORBELL_MEC_RING2;
> + adev->doorbell_index.mec_ring3 = AMDGPU_DOORBELL_MEC_RING3;
> + adev->doorbell_index.mec_ring4 = AMDGPU_DOORBELL_MEC_RING4;
> + adev->doorbell_index.mec_ring5 = AMDGPU_DOORBELL_MEC_RING5;
> + adev->doorbell_index.mec_ring6 = AMDGPU_DOORBELL_MEC_RING6;
> + adev->doorbell_index.mec_ring7 = AMDGPU_DOORBELL_MEC_RING7;
> + adev->doorbell_index.gfx_ring0 = AMDGPU_DOORBELL_GFX_RING0;
> + adev->doorbell_index.sdma_engine0 = AMDGPU_DOORBELL_sDMA_ENGINE0;
> + adev->doorbell_index.sdma_engine1 = AMDGPU_DOORBELL_sDMA_ENGINE1;
> + adev->doorbell_index.ih = AMDGPU_DOORBELL_IH;
> + adev->doorbell_index.max_assignment = AMDGPU_DOORBELL_MAX_ASSIGNMENT;
> +}
> +
> --
> 2.7.4
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
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Re: [PATCH RFC 2/5] cgroup: Add mechanism to register vendor specific DRM devices
(resending because previous email switched to HTML mode and was filtered out) Hi Tejun, On Tue, Nov 20, 2018 at 5:30 PM Tejun Heo wrote: > On Tue, Nov 20, 2018 at 10:21:14PM +, Ho, Kenny wrote: > > By this reply, are you suggesting that vendor specific resources > > will never be acceptable to be managed under cgroup? Let say a user > > I wouldn't say never but whatever which gets included as a cgroup > controller should have clearly defined resource abstractions and the > control schemes around them including support for delegation. AFAICS, > gpu side still seems to have a long way to go (and it's not clear > whether that's somewhere it will or needs to end up). Right, I totally understand that it's not obvious from this RFC because the 'resource' counting demonstrated in this RFC is trivial in nature, mostly to illustrate the 'vendor' concept. The structure of this patch actually give us the ability to support both abstracted resources you mentioned and vendor specific resources. It is probably not obvious as the RFC only includes two resources and they are both vendor specific. To be clear, I am not saying there aren't abstracted resources in drm, there are (we are still working on those). What I am saying is that not all resources are abstracted and for the purpose of this RFC I was hoping to get some feedback on the vendor specific parts early just so that we don't go down the wrong path. That said, I think I am getting a better sense of what you are saying. Please correct me if I misinterpreted: your concern is that abstracting by vendor is too high level and it's too much of a free-for-all. Instead, resources should be abstracted at the controller level even if it's only available to a specific vendor (or even a specific product from a specific vendor). Is that a fair read? A couple of additional side questions: * Is statistic/accounting-only use cases like those enabled by cpuacct controller no longer sufficient? If it is still sufficient, can you elaborate more on what you mean by having control schemes and supporting delegation? * When you wrote delegation, do you mean delegation in the sense described in https://www.kernel.org/doc/Documentation/cgroup-v2.txt ? > > To put the questions in more concrete terms, let say a user wants to > > expose certain part of a gpu to a particular cgroup similar to the > > way selective cpu cores are exposed to a cgroup via cpuset, how > > should we go about enabling such functionality? > > Do what the intel driver or bpf is doing? It's not difficult to hook > into cgroup for identification purposes. Does intel driver or bpf present an interface file in cgroupfs for users to configure the core selection like cpuset? I must admit I am not too familiar with the bpf case as I was referencing mostly the way rdma was implemented when putting this RFC together. Perhaps I wasn't communicating clearly so let me see if I can illustrate this discussion with a hypothetical but concrete example using our competitor's product. Nvidia has something called Tensor Cores in some of their GPUs and the purpose of those cores is to accelerate matrix operations for machine learning applications. This is something unique to Nvidia and to my knowledge no one else has something like it. These cores are different from regular shader processors and there are multiple of them in a GPU. Under the structure of this RFC, if Nvidia wants to make Tensor Cores manageable via cgroup (with the "Allocation" distribution model let say), they will probably have an interface file called "drm.nvidia.tensor_core", in which only nvidia's GPUs will be listed. If a GPU has TC, it will have a positive count, otherwise 0. If I understand you correctly Tejun, is that they should not do that. What they should do is have an abstracted resource, possibly named "drm.matrix_accelerator" where all drm devices available on a system will be listed. All GPUs except some Nvidia's will have a count of 0. Or perhaps that is not sufficiently abstracted so instead there should be just "drm.cores" instead and that file list both device, core types and count. For one vendor they may have shader proc, texture map unit, tensor core, ray tracing cores as types. Others may have ALUs, EUs and subslices. Is that an accurate representation of what you are recommending? Regards, Kenny ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 1/7] drm/amdgpu: Add field in amdgpu_dev to hold reserved doorbell index
On Wed, Nov 21, 2018 at 5:00 PM Oak Zeng wrote:
>
> This is a preparation work to make reserved doorbell index per device,
> instead of using a global macro definition. By doing this, we can easily
> change doorbell layout for future ASICs while not affecting ASICs in
> production.
>
> Change-Id: If08e2bc9d0749748ed4083ba4eb32a4698763085
> Signed-off-by: Oak Zeng
> Suggested-by: Felix Kuehling
> Suggested-by: Alex Deucher
Reviewed-by: Alex Deucher
It would be nice to move all of the doorbell related enums and this
structure into amdgpu_doorbell.h, but that can be later cleanup.
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 50
> +
> 1 file changed, 50 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 2c80453..b7ee4ef 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -813,6 +813,55 @@ struct amd_powerplay {
> uint32_t pp_feature;
> };
>
> +/* Reserved doorbells for amdgpu (including multimedia).
> + * KFD can use all the rest in the 2M doorbell bar.
> + * For asic before vega10, doorbell is 32-bit, so the
> + * index/offset is in dword. For vega10 and after, doorbell
> + * can be 64-bit, so the index defined is in qword.
> + */
> +struct amdgpu_doorbell_index {
> + uint32_t kiq;
> + uint32_t mec_ring0;
> + uint32_t mec_ring1;
> + uint32_t mec_ring2;
> + uint32_t mec_ring3;
> + uint32_t mec_ring4;
> + uint32_t mec_ring5;
> + uint32_t mec_ring6;
> + uint32_t mec_ring7;
> + uint32_t userqueue_start;
> + uint32_t userqueue_end;
> + uint32_t gfx_ring0;
> + uint32_t sdma_engine0;
> + uint32_t sdma_engine1;
> + uint32_t sdma_engine2;
> + uint32_t sdma_engine3;
> + uint32_t sdma_engine4;
> + uint32_t sdma_engine5;
> + uint32_t sdma_engine6;
> + uint32_t sdma_engine7;
> + uint32_t ih;
> + union {
> + struct {
> + uint32_t vcn_ring0_1;
> + uint32_t vcn_ring2_3;
> + uint32_t vcn_ring4_5;
> + uint32_t vcn_ring6_7;
> + } vcn;
> + struct {
> + uint32_t uvd_ring0_1;
> + uint32_t uvd_ring2_3;
> + uint32_t uvd_ring4_5;
> + uint32_t uvd_ring6_7;
> + uint32_t vce_ring0_1;
> + uint32_t vce_ring2_3;
> + uint32_t vce_ring4_5;
> + uint32_t vce_ring6_7;
> + } uvd_vce;
> + };
> + uint32_t max_assignment;
> +};
> +
> #define AMDGPU_RESET_MAGIC_NUM 64
> struct amdgpu_device {
> struct device *dev;
> @@ -1026,6 +1075,7 @@ struct amdgpu_device {
> unsigned long last_mm_index;
> boolin_gpu_reset;
> struct mutex lock_reset;
> + struct amdgpu_doorbell_index doorbell_index;
> };
>
> static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device
> *bdev)
> --
> 2.7.4
>
> ___
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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Re: [PATCH 5/7] drm/amdgpu: Call doorbell index init on device initialization
On Wed, Nov 21, 2018 at 5:00 PM Oak Zeng wrote:
>
> Change-Id: I2f004bbbe2565035460686f4fc16e86b77a2a9b5
> Signed-off-by: Oak Zeng
> Suggested-by: Felix Kuehling
> Suggested-by: Alex Deucher
I think it would be cleaner to call this in the soc files directly
(cik.c, vi.c, soc15.c in the set_ip_blocks() functions). It keeps the
asic specific bits out of amdgpu_device.c.
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index cb06e68..a942a88 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -513,6 +513,13 @@ void amdgpu_device_pci_config_reset(struct amdgpu_device
> *adev)
> */
> static int amdgpu_device_doorbell_init(struct amdgpu_device *adev)
> {
> + if (adev->asic_type < CHIP_VEGA10)
> + vi_doorbell_index_init(adev);
> + else if (adev->asic_type == CHIP_VEGA10)
> + vega10_doorbell_index_init(adev);
> + else
> + vega12_doorbell_index_init(adev);
> +
> /* No doorbell on SI hardware generation */
> if (adev->asic_type < CHIP_BONAIRE) {
> adev->doorbell.base = 0;
> --
> 2.7.4
>
> ___
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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Re: [PATCH v4 2/2] drm/amd: Add abm level drm property
On 2018-11-20 11:00 a.m., David Francis wrote:
> Adaptive Backlight Management (ABM) is a feature
> that reduces backlight level to save power, while
> increasing pixel contrast and pixel luminance
> to maintain readability and image quality.
>
> ABM will adjust in response to the
> pixel luminance of the displayed content.
>
> ABM is made available as a drm property on eDP
> monitors called "abm level", which ranges from 0 to 4.
> When this property is set to 0, ABM is off. Levels 1
> to 4 represent different ranges of backlight reduction.
> At higher levels both the backlight reduction and pixel
> adjustment will be greater.
>
> ABM requires DMCU firmware, which is currently available for
> Raven ASICs only. If the feature does not work, please
> ensure your firmware is up to date.
>
> v2:
> Fix commit message, only attach property if DMCU loaded
> v3:
> Store ABM level in crtc state to accommodate dc
> v4:
> Fix ABM saving on dpms cycle
>
> Signed-off-by: David Francis
Series is
Reviewed-by: Harry Wentland
Harry
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 5 +++
> drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 2 ++
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 36 ---
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 3 ++
> drivers/gpu/drm/amd/display/dc/core/dc.c | 11 +-
> drivers/gpu/drm/amd/display/dc/dc.h | 1 +
> 6 files changed, 53 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> index 7d6a36bca9dd..ced8cefa223b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> @@ -637,6 +637,11 @@ int amdgpu_display_modeset_create_props(struct
> amdgpu_device *adev)
>"freesync_capable");
> if (!adev->mode_info.freesync_capable_property)
> return -ENOMEM;
> + adev->mode_info.abm_level_property =
> + drm_property_create_range(adev->ddev, 0,
> + "abm level", 0, 4);
> + if (!adev->mode_info.abm_level_property)
> + return -ENOMEM;
> }
>
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
> index 1627dd3413c7..2938635c0fc1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
> @@ -342,6 +342,8 @@ struct amdgpu_mode_info {
> struct drm_property *freesync_property;
> /* it is used to know about display capability of freesync mode */
> struct drm_property *freesync_capable_property;
> + /* Adaptive Backlight Modulation (power feature) */
> + struct drm_property *abm_level_property;
> /* hardcoded DFP edid from BIOS */
> struct edid *bios_hardcoded_edid;
> int bios_hardcoded_edid_size;
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index f71febb4210d..95b1106e0662 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -2920,6 +2920,7 @@ dm_crtc_duplicate_state(struct drm_crtc *crtc)
> state->adjust = cur->adjust;
> state->vrr_infopacket = cur->vrr_infopacket;
> state->freesync_enabled = cur->freesync_enabled;
> + state->abm_level = cur->abm_level;
>
> /* TODO Duplicate dc_stream after objects are stream object is
> flattened */
>
> @@ -3038,6 +3039,9 @@ int amdgpu_dm_connector_atomic_set_property(struct
> drm_connector *connector,
> } else if (property == adev->mode_info.freesync_capable_property) {
> dm_new_state->freesync_capable = val;
> ret = 0;
> + } else if (property == adev->mode_info.abm_level_property) {
> + dm_new_state->abm_level = val;
> + ret = 0;
> }
>
> return ret;
> @@ -3086,7 +3090,11 @@ int amdgpu_dm_connector_atomic_get_property(struct
> drm_connector *connector,
> } else if (property == adev->mode_info.freesync_capable_property) {
> *val = dm_state->freesync_capable;
> ret = 0;
> + } else if (property == adev->mode_info.abm_level_property) {
> + *val = dm_state->abm_level;
> + ret = 0;
> }
> +
> return ret;
> }
>
> @@ -3151,6 +3159,7 @@ amdgpu_dm_connector_atomic_duplicate_state(struct
> drm_connector *connector)
>
> new_state->freesync_capable = state->freesync_capable;
> new_state->freesync_enable = state->freesync_enable;
> + new_state->abm_level = state->abm_level;
>
> return _state->base;
> }
> @@ -3904,6 +3913,12 @@ void amdgpu_dm_connector_init_helper(struct
> amdgpu_display_manager *dm,
> drm_object_attach_property(>base.base,
>
Re: [PATCH 2/2] drm/atomic: Create and use __drm_atomic_helper_crtc_reset() everywhere
On 12/11/2018 15:01, Maarten Lankhorst wrote:
> We already have __drm_atomic_helper_connector_reset() and
> __drm_atomic_helper_plane_reset(), extend this to crtc as well.
>
> Most drivers already have a gpu reset hook, correct it.
> Nouveau already implemented its own __drm_atomic_helper_crtc_reset(),
> convert it to the common one.
>
> Signed-off-by: Maarten Lankhorst
> Cc: Harry Wentland
> Cc: Leo Li
> Cc: Alex Deucher
> Cc: "Christian König"
> Cc: "David (ChunMing) Zhou"
> Cc: David Airlie
> Cc: Liviu Dudau
> Cc: Brian Starkey
> Cc: Mali DP Maintainers
> Cc: Boris Brezillon
> Cc: Nicolas Ferre
> Cc: Alexandre Belloni
> Cc: Ludovic Desroches
> Cc: Maarten Lankhorst
> Cc: Maxime Ripard
> Cc: Sean Paul
> Cc: Jani Nikula
> Cc: Joonas Lahtinen
> Cc: Rodrigo Vivi
> Cc: Philipp Zabel
> Cc: CK Hu
> Cc: Matthias Brugger
> Cc: Rob Clark
> Cc: Ben Skeggs
> Cc: Tomi Valkeinen
> Cc: Laurent Pinchart
> Cc: Kieran Bingham
> Cc: Sandy Huang
> Cc: "Heiko Stübner"
> Cc: Thierry Reding
> Cc: Jonathan Hunter
> Cc: Eric Anholt
> Cc: VMware Graphics
> Cc: Sinclair Yeh
> Cc: Thomas Hellstrom
> Cc: Tony Cheng
> Cc: Shirish S
> Cc: Mikita Lipski
> Cc: Bhawanpreet Lakha
> Cc: David Francis
> Cc: Anthony Koo
> Cc: Jeykumar Sankaran
> Cc: Jordan Crouse
> Cc: Bruce Wang
> Cc: Sravanthi Kollukuduru
> Cc: Archit Taneja
> Cc: Steve Kowalik
> Cc: Carsten Behling
> Cc: Haneen Mohammed
> Cc: Daniel Vetter
> Cc: Rodrigo Siqueira
> Cc: Mahesh Kumar
> Cc: amd-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org
> Cc: linux-ker...@vger.kernel.org
> Cc: linux-arm-ker...@lists.infradead.org
> Cc: intel-...@lists.freedesktop.org
> Cc: linux-media...@lists.infradead.org
> Cc: linux-arm-...@vger.kernel.org
> Cc: freedr...@lists.freedesktop.org
> Cc: nouv...@lists.freedesktop.org
> Cc: linux-renesas-...@vger.kernel.org
> Cc: linux-rockc...@lists.infradead.org
> Cc: linux-te...@vger.kernel.org
> ---
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +--
> drivers/gpu/drm/arm/malidp_crtc.c | 5 +--
> .../gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c| 5 +--
> drivers/gpu/drm/drm_atomic_state_helper.c | 31 ---
> drivers/gpu/drm/i915/intel_display.c | 2 +-
> drivers/gpu/drm/imx/ipuv3-crtc.c | 5 +--
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 5 +--
> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 12 ++-
> drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 6 +---
> drivers/gpu/drm/nouveau/dispnv50/head.c | 13 ++--
> drivers/gpu/drm/omapdrm/omap_crtc.c | 7 ++---
> drivers/gpu/drm/rcar-du/rcar_du_crtc.c| 4 +--
> drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 7 +++--
> drivers/gpu/drm/tegra/dc.c| 5 +--
> drivers/gpu/drm/vc4/vc4_crtc.c| 8 ++---
> drivers/gpu/drm/vkms/vkms_crtc.c | 7 +
> drivers/gpu/drm/vmwgfx/vmwgfx_kms.c | 9 +-
> include/drm/drm_atomic_state_helper.h | 2 ++
> 18 files changed, 56 insertions(+), 81 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 5064768642f3..770a71726cd1 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -2802,9 +2802,7 @@ static void dm_crtc_reset_state(struct drm_crtc *crtc)
> if (WARN_ON(!state))
> return;
>
> - crtc->state = >base;
> - crtc->state->crtc = crtc;
> -
> + __drm_atomic_helper_crtc_reset(crtc, >base);
> }
>
> static struct drm_crtc_state *
> diff --git a/drivers/gpu/drm/arm/malidp_crtc.c
> b/drivers/gpu/drm/arm/malidp_crtc.c
> index e1b72782848c..9a924ff27148 100644
> --- a/drivers/gpu/drm/arm/malidp_crtc.c
> +++ b/drivers/gpu/drm/arm/malidp_crtc.c
> @@ -474,10 +474,7 @@ static void malidp_crtc_reset(struct drm_crtc *crtc)
>
> kfree(state);
> state = kzalloc(sizeof(*state), GFP_KERNEL);
> - if (state) {
> - crtc->state = >base;
> - crtc->state->crtc = crtc;
> - }
> + __drm_atomic_helper_crtc_reset(crtc, >base);
> }
>
> static void malidp_crtc_destroy_state(struct drm_crtc *crtc,
> diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
> b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
> index 96f4082671fe..8084d549c7d1 100644
> --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
> +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
> @@ -412,10 +412,7 @@ static void atmel_hlcdc_crtc_reset(struct drm_crtc *crtc)
> }
>
> state = kzalloc(sizeof(*state), GFP_KERNEL);
> - if (state) {
> - crtc->state = >base;
> - crtc->state->crtc = crtc;
> - }
> + __drm_atomic_helper_crtc_reset(crtc, >base);
> }
>
> static struct drm_crtc_state *
> diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c
>
Re: [PATCH 2/7] drm/amdgpu: Vega10 doorbell index initialization
On Wed, Nov 21, 2018 at 5:00 PM Oak Zeng wrote:
>
> v2: Use enum definition instead of hardcoded value
>
> Change-Id: Ib72058337f0aa53adfc6c6aae5341a7cd665111a
> Signed-off-by: Oak Zeng
> Suggested-by: Felix Kuehling
> Suggested-by: Alex Deucher
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/soc15.h | 1 +
> drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c | 28
>
> 2 files changed, 29 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h
> b/drivers/gpu/drm/amd/amdgpu/soc15.h
> index f8ad780..d37c57d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.h
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.h
> @@ -58,4 +58,5 @@ void soc15_program_register_sequence(struct amdgpu_device
> *adev,
> int vega10_reg_base_init(struct amdgpu_device *adev);
> int vega20_reg_base_init(struct amdgpu_device *adev);
>
> +void vega10_doorbell_index_init(struct amdgpu_device *adev);
> #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
> b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
> index c5c9b2b..9ba8e02 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
> @@ -56,4 +56,32 @@ int vega10_reg_base_init(struct amdgpu_device *adev)
> return 0;
> }
>
> +void vega10_doorbell_index_init(struct amdgpu_device *adev)
> +{
> + adev->doorbell_index.kiq = AMDGPU_DOORBELL64_KIQ;
> + adev->doorbell_index.mec_ring0 = AMDGPU_DOORBELL64_MEC_RING0;
> + adev->doorbell_index.mec_ring1 = AMDGPU_DOORBELL64_MEC_RING1;
> + adev->doorbell_index.mec_ring2 = AMDGPU_DOORBELL64_MEC_RING2;
> + adev->doorbell_index.mec_ring3 = AMDGPU_DOORBELL64_MEC_RING3;
> + adev->doorbell_index.mec_ring4 = AMDGPU_DOORBELL64_MEC_RING4;
> + adev->doorbell_index.mec_ring5 = AMDGPU_DOORBELL64_MEC_RING5;
> + adev->doorbell_index.mec_ring6 = AMDGPU_DOORBELL64_MEC_RING6;
> + adev->doorbell_index.mec_ring7 = AMDGPU_DOORBELL64_MEC_RING7;
> + adev->doorbell_index.userqueue_start =
> AMDGPU_DOORBELL64_USERQUEUE_START;
> + adev->doorbell_index.userqueue_end = AMDGPU_DOORBELL64_USERQUEUE_END;
> + adev->doorbell_index.gfx_ring0 = AMDGPU_DOORBELL64_GFX_RING0;
> + adev->doorbell_index.sdma_engine0 =
> AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0;
> + adev->doorbell_index.sdma_engine1 =
> AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1;
> + adev->doorbell_index.ih = AMDGPU_DOORBELL64_IH;
> + adev->doorbell_index.uvd_vce.uvd_ring0_1 =
> AMDGPU_DOORBELL64_UVD_RING0_1;
> + adev->doorbell_index.uvd_vce.uvd_ring2_3 =
> AMDGPU_DOORBELL64_UVD_RING2_3;
> + adev->doorbell_index.uvd_vce.uvd_ring4_5 =
> AMDGPU_DOORBELL64_UVD_RING4_5;
> + adev->doorbell_index.uvd_vce.uvd_ring6_7 =
> AMDGPU_DOORBELL64_UVD_RING6_7;
> + adev->doorbell_index.uvd_vce.vce_ring0_1 =
> AMDGPU_DOORBELL64_VCE_RING0_1;
> + adev->doorbell_index.uvd_vce.vce_ring2_3 =
> AMDGPU_DOORBELL64_VCE_RING2_3;
> + adev->doorbell_index.uvd_vce.vce_ring4_5 =
> AMDGPU_DOORBELL64_VCE_RING4_5;
> + adev->doorbell_index.uvd_vce.vce_ring6_7 =
> AMDGPU_DOORBELL64_VCE_RING6_7;
> + /* In unit of dword doorbell */
> + adev->doorbell_index.max_assignment =
> AMDGPU_DOORBELL64_MAX_ASSIGNMENT << 1;
> +}
>
> --
> 2.7.4
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
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Re: [PATCH 1/5] drm/amdgpu/psp: Add mode 0 reset function.
On Wed, Nov 21, 2018 at 1:10 PM Andrey Grodzovsky
wrote:
>
> Currently just a place holder until support from PSP in place.
>
> Signed-off-by: Andrey Grodzovsky
I think we can drop this patch for now until we figure out what the
proper reset method will be for this. We may end up using baco.
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 3 +++
> drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 8
> 2 files changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
> index 9ec5d1a..2bdb394 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
> @@ -83,6 +83,7 @@ struct psp_funcs
> enum AMDGPU_UCODE_ID ucode_type);
> bool (*smu_reload_quirk)(struct psp_context *psp);
> int (*mode1_reset)(struct psp_context *psp);
> + int (*mode0_reset)(struct psp_context *psp);
> uint64_t (*xgmi_get_node_id)(struct psp_context *psp);
> uint64_t (*xgmi_get_hive_id)(struct psp_context *psp);
> int (*xgmi_get_topology_info)(struct psp_context *psp, int
> number_devices,
> @@ -194,6 +195,8 @@ struct psp_xgmi_topology_info {
> ((psp)->funcs->smu_reload_quirk ?
> (psp)->funcs->smu_reload_quirk((psp)) : false)
> #define psp_mode1_reset(psp) \
> ((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp))
> : false)
> +#define psp_mode0_reset(psp) \
> + ((psp)->funcs->mode0_reset ? (psp)->funcs->mode1_reset((psp))
> : false)
> #define psp_xgmi_get_node_id(psp) \
> ((psp)->funcs->xgmi_get_node_id ?
> (psp)->funcs->xgmi_get_node_id((psp)) : 0)
> #define psp_xgmi_get_hive_id(psp) \
> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
> b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
> index 082093a..8feb580 100644
> --- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
> @@ -573,6 +573,13 @@ static int psp_v11_0_mode1_reset(struct psp_context *psp)
> return 0;
> }
>
> +static int psp_v11_0_mode0_reset(struct psp_context *psp)
> +{
> + /* TBD Once support from PSP in place */
> +
> + return 0;
> +}
> +
> /* TODO: Fill in follow functions once PSP firmware interface for XGMI is
> ready.
> * For now, return success and hack the hive_id so high level code can
> * start testing
> @@ -698,6 +705,7 @@ static const struct psp_funcs psp_v11_0_funcs = {
> .cmd_submit = psp_v11_0_cmd_submit,
> .compare_sram_data = psp_v11_0_compare_sram_data,
> .mode1_reset = psp_v11_0_mode1_reset,
> + .mode0_reset = psp_v11_0_mode0_reset,
> .xgmi_get_topology_info = psp_v11_0_xgmi_get_topology_info,
> .xgmi_set_topology_info = psp_v11_0_xgmi_set_topology_info,
> .xgmi_get_hive_id = psp_v11_0_xgmi_get_hive_id,
> --
> 2.7.4
>
> ___
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
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Re: [PATCH RFC 2/5] cgroup: Add mechanism to register vendor specific DRM devices
Hi Tejun, On Tue, Nov 20, 2018 at 5:30 PM Tejun Heo wrote: > On Tue, Nov 20, 2018 at 10:21:14PM +, Ho, Kenny wrote: > > By this reply, are you suggesting that vendor specific resources > > will never be acceptable to be managed under cgroup? Let say a user > > I wouldn't say never but whatever which gets included as a cgroup > controller should have clearly defined resource abstractions and the > control schemes around them including support for delegation. AFAICS, > gpu side still seems to have a long way to go (and it's not clear > whether that's somewhere it will or needs to end up). Right, I totally understand that it's not obvious from this RFC because the 'resource' counting demonstrated in this RFC is trivial in nature, mostly to illustrate the 'vendor' concept. The structure of this patch actually give us the ability to support both abstracted resources you mentioned and vendor specific resources. But it is probably not very clear as the RFC only includes two resources and they are both vendor specific. To be clear, I am not saying there aren't abstracted resources in drm, there are (we are still working on those). What I am saying is that not all resources are abstracted and for the purpose of this RFC I was hoping to get some feedback on the vendor specific parts early just so that we don't go down the wrong path. That said, I think I am getting a better sense of what you are saying. Please correct me if I misinterpreted: your concern is that abstracting by vendor is too high level and it's too much of a free-for-all. Instead, resources should be abstracted at the controller level even if it's only available to a specific vendor (or even a specific product from a specific vendor). Is that a fair read? A couple of additional side questions: * Is statistic/accounting-only use cases like those enabled by cpuacct controller no longer sufficient? If it is still sufficient, can you elaborate more on what you mean by having control schemes and supporting delegation? * When you wrote delegation, do you mean delegation in the sense described in https://www.kernel.org/doc/Documentation/cgroup-v2.txt ? > > To put the questions in more concrete terms, let say a user wants to > > expose certain part of a gpu to a particular cgroup similar to the > > way selective cpu cores are exposed to a cgroup via cpuset, how > > should we go about enabling such functionality? > > Do what the intel driver or bpf is doing? It's not difficult to hook > into cgroup for identification purposes. Does intel driver or bpf present an interface file in cgroupfs for users to configure the core selection like cpuset? I must admit I am not too familiar with the bpf case as I was referencing mostly the way rdma was implemented when putting this RFC together. Perhaps I wasn't communicating clearly so let me see if I can illustrate this discussion with a hypothetical but concrete example using our competitor's product. Nvidia has something called Tensor Cores in some of their GPUs and the purpose of those cores is to accelerate matrix operations for machine learning applications. This is something unique to Nvidia and to my knowledge no one else has something like it. These cores are different from regular shader processors and there are multiple of them in a GPU. Under the structure of this RFC, if Nvidia wants to make Tensor Cores manageable via cgroup (with the "Allocation" distribution model let say), they will probably have an interface file called "drm.nvidia.tensor_core", in which only nvidia's GPUs will be listed. If a GPU has TC, it will have a positive count, otherwise 0. If I understand you correctly Tejun, is that they should not do that. What they should do is have an abstracted resource, possibly named "drm.matrix_accelerator" where all drm devices available on a system will be listed. All GPUs except some Nvidia's will have a count of 0. Or perhaps that is not sufficiently abstracted so instead there should be just "drm.cores" instead and that file list both device, core types and count. For one vendor they may have shader proc, texture map unit, tensor core, ray tracing cores as types. Others may have ALUs, EUs and subslices. Is that an accurate representation of what you are recommending? Regards, Kenny ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 1/4] drm/edid: Pass connector to AVI inforframe functions
On Wed, Nov 21, 2018 at 01:40:43PM +0200, Jani Nikula wrote:
> On Tue, 20 Nov 2018, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Make life easier for drivers by simply passing the connector
> > to drm_hdmi_avi_infoframe_from_display_mode() and
> > drm_hdmi_avi_infoframe_quant_range(). That way drivers don't
> > need to worry about is_hdmi2_sink mess.
>
> Overall looks about right and nice,
>
> Reviewed-by: Jani Nikula
>
> But please do take that with a grain of salt for everything outside of
> i915 and drm core.
>
> Please also find a few comments inline below.
>
> > Cc: Alex Deucher
> > Cc: "Christian König"
> > Cc: "David (ChunMing) Zhou"
> > Cc: Archit Taneja
> > Cc: Andrzej Hajda
> > Cc: Laurent Pinchart
> > Cc: Inki Dae
> > Cc: Joonyoung Shim
> > Cc: Seung-Woo Kim
> > Cc: Kyungmin Park
> > Cc: Russell King
> > Cc: CK Hu
> > Cc: Philipp Zabel
> > Cc: Rob Clark
> > Cc: Ben Skeggs
> > Cc: Tomi Valkeinen
> > Cc: Sandy Huang
> > Cc: "Heiko Stübner"
> > Cc: Benjamin Gaignard
> > Cc: Vincent Abriou
> > Cc: Thierry Reding
> > Cc: Eric Anholt
> > Cc: Shawn Guo
> > Cc: Ilia Mirkin
> > Cc: amd-gfx@lists.freedesktop.org
> > Cc: linux-arm-...@vger.kernel.org
> > Cc: freedr...@lists.freedesktop.org
> > Cc: nouv...@lists.freedesktop.org
> > Cc: linux-te...@vger.kernel.org
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/amd/amdgpu/dce_v10_0.c| 2 +-
> > drivers/gpu/drm/amd/amdgpu/dce_v11_0.c| 2 +-
> > drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 3 ++-
> > drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 2 +-
> > drivers/gpu/drm/bridge/analogix-anx78xx.c | 5 ++--
> > drivers/gpu/drm/bridge/sii902x.c | 3 ++-
> > drivers/gpu/drm/bridge/sil-sii8620.c | 3 +--
> > drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 3 ++-
> > drivers/gpu/drm/drm_edid.c| 33 ++-
> > drivers/gpu/drm/exynos/exynos_hdmi.c | 3 ++-
> > drivers/gpu/drm/i2c/tda998x_drv.c | 3 ++-
> > drivers/gpu/drm/i915/intel_hdmi.c | 14 +-
> > drivers/gpu/drm/i915/intel_lspcon.c | 15 ++-
> > drivers/gpu/drm/i915/intel_sdvo.c | 10 ---
> > drivers/gpu/drm/mediatek/mtk_hdmi.c | 3 ++-
> > drivers/gpu/drm/msm/hdmi/hdmi_bridge.c| 3 ++-
> > drivers/gpu/drm/nouveau/dispnv50/disp.c | 7 +++--
> > drivers/gpu/drm/omapdrm/omap_encoder.c| 5 ++--
> > drivers/gpu/drm/radeon/radeon_audio.c | 2 +-
> > drivers/gpu/drm/rockchip/inno_hdmi.c | 4 ++-
> > drivers/gpu/drm/sti/sti_hdmi.c| 3 ++-
> > drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c| 3 ++-
> > drivers/gpu/drm/tegra/hdmi.c | 3 ++-
> > drivers/gpu/drm/tegra/sor.c | 3 ++-
> > drivers/gpu/drm/vc4/vc4_hdmi.c| 11 +---
> > drivers/gpu/drm/zte/zx_hdmi.c | 4 ++-
> > include/drm/drm_edid.h| 8 +++---
> > 27 files changed, 94 insertions(+), 66 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> > b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> > index 4cfecdce29a3..1f0426d2fc2a 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> > @@ -1682,7 +1682,7 @@ static void dce_v10_0_afmt_setmode(struct drm_encoder
> > *encoder,
> > dce_v10_0_audio_write_sad_regs(encoder);
> > dce_v10_0_audio_write_latency_fields(encoder, mode);
> >
> > - err = drm_hdmi_avi_infoframe_from_display_mode(, mode, false);
> > + err = drm_hdmi_avi_infoframe_from_display_mode(, connector, mode);
> > if (err < 0) {
> > DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
> > return;
> > diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> > b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> > index 7c868916d90f..2280b971d758 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> > @@ -1724,7 +1724,7 @@ static void dce_v11_0_afmt_setmode(struct drm_encoder
> > *encoder,
> > dce_v11_0_audio_write_sad_regs(encoder);
> > dce_v11_0_audio_write_latency_fields(encoder, mode);
> >
> > - err = drm_hdmi_avi_infoframe_from_display_mode(, mode, false);
> > + err = drm_hdmi_avi_infoframe_from_display_mode(, connector, mode);
> > if (err < 0) {
> > DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
> > return;
> > diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> > b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> > index 17eaaba36017..db443ec53d3a 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> > @@ -1423,6 +1423,7 @@ static void dce_v6_0_audio_set_avi_infoframe(struct
> > drm_encoder *encoder,
> > struct amdgpu_device *adev = dev->dev_private;
> > struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
> > struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
> > + struct
Re: [PATCH 1/4] drm/edid: Pass connector to AVI inforframe functions
On Tue, 20 Nov 2018, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Make life easier for drivers by simply passing the connector
> to drm_hdmi_avi_infoframe_from_display_mode() and
> drm_hdmi_avi_infoframe_quant_range(). That way drivers don't
> need to worry about is_hdmi2_sink mess.
Overall looks about right and nice,
Reviewed-by: Jani Nikula
But please do take that with a grain of salt for everything outside of
i915 and drm core.
Please also find a few comments inline below.
> Cc: Alex Deucher
> Cc: "Christian König"
> Cc: "David (ChunMing) Zhou"
> Cc: Archit Taneja
> Cc: Andrzej Hajda
> Cc: Laurent Pinchart
> Cc: Inki Dae
> Cc: Joonyoung Shim
> Cc: Seung-Woo Kim
> Cc: Kyungmin Park
> Cc: Russell King
> Cc: CK Hu
> Cc: Philipp Zabel
> Cc: Rob Clark
> Cc: Ben Skeggs
> Cc: Tomi Valkeinen
> Cc: Sandy Huang
> Cc: "Heiko Stübner"
> Cc: Benjamin Gaignard
> Cc: Vincent Abriou
> Cc: Thierry Reding
> Cc: Eric Anholt
> Cc: Shawn Guo
> Cc: Ilia Mirkin
> Cc: amd-gfx@lists.freedesktop.org
> Cc: linux-arm-...@vger.kernel.org
> Cc: freedr...@lists.freedesktop.org
> Cc: nouv...@lists.freedesktop.org
> Cc: linux-te...@vger.kernel.org
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/amd/amdgpu/dce_v10_0.c| 2 +-
> drivers/gpu/drm/amd/amdgpu/dce_v11_0.c| 2 +-
> drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 3 ++-
> drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 2 +-
> drivers/gpu/drm/bridge/analogix-anx78xx.c | 5 ++--
> drivers/gpu/drm/bridge/sii902x.c | 3 ++-
> drivers/gpu/drm/bridge/sil-sii8620.c | 3 +--
> drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 3 ++-
> drivers/gpu/drm/drm_edid.c| 33 ++-
> drivers/gpu/drm/exynos/exynos_hdmi.c | 3 ++-
> drivers/gpu/drm/i2c/tda998x_drv.c | 3 ++-
> drivers/gpu/drm/i915/intel_hdmi.c | 14 +-
> drivers/gpu/drm/i915/intel_lspcon.c | 15 ++-
> drivers/gpu/drm/i915/intel_sdvo.c | 10 ---
> drivers/gpu/drm/mediatek/mtk_hdmi.c | 3 ++-
> drivers/gpu/drm/msm/hdmi/hdmi_bridge.c| 3 ++-
> drivers/gpu/drm/nouveau/dispnv50/disp.c | 7 +++--
> drivers/gpu/drm/omapdrm/omap_encoder.c| 5 ++--
> drivers/gpu/drm/radeon/radeon_audio.c | 2 +-
> drivers/gpu/drm/rockchip/inno_hdmi.c | 4 ++-
> drivers/gpu/drm/sti/sti_hdmi.c| 3 ++-
> drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c| 3 ++-
> drivers/gpu/drm/tegra/hdmi.c | 3 ++-
> drivers/gpu/drm/tegra/sor.c | 3 ++-
> drivers/gpu/drm/vc4/vc4_hdmi.c| 11 +---
> drivers/gpu/drm/zte/zx_hdmi.c | 4 ++-
> include/drm/drm_edid.h| 8 +++---
> 27 files changed, 94 insertions(+), 66 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> index 4cfecdce29a3..1f0426d2fc2a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> @@ -1682,7 +1682,7 @@ static void dce_v10_0_afmt_setmode(struct drm_encoder
> *encoder,
> dce_v10_0_audio_write_sad_regs(encoder);
> dce_v10_0_audio_write_latency_fields(encoder, mode);
>
> - err = drm_hdmi_avi_infoframe_from_display_mode(, mode, false);
> + err = drm_hdmi_avi_infoframe_from_display_mode(, connector, mode);
> if (err < 0) {
> DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
> return;
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> index 7c868916d90f..2280b971d758 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> @@ -1724,7 +1724,7 @@ static void dce_v11_0_afmt_setmode(struct drm_encoder
> *encoder,
> dce_v11_0_audio_write_sad_regs(encoder);
> dce_v11_0_audio_write_latency_fields(encoder, mode);
>
> - err = drm_hdmi_avi_infoframe_from_display_mode(, mode, false);
> + err = drm_hdmi_avi_infoframe_from_display_mode(, connector, mode);
> if (err < 0) {
> DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
> return;
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> index 17eaaba36017..db443ec53d3a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> @@ -1423,6 +1423,7 @@ static void dce_v6_0_audio_set_avi_infoframe(struct
> drm_encoder *encoder,
> struct amdgpu_device *adev = dev->dev_private;
> struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
> struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
> + struct drm_connector *connector =
> amdgpu_get_connector_for_encoder(encoder);
> struct hdmi_avi_infoframe frame;
> u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
> uint8_t *payload = buffer + 3;
> @@ -1430,7 +1431,7 @@ static void
Re: [PATCH RFC 5/5] drm/amdgpu: Add accounting of buffer object creation request via DRM cgroup
Am 20.11.18 um 19:58 schrieb Kenny Ho:
Account for the total size of buffer object requested to amdgpu by
buffer type on a per cgroup basis.
x prefix in the control file name x.bo_requested.amd.stat signify
experimental.
Change-Id: Ifb680c4bcf3652879a7a659510e25680c2465cf6
Signed-off-by: Kenny Ho
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.c | 56 +
drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.h | 3 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 13 +
include/uapi/drm/amdgpu_drm.h | 24 ++---
4 files changed, 90 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.c
index 853b77532428..e3d98ed01b79 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.c
@@ -7,6 +7,57 @@
#include "amdgpu_ring.h"
#include "amdgpu_drmcgrp.h"
+void amdgpu_drmcgrp_count_bo_req(struct task_struct *task, struct drm_device *dev,
+ u32 domain, unsigned long size)
+{
+ struct drmcgrp *drmcgrp = get_drmcgrp(task);
+ struct drmcgrp_device_resource *ddr;
+ struct drmcgrp *p;
+ struct amd_drmcgrp_dev_resource *a_ddr;
+int i;
+
+ if (drmcgrp == NULL)
+ return;
+
+ ddr = drmcgrp->dev_resources[dev->primary->index];
+
+ mutex_lock(>ddev->mutex);
+ for (p = drmcgrp; p != NULL; p = parent_drmcgrp(drmcgrp)) {
+ a_ddr = ddr_amdddr(p->dev_resources[dev->primary->index]);
+
+ for (i = 0; i < __MAX_AMDGPU_MEM_DOMAIN; i++)
+ if ( (1 << i) & domain)
+ a_ddr->bo_req_count[i] += size;
+ }
+ mutex_unlock(>ddev->mutex);
+}
+
+int amd_drmcgrp_bo_req_stat_read(struct seq_file *sf, void *v)
+{
+ struct drmcgrp *drmcgrp = css_drmcgrp(seq_css(sf));
+ struct drmcgrp_device_resource *ddr = NULL;
+ struct amd_drmcgrp_dev_resource *a_ddr = NULL;
+ int i, j;
+
+ seq_puts(sf, "---\n");
+ for (i = 0; i < MAX_DRM_DEV; i++) {
+ ddr = drmcgrp->dev_resources[i];
+
+ if (ddr == NULL || ddr->ddev->vid != amd_drmcgrp_vendor_id)
+ continue;
+
+ a_ddr = ddr_amdddr(ddr);
+
+ seq_printf(sf, "card%d:\n", i);
+ for (j = 0; j < __MAX_AMDGPU_MEM_DOMAIN; j++)
+ seq_printf(sf, " %s: %llu\n", amdgpu_mem_domain_names[j],
a_ddr->bo_req_count[j]);
+ }
+
+ return 0;
+}
+
+
+
void amdgpu_drmcgrp_count_cs(struct task_struct *task, struct drm_device *dev,
enum amdgpu_ring_type r_type)
{
@@ -55,6 +106,11 @@ int amd_drmcgrp_cmd_submit_accounting_read(struct seq_file
*sf, void *v)
struct cftype files[] = {
+ {
+ .name = "x.bo_requested.amd.stat",
+ .seq_show = amd_drmcgrp_bo_req_stat_read,
+ .flags = CFTYPE_NOT_ON_ROOT,
+ },
{
.name = "x.cmd_submitted.amd.stat",
.seq_show = amd_drmcgrp_cmd_submit_accounting_read,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.h
index f894a9a1059f..8b9d61e47dde 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.h
@@ -11,10 +11,13 @@
struct amd_drmcgrp_dev_resource {
struct drmcgrp_device_resource ddr;
u64 cs_count[__MAX_AMDGPU_RING_TYPE];
+ u64 bo_req_count[__MAX_AMDGPU_MEM_DOMAIN];
};
void amdgpu_drmcgrp_count_cs(struct task_struct *task, struct drm_device *dev,
enum amdgpu_ring_type r_type);
+void amdgpu_drmcgrp_count_bo_req(struct task_struct *task, struct drm_device
*dev,
+ u32 domain, unsigned long size);
static inline struct amd_drmcgrp_dev_resource *ddr_amdddr(struct drmcgrp_device_resource *ddr)
{
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 7b3d1ebda9df..339e1d3edad8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -31,6 +31,17 @@
#include
#include "amdgpu.h"
#include "amdgpu_display.h"
+#include "amdgpu_drmcgrp.h"
+
+char const *amdgpu_mem_domain_names[] = {
+ [AMDGPU_MEM_DOMAIN_CPU] = "cpu",
+ [AMDGPU_MEM_DOMAIN_GTT] = "gtt",
+ [AMDGPU_MEM_DOMAIN_VRAM]= "vram",
+ [AMDGPU_MEM_DOMAIN_GDS] = "gds",
+ [AMDGPU_MEM_DOMAIN_GWS] = "gws",
+ [AMDGPU_MEM_DOMAIN_OA] = "oa",
+ [__MAX_AMDGPU_MEM_DOMAIN] = "_max"
+};
void amdgpu_gem_object_free(struct drm_gem_object *gobj)
{
@@ -52,6 +63,8 @@ int amdgpu_gem_object_create(struct amdgpu_device *adev,
unsigned long size,
struct amdgpu_bo_param bp;
int r;
+ amdgpu_drmcgrp_count_bo_req(current, adev->ddev, initial_domain, size);
+
memset(, 0,
Re: [PATCH RFC 4/5] drm/amdgpu: Add accounting of command submission via DRM cgroup
Am 20.11.18 um 21:57 schrieb Eric Anholt: Kenny Ho writes: Account for the number of command submitted to amdgpu by type on a per cgroup basis, for the purpose of profiling/monitoring applications. For profiling other drivers, I've used perf tracepoints, which let you get useful timelines of multiple events in the driver. Have you made use of this stat for productive profiling? Yes, but this is not related to profiling at all. What we want to do is to limit the resource usage of processes. Regards, Christian. ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH RFC 2/5] cgroup: Add mechanism to register vendor specific DRM devices
Am 20.11.18 um 19:58 schrieb Kenny Ho:
Since many parts of the DRM subsystem has vendor-specific
implementations, we introduce mechanisms for vendor to register their
specific resources and control files to the DRM cgroup subsystem. A
vendor will register itself with the DRM cgroup subsystem first before
registering individual DRM devices to the cgroup subsystem.
In addition to the cgroup_subsys_state that is common to all DRM
devices, a device-specific state is introduced and it is allocated
according to the vendor of the device.
Mhm, it's most likely just a naming issue but I think we should drop the
term "vendor" here and rather use "driver" instead.
Background is that both Intel as well as AMD have multiple drivers for
different hardware generations and we certainly don't want to handle all
drivers from one vendor the same way.
Christian.
Change-Id: I908ee6975ea0585e4c30eafde4599f87094d8c65
Signed-off-by: Kenny Ho
---
include/drm/drm_cgroup.h | 39
include/drm/drmcgrp_vendors.h | 7 +++
include/linux/cgroup_drm.h| 26 +++
kernel/cgroup/drm.c | 84 +++
4 files changed, 156 insertions(+)
create mode 100644 include/drm/drm_cgroup.h
create mode 100644 include/drm/drmcgrp_vendors.h
diff --git a/include/drm/drm_cgroup.h b/include/drm/drm_cgroup.h
new file mode 100644
index ..26cbea7059a6
--- /dev/null
+++ b/include/drm/drm_cgroup.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: MIT
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ */
+#ifndef __DRM_CGROUP_H__
+#define __DRM_CGROUP_H__
+
+#define DRMCGRP_VENDOR(_x) _x ## _drmcgrp_vendor_id,
+enum drmcgrp_vendor_id {
+#include
+ DRMCGRP_VENDOR_COUNT,
+};
+#undef DRMCGRP_VENDOR
+
+#define DRMCGRP_VENDOR(_x) extern struct drmcgrp_vendor _x ## _drmcgrp_vendor;
+#include
+#undef DRMCGRP_VENDOR
+
+
+
+#ifdef CONFIG_CGROUP_DRM
+
+extern struct drmcgrp_vendor *drmcgrp_vendors[];
+
+int drmcgrp_register_vendor(struct drmcgrp_vendor *vendor, enum
drmcgrp_vendor_id id);
+int drmcgrp_register_device(struct drm_device *device, enum drmcgrp_vendor_id
id);
+
+#else
+static int drmcgrp_register_vendor(struct drmcgrp_vendor *vendor, enum
drmcgrp_vendor_id id)
+{
+ return 0;
+}
+
+static int drmcgrp_register_device(struct drm_device *device, enum
drmcgrp_vendor_id id)
+{
+ return 0;
+}
+
+#endif /* CONFIG_CGROUP_DRM */
+#endif /* __DRM_CGROUP_H__ */
diff --git a/include/drm/drmcgrp_vendors.h b/include/drm/drmcgrp_vendors.h
new file mode 100644
index ..b04d8649851b
--- /dev/null
+++ b/include/drm/drmcgrp_vendors.h
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: MIT
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ */
+#if IS_ENABLED(CONFIG_CGROUP_DRM)
+
+
+#endif
diff --git a/include/linux/cgroup_drm.h b/include/linux/cgroup_drm.h
index 79ab38b0f46d..a776662d9593 100644
--- a/include/linux/cgroup_drm.h
+++ b/include/linux/cgroup_drm.h
@@ -6,10 +6,36 @@
#ifdef CONFIG_CGROUP_DRM
+#include
#include
+#include
+#include
+
+/* limit defined per the way drm_minor_alloc operates */
+#define MAX_DRM_DEV (64 * DRM_MINOR_RENDER)
+
+struct drmcgrp_device {
+ enum drmcgrp_vendor_id vid;
+ struct drm_device *dev;
+ struct mutexmutex;
+};
+
+/* vendor-common resource counting goes here */
+/* this struct should be included in the vendor specific resource */
+struct drmcgrp_device_resource {
+ struct drmcgrp_device *ddev;
+};
+
+struct drmcgrp_vendor {
+ struct cftype *(*get_cftypes)(void);
+ struct drmcgrp_device_resource *(*alloc_dev_resource)(void);
+ void (*free_dev_resource)(struct drmcgrp_device_resource *dev_resource);
+};
+
struct drmcgrp {
struct cgroup_subsys_state css;
+ struct drmcgrp_device_resource *dev_resources[MAX_DRM_DEV];
};
static inline struct drmcgrp *css_drmcgrp(struct cgroup_subsys_state *css)
diff --git a/kernel/cgroup/drm.c b/kernel/cgroup/drm.c
index d9e194b9aead..f9630cc389bc 100644
--- a/kernel/cgroup/drm.c
+++ b/kernel/cgroup/drm.c
@@ -1,8 +1,30 @@
// SPDX-License-Identifier: MIT
// Copyright 2018 Advanced Micro Devices, Inc.
+#include
#include
#include
+#include
+#include
+#include
#include
+#include
+#include
+
+/* generate an array of drm cgroup vendor pointers */
+#define DRMCGRP_VENDOR(_x)[_x ## _drmcgrp_vendor_id] = NULL,
+struct drmcgrp_vendor *drmcgrp_vendors[] = {
+#include
+};
+#undef DRMCGRP_VENDOR
+EXPORT_SYMBOL(drmcgrp_vendors);
+
+static DEFINE_MUTEX(drmcgrp_mutex);
+
+/* indexed by drm_minor for access speed */
+static struct drmcgrp_device *known_drmcgrp_devs[MAX_DRM_DEV];
+
+static int max_minor;
+
static u64 drmcgrp_test_read(struct cgroup_subsys_state *css,
struct cftype *cft)
@@ -13,6 +35,12 @@ static u64 drmcgrp_test_read(struct cgroup_subsys_state *css,
static void drmcgrp_css_free(struct cgroup_subsys_state *css)
Re: [PATCH RFC 3/5] drm/amdgpu: Add DRM cgroup support for AMD devices
Am 20.11.18 um 19:58 schrieb Kenny Ho:
Change-Id: Ib66c44ac1b1c367659e362a2fc05b6fbb3805876
Signed-off-by: Kenny Ho
---
drivers/gpu/drm/amd/amdgpu/Makefile | 3 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7
drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.c | 37 +
drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.h | 19 +++
include/drm/drmcgrp_vendors.h | 1 +
5 files changed, 67 insertions(+)
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 138cb787d27e..5cf8048f2d75 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -186,4 +186,7 @@ amdgpu-y += $(AMD_DISPLAY_FILES)
endif
+#DRM cgroup controller
+amdgpu-y += amdgpu_drmcgrp.o
+
obj-$(CONFIG_DRM_AMDGPU)+= amdgpu.o
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 30bc345d6fdf..ad0373f83ed3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -33,6 +33,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -2645,6 +2646,12 @@ int amdgpu_device_init(struct amdgpu_device *adev,
goto failed;
}
+ /* TODO:docs */
+ if (drmcgrp_vendors[amd_drmcgrp_vendor_id] == NULL)
+ drmcgrp_register_vendor(_drmcgrp_vendor,
amd_drmcgrp_vendor_id);
+
+ drmcgrp_register_device(adev->ddev, amd_drmcgrp_vendor_id);
+
Well that is most likely racy because it is possible that multiple
instances of the driver initialize at the same time.
Better put the call to drmcgrp_register_vendor() into the module init
section.
Christian.
return 0;
failed:
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.c
new file mode 100644
index ..ed8aac17769c
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.c
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: MIT
+// Copyright 2018 Advanced Micro Devices, Inc.
+#include
+#include
+#include
+#include "amdgpu_drmcgrp.h"
+
+struct cftype files[] = {
+ { } /* terminate */
+};
+
+struct cftype *drmcgrp_amd_get_cftypes(void)
+{
+ return files;
+}
+
+struct drmcgrp_device_resource *amd_drmcgrp_alloc_dev_resource(void)
+{
+ struct amd_drmcgrp_dev_resource *a_ddr;
+
+ a_ddr = kzalloc(sizeof(struct amd_drmcgrp_dev_resource), GFP_KERNEL);
+ if (!a_ddr)
+ return ERR_PTR(-ENOMEM);
+
+ return _ddr->ddr;
+}
+
+void amd_drmcgrp_free_dev_resource(struct drmcgrp_device_resource *ddr)
+{
+ kfree(ddr_amdddr(ddr));
+}
+
+struct drmcgrp_vendor amd_drmcgrp_vendor = {
+ .get_cftypes = drmcgrp_amd_get_cftypes,
+ .alloc_dev_resource = amd_drmcgrp_alloc_dev_resource,
+ .free_dev_resource = amd_drmcgrp_free_dev_resource,
+};
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.h
new file mode 100644
index ..e2934b7a49f5
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: MIT
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ */
+#ifndef _AMDGPU_DRMCGRP_H
+#define _AMDGPU_DRMCGRP_H
+
+#include
+
+/* for AMD specific DRM resources */
+struct amd_drmcgrp_dev_resource {
+ struct drmcgrp_device_resource ddr;
+};
+
+static inline struct amd_drmcgrp_dev_resource *ddr_amdddr(struct
drmcgrp_device_resource *ddr)
+{
+ return ddr ? container_of(ddr, struct amd_drmcgrp_dev_resource, ddr) :
NULL;
+}
+
+#endif /* _AMDGPU_DRMCGRP_H */
diff --git a/include/drm/drmcgrp_vendors.h b/include/drm/drmcgrp_vendors.h
index b04d8649851b..6cfbf1825344 100644
--- a/include/drm/drmcgrp_vendors.h
+++ b/include/drm/drmcgrp_vendors.h
@@ -3,5 +3,6 @@
*/
#if IS_ENABLED(CONFIG_CGROUP_DRM)
+DRMCGRP_VENDOR(amd)
#endif
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 6/7] drm/amdgpu: Use asic specific doorbell index instead of macro definition
Also deleted doorbell index macro definition
Change-Id: I84475efcfb482c474fccb133010abb5df5f4
Signed-off-by: Oak Zeng
Suggested-by: Felix Kuehling
Suggested-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 106 -
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 27 +++-
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c| 2 +-
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 10 +--
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 8 +--
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 25 +++
drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 2 +-
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 4 +-
drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 4 +-
drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 2 +-
13 files changed, 36 insertions(+), 160 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index b7ee4ef..5cbd67a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -363,27 +363,6 @@ void amdgpu_fence_slab_fini(void);
/*
* GPU doorbell structures, functions & helpers
*/
-typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
-{
- AMDGPU_DOORBELL_KIQ = 0x000,
- AMDGPU_DOORBELL_HIQ = 0x001,
- AMDGPU_DOORBELL_DIQ = 0x002,
- AMDGPU_DOORBELL_MEC_RING0 = 0x010,
- AMDGPU_DOORBELL_MEC_RING1 = 0x011,
- AMDGPU_DOORBELL_MEC_RING2 = 0x012,
- AMDGPU_DOORBELL_MEC_RING3 = 0x013,
- AMDGPU_DOORBELL_MEC_RING4 = 0x014,
- AMDGPU_DOORBELL_MEC_RING5 = 0x015,
- AMDGPU_DOORBELL_MEC_RING6 = 0x016,
- AMDGPU_DOORBELL_MEC_RING7 = 0x017,
- AMDGPU_DOORBELL_GFX_RING0 = 0x020,
- AMDGPU_DOORBELL_sDMA_ENGINE0= 0x1E0,
- AMDGPU_DOORBELL_sDMA_ENGINE1= 0x1E1,
- AMDGPU_DOORBELL_IH = 0x1E8,
- AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
- AMDGPU_DOORBELL_INVALID = 0x
-} AMDGPU_DOORBELL_ASSIGNMENT;
-
struct amdgpu_doorbell {
/* doorbell mmio */
resource_size_t base;
@@ -393,91 +372,6 @@ struct amdgpu_doorbell {
};
/*
- * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space
- */
-typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
-{
- /*
-* All compute related doorbells: kiq, hiq, diq, traditional compute
queue, user queue, should locate in
-* a continues range so that programming
CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range.
-* Compute related doorbells are allocated from 0x00 to 0x8a
-*/
-
-
- /* kernel scheduling */
- AMDGPU_DOORBELL64_KIQ = 0x00,
-
- /* HSA interface queue and debug queue */
- AMDGPU_DOORBELL64_HIQ = 0x01,
- AMDGPU_DOORBELL64_DIQ = 0x02,
-
- /* Compute engines */
- AMDGPU_DOORBELL64_MEC_RING0 = 0x03,
- AMDGPU_DOORBELL64_MEC_RING1 = 0x04,
- AMDGPU_DOORBELL64_MEC_RING2 = 0x05,
- AMDGPU_DOORBELL64_MEC_RING3 = 0x06,
- AMDGPU_DOORBELL64_MEC_RING4 = 0x07,
- AMDGPU_DOORBELL64_MEC_RING5 = 0x08,
- AMDGPU_DOORBELL64_MEC_RING6 = 0x09,
- AMDGPU_DOORBELL64_MEC_RING7 = 0x0a,
-
- /* User queue doorbell range (128 doorbells) */
- AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b,
- AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a,
-
- /* Graphics engine */
- AMDGPU_DOORBELL64_GFX_RING0 = 0x8b,
-
- /*
-* Other graphics doorbells can be allocated here: from 0x8c to 0xdf
-* Graphics voltage island aperture 1
-* default non-graphics QWORD index is 0xe0 - 0xFF inclusive
-*/
-
- /* sDMA engines reserved from 0xe0 -0xef */
- AMDGPU_DOORBELL64_sDMA_ENGINE0= 0xE0,
- AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xE1,
- AMDGPU_DOORBELL64_sDMA_ENGINE1= 0xE8,
- AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xE9,
-
- /* For vega10 sriov, the sdma doorbell must be fixed as follow
-* to keep the same setting with host driver, or it will
-* happen conflicts
-*/
- AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0= 0xF0,
- AMDGPU_VEGA10_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1,
- AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1= 0xF2,
- AMDGPU_VEGA10_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3,
-
- /* Interrupt handler */
- AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy
interrupt
[PATCH 4/7] drm/amdgpu: Doorbell index initialization for ASICs before vega10
Change-Id: Id64eb98f5b1c24b51eb2fd5a083086fc3515813d
Signed-off-by: Oak Zeng
Suggested-by: Felix Kuehling
Suggested-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/Makefile| 3 +-
drivers/gpu/drm/amd/amdgpu/vi.h| 2 +-
.../gpu/drm/amd/amdgpu/vi_doorbell_index_init.c| 43 ++
3 files changed, 46 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/vi_doorbell_index_init.c
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 96a4e1c..3ab8eba 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -63,7 +63,8 @@ amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o
si_ih.o si_dma.o dce
amdgpu-y += \
vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o
vega10_reg_init.o \
- vega20_reg_init.o nbio_v7_4.o vega10_doorbell_index_init.o
vega12_doorbell_index_init.o
+ vega20_reg_init.o nbio_v7_4.o vega10_doorbell_index_init.o
vega12_doorbell_index_init.o \
+ vi_doorbell_index_init.o
# add DF block
amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.h b/drivers/gpu/drm/amd/amdgpu/vi.h
index 0429fe3..abcb52e 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.h
+++ b/drivers/gpu/drm/amd/amdgpu/vi.h
@@ -29,5 +29,5 @@
void vi_srbm_select(struct amdgpu_device *adev,
u32 me, u32 pipe, u32 queue, u32 vmid);
int vi_set_ip_blocks(struct amdgpu_device *adev);
-
+void vi_doorbell_index_init(struct amdgpu_device *adev);
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/vi_doorbell_index_init.c
b/drivers/gpu/drm/amd/amdgpu/vi_doorbell_index_init.c
new file mode 100644
index 000..cae2ab6
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/vi_doorbell_index_init.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "amdgpu.h"
+
+void vi_doorbell_index_init(struct amdgpu_device *adev)
+{
+ adev->doorbell_index.kiq = 0x00;
+ adev->doorbell_index.mec_ring0 = 0x10;
+ adev->doorbell_index.mec_ring1 = 0x11;
+ adev->doorbell_index.mec_ring2 = 0x12;
+ adev->doorbell_index.mec_ring3 = 0x13;
+ adev->doorbell_index.mec_ring4 = 0x14;
+ adev->doorbell_index.mec_ring5 = 0x15;
+ adev->doorbell_index.mec_ring6 = 0x16;
+ adev->doorbell_index.mec_ring7 = 0x17;
+ adev->doorbell_index.gfx_ring0 = 0x20;
+ adev->doorbell_index.sdma_engine0 = 0x1e0;
+ adev->doorbell_index.sdma_engine1 = 0x1e1;
+ adev->doorbell_index.ih = 0x1e8;
+ adev->doorbell_index.max_assignment = 0x3ff;
+}
+
--
2.7.4
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[PATCH 1/7] drm/amdgpu: Add field in amdgpu_dev to hold reserved doorbell index
This is a preparation work to make reserved doorbell index per device,
instead of using a global macro definition. By doing this, we can easily
change doorbell layout for future ASICs while not affecting ASICs in
production.
Change-Id: If08e2bc9d0749748ed4083ba4eb32a4698763085
Signed-off-by: Oak Zeng
Suggested-by: Felix Kuehling
Suggested-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 50 +
1 file changed, 50 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 2c80453..b7ee4ef 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -813,6 +813,55 @@ struct amd_powerplay {
uint32_t pp_feature;
};
+/* Reserved doorbells for amdgpu (including multimedia).
+ * KFD can use all the rest in the 2M doorbell bar.
+ * For asic before vega10, doorbell is 32-bit, so the
+ * index/offset is in dword. For vega10 and after, doorbell
+ * can be 64-bit, so the index defined is in qword.
+ */
+struct amdgpu_doorbell_index {
+ uint32_t kiq;
+ uint32_t mec_ring0;
+ uint32_t mec_ring1;
+ uint32_t mec_ring2;
+ uint32_t mec_ring3;
+ uint32_t mec_ring4;
+ uint32_t mec_ring5;
+ uint32_t mec_ring6;
+ uint32_t mec_ring7;
+ uint32_t userqueue_start;
+ uint32_t userqueue_end;
+ uint32_t gfx_ring0;
+ uint32_t sdma_engine0;
+ uint32_t sdma_engine1;
+ uint32_t sdma_engine2;
+ uint32_t sdma_engine3;
+ uint32_t sdma_engine4;
+ uint32_t sdma_engine5;
+ uint32_t sdma_engine6;
+ uint32_t sdma_engine7;
+ uint32_t ih;
+ union {
+ struct {
+ uint32_t vcn_ring0_1;
+ uint32_t vcn_ring2_3;
+ uint32_t vcn_ring4_5;
+ uint32_t vcn_ring6_7;
+ } vcn;
+ struct {
+ uint32_t uvd_ring0_1;
+ uint32_t uvd_ring2_3;
+ uint32_t uvd_ring4_5;
+ uint32_t uvd_ring6_7;
+ uint32_t vce_ring0_1;
+ uint32_t vce_ring2_3;
+ uint32_t vce_ring4_5;
+ uint32_t vce_ring6_7;
+ } uvd_vce;
+ };
+ uint32_t max_assignment;
+};
+
#define AMDGPU_RESET_MAGIC_NUM 64
struct amdgpu_device {
struct device *dev;
@@ -1026,6 +1075,7 @@ struct amdgpu_device {
unsigned long last_mm_index;
boolin_gpu_reset;
struct mutex lock_reset;
+ struct amdgpu_doorbell_index doorbell_index;
};
static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
--
2.7.4
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[PATCH 2/7] drm/amdgpu: Vega10 doorbell index initialization
Change-Id: Ib72058337f0aa53adfc6c6aae5341a7cd665111a
Signed-off-by: Oak Zeng
Suggested-by: Felix Kuehling
Suggested-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/Makefile| 2 +-
drivers/gpu/drm/amd/amdgpu/soc15.h | 1 +
.../drm/amd/amdgpu/vega10_doorbell_index_init.c| 54 ++
3 files changed, 56 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/vega10_doorbell_index_init.c
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
b/drivers/gpu/drm/amd/amdgpu/Makefile
index f76bcb9..61cea57 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -63,7 +63,7 @@ amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o
si_ih.o si_dma.o dce
amdgpu-y += \
vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o
vega10_reg_init.o \
- vega20_reg_init.o nbio_v7_4.o
+ vega20_reg_init.o nbio_v7_4.o vega10_doorbell_index_init.o
# add DF block
amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h
b/drivers/gpu/drm/amd/amdgpu/soc15.h
index f8ad780..d37c57d 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.h
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.h
@@ -58,4 +58,5 @@ void soc15_program_register_sequence(struct amdgpu_device
*adev,
int vega10_reg_base_init(struct amdgpu_device *adev);
int vega20_reg_base_init(struct amdgpu_device *adev);
+void vega10_doorbell_index_init(struct amdgpu_device *adev);
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_doorbell_index_init.c
b/drivers/gpu/drm/amd/amdgpu/vega10_doorbell_index_init.c
new file mode 100644
index 000..e8216a3
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_doorbell_index_init.c
@@ -0,0 +1,54 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "amdgpu.h"
+
+void vega10_doorbell_index_init(struct amdgpu_device *adev)
+{
+ adev->doorbell_index.kiq = 0x00;
+ adev->doorbell_index.mec_ring0 = 0x03;
+ adev->doorbell_index.mec_ring1 = 0x04;
+ adev->doorbell_index.mec_ring2 = 0x05;
+ adev->doorbell_index.mec_ring3 = 0x06;
+ adev->doorbell_index.mec_ring4 = 0x07;
+ adev->doorbell_index.mec_ring5 = 0x08;
+ adev->doorbell_index.mec_ring6 = 0x09;
+ adev->doorbell_index.mec_ring7 = 0x0a;
+ adev->doorbell_index.userqueue_start = 0x0b;
+ adev->doorbell_index.userqueue_end = 0x8a;
+ adev->doorbell_index.gfx_ring0 = 0x8b;
+ adev->doorbell_index.sdma_engine0 = 0xf0;
+ adev->doorbell_index.sdma_engine1 = 0xf2;
+ adev->doorbell_index.ih = 0xf4;
+ adev->doorbell_index.uvd_vce.uvd_ring0_1 = 0xf8;
+ adev->doorbell_index.uvd_vce.uvd_ring2_3 = 0xf9;
+ adev->doorbell_index.uvd_vce.uvd_ring4_5 = 0xfa;
+ adev->doorbell_index.uvd_vce.uvd_ring6_7 = 0xfb;
+ adev->doorbell_index.uvd_vce.vce_ring0_1 = 0xfc;
+ adev->doorbell_index.uvd_vce.vce_ring2_3 = 0xfd;
+ adev->doorbell_index.uvd_vce.vce_ring4_5 = 0xfe;
+ adev->doorbell_index.uvd_vce.vce_ring6_7 = 0xff;
+ /* In unit of dword doorbell */
+ adev->doorbell_index.max_assignment = 0xff << 1;
+}
+
--
2.7.4
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[PATCH 7/7] drm/amdgpu: Use new doorbell layout for vega20 and future asic
Change-Id: I04d22fb717ac50483c0835f160a2e860e344f358
Signed-off-by: Oak Zeng
Suggested-by: Felix Kuehling
Suggested-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/Makefile| 4 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +-
drivers/gpu/drm/amd/amdgpu/soc15.h | 1 +
.../drm/amd/amdgpu/vega20_doorbell_index_init.c| 64 ++
4 files changed, 70 insertions(+), 3 deletions(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/vega20_doorbell_index_init.c
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 3ab8eba..b3b150b 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -63,8 +63,8 @@ amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o
si_ih.o si_dma.o dce
amdgpu-y += \
vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o
vega10_reg_init.o \
- vega20_reg_init.o nbio_v7_4.o vega10_doorbell_index_init.o
vega12_doorbell_index_init.o \
- vi_doorbell_index_init.o
+ vega20_reg_init.o nbio_v7_4.o vi_doorbell_index_init.o
vega10_doorbell_index_init.o \
+ vega12_doorbell_index_init.o vega20_doorbell_index_init.o
# add DF block
amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 3ffd8f5..19f2149 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -517,8 +517,10 @@ static int amdgpu_device_doorbell_init(struct
amdgpu_device *adev)
vi_doorbell_index_init(adev);
else if (adev->asic_type == CHIP_VEGA10)
vega10_doorbell_index_init(adev);
- else
+ else if (adev->asic_type == CHIP_VEGA12 || adev->asic_type ==
CHIP_RAVEN)
vega12_doorbell_index_init(adev);
+ else
+ vega20_doorbell_index_init(adev);
/* No doorbell on SI hardware generation */
if (adev->asic_type < CHIP_BONAIRE) {
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h
b/drivers/gpu/drm/amd/amdgpu/soc15.h
index 939c0e8..6ba0d26 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.h
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.h
@@ -60,4 +60,5 @@ int vega20_reg_base_init(struct amdgpu_device *adev);
void vega10_doorbell_index_init(struct amdgpu_device *adev);
void vega12_doorbell_index_init(struct amdgpu_device *adev);
+void vega20_doorbell_index_init(struct amdgpu_device *adev);
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_doorbell_index_init.c
b/drivers/gpu/drm/amd/amdgpu/vega20_doorbell_index_init.c
new file mode 100644
index 000..dcaef7f
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/vega20_doorbell_index_init.c
@@ -0,0 +1,64 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "amdgpu.h"
+
+void vega20_doorbell_index_init(struct amdgpu_device *adev)
+{
+ /* Compute + GFX: 0~255 */
+ adev->doorbell_index.kiq = 0x00;
+ adev->doorbell_index.mec_ring0 = 0x03;
+ adev->doorbell_index.mec_ring1 = 0x04;
+ adev->doorbell_index.mec_ring2 = 0x05;
+ adev->doorbell_index.mec_ring3 = 0x06;
+ adev->doorbell_index.mec_ring4 = 0x07;
+ adev->doorbell_index.mec_ring5 = 0x08;
+ adev->doorbell_index.mec_ring6 = 0x09;
+ adev->doorbell_index.mec_ring7 = 0x0a;
+ adev->doorbell_index.userqueue_start = 0x0b;
+ adev->doorbell_index.userqueue_end = 0x8a;
+ adev->doorbell_index.gfx_ring0 = 0x8b;
+ /* SDMA:256~335*/
+ adev->doorbell_index.sdma_engine0 = 0x100;
+ adev->doorbell_index.sdma_engine1 = 0x10a;
+ adev->doorbell_index.sdma_engine2 = 0x114;
+ adev->doorbell_index.sdma_engine3 = 0x11e;
+ adev->doorbell_index.sdma_engine4 = 0x128;
+ adev->doorbell_index.sdma_engine5 = 0x132;
+ adev->doorbell_index.sdma_engine6
Re: [PATCH 7/7] drm/amdgpu: Use new doorbell layout for vega20 and future asic
The doorbell index defines should be compatible with what is used in
windows driver . I don't see the necessary to introduce the new init
file for this instead of use the original MACRO defines. We need to
coordinate with windows driver team for a new user queue SDMA doorbell
range and used them for vega20 and future asic .
Regards
shaoyun.liu
On 2018-11-21 10:52 a.m., Oak Zeng wrote:
> Change-Id: I04d22fb717ac50483c0835f160a2e860e344f358
> Signed-off-by: Oak Zeng
> Suggested-by: Felix Kuehling
> Suggested-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/Makefile| 4 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +-
> drivers/gpu/drm/amd/amdgpu/soc15.h | 1 +
> .../drm/amd/amdgpu/vega20_doorbell_index_init.c| 64
> ++
> 4 files changed, 70 insertions(+), 3 deletions(-)
> create mode 100644 drivers/gpu/drm/amd/amdgpu/vega20_doorbell_index_init.c
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
> b/drivers/gpu/drm/amd/amdgpu/Makefile
> index 3ab8eba..b3b150b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/Makefile
> +++ b/drivers/gpu/drm/amd/amdgpu/Makefile
> @@ -63,8 +63,8 @@ amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o
> si_ih.o si_dma.o dce
>
> amdgpu-y += \
> vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o
> vega10_reg_init.o \
> - vega20_reg_init.o nbio_v7_4.o vega10_doorbell_index_init.o
> vega12_doorbell_index_init.o \
> - vi_doorbell_index_init.o
> + vega20_reg_init.o nbio_v7_4.o vi_doorbell_index_init.o
> vega10_doorbell_index_init.o \
> + vega12_doorbell_index_init.o vega20_doorbell_index_init.o
>
> # add DF block
> amdgpu-y += \
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 3ffd8f5..19f2149 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -517,8 +517,10 @@ static int amdgpu_device_doorbell_init(struct
> amdgpu_device *adev)
> vi_doorbell_index_init(adev);
> else if (adev->asic_type == CHIP_VEGA10)
> vega10_doorbell_index_init(adev);
> - else
> + else if (adev->asic_type == CHIP_VEGA12 || adev->asic_type ==
> CHIP_RAVEN)
> vega12_doorbell_index_init(adev);
> + else
> + vega20_doorbell_index_init(adev);
>
> /* No doorbell on SI hardware generation */
> if (adev->asic_type < CHIP_BONAIRE) {
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h
> b/drivers/gpu/drm/amd/amdgpu/soc15.h
> index 939c0e8..6ba0d26 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.h
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.h
> @@ -60,4 +60,5 @@ int vega20_reg_base_init(struct amdgpu_device *adev);
>
> void vega10_doorbell_index_init(struct amdgpu_device *adev);
> void vega12_doorbell_index_init(struct amdgpu_device *adev);
> +void vega20_doorbell_index_init(struct amdgpu_device *adev);
> #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_doorbell_index_init.c
> b/drivers/gpu/drm/amd/amdgpu/vega20_doorbell_index_init.c
> new file mode 100644
> index 000..dcaef7f
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/amdgpu/vega20_doorbell_index_init.c
> @@ -0,0 +1,64 @@
> +/*
> + * Copyright 2018 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + */
> +
> +#include "amdgpu.h"
> +
> +void vega20_doorbell_index_init(struct amdgpu_device *adev)
> +{
> + /* Compute + GFX: 0~255 */
> + adev->doorbell_index.kiq = 0x00;
> + adev->doorbell_index.mec_ring0 = 0x03;
> + adev->doorbell_index.mec_ring1 = 0x04;
> + adev->doorbell_index.mec_ring2 = 0x05;
> + adev->doorbell_index.mec_ring3 = 0x06;
> + adev->doorbell_index.mec_ring4 = 0x07;
> + adev->doorbell_index.mec_ring5 = 0x08;
> + adev->doorbell_index.mec_ring6
[PATCH] drm/amd/display/amdgpu_dm/amdgpu_dm.c: Remove duplicate header
Remove dm_services_types.h which is included more than once Signed-off-by: Brajeswar Ghosh --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index e224f23e2215..62a96c683584 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -38,7 +38,6 @@ #include "amd_shared.h" #include "amdgpu_dm_irq.h" #include "dm_helpers.h" -#include "dm_services_types.h" #include "amdgpu_dm_mst_types.h" #if defined(CONFIG_DEBUG_FS) #include "amdgpu_dm_debugfs.h" -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amd/amdgpu: Remove duplicate header
Remove gca/gfx_8_0_sh_mask.h which is included more than once Signed-off-by: Brajeswar Ghosh --- drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c index 64e875d528dd..6a0fcd67662a 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c @@ -37,7 +37,6 @@ #include "gmc/gmc_8_2_sh_mask.h" #include "oss/oss_3_0_d.h" #include "oss/oss_3_0_sh_mask.h" -#include "gca/gfx_8_0_sh_mask.h" #include "dce/dce_10_0_d.h" #include "dce/dce_10_0_sh_mask.h" #include "smu/smu_7_1_3_d.h" -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 2/2] drm/amd/display: Fix Scaling (RMX_*) for DC driver
On 2018-11-16 2:59 p.m., Bhawanpreet Lakha wrote:
> Before:
> We use drm_match_cea_mode() to get the vic for any mode we
> want to set, most of the time vic will be different for the new mode.
>
> DC uses memcmp to check if timing changed, in this case DC will
> say timing changed and we endup doing a full modeset.
>
> Current:
> Now we check if !RMX_OFF and old_refresh == new_refresh if so
> we copy the vic from old timing. In a case where we are currently on
> a lower timing and want to change to higher mode, stream->dst will be
> different and cause us to do a full modeset, which is what we want.
>
> Signed-off-by: Bhawanpreet Lakha
> ---
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 49
> ++-
> 1 file changed, 38 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index e0328e8dcff3..61e994770f08 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -2554,7 +2554,8 @@ static void
> adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_
> static void
> fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream,
>const struct drm_display_mode
> *mode_in,
> - const struct drm_connector
> *connector)
> + const struct drm_connector
> *connector,
> + const struct dc_stream_state
> *old_stream)
> {
> struct dc_crtc_timing *timing_out = >timing;
> const struct drm_display_info *info = >display_info;
> @@ -2580,7 +2581,18 @@ fill_stream_properties_from_drm_display_mode(struct
> dc_stream_state *stream,
> connector);
> timing_out->scan_type = SCANNING_TYPE_NODATA;
> timing_out->hdmi_vic = 0;
> - timing_out->vic = drm_match_cea_mode(mode_in);
> +
> + if(old_stream) {
> + timing_out->vic = old_stream->timing.vic;
> + timing_out->flags.HSYNC_POSITIVE_POLARITY =
> old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
> + timing_out->flags.VSYNC_POSITIVE_POLARITY =
> old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
> + } else {
> + timing_out->vic = drm_match_cea_mode(mode_in);
> + if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
> + timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
> + if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
> + timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
> + }
>
> timing_out->h_addressable = mode_in->crtc_hdisplay;
> timing_out->h_total = mode_in->crtc_htotal;
> @@ -2596,10 +2608,6 @@ fill_stream_properties_from_drm_display_mode(struct
> dc_stream_state *stream,
> mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
> timing_out->pix_clk_khz = mode_in->crtc_clock;
> timing_out->aspect_ratio = get_aspect_ratio(mode_in);
> - if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
> - timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
> - if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
> - timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
>
> stream->output_color_space = get_output_color_space(timing_out);
>
> @@ -2762,13 +2770,18 @@ static void
> dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
> static struct dc_stream_state *
> create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
> const struct drm_display_mode *drm_mode,
> -const struct dm_connector_state *dm_state)
> +const struct dm_connector_state *dm_state,
> +const struct dc_stream_state *old_stream)
> {
> struct drm_display_mode *preferred_mode = NULL;
> struct drm_connector *drm_connector;
> struct dc_stream_state *stream = NULL;
> struct drm_display_mode mode = *drm_mode;
> bool native_mode_found = false;
> + bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
> + int mode_refresh;
> + int preferred_refresh;
> +
> struct dc_sink *sink = NULL;
> if (aconnector == NULL) {
> DRM_ERROR("aconnector is NULL!\n");
> @@ -2807,6 +2820,8 @@ create_stream_for_sink(struct amdgpu_dm_connector
> *aconnector,
> struct drm_display_mode,
> head);
>
> + mode_refresh = drm_mode_vrefresh();
> +
> if (preferred_mode == NULL) {
> /*
>* This may not be an error, the use case is when we have no
> @@ -2824,8 +2839,19 @@ create_stream_for_sink(struct amdgpu_dm_connector
> *aconnector,
> if (!dm_state)
> drm_mode_set_crtcinfo(, 0);
>
> - fill_stream_properties_from_drm_display_mode(stream,
> -
Re: [PATCH] drm/amdgpu: disable page queue support for Vega12
Reviewed-by: Philip Yang On 2018-11-21 9:54 a.m., Alex Deucher wrote: > Keep it disabled until we confirm it's ready. > > Signed-off-by: Alex Deucher > --- > drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c > b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c > index e6cb2c399957..a973dea7b242 100644 > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c > @@ -1455,9 +1455,10 @@ static bool sdma_v4_0_fw_support_paging_queue(struct > amdgpu_device *adev) > case CHIP_VEGA10: > return fw_version >= 430; > case CHIP_VEGA12: > - return fw_version >= 31; > + /*return fw_version >= 31;*/ > + return false; > case CHIP_VEGA20: > - //return fw_version >= 115; > + /*return fw_version >= 115;*/ > return false; > default: > return false; ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: disable page queue support for Vega12
Keep it disabled until we confirm it's ready. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index e6cb2c399957..a973dea7b242 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -1455,9 +1455,10 @@ static bool sdma_v4_0_fw_support_paging_queue(struct amdgpu_device *adev) case CHIP_VEGA10: return fw_version >= 430; case CHIP_VEGA12: - return fw_version >= 31; + /*return fw_version >= 31;*/ + return false; case CHIP_VEGA20: - //return fw_version >= 115; + /*return fw_version >= 115;*/ return false; default: return false; -- 2.13.6 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: disable page queue support for Vega20
Do we need this for vega12 as well? From: amd-gfx on behalf of Alex Deucher Sent: Wednesday, November 21, 2018 2:25:06 AM To: Quan, Evan Cc: amd-gfx list Subject: Re: [PATCH] drm/amdgpu: disable page queue support for Vega20 Reviewed-by: Alex Deucher On Wed, Nov 21, 2018 at 1:40 AM Evan Quan wrote: > > Keep it disabled until we confirm it's ready. > > Change-Id: I2dc4c0f1156dd82f7046672fed6d22b9d18c2010 > Signed-off-by: Evan Quan > --- > drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c > b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c > index 0a3b68dd49a0..e6cb2c399957 100644 > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c > @@ -1457,7 +1457,8 @@ static bool sdma_v4_0_fw_support_paging_queue(struct > amdgpu_device *adev) > case CHIP_VEGA12: > return fw_version >= 31; > case CHIP_VEGA20: > - return fw_version >= 115; > + //return fw_version >= 115; > + return false; > default: > return false; > } > -- > 2.19.1 > > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: add the checking to avoid NULL pointer dereference
when returned fence is not valid mostly due to userspace ignored previous error causes NULL pointer dereference. Signed-off-by: Deepak Sharma --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 024dfbd87f11..14166cd8a12f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -1403,6 +1403,8 @@ static struct dma_fence *amdgpu_cs_get_fence(struct amdgpu_device *adev, fence = amdgpu_ctx_get_fence(ctx, entity, user->seq_no); amdgpu_ctx_put(ctx); + if(!fence) + return ERR_PTR(-EINVAL); return fence; } -- 2.15.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amd: add the checking to avoid NULL pointer dereference
when returned fence is not valid mostly due to userspace ignored
previous error causes NULL pointer dereference
Signed-off-by: Deepak Sharma
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 024dfbd87f11..c85bb313e6df 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -1420,6 +1420,8 @@ int amdgpu_cs_fence_to_handle_ioctl(struct drm_device
*dev, void *data,
fence = amdgpu_cs_get_fence(adev, filp, >in.fence);
if (IS_ERR(fence))
return PTR_ERR(fence);
+ if (!fence)
+ return -EINVAL;
switch (info->in.what) {
case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ:
--
2.15.1
___
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RE: [PATCH] drm/amd: add the checking to avoid NULL pointer dereference
> -Original Message-
> From: amd-gfx On Behalf Of
> Sharma, Deepak
> Sent: Thursday, November 22, 2018 10:37 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Sharma, Deepak
> Subject: [PATCH] drm/amd: add the checking to avoid NULL pointer
> dereference
>
> when returned fence is not valid mostly due to userspace ignored previous
> error causes NULL pointer dereference
>
> Signed-off-by: Deepak Sharma
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> index 024dfbd87f11..c85bb313e6df 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> @@ -1420,6 +1420,8 @@ int amdgpu_cs_fence_to_handle_ioctl(struct
> drm_device *dev, void *data,
> fence = amdgpu_cs_get_fence(adev, filp, >in.fence);
> if (IS_ERR(fence))
> return PTR_ERR(fence);
> + if (!fence)
> + return -EINVAL;
Could you move them into the end of amdgpu_cs_get_fence()? Like:
If (!fence)
return ERR_PTR(-EINVAL);
Thanks,
-David
>
> switch (info->in.what) {
> case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ:
> --
> 2.15.1
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
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Re: [PATCH] drm/amdgpu: add the checking to avoid NULL pointer dereference
On 2018年11月22日 14:56, Sharma, Deepak wrote: when returned fence is not valid mostly due to userspace ignored previous error causes NULL pointer dereference. Signed-off-by: Deepak Sharma Reviewed-by: Chunming Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 024dfbd87f11..14166cd8a12f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -1403,6 +1403,8 @@ static struct dma_fence *amdgpu_cs_get_fence(struct amdgpu_device *adev, fence = amdgpu_ctx_get_fence(ctx, entity, user->seq_no); amdgpu_ctx_put(ctx); + if(!fence) + return ERR_PTR(-EINVAL); return fence; } ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] mm: convert totalram_pages, totalhigh_pages and managed_pages to atomic.
On Mon, Oct 22, 2018 at 10:53:22PM +0530, Arun KS wrote: > Remove managed_page_count_lock spinlock and instead use atomic > variables. > > Suggested-by: Michal Hocko > Suggested-by: Vlastimil Babka > Signed-off-by: Arun KS > > --- > As discussed here, > https://patchwork.kernel.org/patch/10627521/#22261253 > --- > --- > arch/csky/mm/init.c | 4 +- > arch/powerpc/platforms/pseries/cmm.c | 11 ++-- > arch/s390/mm/init.c | 2 +- > arch/um/kernel/mem.c | 4 +- > arch/x86/kernel/cpu/microcode/core.c | 5 +- > drivers/char/agp/backend.c| 4 +- > drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 2 +- > drivers/gpu/drm/i915/i915_gem.c | 2 +- > drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 4 +- > drivers/hv/hv_balloon.c | 19 +++ > drivers/md/dm-bufio.c | 5 +- > drivers/md/dm-crypt.c | 4 +- > drivers/md/dm-integrity.c | 4 +- > drivers/md/dm-stats.c | 3 +- > drivers/media/platform/mtk-vpu/mtk_vpu.c | 3 +- > drivers/misc/vmw_balloon.c| 2 +- > drivers/parisc/ccio-dma.c | 5 +- > drivers/parisc/sba_iommu.c| 5 +- > drivers/staging/android/ion/ion_system_heap.c | 2 +- > drivers/xen/xen-selfballoon.c | 7 +-- > fs/ceph/super.h | 3 +- > fs/file_table.c | 9 ++-- > fs/fuse/inode.c | 4 +- > fs/nfs/write.c| 3 +- > fs/nfsd/nfscache.c| 3 +- > fs/ntfs/malloc.h | 2 +- > fs/proc/base.c| 3 +- > include/linux/highmem.h | 2 +- > include/linux/mm.h| 2 +- > include/linux/mmzone.h| 10 +--- > include/linux/swap.h | 2 +- > kernel/fork.c | 6 +-- > kernel/kexec_core.c | 5 +- > kernel/power/snapshot.c | 2 +- > lib/show_mem.c| 3 +- > mm/highmem.c | 2 +- > mm/huge_memory.c | 2 +- > mm/kasan/quarantine.c | 4 +- > mm/memblock.c | 6 +-- > mm/memory_hotplug.c | 4 +- > mm/mm_init.c | 3 +- > mm/oom_kill.c | 2 +- > mm/page_alloc.c | 75 > ++- > mm/shmem.c| 12 +++-- > mm/slab.c | 3 +- > mm/swap.c | 3 +- > mm/util.c | 2 +- > mm/vmalloc.c | 4 +- > mm/vmstat.c | 4 +- > mm/workingset.c | 2 +- > mm/zswap.c| 2 +- > net/dccp/proto.c | 6 +-- > net/decnet/dn_route.c | 2 +- > net/ipv4/tcp_metrics.c| 2 +- > net/netfilter/nf_conntrack_core.c | 6 +-- > net/netfilter/xt_hashlimit.c | 4 +- > net/sctp/protocol.c | 6 +-- > security/integrity/ima/ima_kexec.c| 2 +- > 58 files changed, 171 insertions(+), 143 deletions(-) > > diff --git a/arch/csky/mm/init.c b/arch/csky/mm/init.c > index dc07c07..3f4d35e 100644 > --- a/arch/csky/mm/init.c > +++ b/arch/csky/mm/init.c > @@ -71,7 +71,7 @@ void free_initrd_mem(unsigned long start, unsigned long end) > ClearPageReserved(virt_to_page(start)); > init_page_count(virt_to_page(start)); > free_page(start); > - totalram_pages++; > + atomic_long_inc(_pages); > } > } > #endif > @@ -88,7 +88,7 @@ void free_initmem(void) > ClearPageReserved(virt_to_page(addr)); > init_page_count(virt_to_page(addr)); > free_page(addr); > - totalram_pages++; > + atomic_long_inc(_pages); > addr += PAGE_SIZE; > } For csky part, it's OK. Guo Ren ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 3/5] drm/amdgpu: Refactor amdgpu_xgmi_add_device
This is prep work for updating each PSP FW in hive after
GPU reset.
Split into build topology SW state and update each PSP FW in the hive.
Save topology and count of XGMI devices for reuse.
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 55 +++-
2 files changed, 38 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 2c80453..3e5bede 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1226,6 +1226,11 @@ long amdgpu_kms_compat_ioctl(struct file *filp, unsigned
int cmd,
/*
* functions used by amdgpu_xgmi.c
*/
+
+struct amdgpu_hive_info;
+
+struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev);
+int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive);
int amdgpu_xgmi_add_device(struct amdgpu_device *adev);
/*
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
index 909216a..23e4e16 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
@@ -34,12 +34,14 @@ static DEFINE_MUTEX(xgmi_mutex);
struct amdgpu_hive_info {
uint64_thive_id;
struct list_headdevice_list;
+ struct psp_xgmi_topology_info topology_info;
+ int number_devices;
};
static struct amdgpu_hive_info xgmi_hives[AMDGPU_MAX_XGMI_HIVE];
static unsigned hive_count = 0;
-static struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device
*adev)
+struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev)
{
int i;
struct amdgpu_hive_info *tmp;
@@ -61,12 +63,33 @@ static struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct
amdgpu_device *adev)
return tmp;
}
+int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive, struct
amdgpu_device *adev)
+{
+ int ret = -EINVAL;
+
+ /* Each psp need to set the latest topology */
+ ret = psp_xgmi_set_topology_info(>psp,
+hive->number_devices,
+>topology_info);
+ if (ret)
+ dev_err(adev->dev,
+ "XGMI: Set topology failure on device %llx,
hive %llx, ret %d",
+ adev->gmc.xgmi.node_id,
+ adev->gmc.xgmi.hive_id, ret);
+ else
+ dev_info(adev->dev, "XGMI: Add node %d to hive
0x%llx.\n",
+adev->gmc.xgmi.physical_node_id,
+adev->gmc.xgmi.hive_id);
+
+ return ret;
+}
+
int amdgpu_xgmi_add_device(struct amdgpu_device *adev)
{
- struct psp_xgmi_topology_info *tmp_topology;
+ struct psp_xgmi_topology_info *hive_topology;
struct amdgpu_hive_info *hive;
struct amdgpu_xgmi *entry;
- struct amdgpu_device*tmp_adev;
+ struct amdgpu_device *tmp_adev = NULL;
int count = 0, ret = -EINVAL;
@@ -76,21 +99,21 @@ int amdgpu_xgmi_add_device(struct amdgpu_device *adev)
adev->gmc.xgmi.node_id = psp_xgmi_get_node_id(>psp);
adev->gmc.xgmi.hive_id = psp_xgmi_get_hive_id(>psp);
- tmp_topology = kzalloc(sizeof(struct psp_xgmi_topology_info),
GFP_KERNEL);
- if (!tmp_topology)
- return -ENOMEM;
mutex_lock(_mutex);
hive = amdgpu_get_xgmi_hive(adev);
if (!hive)
goto exit;
+ hive_topology = >topology_info;
+
list_add_tail(>gmc.xgmi.head, >device_list);
list_for_each_entry(entry, >device_list, head)
- tmp_topology->nodes[count++].node_id = entry->node_id;
+ hive_topology->nodes[count++].node_id = entry->node_id;
+ hive->number_devices = count;
/* Each psp need to get the latest topology */
list_for_each_entry(tmp_adev, >device_list, gmc.xgmi.head) {
- ret = psp_xgmi_get_topology_info(_adev->psp, count,
tmp_topology);
+ ret = psp_xgmi_get_topology_info(_adev->psp, count,
hive_topology);
if (ret) {
dev_err(tmp_adev->dev,
"XGMI: Get topology failure on device %llx,
hive %llx, ret %d",
@@ -101,25 +124,13 @@ int amdgpu_xgmi_add_device(struct amdgpu_device *adev)
}
}
- /* Each psp need to set the latest topology */
list_for_each_entry(tmp_adev, >device_list, gmc.xgmi.head) {
- ret = psp_xgmi_set_topology_info(_adev->psp, count,
tmp_topology);
- if (ret) {
- dev_err(tmp_adev->dev,
- "XGMI: Set topology failure on device %llx,
hive %llx, ret %d",
- tmp_adev->gmc.xgmi.node_id,
-
[PATCH 0/5] Add support for XGMI hive reset.
This set of patches adds support to reset entire XGMI hive when reset is required. Patches 1 and 2 add place holder for PSP mode 0 reset. The actual implementation is still TBD on PSP side. Patches 3-4 refactoring a bit the XGMI infrastructure as preparaton for the actual hive reset change. Patch 5 is GPU reset/recovery refactored to support XGMI hive reset. Andrey Grodzovsky (5) drm/amdgpu/psp: Add mode 0 reset function. drm/amdgpu/psp: Enable mode 0 reset for XGMI. drm/amdgpu: Refactor amdgpu_xgmi_add_device drm/amdgpu: Expose hive adev list and xgmi_mutex drm/amdgpu: Refactor GPU reset for XGMI hive case. drivers/gpu/drm/amd/amdgpu/amdgpu.h| 10 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 371 + drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c| 6 +- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h| 3 + drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 62 +++ drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 8 ++ 6 files changed, 321 insertions(+), 139 deletions(-) ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 4/5] drm/amdgpu: Expose hive adev list and xgmi_mutex
It's needed for device reset of entire hive.
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 7 ++-
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 3e5bede..4ef5f7a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1227,8 +1227,10 @@ long amdgpu_kms_compat_ioctl(struct file *filp, unsigned
int cmd,
* functions used by amdgpu_xgmi.c
*/
+extern struct mutex xgmi_mutex;
struct amdgpu_hive_info;
+struct list_head *amdgpu_xgmi_get_adev_list_handle(struct amdgpu_hive_info
*hive);
struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev);
int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive);
int amdgpu_xgmi_add_device(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
index 23e4e16..e483e60 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
@@ -26,7 +26,7 @@
#include "amdgpu_psp.h"
-static DEFINE_MUTEX(xgmi_mutex);
+DEFINE_MUTEX(xgmi_mutex);
#define AMDGPU_MAX_XGMI_HIVE 8
#define AMDGPU_MAX_XGMI_DEVICE_PER_HIVE4
@@ -41,6 +41,11 @@ struct amdgpu_hive_info {
static struct amdgpu_hive_info xgmi_hives[AMDGPU_MAX_XGMI_HIVE];
static unsigned hive_count = 0;
+struct list_head *amdgpu_xgmi_get_adev_list_handle(struct amdgpu_hive_info
*hive)
+{
+ return >device_list;
+}
+
struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev)
{
int i;
--
2.7.4
___
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[PATCH 1/5] drm/amdgpu/psp: Add mode 0 reset function.
Currently just a place holder until support from PSP in place.
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 3 +++
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 8
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index 9ec5d1a..2bdb394 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -83,6 +83,7 @@ struct psp_funcs
enum AMDGPU_UCODE_ID ucode_type);
bool (*smu_reload_quirk)(struct psp_context *psp);
int (*mode1_reset)(struct psp_context *psp);
+ int (*mode0_reset)(struct psp_context *psp);
uint64_t (*xgmi_get_node_id)(struct psp_context *psp);
uint64_t (*xgmi_get_hive_id)(struct psp_context *psp);
int (*xgmi_get_topology_info)(struct psp_context *psp, int
number_devices,
@@ -194,6 +195,8 @@ struct psp_xgmi_topology_info {
((psp)->funcs->smu_reload_quirk ?
(psp)->funcs->smu_reload_quirk((psp)) : false)
#define psp_mode1_reset(psp) \
((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) :
false)
+#define psp_mode0_reset(psp) \
+ ((psp)->funcs->mode0_reset ? (psp)->funcs->mode1_reset((psp)) :
false)
#define psp_xgmi_get_node_id(psp) \
((psp)->funcs->xgmi_get_node_id ?
(psp)->funcs->xgmi_get_node_id((psp)) : 0)
#define psp_xgmi_get_hive_id(psp) \
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index 082093a..8feb580 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -573,6 +573,13 @@ static int psp_v11_0_mode1_reset(struct psp_context *psp)
return 0;
}
+static int psp_v11_0_mode0_reset(struct psp_context *psp)
+{
+ /* TBD Once support from PSP in place */
+
+ return 0;
+}
+
/* TODO: Fill in follow functions once PSP firmware interface for XGMI is
ready.
* For now, return success and hack the hive_id so high level code can
* start testing
@@ -698,6 +705,7 @@ static const struct psp_funcs psp_v11_0_funcs = {
.cmd_submit = psp_v11_0_cmd_submit,
.compare_sram_data = psp_v11_0_compare_sram_data,
.mode1_reset = psp_v11_0_mode1_reset,
+ .mode0_reset = psp_v11_0_mode0_reset,
.xgmi_get_topology_info = psp_v11_0_xgmi_get_topology_info,
.xgmi_set_topology_info = psp_v11_0_xgmi_set_topology_info,
.xgmi_get_hive_id = psp_v11_0_xgmi_get_hive_id,
--
2.7.4
___
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[PATCH 2/5] drm/amdgpu/psp: Enable mode 0 reset for XGMI.
In case of active XGMI hive do mode 0 reset as requsted by design. Signed-off-by: Andrey Grodzovsky --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index e05dc66..befee12 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -733,7 +733,11 @@ int psp_gpu_reset(struct amdgpu_device *adev) if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) return 0; - return psp_mode1_reset(>psp); + + if (adev->gmc.xgmi.num_physical_nodes > 1) + return psp_mode0_reset(>psp); + else + return psp_mode1_reset(>psp); } static bool psp_check_fw_loading_status(struct amdgpu_device *adev, -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 5/5] drm/amdgpu: Refactor GPU reset for XGMI hive case.
For XGMI hive case do reset in steps where each step iterates over
all devs in hive. This especially important for asic reset
since all PSP FW in hive must come up within a limited time
(around 1 sec) to properply negotiate the link.
Do this by refactoring amdgpu_device_gpu_recover and amdgpu_device_reset
into pre_asic_reset, asic_reset and post_asic_reset functions where is part
is exectued for all the GPUs in the hive before going to the next step.
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 5 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 375 -
2 files changed, 264 insertions(+), 116 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 4ef5f7a..bd06d45 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1026,6 +1026,9 @@ struct amdgpu_device {
unsigned long last_mm_index;
boolin_gpu_reset;
struct mutex lock_reset;
+
+ int asic_reset_res;
+ int resched;
};
static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
@@ -1232,7 +1235,7 @@ struct amdgpu_hive_info;
struct list_head *amdgpu_xgmi_get_adev_list_handle(struct amdgpu_hive_info
*hive);
struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev);
-int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive);
+int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive, struct
amdgpu_device *adev);
int amdgpu_xgmi_add_device(struct amdgpu_device *adev);
/*
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index cb06e68..8e94d7f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3157,86 +3157,6 @@ static int amdgpu_device_recover_vram(struct
amdgpu_device *adev)
return 0;
}
-/**
- * amdgpu_device_reset - reset ASIC/GPU for bare-metal or passthrough
- *
- * @adev: amdgpu device pointer
- *
- * attempt to do soft-reset or full-reset and reinitialize Asic
- * return 0 means succeeded otherwise failed
- */
-static int amdgpu_device_reset(struct amdgpu_device *adev)
-{
- bool need_full_reset, vram_lost = 0;
- int r;
-
- need_full_reset = amdgpu_device_ip_need_full_reset(adev);
-
- if (!need_full_reset) {
- amdgpu_device_ip_pre_soft_reset(adev);
- r = amdgpu_device_ip_soft_reset(adev);
- amdgpu_device_ip_post_soft_reset(adev);
- if (r || amdgpu_device_ip_check_soft_reset(adev)) {
- DRM_INFO("soft reset failed, will fallback to full
reset!\n");
- need_full_reset = true;
- }
- }
-
- if (need_full_reset) {
- r = amdgpu_device_ip_suspend(adev);
-
-retry:
- r = amdgpu_asic_reset(adev);
- /* post card */
- amdgpu_atom_asic_init(adev->mode_info.atom_context);
-
- if (!r) {
- dev_info(adev->dev, "GPU reset succeeded, trying to
resume\n");
- r = amdgpu_device_ip_resume_phase1(adev);
- if (r)
- goto out;
-
- vram_lost = amdgpu_device_check_vram_lost(adev);
- if (vram_lost) {
- DRM_ERROR("VRAM is lost!\n");
- atomic_inc(>vram_lost_counter);
- }
-
- r = amdgpu_gtt_mgr_recover(
- >mman.bdev.man[TTM_PL_TT]);
- if (r)
- goto out;
-
- r = amdgpu_device_fw_loading(adev);
- if (r)
- return r;
-
- r = amdgpu_device_ip_resume_phase2(adev);
- if (r)
- goto out;
-
- if (vram_lost)
- amdgpu_device_fill_reset_magic(adev);
- }
- }
-
-out:
- if (!r) {
- amdgpu_irq_gpu_reset_resume_helper(adev);
- r = amdgpu_ib_ring_tests(adev);
- if (r) {
- dev_err(adev->dev, "ib ring test failed (%d).\n", r);
- r = amdgpu_device_ip_suspend(adev);
- need_full_reset = true;
- goto retry;
- }
- }
-
- if (!r)
- r = amdgpu_device_recover_vram(adev);
-
- return r;
-}
/**
* amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf
@@ -3335,31 +3255,16 @@ bool amdgpu_device_should_recover_gpu(struct
amdgpu_device *adev)
return false;
}
-/**
- * amdgpu_device_gpu_recover - reset the asic and recover scheduler
- *
- * @adev: amdgpu device pointer
- *
Re: [PATCH 1/4] drm/edid: Pass connector to AVI inforframe functions
Hi Ville, Thank you for the patch. On Tuesday, 20 November 2018 18:13:42 EET Ville Syrjala wrote: > From: Ville Syrjälä > > Make life easier for drivers by simply passing the connector > to drm_hdmi_avi_infoframe_from_display_mode() and > drm_hdmi_avi_infoframe_quant_range(). That way drivers don't > need to worry about is_hdmi2_sink mess. While this is good for display controller drivers, the change isn't great for bridge drivers. Down the road we're looking at moving connector support out of the bridge drivers. Adding an additional dependency to connectors in the bridges will make that more difficult. Ideally bridges should retrieve the information from their sink, regardless of whether it is a connector or another bridge. Please see below for an additional comment. > Cc: Alex Deucher > Cc: "Christian König" > Cc: "David (ChunMing) Zhou" > Cc: Archit Taneja > Cc: Andrzej Hajda > Cc: Laurent Pinchart > Cc: Inki Dae > Cc: Joonyoung Shim > Cc: Seung-Woo Kim > Cc: Kyungmin Park > Cc: Russell King > Cc: CK Hu > Cc: Philipp Zabel > Cc: Rob Clark > Cc: Ben Skeggs > Cc: Tomi Valkeinen > Cc: Sandy Huang > Cc: "Heiko Stübner" > Cc: Benjamin Gaignard > Cc: Vincent Abriou > Cc: Thierry Reding > Cc: Eric Anholt > Cc: Shawn Guo > Cc: Ilia Mirkin > Cc: amd-gfx@lists.freedesktop.org > Cc: linux-arm-...@vger.kernel.org > Cc: freedr...@lists.freedesktop.org > Cc: nouv...@lists.freedesktop.org > Cc: linux-te...@vger.kernel.org > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/amd/amdgpu/dce_v10_0.c| 2 +- > drivers/gpu/drm/amd/amdgpu/dce_v11_0.c| 2 +- > drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 3 ++- > drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 2 +- > drivers/gpu/drm/bridge/analogix-anx78xx.c | 5 ++-- > drivers/gpu/drm/bridge/sii902x.c | 3 ++- > drivers/gpu/drm/bridge/sil-sii8620.c | 3 +-- > drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 3 ++- > drivers/gpu/drm/drm_edid.c| 33 ++- > drivers/gpu/drm/exynos/exynos_hdmi.c | 3 ++- > drivers/gpu/drm/i2c/tda998x_drv.c | 3 ++- > drivers/gpu/drm/i915/intel_hdmi.c | 14 +- > drivers/gpu/drm/i915/intel_lspcon.c | 15 ++- > drivers/gpu/drm/i915/intel_sdvo.c | 10 --- > drivers/gpu/drm/mediatek/mtk_hdmi.c | 3 ++- > drivers/gpu/drm/msm/hdmi/hdmi_bridge.c| 3 ++- > drivers/gpu/drm/nouveau/dispnv50/disp.c | 7 +++-- > drivers/gpu/drm/omapdrm/omap_encoder.c| 5 ++-- > drivers/gpu/drm/radeon/radeon_audio.c | 2 +- > drivers/gpu/drm/rockchip/inno_hdmi.c | 4 ++- > drivers/gpu/drm/sti/sti_hdmi.c| 3 ++- > drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c| 3 ++- > drivers/gpu/drm/tegra/hdmi.c | 3 ++- > drivers/gpu/drm/tegra/sor.c | 3 ++- > drivers/gpu/drm/vc4/vc4_hdmi.c| 11 +--- > drivers/gpu/drm/zte/zx_hdmi.c | 4 ++- > include/drm/drm_edid.h| 8 +++--- > 27 files changed, 94 insertions(+), 66 deletions(-) For dw-hdmi and omapdrm, Reviewed-by: Laurent Pinchart -- Regards, Laurent Pinchart ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 2/7] drm/amdgpu: Vega10 doorbell index initialization
On Wed, Nov 21, 2018 at 10:52 AM Oak Zeng wrote:
>
> Change-Id: Ib72058337f0aa53adfc6c6aae5341a7cd665111a
> Signed-off-by: Oak Zeng
> Suggested-by: Felix Kuehling
> Suggested-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/Makefile| 2 +-
> drivers/gpu/drm/amd/amdgpu/soc15.h | 1 +
> .../drm/amd/amdgpu/vega10_doorbell_index_init.c| 54
> ++
> 3 files changed, 56 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/amd/amdgpu/vega10_doorbell_index_init.c
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
> b/drivers/gpu/drm/amd/amdgpu/Makefile
> index f76bcb9..61cea57 100644
> --- a/drivers/gpu/drm/amd/amdgpu/Makefile
> +++ b/drivers/gpu/drm/amd/amdgpu/Makefile
> @@ -63,7 +63,7 @@ amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o
> si_ih.o si_dma.o dce
>
> amdgpu-y += \
> vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o
> vega10_reg_init.o \
> - vega20_reg_init.o nbio_v7_4.o
> + vega20_reg_init.o nbio_v7_4.o vega10_doorbell_index_init.o
>
> # add DF block
> amdgpu-y += \
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h
> b/drivers/gpu/drm/amd/amdgpu/soc15.h
> index f8ad780..d37c57d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.h
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.h
> @@ -58,4 +58,5 @@ void soc15_program_register_sequence(struct amdgpu_device
> *adev,
> int vega10_reg_base_init(struct amdgpu_device *adev);
> int vega20_reg_base_init(struct amdgpu_device *adev);
>
> +void vega10_doorbell_index_init(struct amdgpu_device *adev);
> #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_doorbell_index_init.c
> b/drivers/gpu/drm/amd/amdgpu/vega10_doorbell_index_init.c
> new file mode 100644
> index 000..e8216a3
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/amdgpu/vega10_doorbell_index_init.c
> @@ -0,0 +1,54 @@
> +/*
> + * Copyright 2018 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + */
> +
> +#include "amdgpu.h"
> +
> +void vega10_doorbell_index_init(struct amdgpu_device *adev)
> +{
> + adev->doorbell_index.kiq = 0x00;
> + adev->doorbell_index.mec_ring0 = 0x03;
> + adev->doorbell_index.mec_ring1 = 0x04;
> + adev->doorbell_index.mec_ring2 = 0x05;
> + adev->doorbell_index.mec_ring3 = 0x06;
> + adev->doorbell_index.mec_ring4 = 0x07;
> + adev->doorbell_index.mec_ring5 = 0x08;
> + adev->doorbell_index.mec_ring6 = 0x09;
> + adev->doorbell_index.mec_ring7 = 0x0a;
> + adev->doorbell_index.userqueue_start = 0x0b;
> + adev->doorbell_index.userqueue_end = 0x8a;
> + adev->doorbell_index.gfx_ring0 = 0x8b;
> + adev->doorbell_index.sdma_engine0 = 0xf0;
> + adev->doorbell_index.sdma_engine1 = 0xf2;
> + adev->doorbell_index.ih = 0xf4;
> + adev->doorbell_index.uvd_vce.uvd_ring0_1 = 0xf8;
> + adev->doorbell_index.uvd_vce.uvd_ring2_3 = 0xf9;
> + adev->doorbell_index.uvd_vce.uvd_ring4_5 = 0xfa;
> + adev->doorbell_index.uvd_vce.uvd_ring6_7 = 0xfb;
> + adev->doorbell_index.uvd_vce.vce_ring0_1 = 0xfc;
> + adev->doorbell_index.uvd_vce.vce_ring2_3 = 0xfd;
> + adev->doorbell_index.uvd_vce.vce_ring4_5 = 0xfe;
> + adev->doorbell_index.uvd_vce.vce_ring6_7 = 0xff;
> + /* In unit of dword doorbell */
> + adev->doorbell_index.max_assignment = 0xff << 1;
> +}
No need to add a new file for this. Just add this to
vega10_reg_init.c. Also, please use the doorbell enums rather than
hardcoding the numbers.
Alex
> +
> --
> 2.7.4
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 7/7] drm/amdgpu: Use new doorbell layout for vega20 and future asic
On Wed, Nov 21, 2018 at 10:52 AM Oak Zeng wrote:
>
> Change-Id: I04d22fb717ac50483c0835f160a2e860e344f358
> Signed-off-by: Oak Zeng
> Suggested-by: Felix Kuehling
> Suggested-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/Makefile| 4 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +-
> drivers/gpu/drm/amd/amdgpu/soc15.h | 1 +
> .../drm/amd/amdgpu/vega20_doorbell_index_init.c| 64
> ++
> 4 files changed, 70 insertions(+), 3 deletions(-)
> create mode 100644 drivers/gpu/drm/amd/amdgpu/vega20_doorbell_index_init.c
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
> b/drivers/gpu/drm/amd/amdgpu/Makefile
> index 3ab8eba..b3b150b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/Makefile
> +++ b/drivers/gpu/drm/amd/amdgpu/Makefile
> @@ -63,8 +63,8 @@ amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o
> si_ih.o si_dma.o dce
>
> amdgpu-y += \
> vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o
> vega10_reg_init.o \
> - vega20_reg_init.o nbio_v7_4.o vega10_doorbell_index_init.o
> vega12_doorbell_index_init.o \
> - vi_doorbell_index_init.o
> + vega20_reg_init.o nbio_v7_4.o vi_doorbell_index_init.o
> vega10_doorbell_index_init.o \
> + vega12_doorbell_index_init.o vega20_doorbell_index_init.o
>
> # add DF block
> amdgpu-y += \
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 3ffd8f5..19f2149 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -517,8 +517,10 @@ static int amdgpu_device_doorbell_init(struct
> amdgpu_device *adev)
> vi_doorbell_index_init(adev);
> else if (adev->asic_type == CHIP_VEGA10)
> vega10_doorbell_index_init(adev);
> - else
> + else if (adev->asic_type == CHIP_VEGA12 || adev->asic_type ==
> CHIP_RAVEN)
> vega12_doorbell_index_init(adev);
> + else
> + vega20_doorbell_index_init(adev);
>
> /* No doorbell on SI hardware generation */
> if (adev->asic_type < CHIP_BONAIRE) {
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h
> b/drivers/gpu/drm/amd/amdgpu/soc15.h
> index 939c0e8..6ba0d26 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.h
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.h
> @@ -60,4 +60,5 @@ int vega20_reg_base_init(struct amdgpu_device *adev);
>
> void vega10_doorbell_index_init(struct amdgpu_device *adev);
> void vega12_doorbell_index_init(struct amdgpu_device *adev);
> +void vega20_doorbell_index_init(struct amdgpu_device *adev);
> #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_doorbell_index_init.c
> b/drivers/gpu/drm/amd/amdgpu/vega20_doorbell_index_init.c
> new file mode 100644
> index 000..dcaef7f
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/amdgpu/vega20_doorbell_index_init.c
> @@ -0,0 +1,64 @@
> +/*
> + * Copyright 2018 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + */
> +
> +#include "amdgpu.h"
> +
> +void vega20_doorbell_index_init(struct amdgpu_device *adev)
> +{
> + /* Compute + GFX: 0~255 */
> + adev->doorbell_index.kiq = 0x00;
> + adev->doorbell_index.mec_ring0 = 0x03;
> + adev->doorbell_index.mec_ring1 = 0x04;
> + adev->doorbell_index.mec_ring2 = 0x05;
> + adev->doorbell_index.mec_ring3 = 0x06;
> + adev->doorbell_index.mec_ring4 = 0x07;
> + adev->doorbell_index.mec_ring5 = 0x08;
> + adev->doorbell_index.mec_ring6 = 0x09;
> + adev->doorbell_index.mec_ring7 = 0x0a;
> + adev->doorbell_index.userqueue_start = 0x0b;
> + adev->doorbell_index.userqueue_end = 0x8a;
> + adev->doorbell_index.gfx_ring0 = 0x8b;
> + /* SDMA:256~335*/
> + adev->doorbell_index.sdma_engine0 = 0x100;
> +
RE: [PATCH 7/7] drm/amdgpu: Use new doorbell layout for vega20 and future asic
The new doorbell layout for vega20 was an agreement b/t Felix/Alex and Windows
team. Windows team want us to try the new layout first. If it works, they will
apply the same layout.
Previously we used a MACRO definitions for doorbell layout. There are 32-bit
and 64-bit doorbell layout. Pre-vega10 use 32-bit definition and Vega10 and
after use 64-bit definition. All the doorbell layout change need to be backward
compatible, otherwise we break compatibility with GIM and the Windows driver on
SRIOV. If we do it in the old way, we will have to add a new set of layout for
vega20 because the agreed layout for vega20 is totally different. Making
doorbell layout asic-specific makes things clear and easy to extend in the
future if we want to use different layout for new asics.
The old MACRO definition is pretty messy. Sometimes people might be confusing
when to use the 32-bit layout and when 64-bit. I actually found a typo in
gfx_v9_0.c where 64-bit doorbell should be used but 32-bit was programmed. If
you guys agree, what I can do is, keep the old MACRO definition but do the
asic-specific doorbell initialization at the same time?
thanks,
Oak
-Original Message-
From: amd-gfx On Behalf Of Liu, Shaoyun
Sent: Wednesday, November 21, 2018 11:10 AM
To: Zeng, Oak ; amd-gfx@lists.freedesktop.org
Cc: Zeng, Oak
Subject: Re: [PATCH 7/7] drm/amdgpu: Use new doorbell layout for vega20 and
future asic
The doorbell index defines should be compatible with what is used in windows
driver . I don't see the necessary to introduce the new init file for this
instead of use the original MACRO defines. We need to coordinate with windows
driver team for a new user queue SDMA doorbell range and used them for vega20
and future asic .
Regards
shaoyun.liu
On 2018-11-21 10:52 a.m., Oak Zeng wrote:
> Change-Id: I04d22fb717ac50483c0835f160a2e860e344f358
> Signed-off-by: Oak Zeng
> Suggested-by: Felix Kuehling
> Suggested-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/Makefile| 4 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +-
> drivers/gpu/drm/amd/amdgpu/soc15.h | 1 +
> .../drm/amd/amdgpu/vega20_doorbell_index_init.c| 64
> ++
> 4 files changed, 70 insertions(+), 3 deletions(-)
> create mode 100644
> drivers/gpu/drm/amd/amdgpu/vega20_doorbell_index_init.c
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
> b/drivers/gpu/drm/amd/amdgpu/Makefile
> index 3ab8eba..b3b150b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/Makefile
> +++ b/drivers/gpu/drm/amd/amdgpu/Makefile
> @@ -63,8 +63,8 @@ amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o
> gfx_v6_0.o si_ih.o si_dma.o dce
>
> amdgpu-y += \
> vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o
> vega10_reg_init.o \
> - vega20_reg_init.o nbio_v7_4.o vega10_doorbell_index_init.o
> vega12_doorbell_index_init.o \
> - vi_doorbell_index_init.o
> + vega20_reg_init.o nbio_v7_4.o vi_doorbell_index_init.o
> vega10_doorbell_index_init.o \
> + vega12_doorbell_index_init.o vega20_doorbell_index_init.o
>
> # add DF block
> amdgpu-y += \
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 3ffd8f5..19f2149 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -517,8 +517,10 @@ static int amdgpu_device_doorbell_init(struct
> amdgpu_device *adev)
> vi_doorbell_index_init(adev);
> else if (adev->asic_type == CHIP_VEGA10)
> vega10_doorbell_index_init(adev);
> - else
> + else if (adev->asic_type == CHIP_VEGA12 || adev->asic_type ==
> +CHIP_RAVEN)
> vega12_doorbell_index_init(adev);
> + else
> + vega20_doorbell_index_init(adev);
>
> /* No doorbell on SI hardware generation */
> if (adev->asic_type < CHIP_BONAIRE) { diff --git
> a/drivers/gpu/drm/amd/amdgpu/soc15.h
> b/drivers/gpu/drm/amd/amdgpu/soc15.h
> index 939c0e8..6ba0d26 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.h
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.h
> @@ -60,4 +60,5 @@ int vega20_reg_base_init(struct amdgpu_device
> *adev);
>
> void vega10_doorbell_index_init(struct amdgpu_device *adev);
> void vega12_doorbell_index_init(struct amdgpu_device *adev);
> +void vega20_doorbell_index_init(struct amdgpu_device *adev);
> #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_doorbell_index_init.c
> b/drivers/gpu/drm/amd/amdgpu/vega20_doorbell_index_init.c
> new file mode 100644
> index 000..dcaef7f
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/amdgpu/vega20_doorbell_index_init.c
> @@ -0,0 +1,64 @@
> +/*
> + * Copyright 2018 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person
> +obtaining a
> + * copy of this software and associated documentation files (the
> +"Software"),
> + * to deal in the Software
RE: [PATCH 7/7] drm/amdgpu: Use new doorbell layout for vega20 and future asic
>No need to add a new file for this. Just add this to vega20_reg_init.c.
Agreed.
>Also, please use the doorbell enums rather than hardcoding the numbers.
Ok. Where should I put the doorbell enums for vega20? In amdgpu.h or in
vega20_reg_init.c?
thanks,
Oak
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Wednesday, November 21, 2018 11:22 AM
To: Zeng, Oak
Cc: Zeng, Oak ; amd-gfx list
Subject: Re: [PATCH 7/7] drm/amdgpu: Use new doorbell layout for vega20 and
future asic
On Wed, Nov 21, 2018 at 10:52 AM Oak Zeng wrote:
>
> Change-Id: I04d22fb717ac50483c0835f160a2e860e344f358
> Signed-off-by: Oak Zeng
> Suggested-by: Felix Kuehling
> Suggested-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/Makefile| 4 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +-
> drivers/gpu/drm/amd/amdgpu/soc15.h | 1 +
> .../drm/amd/amdgpu/vega20_doorbell_index_init.c| 64
> ++
> 4 files changed, 70 insertions(+), 3 deletions(-) create mode 100644
> drivers/gpu/drm/amd/amdgpu/vega20_doorbell_index_init.c
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
> b/drivers/gpu/drm/amd/amdgpu/Makefile
> index 3ab8eba..b3b150b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/Makefile
> +++ b/drivers/gpu/drm/amd/amdgpu/Makefile
> @@ -63,8 +63,8 @@ amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o
> gfx_v6_0.o si_ih.o si_dma.o dce
>
> amdgpu-y += \
> vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o
> vega10_reg_init.o \
> - vega20_reg_init.o nbio_v7_4.o vega10_doorbell_index_init.o
> vega12_doorbell_index_init.o \
> - vi_doorbell_index_init.o
> + vega20_reg_init.o nbio_v7_4.o vi_doorbell_index_init.o
> vega10_doorbell_index_init.o \
> + vega12_doorbell_index_init.o vega20_doorbell_index_init.o
>
> # add DF block
> amdgpu-y += \
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 3ffd8f5..19f2149 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -517,8 +517,10 @@ static int amdgpu_device_doorbell_init(struct
> amdgpu_device *adev)
> vi_doorbell_index_init(adev);
> else if (adev->asic_type == CHIP_VEGA10)
> vega10_doorbell_index_init(adev);
> - else
> + else if (adev->asic_type == CHIP_VEGA12 || adev->asic_type ==
> + CHIP_RAVEN)
> vega12_doorbell_index_init(adev);
> + else
> + vega20_doorbell_index_init(adev);
>
> /* No doorbell on SI hardware generation */
> if (adev->asic_type < CHIP_BONAIRE) { diff --git
> a/drivers/gpu/drm/amd/amdgpu/soc15.h
> b/drivers/gpu/drm/amd/amdgpu/soc15.h
> index 939c0e8..6ba0d26 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.h
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.h
> @@ -60,4 +60,5 @@ int vega20_reg_base_init(struct amdgpu_device
> *adev);
>
> void vega10_doorbell_index_init(struct amdgpu_device *adev); void
> vega12_doorbell_index_init(struct amdgpu_device *adev);
> +void vega20_doorbell_index_init(struct amdgpu_device *adev);
> #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_doorbell_index_init.c
> b/drivers/gpu/drm/amd/amdgpu/vega20_doorbell_index_init.c
> new file mode 100644
> index 000..dcaef7f
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/amdgpu/vega20_doorbell_index_init.c
> @@ -0,0 +1,64 @@
> +/*
> + * Copyright 2018 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person
> +obtaining a
> + * copy of this software and associated documentation files (the
> +"Software"),
> + * to deal in the Software without restriction, including without
> +limitation
> + * the rights to use, copy, modify, merge, publish, distribute,
> +sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom
> +the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> +included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> +EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> +MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
> +SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM,
> +DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
> +OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
> +OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + */
> +
> +#include "amdgpu.h"
> +
> +void vega20_doorbell_index_init(struct amdgpu_device *adev) {
> + /* Compute + GFX: 0~255 */
> + adev->doorbell_index.kiq = 0x00;
> + adev->doorbell_index.mec_ring0 = 0x03;
> + adev->doorbell_index.mec_ring1 =
[pull] amdgpu, amdkfd drm-fixes-4.20
Hi Dave, - OD fixes for powerplay - Vega20 fixes - KFD fix for Kaveri - add missing firmware declaration for hainan (SI chip) - Fix DC user experience regressions related to panels that support >8 bpc The following changes since commit 9826b1138e497dfb48f5cc64a82c219b4d0932da: Merge branch 'drm-fixes-4.20' of git://people.freedesktop.org/~agd5f/linux into drm-fixes (2018-11-16 02:15:00 +1000) are available in the git repository at: git://people.freedesktop.org/~agd5f/linux drm-fixes-4.20 for you to fetch changes up to a5d0f4565996e5595a10cb57b3d1e3d74379c502: drm/amdgpu: Enable HDP memory light sleep (2018-11-20 14:40:15 -0500) Evan Quan (1): drm/amd/powerplay: disable Vega20 DS related features Felix Kuehling (1): drm/amdgpu: Fix oops when pp_funcs->switch_power_profile is unset Greathouse, Joseph (1): drm/amd/pp: handle negative values when reading OD Kenneth Feng (1): drm/amdgpu: Enable HDP memory light sleep Nicholas Kazlauskas (2): drm/amdgpu: Add amdgpu "max bpc" connector property (v2) drm/amd/display: Support amdgpu "max bpc" connector property (v2) Takashi Iwai (1): drm/amdgpu: Add missing firmware entry for HAINAN drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 7 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c| 7 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 2 ++ drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 1 + drivers/gpu/drm/amd/amdgpu/soc15.c | 39 ++ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 16 + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 1 + drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 20 +-- drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 25 ++ drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 23 ++--- drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 30 - 11 files changed, 115 insertions(+), 56 deletions(-) ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 3/7] drm/amdgpu: Vega12 doorbell index initialization
On Wed, Nov 21, 2018 at 10:52 AM Oak Zeng wrote:
>
> Change-Id: Ib2c570224321bb7002d2ed01f43ac70203e86f88
> Signed-off-by: Oak Zeng
> Suggested-by: Felix Kuehling
> Suggested-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/Makefile| 2 +-
> drivers/gpu/drm/amd/amdgpu/soc15.h | 1 +
> .../drm/amd/amdgpu/vega12_doorbell_index_init.c| 54
> ++
> 3 files changed, 56 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/amd/amdgpu/vega12_doorbell_index_init.c
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
> b/drivers/gpu/drm/amd/amdgpu/Makefile
> index 61cea57..96a4e1c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/Makefile
> +++ b/drivers/gpu/drm/amd/amdgpu/Makefile
> @@ -63,7 +63,7 @@ amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o
> si_ih.o si_dma.o dce
>
> amdgpu-y += \
> vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o
> vega10_reg_init.o \
> - vega20_reg_init.o nbio_v7_4.o vega10_doorbell_index_init.o
> + vega20_reg_init.o nbio_v7_4.o vega10_doorbell_index_init.o
> vega12_doorbell_index_init.o
>
> # add DF block
> amdgpu-y += \
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h
> b/drivers/gpu/drm/amd/amdgpu/soc15.h
> index d37c57d..939c0e8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.h
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.h
> @@ -59,4 +59,5 @@ int vega10_reg_base_init(struct amdgpu_device *adev);
> int vega20_reg_base_init(struct amdgpu_device *adev);
>
> void vega10_doorbell_index_init(struct amdgpu_device *adev);
> +void vega12_doorbell_index_init(struct amdgpu_device *adev);
> #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/vega12_doorbell_index_init.c
> b/drivers/gpu/drm/amd/amdgpu/vega12_doorbell_index_init.c
> new file mode 100644
> index 000..43be474
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/amdgpu/vega12_doorbell_index_init.c
> @@ -0,0 +1,54 @@
> +/*
> + * Copyright 2018 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + */
> +
> +#include "amdgpu.h"
> +
> +void vega12_doorbell_index_init(struct amdgpu_device *adev)
> +{
> + adev->doorbell_index.kiq = 0x00;
> + adev->doorbell_index.mec_ring0 = 0x03;
> + adev->doorbell_index.mec_ring1 = 0x04;
> + adev->doorbell_index.mec_ring2 = 0x05;
> + adev->doorbell_index.mec_ring3 = 0x06;
> + adev->doorbell_index.mec_ring4 = 0x07;
> + adev->doorbell_index.mec_ring5 = 0x08;
> + adev->doorbell_index.mec_ring6 = 0x09;
> + adev->doorbell_index.mec_ring7 = 0x0a;
> + adev->doorbell_index.userqueue_start = 0x0b;
> + adev->doorbell_index.userqueue_end = 0x8a;
> + adev->doorbell_index.gfx_ring0 = 0x8b;
> + adev->doorbell_index.sdma_engine0 = 0xe0;
> + adev->doorbell_index.sdma_engine1 = 0xe8;
> + adev->doorbell_index.ih = 0xf4;
> + adev->doorbell_index.uvd_vce.uvd_ring0_1 = 0xf8;
> + adev->doorbell_index.uvd_vce.uvd_ring2_3 = 0xf9;
> + adev->doorbell_index.uvd_vce.uvd_ring4_5 = 0xfa;
> + adev->doorbell_index.uvd_vce.uvd_ring6_7 = 0xfb;
> + adev->doorbell_index.uvd_vce.vce_ring0_1 = 0xfc;
> + adev->doorbell_index.uvd_vce.vce_ring2_3 = 0xfd;
> + adev->doorbell_index.uvd_vce.vce_ring4_5 = 0xfe;
> + adev->doorbell_index.uvd_vce.vce_ring6_7 = 0xff;
> + /* In unit of dword doorbell */
> + adev->doorbell_index.max_assignment = 0xff << 1;
> +}
You can drop this patch. Just use the vega10 one for vega12. It's the same.
Alex
> +
> --
> 2.7.4
>
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Re: [PATCH 5/7] drm/amdgpu: Call doorbell index init on device initialization
On Wed, Nov 21, 2018 at 10:52 AM Oak Zeng wrote:
>
> Change-Id: I2f004bbbe2565035460686f4fc16e86b77a2a9b5
> Signed-off-by: Oak Zeng
> Suggested-by: Felix Kuehling
> Suggested-by: Alex Deucher
I think it would be cleaner to add this to the *_set_ip_blocks()
functions in cik.c, vi.c, and soc15.c so it aligns with the
*_reg_base_init() calls.
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index cb06e68..a942a88 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -513,6 +513,13 @@ void amdgpu_device_pci_config_reset(struct amdgpu_device
> *adev)
> */
> static int amdgpu_device_doorbell_init(struct amdgpu_device *adev)
> {
> + if (adev->asic_type < CHIP_VEGA10)
> + vi_doorbell_index_init(adev);
> + else if (adev->asic_type == CHIP_VEGA10)
> + vega10_doorbell_index_init(adev);
> + else
> + vega12_doorbell_index_init(adev);
> +
> /* No doorbell on SI hardware generation */
> if (adev->asic_type < CHIP_BONAIRE) {
> adev->doorbell.base = 0;
> --
> 2.7.4
>
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Re: [PATCH 7/7] drm/amdgpu: Use new doorbell layout for vega20 and future asic
On Wed, Nov 21, 2018 at 11:37 AM Zeng, Oak wrote:
>
> >No need to add a new file for this. Just add this to vega20_reg_init.c.
> Agreed.
>
> >Also, please use the doorbell enums rather than hardcoding the numbers.
> Ok. Where should I put the doorbell enums for vega20? In amdgpu.h or in
> vega20_reg_init.c?
Maybe add amdgpu_doorbell.h and move all of the enums there?
Alex
>
> thanks,
> Oak
>
> -Original Message-
> From: amd-gfx On Behalf Of Alex
> Deucher
> Sent: Wednesday, November 21, 2018 11:22 AM
> To: Zeng, Oak
> Cc: Zeng, Oak ; amd-gfx list
> Subject: Re: [PATCH 7/7] drm/amdgpu: Use new doorbell layout for vega20 and
> future asic
>
> On Wed, Nov 21, 2018 at 10:52 AM Oak Zeng wrote:
> >
> > Change-Id: I04d22fb717ac50483c0835f160a2e860e344f358
> > Signed-off-by: Oak Zeng
> > Suggested-by: Felix Kuehling
> > Suggested-by: Alex Deucher
> > ---
> > drivers/gpu/drm/amd/amdgpu/Makefile| 4 +-
> > drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +-
> > drivers/gpu/drm/amd/amdgpu/soc15.h | 1 +
> > .../drm/amd/amdgpu/vega20_doorbell_index_init.c| 64
> > ++
> > 4 files changed, 70 insertions(+), 3 deletions(-) create mode 100644
> > drivers/gpu/drm/amd/amdgpu/vega20_doorbell_index_init.c
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
> > b/drivers/gpu/drm/amd/amdgpu/Makefile
> > index 3ab8eba..b3b150b 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/Makefile
> > +++ b/drivers/gpu/drm/amd/amdgpu/Makefile
> > @@ -63,8 +63,8 @@ amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o
> > gfx_v6_0.o si_ih.o si_dma.o dce
> >
> > amdgpu-y += \
> > vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o
> > nbio_v7_0.o vega10_reg_init.o \
> > - vega20_reg_init.o nbio_v7_4.o vega10_doorbell_index_init.o
> > vega12_doorbell_index_init.o \
> > - vi_doorbell_index_init.o
> > + vega20_reg_init.o nbio_v7_4.o vi_doorbell_index_init.o
> > vega10_doorbell_index_init.o \
> > + vega12_doorbell_index_init.o vega20_doorbell_index_init.o
> >
> > # add DF block
> > amdgpu-y += \
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > index 3ffd8f5..19f2149 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > @@ -517,8 +517,10 @@ static int amdgpu_device_doorbell_init(struct
> > amdgpu_device *adev)
> > vi_doorbell_index_init(adev);
> > else if (adev->asic_type == CHIP_VEGA10)
> > vega10_doorbell_index_init(adev);
> > - else
> > + else if (adev->asic_type == CHIP_VEGA12 || adev->asic_type ==
> > + CHIP_RAVEN)
> > vega12_doorbell_index_init(adev);
> > + else
> > + vega20_doorbell_index_init(adev);
> >
> > /* No doorbell on SI hardware generation */
> > if (adev->asic_type < CHIP_BONAIRE) { diff --git
> > a/drivers/gpu/drm/amd/amdgpu/soc15.h
> > b/drivers/gpu/drm/amd/amdgpu/soc15.h
> > index 939c0e8..6ba0d26 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/soc15.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/soc15.h
> > @@ -60,4 +60,5 @@ int vega20_reg_base_init(struct amdgpu_device
> > *adev);
> >
> > void vega10_doorbell_index_init(struct amdgpu_device *adev); void
> > vega12_doorbell_index_init(struct amdgpu_device *adev);
> > +void vega20_doorbell_index_init(struct amdgpu_device *adev);
> > #endif
> > diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_doorbell_index_init.c
> > b/drivers/gpu/drm/amd/amdgpu/vega20_doorbell_index_init.c
> > new file mode 100644
> > index 000..dcaef7f
> > --- /dev/null
> > +++ b/drivers/gpu/drm/amd/amdgpu/vega20_doorbell_index_init.c
> > @@ -0,0 +1,64 @@
> > +/*
> > + * Copyright 2018 Advanced Micro Devices, Inc.
> > + *
> > + * Permission is hereby granted, free of charge, to any person
> > +obtaining a
> > + * copy of this software and associated documentation files (the
> > +"Software"),
> > + * to deal in the Software without restriction, including without
> > +limitation
> > + * the rights to use, copy, modify, merge, publish, distribute,
> > +sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom
> > +the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice shall be
> > +included in
> > + * all copies or substantial portions of the Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> > +EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> > +MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
> > +SHALL
> > + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM,
> > +DAMAGES OR
> > + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
> > +OTHERWISE,
> > + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
