[PATCH 3/3] drm/radeon: enable ABGR and XBGR formats
Add support for DRM_FORMAT_{A,X}BGR in atombios_crtc
R6xx crossbar registers are defined and used based on ASIC_IS_DCE2 condition,
for DCE1/R5xx AVIVO_D1GRPH_SWAP_RB bit is used to swap red and blue channels.
Signed-off-by: Mauro Rossi
---
drivers/gpu/drm/radeon/atombios_crtc.c | 25 +
drivers/gpu/drm/radeon/r600_reg.h | 31 +-
2 files changed, 51 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c
b/drivers/gpu/drm/radeon/atombios_crtc.c
index efbd5816082d..a06ad6ab24a6 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -1254,6 +1254,16 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
/* Greater 8 bpc fb needs to bypass hw-lut to retain precision
*/
bypass_lut = true;
break;
+ case DRM_FORMAT_XBGR:
+ case DRM_FORMAT_ABGR:
+ fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
+
EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB));
+ fb_swap =
(EVERGREEN_GRPH_RED_CROSSBAR(EVERGREEN_GRPH_RED_SEL_B) |
+
EVERGREEN_GRPH_BLUE_CROSSBAR(EVERGREEN_GRPH_BLUE_SEL_R));
+#ifdef __BIG_ENDIAN
+ fb_swap =
EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
+#endif
+ break;
default:
DRM_ERROR("Unsupported screen format %s\n",
drm_get_format_name(target_fb->format->format,
_name));
@@ -1551,6 +1561,21 @@ static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
/* Greater 8 bpc fb needs to bypass hw-lut to retain precision
*/
bypass_lut = true;
break;
+ case DRM_FORMAT_XBGR:
+ case DRM_FORMAT_ABGR:
+ fb_format =
+ AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
+ AVIVO_D1GRPH_CONTROL_32BPP_ARGB;
+ if (ASIC_IS_DCE2(rdev))
+ fb_swap =
+ (R600_D1GRPH_RED_CROSSBAR(R600_D1GRPH_RED_SEL_B) |
+R600_D1GRPH_BLUE_CROSSBAR(R600_D1GRPH_BLUE_SEL_B));
+ else /* DCE1 */
+ fb_swap = AVIVO_D1GRPH_SWAP_RB;
+#ifdef __BIG_ENDIAN
+ fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
+#endif
+ break;
default:
DRM_ERROR("Unsupported screen format %s\n",
drm_get_format_name(target_fb->format->format,
_name));
diff --git a/drivers/gpu/drm/radeon/r600_reg.h
b/drivers/gpu/drm/radeon/r600_reg.h
index 3ef202629e7e..85e85ac3ba4d 100644
--- a/drivers/gpu/drm/radeon/r600_reg.h
+++ b/drivers/gpu/drm/radeon/r600_reg.h
@@ -87,11 +87,32 @@
#define R600_MEDIUM_VID_LOWER_GPIO_CNTL0x720
#define R600_LOW_VID_LOWER_GPIO_CNTL 0x724
-#define R600_D1GRPH_SWAP_CONTROL 0x610C
-# define R600_D1GRPH_SWAP_ENDIAN_NONE(0 << 0)
-# define R600_D1GRPH_SWAP_ENDIAN_16BIT (1 << 0)
-# define R600_D1GRPH_SWAP_ENDIAN_32BIT (2 << 0)
-# define R600_D1GRPH_SWAP_ENDIAN_64BIT (3 << 0)
+#define R600_D1GRPH_SWAP_CONTROL 0x610C
+# define R600_D1GRPH_ENDIAN_SWAP(x)(((x) & 0x3) << 0)
+# define R600_D1GRPH_SWAP_ENDIAN_NONE 0
+# define R600_D1GRPH_SWAP_ENDIAN_16BIT 1
+# define R600_D1GRPH_SWAP_ENDIAN_32BIT 2
+# define R600_D1GRPH_SWAP_ENDIAN_64BIT 3
+# define R600_D1GRPH_RED_CROSSBAR(x) (((x) & 0x3) << 4)
+# define R600_D1GRPH_RED_SEL_R 0
+# define R600_D1GRPH_RED_SEL_G 1
+# define R600_D1GRPH_RED_SEL_B 2
+# define R600_D1GRPH_RED_SEL_A 3
+# define R600_D1GRPH_GREEN_CROSSBAR(x) (((x) & 0x3) << 6)
+# define R600_D1GRPH_GREEN_SEL_G 0
+# define R600_D1GRPH_GREEN_SEL_B 1
+# define R600_D1GRPH_GREEN_SEL_A 2
+# define R600_D1GRPH_GREEN_SEL_R 3
+# define R600_D1GRPH_BLUE_CROSSBAR(x) (((x) & 0x3) << 8)
+# define R600_D1GRPH_BLUE_SEL_B0
+# define R600_D1GRPH_BLUE_SEL_A1
+# define R600_D1GRPH_BLUE_SEL_R2
+# define R600_D1GRPH_BLUE_SEL_G3
+# define R600_D1GRPH_ALPHA_CROSSBAR(x) (((x) & 0x3) << 10)
+# define R600_D1GRPH_ALPHA_SEL_A 0
+# define R600_D1GRPH_ALPHA_SEL_R 1
+# define R600_D1GRPH_ALPHA_SEL_G 2
+# define R600_D1GRPH_ALPHA_SE
drm/radeon,amdgpu,dc: enable ABGR and XBGR formats
Sending a respin for support of {A,X}RGB pixel formats in DCE1 and later,
with separate patches for amd dc, amdgpu and radeon
Please review taking in to account following doubts I have:
For amd dc crossbars register controls to swap red and blue channels
are already implemented in drm/amd/display/dc/dce/dce_mem_input.c
Do we need them also in dce 8, 10, 11 modules?
For amdgpu: What are the necessary *_reg.h header to consider for
crossbars register controls in amdgpu in order to cover all parts
(si, cik and later) with amd dc disabled?
[PATCH v2 1/3] drm/amd/display: enable ABGR and XBGR formats (v3)
[PATCH v2 2/3] drm/amdgpu: enable enable ABGR and XBGR formats
[PATCH v2 3/3] drm/radeon: enable ABGR and XBGR formats
___
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[PATCH 1/3] drm/amd/display: enable ABGR and XBGR formats (v3)
SURFACE_PIXEL_FORMAT_GRPH_ABGR already listed in
amd/display/dc/dc_hw_types.h
and the necessary crossbars register controls to swap red and blue channels
are already implemented in drm/amd/display/dc/dce/dce_mem_input.c
Logic to handle new formats is added in amdgpu_dm and dce 8.0, 10.0, 11.0
modules.
Signed-off-by: Mauro Rossi
---
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c| 9 +
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c| 9 +
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 8
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 ++
4 files changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index ada241bfeee9..ffb112ed825b 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -1941,6 +1941,15 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc
*crtc,
/* Greater 8 bpc fb needs to bypass hw-lut to retain precision
*/
bypass_lut = true;
break;
+ case DRM_FORMAT_XBGR:
+ case DRM_FORMAT_ABGR:
+ fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
+ fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT,
0);
+#ifdef __BIG_ENDIAN
+ fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL,
GRPH_ENDIAN_SWAP,
+ ENDIAN_8IN32);
+#endif
+ break;
default:
DRM_ERROR("Unsupported screen format %s\n",
drm_get_format_name(target_fb->format->format,
_name));
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index a5b96eac3033..283d8ce9dd7e 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -1983,6 +1983,15 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc
*crtc,
/* Greater 8 bpc fb needs to bypass hw-lut to retain precision
*/
bypass_lut = true;
break;
+ case DRM_FORMAT_XBGR:
+ case DRM_FORMAT_ABGR:
+ fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
+ fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT,
0);
+#ifdef __BIG_ENDIAN
+ fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL,
GRPH_ENDIAN_SWAP,
+ ENDIAN_8IN32);
+#endif
+ break;
default:
DRM_ERROR("Unsupported screen format %s\n",
drm_get_format_name(target_fb->format->format,
_name));
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index c9b9ab8f1b05..2c96fb811083 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -1865,6 +1865,14 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc
*crtc,
/* Greater 8 bpc fb needs to bypass hw-lut to retain precision
*/
bypass_lut = true;
break;
+ case DRM_FORMAT_XBGR:
+ case DRM_FORMAT_ABGR:
+ fb_format = ((GRPH_DEPTH_32BPP <<
GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
+(GRPH_FORMAT_ARGB <<
GRPH_CONTROL__GRPH_FORMAT__SHIFT));
+#ifdef __BIG_ENDIAN
+ fb_swap = (GRPH_ENDIAN_8IN32 <<
GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
+#endif
+ break;
default:
DRM_ERROR("Unsupported screen format %s\n",
drm_get_format_name(target_fb->format->format,
_name));
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 770c6b24be0b..4f689f47d7c3 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1892,6 +1892,10 @@ static int fill_plane_attributes_from_fb(struct
amdgpu_device *adev,
case DRM_FORMAT_ABGR2101010:
plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
break;
+ case DRM_FORMAT_XBGR:
+ case DRM_FORMAT_ABGR:
+ plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR;
+ break;
case DRM_FORMAT_NV21:
plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
break;
@@ -3190,6 +3194,8 @@ static const uint32_t rgb_formats[] = {
DRM_FORMAT_XBGR2101010,
DRM_FORMAT_ARGB2101010,
DRM_FORMAT_ABGR2101010,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_ABGR,
};
static const uint32_t yuv_formats[] = {
--
2.17.1
___
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[PATCH 2/3] drm/amdgpu: enable enable ABGR and XBGR formats
Add support for DRM_FORMAT_{A,X}BGR in amdgpu, for si and amd dc disabled
Here is it necessary to define and set crossbar registers
to swap red and blue channels
Signed-off-by: Mauro Rossi
---
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 10 ++
drivers/gpu/drm/amd/amdgpu/si_enums.h | 20
drivers/gpu/drm/amd/amdgpu/sid.h | 20
3 files changed, 50 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index 394cc1e8fe20..f2c3f6676352 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -1888,6 +1888,16 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc
*crtc,
/* Greater 8 bpc fb needs to bypass hw-lut to retain precision
*/
bypass_lut = true;
break;
+ case DRM_FORMAT_XBGR:
+ case DRM_FORMAT_ABGR:
+ fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) |
+GRPH_FORMAT(GRPH_FORMAT_ARGB));
+ fb_swap = (GRPH_RED_CROSSBAR(GRPH_RED_SEL_B) |
+ GRPH_BLUE_CROSSBAR(GRPH_BLUE_SEL_R));
+#ifdef __BIG_ENDIAN
+ fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32);
+#endif
+ break;
default:
DRM_ERROR("Unsupported screen format %s\n",
drm_get_format_name(target_fb->format->format,
_name));
diff --git a/drivers/gpu/drm/amd/amdgpu/si_enums.h
b/drivers/gpu/drm/amd/amdgpu/si_enums.h
index dc9e0e6b4558..790ba46eaebb 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_enums.h
+++ b/drivers/gpu/drm/amd/amdgpu/si_enums.h
@@ -46,6 +46,26 @@
#define GRPH_ENDIAN_8IN16 1
#define GRPH_ENDIAN_8IN32 2
#define GRPH_ENDIAN_8IN64 3
+#define GRPH_RED_CROSSBAR(x) (((x) & 0x3) << 4)
+#define GRPH_RED_SEL_R 0
+#define GRPH_RED_SEL_G 1
+#define GRPH_RED_SEL_B 2
+#define GRPH_RED_SEL_A 3
+#define GRPH_GREEN_CROSSBAR(x) (((x) & 0x3) << 6)
+#define GRPH_GREEN_SEL_G 0
+#define GRPH_GREEN_SEL_B 1
+#define GRPH_GREEN_SEL_A 2
+#define GRPH_GREEN_SEL_R 3
+#define GRPH_BLUE_CROSSBAR(x) (((x) & 0x3) << 8)
+#define GRPH_BLUE_SEL_B0
+#define GRPH_BLUE_SEL_A1
+#define GRPH_BLUE_SEL_R2
+#define GRPH_BLUE_SEL_G3
+#define GRPH_ALPHA_CROSSBAR(x) (((x) & 0x3) << 10)
+#define GRPH_ALPHA_SEL_A 0
+#define GRPH_ALPHA_SEL_R 1
+#define GRPH_ALPHA_SEL_G 2
+#define GRPH_ALPHA_SEL_B 3
#define GRPH_DEPTH(x) (((x) & 0x3) << 0)
#define GRPH_DEPTH_8BPP0
diff --git a/drivers/gpu/drm/amd/amdgpu/sid.h b/drivers/gpu/drm/amd/amdgpu/sid.h
index c57eff159374..7cf12adb3915 100644
--- a/drivers/gpu/drm/amd/amdgpu/sid.h
+++ b/drivers/gpu/drm/amd/amdgpu/sid.h
@@ -2201,6 +2201,26 @@
# define EVERGREEN_GRPH_ENDIAN_8IN16 1
# define EVERGREEN_GRPH_ENDIAN_8IN32 2
# define EVERGREEN_GRPH_ENDIAN_8IN64 3
+#define EVERGREEN_GRPH_RED_CROSSBAR(x) (((x) & 0x3) << 4)
+# define EVERGREEN_GRPH_RED_SEL_R 0
+# define EVERGREEN_GRPH_RED_SEL_G 1
+# define EVERGREEN_GRPH_RED_SEL_B 2
+# define EVERGREEN_GRPH_RED_SEL_A 3
+#define EVERGREEN_GRPH_GREEN_CROSSBAR(x) (((x) & 0x3) << 6)
+# define EVERGREEN_GRPH_GREEN_SEL_G 0
+# define EVERGREEN_GRPH_GREEN_SEL_B 1
+# define EVERGREEN_GRPH_GREEN_SEL_A 2
+# define EVERGREEN_GRPH_GREEN_SEL_R 3
+#define EVERGREEN_GRPH_BLUE_CROSSBAR(x) (((x) & 0x3) << 8)
+# define EVERGREEN_GRPH_BLUE_SEL_B0
+# define EVERGREEN_GRPH_BLUE_SEL_A1
+# define EVERGREEN_GRPH_BLUE_SEL_R2
+# define EVERGREEN_GRPH_BLUE_SEL_G3
+#define EVERGREEN_GRPH_ALPHA_CROSSBAR(x) (((x) & 0x3) << 10)
+# define EVERGREEN_GRPH_ALPHA_SEL_A 0
+# define EVERGREEN_GRPH_ALPHA_SEL_R 1
+# define EVERGREEN_GRPH_ALPHA_SEL_G 2
+# define EVERGREEN_GRPH_ALPHA_SEL_B 3
#define EVERGREEN_D3VGA_CONTROL 0xf8
#define EVERGREEN_D4VGA_CONTROL 0xf9
--
2.17.1
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[PATCH v3 3/3] drm/radeon: enable ABGR and XBGR formats (v2)
Add support for DRM_FORMAT_{A,X}BGR in atombios_crtc
Swapping of red and blue channels is implemented for radeon chipsets:
DCE2/R6xx and later - crossbar registers defined where needed and used
DCE1/R5xx - AVIVO_D1GRPH_SWAP_RB bit is used
(v2) Set AVIVO_D1GRPH_SWAP_RB bit in fb_format, using bitwise OR for DCE1 path
Use bitwise OR where required for big endian settings in fb_swap
Use existing code style CHIP_R600 condition, fix typo in R600 blue crossbar
Signed-off-by: Mauro Rossi
---
drivers/gpu/drm/radeon/atombios_crtc.c | 25 +
drivers/gpu/drm/radeon/r600_reg.h | 31 +-
2 files changed, 51 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c
b/drivers/gpu/drm/radeon/atombios_crtc.c
index efbd5816082d..aacecca028f1 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -1254,6 +1254,16 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
/* Greater 8 bpc fb needs to bypass hw-lut to retain precision
*/
bypass_lut = true;
break;
+ case DRM_FORMAT_XBGR:
+ case DRM_FORMAT_ABGR:
+ fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
+
EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB));
+ fb_swap =
(EVERGREEN_GRPH_RED_CROSSBAR(EVERGREEN_GRPH_RED_SEL_B) |
+
EVERGREEN_GRPH_BLUE_CROSSBAR(EVERGREEN_GRPH_BLUE_SEL_R));
+#ifdef __BIG_ENDIAN
+ fb_swap |=
EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
+#endif
+ break;
default:
DRM_ERROR("Unsupported screen format %s\n",
drm_get_format_name(target_fb->format->format,
_name));
@@ -1551,6 +1561,21 @@ static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
/* Greater 8 bpc fb needs to bypass hw-lut to retain precision
*/
bypass_lut = true;
break;
+ case DRM_FORMAT_XBGR:
+ case DRM_FORMAT_ABGR:
+ fb_format =
+ AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
+ AVIVO_D1GRPH_CONTROL_32BPP_ARGB;
+ if (rdev->family >= CHIP_R600)
+ fb_swap =
+ (R600_D1GRPH_RED_CROSSBAR(R600_D1GRPH_RED_SEL_B) |
+R600_D1GRPH_BLUE_CROSSBAR(R600_D1GRPH_BLUE_SEL_R));
+ else /* DCE1 (R5xx) */
+ fb_format |= AVIVO_D1GRPH_SWAP_RB;
+#ifdef __BIG_ENDIAN
+ fb_swap |= R600_D1GRPH_SWAP_ENDIAN_32BIT;
+#endif
+ break;
default:
DRM_ERROR("Unsupported screen format %s\n",
drm_get_format_name(target_fb->format->format,
_name));
diff --git a/drivers/gpu/drm/radeon/r600_reg.h
b/drivers/gpu/drm/radeon/r600_reg.h
index 3ef202629e7e..85e85ac3ba4d 100644
--- a/drivers/gpu/drm/radeon/r600_reg.h
+++ b/drivers/gpu/drm/radeon/r600_reg.h
@@ -87,11 +87,32 @@
#define R600_MEDIUM_VID_LOWER_GPIO_CNTL0x720
#define R600_LOW_VID_LOWER_GPIO_CNTL 0x724
-#define R600_D1GRPH_SWAP_CONTROL 0x610C
-# define R600_D1GRPH_SWAP_ENDIAN_NONE(0 << 0)
-# define R600_D1GRPH_SWAP_ENDIAN_16BIT (1 << 0)
-# define R600_D1GRPH_SWAP_ENDIAN_32BIT (2 << 0)
-# define R600_D1GRPH_SWAP_ENDIAN_64BIT (3 << 0)
+#define R600_D1GRPH_SWAP_CONTROL 0x610C
+# define R600_D1GRPH_ENDIAN_SWAP(x)(((x) & 0x3) << 0)
+# define R600_D1GRPH_SWAP_ENDIAN_NONE 0
+# define R600_D1GRPH_SWAP_ENDIAN_16BIT 1
+# define R600_D1GRPH_SWAP_ENDIAN_32BIT 2
+# define R600_D1GRPH_SWAP_ENDIAN_64BIT 3
+# define R600_D1GRPH_RED_CROSSBAR(x) (((x) & 0x3) << 4)
+# define R600_D1GRPH_RED_SEL_R 0
+# define R600_D1GRPH_RED_SEL_G 1
+# define R600_D1GRPH_RED_SEL_B 2
+# define R600_D1GRPH_RED_SEL_A 3
+# define R600_D1GRPH_GREEN_CROSSBAR(x) (((x) & 0x3) << 6)
+# define R600_D1GRPH_GREEN_SEL_G 0
+# define R600_D1GRPH_GREEN_SEL_B 1
+# define R600_D1GRPH_GREEN_SEL_A 2
+# define R600_D1GRPH_GREEN_SEL_R 3
+# define R600_D1GRPH_BLUE_CROSSBAR(x) (((x) & 0x3) << 8)
+# define R600_D1GRPH_BLUE_SEL_B0
+# define R600_D1GRPH_BLUE_SEL_A1
+# define R600_D1GRPH_BLUE_SEL_R2
+# define R600_D1GRPH_BLUE_SEL_G3
+# define R600_D1GRPH
[PATCH v3 2/3] drm/amdgpu: enable ABGR and XBGR formats (v2)
Add support for DRM_FORMAT_{A,X}BGR in amdgpu with amd dc disabled
(v2) Crossbar registers are defined and used to swap red and blue channels,
keeping the existing coding style in each of the dce modules.
After setting crossbar bits in fb_swap, use bitwise OR for big endian
where required in DCE6 and DCE8 which do not rely on REG_SET_FIELD()
Signed-off-by: Mauro Rossi
---
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 11 +++
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 11 +++
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 10 ++
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 10 ++
drivers/gpu/drm/amd/amdgpu/si_enums.h | 20
drivers/gpu/drm/amd/amdgpu/sid.h | 20
6 files changed, 82 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index ada241bfeee9..82290759837c 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -1941,6 +1941,17 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc
*crtc,
/* Greater 8 bpc fb needs to bypass hw-lut to retain precision
*/
bypass_lut = true;
break;
+ case DRM_FORMAT_XBGR:
+ case DRM_FORMAT_ABGR:
+ fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
+ fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT,
0);
+ fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL,
GRPH_RED_CROSSBAR, 2);
+ fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL,
GRPH_BLUE_CROSSBAR, 2);
+#ifdef __BIG_ENDIAN
+ fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL,
GRPH_ENDIAN_SWAP,
+ ENDIAN_8IN32);
+#endif
+ break;
default:
DRM_ERROR("Unsupported screen format %s\n",
drm_get_format_name(target_fb->format->format,
_name));
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index a5b96eac3033..88a5336cb4a4 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -1983,6 +1983,17 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc
*crtc,
/* Greater 8 bpc fb needs to bypass hw-lut to retain precision
*/
bypass_lut = true;
break;
+ case DRM_FORMAT_XBGR:
+ case DRM_FORMAT_ABGR:
+ fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
+ fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT,
0);
+ fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL,
GRPH_RED_CROSSBAR, 2);
+ fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL,
GRPH_BLUE_CROSSBAR, 2);
+#ifdef __BIG_ENDIAN
+ fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL,
GRPH_ENDIAN_SWAP,
+ ENDIAN_8IN32);
+#endif
+ break;
default:
DRM_ERROR("Unsupported screen format %s\n",
drm_get_format_name(target_fb->format->format,
_name));
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index 394cc1e8fe20..df205de5a3b7 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -1888,6 +1888,16 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc
*crtc,
/* Greater 8 bpc fb needs to bypass hw-lut to retain precision
*/
bypass_lut = true;
break;
+ case DRM_FORMAT_XBGR:
+ case DRM_FORMAT_ABGR:
+ fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) |
+GRPH_FORMAT(GRPH_FORMAT_ARGB));
+ fb_swap = (GRPH_RED_CROSSBAR(GRPH_RED_SEL_B) |
+ GRPH_BLUE_CROSSBAR(GRPH_BLUE_SEL_R));
+#ifdef __BIG_ENDIAN
+ fb_swap |= GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32);
+#endif
+ break;
default:
DRM_ERROR("Unsupported screen format %s\n",
drm_get_format_name(target_fb->format->format,
_name));
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index c9b9ab8f1b05..7dbec90fe402 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -1865,6 +1865,16 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc
*crtc,
/* Greater 8 bpc fb needs to bypass hw-lut to retain precision
*/
bypass_lut = true;
break;
+ case DRM_FORMAT_XBGR:
+ case DRM_FORMAT_ABGR:
+ fb_format = ((GRPH_DEPTH_32BPP <<
GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
+(GRPH_FORMAT_ARGB <<
GRPH_CONTROL__GRPH
[PATCH v3 1/3] drm/amd/display: enable ABGR and XBGR formats (v4)
SURFACE_PIXEL_FORMAT_GRPH_ABGR is supported in amd/display/dc/dc_hw_types.h
and the necessary crossbars register controls to swap red and blue channels
are already implemented in drm/amd/display/dc/dce/dce_mem_input.c
(v4) Logic to handle new formats is added only in amdgpu_dm module.
Signed-off-by: Mauro Rossi
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 770c6b24be0b..4f689f47d7c3 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1892,6 +1892,10 @@ static int fill_plane_attributes_from_fb(struct
amdgpu_device *adev,
case DRM_FORMAT_ABGR2101010:
plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
break;
+ case DRM_FORMAT_XBGR:
+ case DRM_FORMAT_ABGR:
+ plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR;
+ break;
case DRM_FORMAT_NV21:
plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
break;
@@ -3190,6 +3194,8 @@ static const uint32_t rgb_formats[] = {
DRM_FORMAT_XBGR2101010,
DRM_FORMAT_ARGB2101010,
DRM_FORMAT_ABGR2101010,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_ABGR,
};
static const uint32_t yuv_formats[] = {
--
2.17.1
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[PATCH v3] drm/radeon,amdgpu,dc: enable ABGR and XBGR formats
Sending PATCH v3 series for support of {A,X}RGB pixel formats
in DCE1/R5xx and later, with separated patches for amd dc,
amdgpu and radeon, based on Alexander Deucher comments
Tested and working on R5xx (X1300), R6xx (HD2400), R7xx (HD4830),
Juniper (HD5770), Turks (HD7600M), Tahiti (HD7950),
Bonaire (HD7790), Tonga (R9 380), Polaris (RX560) and Vega RX
Legacy radeon crtc was left unchanged, because R3xx/R4xx chipsets
do not support {A,X}BGR_ pixel formats natively,
moreover the legacy code path is still based on KMS API
[PATCH v3 1/3] drm/amd/display: enable ABGR and XBGR formats (v4)
[PATCH v3 2/3] drm/amdgpu: enable ABGR and XBGR formats (v2)
[PATCH v3 3/3] drm/radeon: enable ABGR and XBGR formats (v2)
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Re: [PATCH] RFC: drm/amd/display: enable ABGR and XBGR formats (v2)
Hi Alex,
Il giorno mar 17 lug 2018 alle ore 15:43 Alex Deucher
ha scritto:
> On Sun, Jul 15, 2018 at 10:03 PM, Mauro Rossi
> wrote:
> > From: Mauro Rossi
> >
> > (v1) {A,X}BGR code paths are added in amdgpu_dm, by using an
> fb_format
> > already listed in dc/dc_hw_types.h
> (SURFACE_PIXEL_FORMAT_GRPH_ABGR),
> > and in dce 8.0, 10.0 and 11.0, i.e. Bonaire and later.
> > GRPH_FORMAT_ARGB is used due to lack of specific
> GRPH_FORMAT_ABGR
> >
> > (v2) support for {A,X}BGR in atombios_crtc (now in dce4 path, to be
> refined)
> > to initialize frame buffer device and avoid following dmesg error:
> > "[drm] Cannot find any crtc or sizes"
> >
> > Tested with oreo-x86 (hwcomposer.drm + gralloc.gbm + mesa-dev/radv)
> > SurfaceFlinger can now select RGBA_ format for HWC_FRAMEBUFFER_TARGET
> > No major regression or crash observed so far, but some android 2D overlay
> > may be affected by color artifacts. Kind feedback requested.
> >
> > Signed-off-by: Mauro Rossi
>
> Please split the patch in three (one for radeon and one for amdgpu dc
> and one for amdgpu non-dc). Also the GRPH_SWAP_CONTROL register has a
> crossbar where you can change the channel routing. You may need that
> for the channel routing to work correctly.
>
> Alex
>
Thanks for your suggestion and guidance! :-)
I may need some time to assimilate the suggestions and some confirmations,
as I am an amateur in AMD GPU coding, to be honest, I should have mentioned
that before.
Regarding the radeon scope of changes,
do you recommend to keep the enablement of {A,X}BGR for dce4 and later,
or to extend the enablement of {A,X}BGR to older families of radeon
gpus/chipsets?
What is the lower radeon family where {A,X}BGR can be natively
supported by HW,
by means of swap control registers for channel routing configuration?
Based on the scope of {A,X}BGR support in final patches,
I may need to add handling in other dce code and maybe other modules,
could you please provide information in terms of necessary changes/high
level steps to follow?
Do you have some pointer to documentation on swap control registers for
the families
that may be considered as 'safe to be kept in scope' for {A,X}BGR
support?
Last but not least I would like to ask you about how to test no-regression,
even if this will come later,
when patches will be in good shape for further evaluation, do you have
tools and samples for conformance/no-regression testing?
I am asking because I don't have samples for all families.
Kind regards
Mauro
>
>
> > ---
> > drivers/gpu/drm/amd/amdgpu/dce_v10_0.c| 9 +
> > drivers/gpu/drm/amd/amdgpu/dce_v11_0.c| 9 +
> > drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 8
> > drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 ++
> > drivers/gpu/drm/radeon/atombios_crtc.c| 8
> > 5 files changed, 40 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> > index 022f303463fc..d4280d2e7737 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> > @@ -2005,6 +2005,15 @@ static int dce_v10_0_crtc_do_set_base(struct
> drm_crtc *crtc,
> > /* Greater 8 bpc fb needs to bypass hw-lut to retain
> precision */
> > bypass_lut = true;
> > break;
> > + case DRM_FORMAT_XBGR:
> > + case DRM_FORMAT_ABGR:
> > + fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH,
> 2);
> > + fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL,
> GRPH_FORMAT, 0); /* Hack */
> > +#ifdef __BIG_ENDIAN
> > + fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL,
> GRPH_ENDIAN_SWAP,
> > + ENDIAN_8IN32);
> > +#endif
> > + break;
> > default:
> > DRM_ERROR("Unsupported screen format %s\n",
> > drm_get_format_name(target_fb->format->format,
> _name));
> > diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> > index 800a9f36ab4f..d48ee8f2e192 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> > @@ -2044,6 +2044,15 @@ static int dce_v11_0_crtc_do_set_base(struct
> drm_crtc *crtc,
> > /* Greater 8 bpc fb needs to bypass hw-lut to retain
> precision */
> >
[PATCH] RFC: drm/amd/display: enable ABGR and XBGR formats (v2)
From: Mauro Rossi
(v1) {A,X}BGR code paths are added in amdgpu_dm, by using an fb_format
already listed in dc/dc_hw_types.h (SURFACE_PIXEL_FORMAT_GRPH_ABGR),
and in dce 8.0, 10.0 and 11.0, i.e. Bonaire and later.
GRPH_FORMAT_ARGB is used due to lack of specific GRPH_FORMAT_ABGR
(v2) support for {A,X}BGR in atombios_crtc (now in dce4 path, to be refined)
to initialize frame buffer device and avoid following dmesg error:
"[drm] Cannot find any crtc or sizes"
Tested with oreo-x86 (hwcomposer.drm + gralloc.gbm + mesa-dev/radv)
SurfaceFlinger can now select RGBA_ format for HWC_FRAMEBUFFER_TARGET
No major regression or crash observed so far, but some android 2D overlay
may be affected by color artifacts. Kind feedback requested.
Signed-off-by: Mauro Rossi
---
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c| 9 +
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c| 9 +
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 8
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 ++
drivers/gpu/drm/radeon/atombios_crtc.c| 8
5 files changed, 40 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index 022f303463fc..d4280d2e7737 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -2005,6 +2005,15 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc
*crtc,
/* Greater 8 bpc fb needs to bypass hw-lut to retain precision
*/
bypass_lut = true;
break;
+ case DRM_FORMAT_XBGR:
+ case DRM_FORMAT_ABGR:
+ fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
+ fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT,
0); /* Hack */
+#ifdef __BIG_ENDIAN
+ fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL,
GRPH_ENDIAN_SWAP,
+ ENDIAN_8IN32);
+#endif
+ break;
default:
DRM_ERROR("Unsupported screen format %s\n",
drm_get_format_name(target_fb->format->format,
_name));
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index 800a9f36ab4f..d48ee8f2e192 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -2044,6 +2044,15 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc
*crtc,
/* Greater 8 bpc fb needs to bypass hw-lut to retain precision
*/
bypass_lut = true;
break;
+ case DRM_FORMAT_XBGR:
+ case DRM_FORMAT_ABGR:
+ fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
+ fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT,
0); /* Hack */
+#ifdef __BIG_ENDIAN
+ fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL,
GRPH_ENDIAN_SWAP,
+ ENDIAN_8IN32);
+#endif
+ break;
default:
DRM_ERROR("Unsupported screen format %s\n",
drm_get_format_name(target_fb->format->format,
_name));
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index 012e0a9ae0ff..0e2fc1ac475f 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -1929,6 +1929,14 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc
*crtc,
/* Greater 8 bpc fb needs to bypass hw-lut to retain precision
*/
bypass_lut = true;
break;
+ case DRM_FORMAT_XBGR:
+ case DRM_FORMAT_ABGR:
+ fb_format = ((GRPH_DEPTH_32BPP <<
GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
+(GRPH_FORMAT_ARGB <<
GRPH_CONTROL__GRPH_FORMAT__SHIFT)); /* Hack */
+#ifdef __BIG_ENDIAN
+ fb_swap = (GRPH_ENDIAN_8IN32 <<
GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
+#endif
+ break;
default:
DRM_ERROR("Unsupported screen format %s\n",
drm_get_format_name(target_fb->format->format,
_name));
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 63c67346d316..6c10fa291150 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1824,6 +1824,10 @@ static int fill_plane_attributes_from_fb(struct
amdgpu_device *adev,
case DRM_FORMAT_ABGR2101010:
plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
break;
+ case DRM_FORMAT_XBGR:
+ case DRM_FORMAT_ABGR:
+ plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR;
+
[PATCH 09/10] drm/amdgpu: enable DC support for SI parts
This commit enables DC support and Display Manager IP block
conditionally to CONFIG_DRM_AMD_DC_SI kernel configuration
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 +++
drivers/gpu/drm/amd/amdgpu/si.c| 14 ++
2 files changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 43c030459af7..f479f7274412 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2250,6 +2250,13 @@ bool amdgpu_device_asic_has_dc_support(enum
amd_asic_type asic_type)
{
switch (asic_type) {
#if defined(CONFIG_DRM_AMD_DC)
+#if defined(CONFIG_DRM_AMD_DC_SI)
+ case CHIP_TAHITI:
+ case CHIP_PITCAIRN:
+ case CHIP_VERDE:
+ case CHIP_OLAND:
+ case CHIP_HAINAN:
+#endif
case CHIP_BONAIRE:
case CHIP_HAWAII:
case CHIP_KAVERI:
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index c364ef94cc36..f898f548140c 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -48,6 +48,8 @@
#include "uvd/uvd_4_0_d.h"
#include "bif/bif_3_0_d.h"
+#include "amdgpu_dm.h"
+
static const u32 tahiti_golden_registers[] =
{
mmAZALIA_SCLK_CONTROL, 0x0030, 0x0011,
@@ -2060,6 +2062,10 @@ int si_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, _smu_ip_block);
if (adev->enable_virtual_display)
amdgpu_device_ip_block_add(adev, _virtual_ip_block);
+#if defined(CONFIG_DRM_AMD_DC) && defined(CONFIG_DRM_AMD_DC_SI)
+ else if (amdgpu_device_has_dc_support(adev))
+ amdgpu_device_ip_block_add(adev, _ip_block);
+#endif
else
amdgpu_device_ip_block_add(adev, _v6_0_ip_block);
amdgpu_device_ip_block_add(adev, _v6_0_ip_block);
@@ -2074,6 +2080,10 @@ int si_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, _smu_ip_block);
if (adev->enable_virtual_display)
amdgpu_device_ip_block_add(adev, _virtual_ip_block);
+#if defined(CONFIG_DRM_AMD_DC) && defined(CONFIG_DRM_AMD_DC_SI)
+ else if (amdgpu_device_has_dc_support(adev))
+ amdgpu_device_ip_block_add(adev, _ip_block);
+#endif
else
amdgpu_device_ip_block_add(adev, _v6_4_ip_block);
amdgpu_device_ip_block_add(adev, _v6_0_ip_block);
@@ -2088,6 +2098,10 @@ int si_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, _smu_ip_block);
if (adev->enable_virtual_display)
amdgpu_device_ip_block_add(adev, _virtual_ip_block);
+#if defined(CONFIG_DRM_AMD_DC) && defined(CONFIG_DRM_AMD_DC_SI)
+ else if (amdgpu_device_has_dc_support(adev))
+ amdgpu_device_ip_block_add(adev, _ip_block);
+#endif
amdgpu_device_ip_block_add(adev, _v6_0_ip_block);
amdgpu_device_ip_block_add(adev, _dma_ip_block);
break;
--
2.17.1
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[PATCH 08/10] drm/amd/display: amdgpu_dm: add SI support
This commit adds Display Manager early initialization for SI parts
conditionally to CONFIG_DRM_AMD_DC_SI kernel configuration
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 26 +++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index ef02d26f7151..e776ac33a857 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1638,6 +1638,13 @@ static int amdgpu_dm_initialize_drm_device(struct
amdgpu_device *adev)
/* Software is initialized. Now we can register interrupt handlers. */
switch (adev->asic_type) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+ case CHIP_TAHITI:
+ case CHIP_PITCAIRN:
+ case CHIP_VERDE:
+ case CHIP_OLAND:
+ case CHIP_HAINAN:
+#endif
case CHIP_BONAIRE:
case CHIP_HAWAII:
case CHIP_KAVERI:
@@ -1782,6 +1789,23 @@ static int dm_early_init(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
switch (adev->asic_type) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+ case CHIP_TAHITI:
+ case CHIP_PITCAIRN:
+ case CHIP_VERDE:
+ case CHIP_HAINAN:
+ adev->mode_info.num_crtc = 6;
+ adev->mode_info.num_hpd = 6;
+ adev->mode_info.num_dig = 6;
+ adev->mode_info.plane_type = dm_plane_type_default;
+ break;
+ case CHIP_OLAND:
+ adev->mode_info.num_crtc = 2;
+ adev->mode_info.num_hpd = 2;
+ adev->mode_info.num_dig = 2;
+ adev->mode_info.plane_type = dm_plane_type_default;
+ break;
+#endif
case CHIP_BONAIRE:
case CHIP_HAWAII:
adev->mode_info.num_crtc = 6;
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 04/10] drm/amd/display: dc/bios: add support for DCE6
DCE6 targets are added replicating existing DCE8 implementation.
---
drivers/gpu/drm/amd/display/dc/bios/Makefile | 9 +
.../display/dc/bios/command_table_helper.c| 8 +
.../display/dc/bios/command_table_helper.h| 3 +
.../display/dc/bios/command_table_helper2.c | 8 +
.../display/dc/bios/command_table_helper2.h | 3 +
.../bios/dce60/command_table_helper_dce60.c | 354 ++
.../bios/dce60/command_table_helper_dce60.h | 33 ++
7 files changed, 418 insertions(+)
create mode 100644
drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c
create mode 100644
drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.h
diff --git a/drivers/gpu/drm/amd/display/dc/bios/Makefile
b/drivers/gpu/drm/amd/display/dc/bios/Makefile
index 239e86bbec5a..ed6b5e9763f6 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/bios/Makefile
@@ -31,6 +31,15 @@ AMD_DAL_BIOS = $(addprefix $(AMDDALPATH)/dc/bios/,$(BIOS))
AMD_DISPLAY_FILES += $(AMD_DAL_BIOS)
+###
+# DCE 6x
+###
+# All DCE6.x are derived from DCE6.0, so 6.0 MUST be defined if ANY of
+# DCE6.x is compiled.
+ifdef CONFIG_DRM_AMD_DC_SI
+AMD_DISPLAY_FILES += $(AMDDALPATH)/dc/bios/dce60/command_table_helper_dce60.o
+endif
+
###
# DCE 8x
###
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
index 253bbb1eea60..48b4ef03fc8f 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
@@ -36,6 +36,14 @@ bool dal_bios_parser_init_cmd_tbl_helper(
enum dce_version dce)
{
switch (dce) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+ case DCE_VERSION_6_0:
+ case DCE_VERSION_6_1:
+ case DCE_VERSION_6_4:
+ *h = dal_cmd_tbl_helper_dce60_get_table();
+ return true;
+#endif
+
case DCE_VERSION_8_0:
case DCE_VERSION_8_1:
case DCE_VERSION_8_3:
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h
b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h
index 4c3789df253d..dfd30aaf4032 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h
@@ -26,6 +26,9 @@
#ifndef __DAL_COMMAND_TABLE_HELPER_H__
#define __DAL_COMMAND_TABLE_HELPER_H__
+#if defined(CONFIG_DRM_AMD_DC_SI)
+#include "dce60/command_table_helper_dce60.h"
+#endif
#include "dce80/command_table_helper_dce80.h"
#include "dce110/command_table_helper_dce110.h"
#include "dce112/command_table_helper_dce112.h"
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
index bbbcef566c55..dad302564da4 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
@@ -37,6 +37,14 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
enum dce_version dce)
{
switch (dce) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+ case DCE_VERSION_6_0:
+ case DCE_VERSION_6_1:
+ case DCE_VERSION_6_4:
+ *h = dal_cmd_tbl_helper_dce60_get_table();
+ return true;
+#endif
+
case DCE_VERSION_8_0:
case DCE_VERSION_8_1:
case DCE_VERSION_8_3:
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h
b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h
index 785fcb20a1b9..66e0a3e73768 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h
@@ -26,6 +26,9 @@
#ifndef __DAL_COMMAND_TABLE_HELPER2_H__
#define __DAL_COMMAND_TABLE_HELPER2_H__
+#if defined(CONFIG_DRM_AMD_DC_SI)
+#include "dce60/command_table_helper_dce60.h"
+#endif
#include "dce80/command_table_helper_dce80.h"
#include "dce110/command_table_helper_dce110.h"
#include "dce112/command_table_helper2_dce112.h"
diff --git
a/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c
b/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c
new file mode 100644
index ..552778ce9835
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c
@@ -0,0 +1,354 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the
[PATCH 07/10] drm/amd/display: dc/irq: add support for DCE6
DCE6 targets are added replicating existing DCE8 implementation.
NOTE: due to missing CRTC_VERTICAL_INTERRUPT0_CONTROL registers/masks,
dce/dce_8_0_{d,sh_mask}.h headers were used instead of dce/dce_6_0_{d,sh_mask}.h
but only as exception in dce/irq_service_dce60.c
IMPORTANT: Coding of dce/irq_service_dce60.c requires review to understand
if dce_6_0_{d,sh_mask}.h should be updated with macros/registers/masks
---
drivers/gpu/drm/amd/display/dc/irq/Makefile | 11 +
.../display/dc/irq/dce60/irq_service_dce60.c | 303 ++
.../display/dc/irq/dce60/irq_service_dce60.h | 35 ++
.../gpu/drm/amd/display/dc/irq/irq_service.c | 3 +
4 files changed, 352 insertions(+)
create mode 100644 drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
create mode 100644 drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.h
diff --git a/drivers/gpu/drm/amd/display/dc/irq/Makefile
b/drivers/gpu/drm/amd/display/dc/irq/Makefile
index 498515aad4a5..e38b6d8d614d 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/irq/Makefile
@@ -30,6 +30,17 @@ AMD_DAL_IRQ = $(addprefix $(AMDDALPATH)/dc/irq/,$(IRQ))
AMD_DISPLAY_FILES += $(AMD_DAL_IRQ)
+###
+# DCE 6x
+###
+ifdef CONFIG_DRM_AMD_DC_SI
+IRQ_DCE60 = irq_service_dce60.o
+
+AMD_DAL_IRQ_DCE60 = $(addprefix $(AMDDALPATH)/dc/irq/dce60/,$(IRQ_DCE60))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCE60)
+endif
+
###
# DCE 8x
###
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
b/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
new file mode 100644
index ..107e0dcb5f80
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
@@ -0,0 +1,303 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+
+#include "include/logger_interface.h"
+
+#include "irq_service_dce60.h"
+#include "../dce110/irq_service_dce110.h"
+
+#include "dce/dce_8_0_d.h"
+#include "dce/dce_8_0_sh_mask.h"
+
+#include "ivsrcid/ivsrcid_vislands30.h"
+
+#include "dc_types.h"
+
+static bool hpd_ack(
+ struct irq_service *irq_service,
+ const struct irq_source_info *info)
+{
+ uint32_t addr = info->status_reg;
+ uint32_t value = dm_read_reg(irq_service->ctx, addr);
+ uint32_t current_status =
+ get_reg_field_value(
+ value,
+ DC_HPD1_INT_STATUS,
+ DC_HPD1_SENSE_DELAYED);
+
+ dal_irq_service_ack_generic(irq_service, info);
+
+ value = dm_read_reg(irq_service->ctx, info->enable_reg);
+
+ set_reg_field_value(
+ value,
+ current_status ? 0 : 1,
+ DC_HPD1_INT_CONTROL,
+ DC_HPD1_INT_POLARITY);
+
+ dm_write_reg(irq_service->ctx, info->enable_reg, value);
+
+ return true;
+}
+
+static const struct irq_source_info_funcs hpd_irq_info_funcs = {
+ .set = NULL,
+ .ack = hpd_ack
+};
+
+static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
+ .set = NULL,
+ .ack = NULL
+};
+
+static const struct irq_source_info_funcs pflip_irq_info_funcs = {
+ .set = NULL,
+ .ack = NULL
+};
+
+static const struct irq_source_info_funcs vblank_irq_info_funcs = {
+ .set = dce110_vblank_set,
+ .ack = NULL
+};
+
+
+#define hpd_int_entry(reg_num)\
+ [DC_IRQ_SOURCE_INVALID + reg_num] = {\
+ .enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
+ .enable_mask =
[PATCH 05/10] drm/amd/display: dc/gpio: add support for DCE6
DCE6 targets are added replicating existing DCE8 implementation.
---
drivers/gpu/drm/amd/display/dc/gpio/Makefile | 12 +
.../display/dc/gpio/dce60/hw_factory_dce60.c | 174
.../display/dc/gpio/dce60/hw_factory_dce60.h | 32 ++
.../dc/gpio/dce60/hw_translate_dce60.c| 411 ++
.../dc/gpio/dce60/hw_translate_dce60.h| 32 ++
.../gpu/drm/amd/display/dc/gpio/hw_factory.c | 10 +
.../drm/amd/display/dc/gpio/hw_translate.c| 10 +
7 files changed, 681 insertions(+)
create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.c
create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.h
create mode 100644
drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c
create mode 100644
drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.h
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/Makefile
b/drivers/gpu/drm/amd/display/dc/gpio/Makefile
index 562ee189d780..122ca9991100 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/gpio/Makefile
@@ -30,6 +30,18 @@ AMD_DAL_GPIO = $(addprefix $(AMDDALPATH)/dc/gpio/,$(GPIO))
AMD_DISPLAY_FILES += $(AMD_DAL_GPIO)
+###
+# DCE 6x
+###
+# all DCE6.x are derived from DCE6.0
+ifdef CONFIG_DRM_AMD_DC_SI
+GPIO_DCE60 = hw_translate_dce60.o hw_factory_dce60.o
+
+AMD_DAL_GPIO_DCE60 = $(addprefix $(AMDDALPATH)/dc/gpio/dce60/,$(GPIO_DCE60))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCE60)
+endif
+
###
# DCE 8x
###
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.c
b/drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.c
new file mode 100644
index ..64afe9b48c5f
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.c
@@ -0,0 +1,174 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ * Copyright 2018 Mauro Rossi
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+#include "include/gpio_types.h"
+#include "../hw_factory.h"
+
+#include "hw_factory_dce60.h"
+
+#include "../hw_gpio.h"
+#include "../hw_ddc.h"
+#include "../hw_hpd.h"
+
+#include "dce/dce_6_0_d.h"
+#include "dce/dce_6_0_sh_mask.h"
+
+#define REG(reg_name)\
+ mm ## reg_name
+
+#include "reg_helper.h"
+#include "../hpd_regs.h"
+
+#define HPD_REG_LIST_DCE6(id) \
+ HPD_GPIO_REG_LIST(id), \
+ .int_status = mmDC_HPD ## id ## _INT_STATUS,\
+ .toggle_filt_cntl = mmDC_HPD ## id ## _TOGGLE_FILT_CNTL
+
+#define HPD_MASK_SH_LIST_DCE6(mask_sh) \
+ .DC_HPD_SENSE_DELAYED =
DC_HPD1_INT_STATUS__DC_HPD1_SENSE_DELAYED ## mask_sh,\
+ .DC_HPD_SENSE = DC_HPD1_INT_STATUS__DC_HPD1_SENSE ## mask_sh,\
+ .DC_HPD_CONNECT_INT_DELAY =
DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_CONNECT_INT_DELAY ## mask_sh,\
+ .DC_HPD_DISCONNECT_INT_DELAY =
DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_DISCONNECT_INT_DELAY ## mask_sh
+
+#define hpd_regs(id) \
+{\
+ HPD_REG_LIST_DCE6(id)\
+}
+
+static const struct hpd_registers hpd_regs[] = {
+ hpd_regs(1),
+ hpd_regs(2),
+ hpd_regs(3),
+ hpd_regs(4),
+ hpd_regs(5),
+ hpd_regs(6)
+};
+
+static const struct hpd_sh_mask hpd_shift = {
+ HPD_MASK_SH_LIST_DCE6(__SHIFT)
+};
+
+static const struct hpd_sh_mask hpd_mask = {
+ HPD_MASK_SH_LIST_DCE6(_MASK)
+};
+
+#include "../ddc_regs.h"
+
+ /* set field name */
+#define SF_DDC(reg_na
[PATCH 02/10] drm/amd/display: dc/dce: add DCE6 support
DCE6 targets are added replicating existing DCE8 implementation.
NOTE: dce_8_0_{d,sh_mask}.h headers used instead of dce_6_0_{d,sh_mask}.h
only to build dce60_resource.c due to missing *_DCE60 macros/registers/masks
IMPORTANT: Coding of dce60_resource.c requires review to understand
if dce_6_0_{d,sh_mask}.h should be updated with macros/registers/masks
---
drivers/gpu/drm/amd/display/dc/Makefile |4 +
.../drm/amd/display/dc/dce/dce_clock_source.c | 15 +
drivers/gpu/drm/amd/display/dc/dce60/Makefile | 34 +
.../amd/display/dc/dce60/dce60_hw_sequencer.c | 81 +
.../amd/display/dc/dce60/dce60_hw_sequencer.h | 36 +
.../drm/amd/display/dc/dce60/dce60_resource.c | 1348 +
.../drm/amd/display/dc/dce60/dce60_resource.h | 47 +
.../display/dc/dce60/dce60_timing_generator.c | 242 +++
.../display/dc/dce60/dce60_timing_generator.h | 39 +
.../include/asic_reg/dce/dce_6_0_sh_mask.h|4 +
10 files changed, 1850 insertions(+)
create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/Makefile
create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.h
create mode 100644
drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c
create mode 100644
drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.h
diff --git a/drivers/gpu/drm/amd/display/dc/Makefile
b/drivers/gpu/drm/amd/display/dc/Makefile
index aed538a4d1ba..d5d5acd57559 100644
--- a/drivers/gpu/drm/amd/display/dc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/Makefile
@@ -36,6 +36,10 @@ DC_LIBS += dce110
DC_LIBS += dce100
DC_LIBS += dce80
+ifdef CONFIG_DRM_AMD_DC_SI
+DC_LIBS += dce60
+endif
+
AMD_DC = $(addsuffix /Makefile, $(addprefix
$(FULL_AMD_DISPLAY_PATH)/dc/,$(DC_LIBS)))
include $(AMD_DC)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
index ca137757a69e..d96c977e451b 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -580,6 +580,11 @@ static uint32_t dce110_get_pix_clk_dividers(
}
switch (cs->ctx->dce_version) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+ case DCE_VERSION_6_0:
+ case DCE_VERSION_6_1:
+ case DCE_VERSION_6_4:
+#endif
case DCE_VERSION_8_0:
case DCE_VERSION_8_1:
case DCE_VERSION_8_3:
@@ -941,6 +946,11 @@ static bool dce110_program_pix_clk(
bp_pc_params.signal_type = pix_clk_params->signal_type;
switch (clock_source->ctx->dce_version) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+ case DCE_VERSION_6_0:
+ case DCE_VERSION_6_1:
+ case DCE_VERSION_6_4:
+#endif
case DCE_VERSION_8_0:
case DCE_VERSION_8_1:
case DCE_VERSION_8_3:
@@ -1296,6 +1306,11 @@ bool dce110_clk_src_construct(
fw_info.external_clock_source_frequency_for_dp;
switch (clk_src->base.ctx->dce_version) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+ case DCE_VERSION_6_0:
+ case DCE_VERSION_6_1:
+ case DCE_VERSION_6_4:
+#endif
case DCE_VERSION_8_0:
case DCE_VERSION_8_1:
case DCE_VERSION_8_3:
diff --git a/drivers/gpu/drm/amd/display/dc/dce60/Makefile
b/drivers/gpu/drm/amd/display/dc/dce60/Makefile
new file mode 100644
index ..39afd7c59a7c
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dce60/Makefile
@@ -0,0 +1,34 @@
+#
+# Copyright 2017 Advanced Micro Devices, Inc.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+# OTHER DEALINGS IN THE SOFTWARE.
+#
+#
+# Makefile for the 'controller' sub-component of DAL.
+# It provides the control and status of HW CRTC block.
+
+DCE60 = dce60_timing_generator.o dce60_hw_sequencer.o \
+ dce60_resource.o
+
+AMD_DAL_DCE60 =
[PATCH 03/10] drm/amd/display: dc/core: add DCE6 support
DCE6 targets are added as branching of existing DCE8 implementation.
---
.../gpu/drm/amd/display/dc/core/dc_resource.c | 29 +++
1 file changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index ea6beccfd89d..16568e79d4b5 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -37,6 +37,9 @@
#include "virtual/virtual_stream_encoder.h"
#include "dpcd_defs.h"
+#if defined(CONFIG_DRM_AMD_DC_SI)
+#include "dce60/dce60_resource.h"
+#endif
#include "dce80/dce80_resource.h"
#include "dce100/dce100_resource.h"
#include "dce110/dce110_resource.h"
@@ -53,6 +56,18 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id
asic_id)
enum dce_version dc_version = DCE_VERSION_UNKNOWN;
switch (asic_id.chip_family) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+ case FAMILY_SI:
+ if (ASIC_REV_IS_TAHITI_P(asic_id.hw_internal_rev) ||
+ ASIC_REV_IS_PITCAIRN_PM(asic_id.hw_internal_rev) ||
+ ASIC_REV_IS_CAPEVERDE_M(asic_id.hw_internal_rev))
+ dc_version = DCE_VERSION_6_0;
+ else if (ASIC_REV_IS_OLAND_M(asic_id.hw_internal_rev))
+ dc_version = DCE_VERSION_6_4;
+ else
+ dc_version = DCE_VERSION_6_1;
+ break;
+#endif
case FAMILY_CI:
dc_version = DCE_VERSION_8_0;
break;
@@ -106,6 +121,20 @@ struct resource_pool *dc_create_resource_pool(
struct resource_pool *res_pool = NULL;
switch (dc_version) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+ case DCE_VERSION_6_0:
+ res_pool = dce60_create_resource_pool(
+ num_virtual_links, dc);
+ break;
+ case DCE_VERSION_6_1:
+ res_pool = dce61_create_resource_pool(
+ num_virtual_links, dc);
+ break;
+ case DCE_VERSION_6_4:
+ res_pool = dce64_create_resource_pool(
+ num_virtual_links, dc);
+ break;
+#endif
case DCE_VERSION_8_0:
res_pool = dce80_create_resource_pool(
num_virtual_links, dc);
--
2.17.1
___
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[PATCH 01/10] drm/amd/display: add asics info for SI parts
Asics info retrieved from si_id.h in https://github.com/GPUOpen-Tools/CodeXL
Tree path:
./CodeXL/Components/ShaderAnalyzer/AMDTBackEnd/Include/Common/asic_reg/si_id.h
---
.../gpu/drm/amd/display/include/dal_asic_id.h | 40 +++
.../gpu/drm/amd/display/include/dal_types.h | 3 ++
2 files changed, 43 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
index 25029ed42d89..adea98e0b4b6 100644
--- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
@@ -30,6 +30,34 @@
* ASIC internal revision ID
*/
+/* DCE60 (based on si_id.h in GPUOpen-Tools CodeXL) */
+#define SI_TAHITI_P_A00x01
+#define SI_TAHITI_P_B00x05
+#define SI_TAHITI_P_B10x06
+#define SI_PITCAIRN_PM_A0 0x14
+#define SI_PITCAIRN_PM_A1 0x15
+#define SI_CAPEVERDE_M_A0 0x28
+#define SI_CAPEVERDE_M_A1 0x29
+#define SI_OLAND_M_A0 0x3C
+#define SI_HAINAN_V_A00x46
+
+#define SI_UNKNOWN0xFF
+
+#define ASIC_REV_IS_TAHITI_P(rev) \
+ ((rev >= SI_TAHITI_P_A0) && (rev < SI_PITCAIRN_PM_A0))
+
+#define ASIC_REV_IS_PITCAIRN_PM(rev) \
+ ((rev >= SI_PITCAIRN_PM_A0) && (rev < SI_CAPEVERDE_M_A0))
+
+#define ASIC_REV_IS_CAPEVERDE_M(rev) \
+ ((rev >= SI_CAPEVERDE_M_A0) && (rev < SI_OLAND_M_A0))
+
+#define ASIC_REV_IS_OLAND_M(rev) \
+ ((rev >= SI_OLAND_M_A0) && (rev < SI_HAINAN_V_A0))
+
+#define ASIC_REV_IS_HAINAN_V(rev) \
+ ((rev >= SI_HAINAN_V_A0) && (rev < SI_UNKNOWN))
+
/* DCE80 (based on ci_id.h in Perforce) */
#defineCI_BONAIRE_M_A0 0x14
#defineCI_BONAIRE_M_A1 0x15
@@ -143,12 +171,24 @@
/*
* ASIC chip ID
*/
+
+/* DCE60 */
+#define DEVICE_ID_SI_TAHITI_P_6780 0x6780
+#define DEVICE_ID_SI_PITCAIRN_PM_6800 0x6800
+#define DEVICE_ID_SI_PITCAIRN_PM_6808 0x6808
+#define DEVICE_ID_SI_CAPEVERDE_M_6820 0x6820
+#define DEVICE_ID_SI_CAPEVERDE_M_6828 0x6828
+#define DEVICE_ID_SI_OLAND_M_6600 0x6600
+#define DEVICE_ID_SI_OLAND_M_6608 0x6608
+#define DEVICE_ID_SI_HAINAN_V_6660 0x6660
+
/* DCE80 */
#define DEVICE_ID_KALINDI_9834 0x9834
#define DEVICE_ID_TEMASH_9839 0x9839
#define DEVICE_ID_TEMASH_983D 0x983D
/* Asic Family IDs for different asic family. */
+#define FAMILY_SI 110 /* Southern Islands: Tahiti (P), Pitcairn (PM), Cape
Verde (M), Oland (M), Hainan (V) */
#define FAMILY_CI 120 /* Sea Islands: Hawaii (P), Bonaire (M) */
#define FAMILY_KV 125 /* Fusion => Kaveri: Spectre, Spooky; Kabini: Kalindi */
#define FAMILY_VI 130 /* Volcanic Islands: Iceland (V), Tonga (M) */
diff --git a/drivers/gpu/drm/amd/display/include/dal_types.h
b/drivers/gpu/drm/amd/display/include/dal_types.h
index 840142b65f8b..df1d3f9d8e14 100644
--- a/drivers/gpu/drm/amd/display/include/dal_types.h
+++ b/drivers/gpu/drm/amd/display/include/dal_types.h
@@ -34,6 +34,9 @@ struct dc_bios;
enum dce_version {
DCE_VERSION_UNKNOWN = (-1),
+ DCE_VERSION_6_0,
+ DCE_VERSION_6_1,
+ DCE_VERSION_6_4,
DCE_VERSION_8_0,
DCE_VERSION_8_1,
DCE_VERSION_8_3,
--
2.17.1
___
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[PATCH 06/10] drm/amd/display: dc/i2caux: add support for DCE6
DCE6 targets are added replicating existing DCE8 implementation.
---
.../gpu/drm/amd/display/dc/i2caux/Makefile| 12 +
.../dc/i2caux/dce60/i2c_hw_engine_dce60.c | 875 ++
.../dc/i2caux/dce60/i2c_hw_engine_dce60.h | 54 ++
.../dc/i2caux/dce60/i2c_sw_engine_dce60.c | 173
.../dc/i2caux/dce60/i2c_sw_engine_dce60.h | 43 +
.../display/dc/i2caux/dce60/i2caux_dce60.c| 284 ++
.../display/dc/i2caux/dce60/i2caux_dce60.h| 38 +
.../gpu/drm/amd/display/dc/i2caux/i2caux.c| 10 +
8 files changed, 1489 insertions(+)
create mode 100644
drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_hw_engine_dce60.c
create mode 100644
drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_hw_engine_dce60.h
create mode 100644
drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_sw_engine_dce60.c
create mode 100644
drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_sw_engine_dce60.h
create mode 100644 drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2caux_dce60.c
create mode 100644 drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2caux_dce60.h
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/Makefile
b/drivers/gpu/drm/amd/display/dc/i2caux/Makefile
index 352885cb4d07..80f58a357879 100644
--- a/drivers/gpu/drm/amd/display/dc/i2caux/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/Makefile
@@ -30,6 +30,18 @@ AMD_DAL_I2CAUX = $(addprefix
$(AMDDALPATH)/dc/i2caux/,$(I2CAUX))
AMD_DISPLAY_FILES += $(AMD_DAL_I2CAUX)
+###
+# DCE 6x family
+###
+ifdef CONFIG_DRM_AMD_DC_SI
+I2CAUX_DCE60 = i2caux_dce60.o i2c_hw_engine_dce60.o \
+ i2c_sw_engine_dce60.o
+
+AMD_DAL_I2CAUX_DCE60 = $(addprefix
$(AMDDALPATH)/dc/i2caux/dce60/,$(I2CAUX_DCE60))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_I2CAUX_DCE60)
+endif
+
###
# DCE 8x family
###
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_hw_engine_dce60.c
b/drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_hw_engine_dce60.c
new file mode 100644
index ..a945e00ce913
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_hw_engine_dce60.c
@@ -0,0 +1,875 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+
+/*
+ * Pre-requisites: headers required by header of this unit
+ */
+#include "include/i2caux_interface.h"
+#include "../engine.h"
+#include "../i2c_engine.h"
+#include "../i2c_hw_engine.h"
+#include "../i2c_generic_hw_engine.h"
+/*
+ * Header of this unit
+ */
+
+#include "i2c_hw_engine_dce60.h"
+
+/*
+ * Post-requisites: headers required by this unit
+ */
+
+#include "dce/dce_6_0_d.h"
+#include "dce/dce_6_0_sh_mask.h"
+/*
+ * This unit
+ */
+
+enum dc_i2c_status {
+ DC_I2C_STATUS__DC_I2C_STATUS_IDLE,
+ DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_SW,
+ DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_HW
+};
+
+enum dc_i2c_arbitration {
+ DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_NORMAL,
+ DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_HIGH
+};
+
+enum {
+ /* No timeout in HW
+* (timeout implemented in SW by querying status) */
+ I2C_SETUP_TIME_LIMIT = 255,
+ I2C_HW_BUFFER_SIZE = 144
+};
+
+/*
+ * @brief
+ * Cast 'struct i2c_hw_engine *'
+ * to 'struct i2c_hw_engine_dce60 *'
+ */
+#define FROM_I2C_HW_ENGINE(ptr) \
+ container_of((ptr), struct i2c_hw_engine_dce60, base)
+
+/*
+ * @brief
+ * Cast pointer to 'struct i2c_engine *'
+ * to pointer to 'struct i2c_hw_engine_dce60 *'
+ */
+#define FROM_I2C_ENGINE(ptr) \
+ FROM_I2C_HW_ENGINE(container_of((ptr), struct i2c_hw_engine, base))
+
+/*
+ * @brief
+ * Cast pointer to 'struct engine *'
+ *
[PATCH 10/10] drm/amd/display: enable SI support in the Kconfig
CONFIG_DRM_AMD_DC_SI configuration option is added, default setting is disabled --- drivers/gpu/drm/amd/display/Kconfig | 8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig index ed654a76c76a..c79afe89e6e2 100644 --- a/drivers/gpu/drm/amd/display/Kconfig +++ b/drivers/gpu/drm/amd/display/Kconfig @@ -15,6 +15,14 @@ config DRM_AMD_DC_DCN1_0 help RV family support for display engine +config DRM_AMD_DC_SI + bool "AMD DC support for Southern Islands ASICs" + default n + help + Choose this option to enable new AMD DC support for SI asics + by default. This includes Tahiti, Pitcairn, Cape Verde, Oland + and Hainan. + config DEBUG_KERNEL_DC bool "Enable kgdb break in DC" depends on DRM_AMD_DC -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[RFC] drm/amd/display: add SI support to AMD DC
[PATCH 01/10] drm/amd/display: add asics info for SI parts
[PATCH 02/10] drm/amd/display: dc/dce: add DCE6 support
[PATCH 03/10] drm/amd/display: dc/core: add DCE6 support
[PATCH 04/10] drm/amd/display: dc/bios: add support for DCE6
[PATCH 05/10] drm/amd/display: dc/gpio: add support for DCE6
[PATCH 06/10] drm/amd/display: dc/i2caux: add support for DCE6
[PATCH 07/10] drm/amd/display: dc/irq: add support for DCE6
[PATCH 08/10] drm/amd/display: amdgpu_dm: add SI support
[PATCH 09/10] drm/amdgpu: enable DC support for SI parts
[PATCH 10/10] drm/amd/display: enable SI support in the Kconfig
The series adds preliminar SI support as a Proof Of Concept,
based on the idea that DCE6 is similar to DCE8, to be reviewed and refined
Android-x86 need/motivation lies in the following chain of dependencies:
Vulkan radv requires gbm gralloc prime_fd support,
gbm gralloc requires drm hwcomposer,
drm hwcomposer requires Atomic Display Framework,
Atomic Display Framework requires AMD DC, currently not supporting SI.
So the goals are:
1) to get Vulkan radv working on SI parts for android-x86.
2) to remove the gap in SI (GCN 1st gen) not having atomic support.
DCE6 specific code was implemented as a replica of existing DCE8 support
and based on how DCE8 specific code was added on top of DCE10,11 support
by adding dce60* sources, functions, macros for each existing in dce80*
CONFIG_DRM_AMD_DC_SI parameter has been added to control SI support in DC
During this first iteration of review, there are aspects to verify:
- dce60 code has been added mechanically, so there may be redundancies
and space for refactoring part of the code
- dce60_resources was having too many building errors due to missing DCE6 macros
in order to temporarily overcome the problem dce_8_0_{d,sh_mask}.h headers
were used for the PoC
- dc/irq suffered the same problem dce_8_0_{d,sh_mask}.h headers
were used for the PoC
- gfx6 may require some ad hoc initialization, skipped for the moment
- Hainan specific code requires review, as some documentation and code paths
seem to point that famility may not have DCE6, please confirm
- video decoding blocks code have not been touched
- dc/dce/dce_clock_source.{c,h} may be missing some SI/DCE6 specifics
- dc/dce/dce_dmcu.{c,h} may be missing some SI/DCE6 specifics
- dc/dce/dce_hwseq.h may be missing some SI/DCE6 specifics
- dc/dce/dce_link_encoder.h may be missing some SI/DCE6 specifics
- dc/dce/dce_stream_encoder.h may be missing some SI/DCE6 specifics
- dc/amdgpu_dm/* changes may be incomplete
- Any other omissis to be reviewed
- Feedback on best testing strategy required
Review from an expert of the DC impacted modules is recommended
SW Layer
/===\
| DCDisplay Timing ModeAsic|
| Interface Service Service Manager Capability* |
| |
| Display TopologyDisplay LinkAdapter |
| Path Manager Capability Service Service |
| Service |
|---|
| GPIO* IRQ I2cAux HW BIOS|
| Service** Manager*Sequencer* Parser* |
| |
| Connector Encoder Audio GPU Controller |
| |
\===/
HW Layer
Legend:
*dce60 support was added cleanly with dce_6_0_{d,sh_mask}.h headers
**dce60 support was added using dce_8_0_{d,sh_mask}.h headers
Android-x86 preliminary tests results:
[Boots with drm gralloc]
3DMark Slingshot
GFXbench OpenGLES benchmarks OK
V1 GPU benchmark (OpenGLES) OK
Regression in Google Chrome, Youtube (app does not show up)
Regression in Olympus Rising, Chicken Invaders (app does not show up)
[Boots with drm hwcomposer + gbm gralloc]
Google Chrome, Youtube are OK
Vulkan radv HAL API becomes available with hwc+gbm gralloc
V1 GPU benchmark (Vulkan API) OK
Sacha Willems examples OK
Some glitch/freeze in 3DMark Slingshot Extreeme and API overhead
Kind regards
Mauro Rossi
android-x86 team
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Re: [RFC] drm/amd/display: add SI support to AMD DC
Hi Mike,
On Mon, Oct 8, 2018 at 1:00 PM Mike Lothian wrote:
> Hi Mauro
>
> Do you know if there are any plans to add in UVD support on SI too?
>
> Thanks
>
> Mike
>
At the moment my focus is on getting a conformant, working and stable
implementation of Atomic Display Framework, with the objective to have it
upstreamed to amd-gfx branch, then staging (drm-next) and maybe merged in
linux kernel.
To be honest my attempt is based on code paths inspection and mimicking,
so in this moment I do not even know the state of UVD and what changes are
needed,
but, based on what I saw for DCE6 support addition on top of DCE8,
covering all compatible HW modules makes a lot of sense and it is an
opportunity to exploit,
if feasible.
For this to happen in most complete and reliable way the feedback of staff
who worked on DAL/DC
will be essential, because what I did now was to adapt code for DCE8 to
work for DCE6,
but it was like an "optimistic monkey with a keyboard" approach, with all
due respect for monkeys with keyboards,
:-) I may have missed dozen of changes.
Mauro
>
> On Mon, 8 Oct 2018 at 03:24 Mauro Rossi wrote:
>
>> [PATCH 01/10] drm/amd/display: add asics info for SI parts
>> [PATCH 02/10] drm/amd/display: dc/dce: add DCE6 support
>> [PATCH 03/10] drm/amd/display: dc/core: add DCE6 support
>> [PATCH 04/10] drm/amd/display: dc/bios: add support for DCE6
>> [PATCH 05/10] drm/amd/display: dc/gpio: add support for DCE6
>> [PATCH 06/10] drm/amd/display: dc/i2caux: add support for DCE6
>> [PATCH 07/10] drm/amd/display: dc/irq: add support for DCE6
>> [PATCH 08/10] drm/amd/display: amdgpu_dm: add SI support
>> [PATCH 09/10] drm/amdgpu: enable DC support for SI parts
>> [PATCH 10/10] drm/amd/display: enable SI support in the Kconfig
>>
>> The series adds preliminar SI support as a Proof Of Concept,
>> based on the idea that DCE6 is similar to DCE8, to be reviewed and refined
>>
>> Android-x86 need/motivation lies in the following chain of dependencies:
>> Vulkan radv requires gbm gralloc prime_fd support,
>> gbm gralloc requires drm hwcomposer,
>> drm hwcomposer requires Atomic Display Framework,
>> Atomic Display Framework requires AMD DC, currently not supporting SI.
>>
>> So the goals are:
>> 1) to get Vulkan radv working on SI parts for android-x86.
>> 2) to remove the gap in SI (GCN 1st gen) not having atomic support.
>>
>> DCE6 specific code was implemented as a replica of existing DCE8 support
>> and based on how DCE8 specific code was added on top of DCE10,11 support
>> by adding dce60* sources, functions, macros for each existing in dce80*
>>
>> CONFIG_DRM_AMD_DC_SI parameter has been added to control SI support in DC
>>
>> During this first iteration of review, there are aspects to verify:
>> - dce60 code has been added mechanically, so there may be redundancies
>> and space for refactoring part of the code
>> - dce60_resources was having too many building errors due to missing DCE6
>> macros
>> in order to temporarily overcome the problem dce_8_0_{d,sh_mask}.h headers
>> were used for the PoC
>> - dc/irq suffered the same problem dce_8_0_{d,sh_mask}.h headers
>> were used for the PoC
>> - gfx6 may require some ad hoc initialization, skipped for the moment
>> - Hainan specific code requires review, as some documentation and code
>> paths
>> seem to point that famility may not have DCE6, please confirm
>> - video decoding blocks code have not been touched
>> - dc/dce/dce_clock_source.{c,h} may be missing some SI/DCE6 specifics
>> - dc/dce/dce_dmcu.{c,h} may be missing some SI/DCE6 specifics
>> - dc/dce/dce_hwseq.h may be missing some SI/DCE6 specifics
>> - dc/dce/dce_link_encoder.h may be missing some SI/DCE6 specifics
>> - dc/dce/dce_stream_encoder.h may be missing some SI/DCE6 specifics
>> - dc/amdgpu_dm/* changes may be incomplete
>> - Any other omissis to be reviewed
>> - Feedback on best testing strategy required
>>
>> Review from an expert of the DC impacted modules is recommended
>>
>> SW Layer
>> /===\
>> | DCDisplay Timing ModeAsic|
>> | Interface Service Service Manager Capability* |
>> | |
>> | Display TopologyDisplay LinkAdapter |
>> | Path Manager Capability Service Service |
>> | Service |
>> |---|
>> | GPIO* IRQ I
Re: [RFC] drm/amd/display: add SI support to AMD DC
Hi Sylvain, On Mon, Oct 8, 2018 at 2:04 PM wrote: > > I am currently testing your patch set, on amd-staging-drm-next > (380d480842d584278dba9aa74341017d8c7d8c23) with an AMD tahiti xt part and a > displayport monitor. > patch02 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c did not apply > but > seems kind of benign. > > It's working out of the box on my AMD tahiti xt part. I did not manage to > break > it with aggressive mode programming. Let's see how it goes with my everday > usage. Thanks for info, do you have some github or patch to share for comparison/mutual knowledge? > > > The series adds preliminar SI support as a Proof Of Concept, > > based on the idea that DCE6 is similar to DCE8, to be reviewed and refined > > Did want to do it, but did drop it due to DC code getting fixed with too much > changes. > Brutally mapping DCE6 to DCE8 is an act of faith... and it's working on my > part. Do you mean just pretending SI/DCE6 parts were belonging to CIK/DCE8 family? That was a doubt for me, because GCN 2nd Generation additions were: FreeSync support (which should be missing in SI/GCN 1st generation), AMD TrueAudio (not sure about impacts in DC), A revised version of AMD PowerTune technology (less states in GCN 1st gen), GCN 2nd generation introduced an entity called "Shader Engine" While implementing the DCE6 code paths with 'systematic conservative approach' I have started to check how/if extend the approach to dce60/resources and dce60/irq, I'd like to know if to push further in that direction or if keep the DCE8 headers/masks "hack" One problem I see are Mosaic Colored Artifacts on screen surface in the 3D renders of 3Dmark Slingshot Extreeme, another visual problem is some imperfection of video sync/buffer swaps with drm_hwcomposer stack, same as per other GCN families. It will be interesting to launch some conformance tool like Piglit on linux, Android CTS dEQP VK tests, but after having triaged/removed most of the current drm gralloc regressions. Mauro > > > > Android-x86 need/motivation lies in the following chain of dependencies: > > Vulkan radv requires gbm gralloc prime_fd support, > > gbm gralloc requires drm hwcomposer, > > drm hwcomposer requires Atomic Display Framework, > > Atomic Display Framework requires AMD DC, currently not supporting SI. > > > > So the goals are: > > 1) to get Vulkan radv working on SI parts for android-x86. > > AFAIK, Vulkan support is not dependent on the display block. I am running > heavy > vulkan games on a custom gnu/linux x86_64 AMD hardware based system, then the > hwcomposer is android only? Yes, at the moment drm_hwcomposer is used only in Android builds > > > 2) to remove the gap in SI (GCN 1st gen) not having atomic support. > > I was nearly sure that atomic support was implicitely added for parts > supporting only legacy DRM mode programming interfaces? drm_hwcomposer API does not see atomic properties with amdgpu on SI parts. if Atomic Display Framework available in amdgpu, then hwc, gbm gralloc and radv would be already working on Android. Also radeondrmfb does not support Atomic Display Framework and that is a problem to have one stack for all drivers, becase with AMD DC, radeon r5xx... r7xx parts will not work even if OpenGLES supported. Mauro > > > -- > Sylvain ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [RFC] drm/amd/display: add SI support to AMD DC
Hi,
reporting about some progress made during the weekend,
thanks to Sylvain feedback & suggestions.
I have rebased and updated the series on top of
https://cgit.freedesktop.org/~agd5f/linux/?h=amd-staging-drm-next
Here is the amd_dc_si branch:
https://github.com/maurossi/linux/tree/amd_dc_si (uploading)
NOTE: arch/x86/kernel/tsc.c changes for 4K display modes are not
there, as they are not strictly needed for amd-gfx
Copying also Harry, Alex, Christian and Mike in order to get some
objective and infallible
clues/feedbacks about blocking points and about "no care" items.
Please, also big things I may have missed.
M.
>On Mon, Oct 8, 2018 at 11:23 PM wrote:
>
> Sylvain - I did hack a bit your patch set on amd-staging-drm-next to make it
> go through the
> asic init and I managed to get a x11 display with lines kind of garbled, but
> you can still understand easily what's on the screen.
I forgot to mention that since I'm gorgeously trying AMD DC also on Mullins
I have reverted d9fda24 (""drm/amdgpu: Don't default to DC support for
Kaveri and older")
because on Mullins I can boot with HDMI and HDMI-to-VGA converter
I was hoping for AMD DC being re-enabled for Kaveri and older,
but I'm available to submit new version of specific patch if required.
> Sylvain - ... The lines may be garbled in your driver code because,
> if I recall properly, "line buffer" programing in dce8 is not
> the same than in dce6 (look for registers with the "LB" abbreviation). Or some
> slight differences in frame buffer tiling.
So the problem could be related to some kind of scan line or tiling
buffer issue,
at the moment the dce_resouces model is grabbed "AS IS" from DCE8
registers/masks
>
> Sylvain - I checked the kernel log, and like you said, I got errors in
> DM_PPLIB due to an
> invalid powerlevel and atombios/vbios table parsing regarding connectors.
> general dpm is in amdgpu(no DC) for SI, it means the DCE related dpm part in
> current SI amdgpu code path should be "copied" in DC. It is related very
> probably to the parsing of VBIOS/ATOMBIOS tables.
10-09 21:10:14.427 0 0 E :
[drm:dm_pp_get_static_clocks [amdgpu]] *ERROR* DM_PPLIB: invalid
powerlevel state: 0!
NOTE: the error is the result of Powerplay dependency introduced by
using AMD DC for SI
it's not fatal and it does not seem to affect performance in the Benchmarks
DOUBT: I think that it would make sense to set "power level 0" i.e.
the "lower state" as safe default,
considering that powerplay smu6/hwmgr are not implemented for SI and
smu7 CIK functions do not work,
the AS-IS dpm is the only available option. (and it seams to be
working, looking at the framerates 250-280 in the V1 Vulkan benchmark)
>10-09 21:10:14.427 0 0 W [drm] dce110_link_encoder_construct: Failed
>to get encoder_cap_info from VBIOS with error code 4!
>10-09 21:10:14.427 0 0 W [drm] dce110_link_encoder_construct: Failed
>to get encoder_cap_info from VBIOS with error code 4!
NOTE: the warning also appears with Tonga and Vega, it is a Warning
and does not seem to cause issues, so I would assume there is a
default treatment in place,
is this related to missing encoder for drm crtc or to other kind of encoder?
> Sylvain - Did add SI handling in some raven firmware loader function.
> In drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c, "load_dmcu_fw"
> function augmented with SI chip asic_type.
I've merged the change in the (v2) branch
https://github.com/maurossi/linux/tree/amd_dc_si
> Sylvain - AFAIK, the real thing that you additionally get with DC is
> freesync. But
> freesync is actually going to be interesting only if displays are able to
> get their sync range lower bound to 0, and get significant power saving
> thanks to this. For the use case of very low display refresh rate I don't even
> think displayport or hdmi can do that, and be power friendly (you would have
> to retrain the link probably each time you send a framebuffer to the display).
If freesync is about reducing the framerate rate for power saving,
provided that I've seen it be mentioned the first time for GCN 2nd generation,
I'm not expecting freesync as a mandatory capability for the series.
> Mauro -- dce60_resources was having too many building errors due to missing
> DCE6 macros
>in order to temporarily overcome the problem dce_8_0_{d,sh_mask}.h headers
>were used for the PoC
Still to many building errors due to quite different registers naming,
pointers to GPU register info (either in GPUopen or by means of
listing the DCE6 vs DC8 differences),
or keeping the DCE6 is exactly like DCE8 as register changes are
apparently not mission critical.
> Mauro - dc/irq suffered the same problem dce_8_0_{d,sh_mask}.h headers
>were used for the PoC
I could not update dc/irq VBI Vertical Blank Interrupt, because i
cannot find the corresponding IRQ register in amdgpu/dce6 registers
headers/mask
-CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK
+?seems
Re: [RFC] drm/amd/display: add SI support to AMD DC
Hi Sylvain, Il lun 15 ott 2018, 03:25 ha scritto: > On Sun, Oct 14, 2018 at 11:47:18PM +0200, Mauro Rossi wrote: > > DOUBT: I think that it would make sense to set "power level 0" i.e. > > the "lower state" as safe default, > > considering that powerplay smu6/hwmgr are not implemented for SI and > > smu7 CIK functions do not work, > > the AS-IS dpm is the only available option. (and it seams to be > > working, looking at the framerates 250-280 in the V1 Vulkan benchmark) > > dpm not implemented for SI? Are you sure? Because I recall passing > "messages" > dpm for SI is available, while powerplay for SI is not, but display/amdgpu_dm uses some powerplay calls, where get_static_clock functions not available and the *ERROR* DM_PPLIB is due to missing handling in powerplay to the smu6 to switch between major power modes. And currently in amdgpu I > switch back and forth between "high" and "auto". And if I stay on "high" > my GPU > fans are going crazy all the time, which forces me to switch back to > "auto" in > order to quiet the fans. > Any major state change for any block would have to go through the dpm block > (smu), because it has to be accounted by this block for proper operation. > One > of the hard thing to code, coze no proper documentation, was to set the > blocks > in an initial state from a poweron/hard reset/etc which the dpm will know > how to start/catch-up its operations from. In a perfect world, the dpm > block > would have the knowledge on how to program any block in an initial working > state from any unknown state (and in case of hard block hang, would know > how to > hard reset it and set it in a initial state). > > > If freesync is about reducing the framerate rate for power saving, > > provided that I've seen it be mentioned the first time for GCN 2nd > generation, > > I'm not expecting freesync as a mandatory capability for the series. > > Well, there are the low FPS games, and the movies. I am a regular gamer, > and I > know that sustained 60 fps is the very lower bound for many games on a > desktop > computer display. > It does not apply to mobile size display, and "couch playing" on a TV. The > readibilty of the game depends directly on the amplitude of movements in > physical distance on the display, their speed, the viewing distance, and > the > FPS. From my personal comfort point of view and types of games I play, on a > desktop display (dpi, typical viewing distance, typical size), I would > target a > minimum of 80-100 fps (120/144 fps seems to be "perfect" targets). > Played rise of the tomb raider (vulkan) on my tahiti part, and even with a > blur > effect to "smooth" the perceived fps like in movies, sub-60 fps is really > uncomfortable. I was about to stop playing to this game even though it is a > rather "slow" video game. > > > In amd-staging-drm-next dce_clock_source is generic, SI specifics are > > not necessary anymore. > > If I recall properly, "bandwidths" and "watermarks" calcs had asic > generations > specific code paths. bandwidth is important for displayport programming or > maybe you can presume the maximum all the time (and sacrifice some unkown > amount of power) and watermarks, I know in my old driver I was giving the > highest priority the the dce block anyway (something related to a "memory > aribtrer" and "line buffer"). > > > Any other testing tools worth a run? > > AAA games (vulkan: rize of the tomb raider, GL:bioshock infinite) and > games > (dota2(gl and vulkan), cs:go...) > > -- > Sylvain > Thanks a lot Mauro > ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v2 10/10] drm/amd/display: enable SI support in the Kconfig (v2)
CONFIG_DRM_AMD_DC_SI configuration option is added, default setting is disabled (v2) Hainan is not supported, description updated accordingly --- drivers/gpu/drm/amd/display/Kconfig | 8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig index 13a6ce9c8e94..32cdb2da603e 100644 --- a/drivers/gpu/drm/amd/display/Kconfig +++ b/drivers/gpu/drm/amd/display/Kconfig @@ -21,6 +21,14 @@ config DRM_AMD_DC_DCN1_01 help RV2 family for display engine +config DRM_AMD_DC_SI + bool "AMD DC support for Southern Islands ASICs" + default n + help + Choose this option to enable new AMD DC support for SI asics + by default. This includes Tahiti, Pitcairn, Cape Verde, Oland. + Hainan is not supported by AMD DC and it has no physical DCE6. + config DEBUG_KERNEL_DC bool "Enable kgdb break in DC" depends on DRM_AMD_DC -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v2 09/10] drm/amdgpu: enable DC support for SI parts (v2)
This commit enables DC support and Display Manager IP block
conditionally to CONFIG_DRM_AMD_DC_SI kernel configuration
(v1) pre-requisite to have Kaveri and Hawaii is revert of d9fda24804
("drm/amdgpu: Don't default to DC support for Kaveri and older")
(v2) fix for bc011f9350 ("drm/amdgpu: Change SI/CI gfx/sdma/smu init sequence")
remove CHIP_HAINAN support since it does not have physical DCE6 module
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 ++
drivers/gpu/drm/amd/amdgpu/si.c| 10 ++
2 files changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 27de8442e808..2d17d760af64 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2290,6 +2290,12 @@ bool amdgpu_device_asic_has_dc_support(enum
amd_asic_type asic_type)
{
switch (asic_type) {
#if defined(CONFIG_DRM_AMD_DC)
+#if defined(CONFIG_DRM_AMD_DC_SI)
+ case CHIP_TAHITI:
+ case CHIP_PITCAIRN:
+ case CHIP_VERDE:
+ case CHIP_OLAND:
+#endif
case CHIP_BONAIRE:
case CHIP_HAWAII:
case CHIP_KAVERI:
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index f8408f88cd37..700d6a914b30 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -48,6 +48,8 @@
#include "uvd/uvd_4_0_d.h"
#include "bif/bif_3_0_d.h"
+#include "amdgpu_dm.h"
+
static const u32 tahiti_golden_registers[] =
{
mmAZALIA_SCLK_CONTROL, 0x0030, 0x0011,
@@ -2062,6 +2064,10 @@ int si_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, _smu_ip_block);
if (adev->enable_virtual_display)
amdgpu_device_ip_block_add(adev, _virtual_ip_block);
+#if defined(CONFIG_DRM_AMD_DC) && defined(CONFIG_DRM_AMD_DC_SI)
+ else if (amdgpu_device_has_dc_support(adev))
+ amdgpu_device_ip_block_add(adev, _ip_block);
+#endif
else
amdgpu_device_ip_block_add(adev, _v6_0_ip_block);
/* amdgpu_device_ip_block_add(adev, _v3_1_ip_block); */
@@ -2076,6 +2082,10 @@ int si_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, _smu_ip_block);
if (adev->enable_virtual_display)
amdgpu_device_ip_block_add(adev, _virtual_ip_block);
+#if defined(CONFIG_DRM_AMD_DC) && defined(CONFIG_DRM_AMD_DC_SI)
+ else if (amdgpu_device_has_dc_support(adev))
+ amdgpu_device_ip_block_add(adev, _ip_block);
+#endif
else
amdgpu_device_ip_block_add(adev, _v6_4_ip_block);
--
2.17.1
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[PATCH v2 08/10] drm/amd/display: amdgpu_dm: add SI support (v2)
This commit adds Display Manager early initialization for SI parts
conditionally to CONFIG_DRM_AMD_DC_SI kernel configuration
(v2) remove CHIP_HAINAN support since it does not have physical DCE6 module
add SI families except CHIP_HAINAN in load_dmcu_fw() new function
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 28 +++
1 file changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 492230c41b4a..7dedb363a476 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -514,6 +514,12 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
const struct dmcu_firmware_header_v1_0 *hdr;
switch(adev->asic_type) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+ case CHIP_TAHITI:
+ case CHIP_PITCAIRN:
+ case CHIP_VERDE:
+ case CHIP_OLAND:
+#endif
case CHIP_BONAIRE:
case CHIP_HAWAII:
case CHIP_KAVERI:
@@ -1728,6 +1734,12 @@ static int amdgpu_dm_initialize_drm_device(struct
amdgpu_device *adev)
/* Software is initialized. Now we can register interrupt handlers. */
switch (adev->asic_type) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+ case CHIP_TAHITI:
+ case CHIP_PITCAIRN:
+ case CHIP_VERDE:
+ case CHIP_OLAND:
+#endif
case CHIP_BONAIRE:
case CHIP_HAWAII:
case CHIP_KAVERI:
@@ -1918,6 +1930,22 @@ static int dm_early_init(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
switch (adev->asic_type) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+ case CHIP_TAHITI:
+ case CHIP_PITCAIRN:
+ case CHIP_VERDE:
+ adev->mode_info.num_crtc = 6;
+ adev->mode_info.num_hpd = 6;
+ adev->mode_info.num_dig = 6;
+ adev->mode_info.plane_type = dm_plane_type_default;
+ break;
+ case CHIP_OLAND:
+ adev->mode_info.num_crtc = 2;
+ adev->mode_info.num_hpd = 2;
+ adev->mode_info.num_dig = 2;
+ adev->mode_info.plane_type = dm_plane_type_default;
+ break;
+#endif
case CHIP_BONAIRE:
case CHIP_HAWAII:
adev->mode_info.num_crtc = 6;
--
2.17.1
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[PATCH v2 07/10] drm/amd/display: dc/irq: add support for DCE6
DCE6 targets are added replicating existing DCE8 implementation.
NOTE: due to missing CRTC_VERTICAL_INTERRUPT0_CONTROL registers/masks,
dce/dce_8_0_{d,sh_mask}.h headers were used instead of dce/dce_6_0_{d,sh_mask}.h
but only as exception in dce/irq_service_dce60.c
IMPORTANT: Coding of dce/irq_service_dce60.c requires review to understand
if dce_6_0_{d,sh_mask}.h should be updated with macros/registers/masks
---
drivers/gpu/drm/amd/display/dc/irq/Makefile | 11 +
.../display/dc/irq/dce60/irq_service_dce60.c | 303 ++
.../display/dc/irq/dce60/irq_service_dce60.h | 35 ++
.../gpu/drm/amd/display/dc/irq/irq_service.c | 3 +
4 files changed, 352 insertions(+)
create mode 100644 drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
create mode 100644 drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.h
diff --git a/drivers/gpu/drm/amd/display/dc/irq/Makefile
b/drivers/gpu/drm/amd/display/dc/irq/Makefile
index 498515aad4a5..e38b6d8d614d 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/irq/Makefile
@@ -30,6 +30,17 @@ AMD_DAL_IRQ = $(addprefix $(AMDDALPATH)/dc/irq/,$(IRQ))
AMD_DISPLAY_FILES += $(AMD_DAL_IRQ)
+###
+# DCE 6x
+###
+ifdef CONFIG_DRM_AMD_DC_SI
+IRQ_DCE60 = irq_service_dce60.o
+
+AMD_DAL_IRQ_DCE60 = $(addprefix $(AMDDALPATH)/dc/irq/dce60/,$(IRQ_DCE60))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCE60)
+endif
+
###
# DCE 8x
###
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
b/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
new file mode 100644
index ..107e0dcb5f80
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
@@ -0,0 +1,303 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+
+#include "include/logger_interface.h"
+
+#include "irq_service_dce60.h"
+#include "../dce110/irq_service_dce110.h"
+
+#include "dce/dce_8_0_d.h"
+#include "dce/dce_8_0_sh_mask.h"
+
+#include "ivsrcid/ivsrcid_vislands30.h"
+
+#include "dc_types.h"
+
+static bool hpd_ack(
+ struct irq_service *irq_service,
+ const struct irq_source_info *info)
+{
+ uint32_t addr = info->status_reg;
+ uint32_t value = dm_read_reg(irq_service->ctx, addr);
+ uint32_t current_status =
+ get_reg_field_value(
+ value,
+ DC_HPD1_INT_STATUS,
+ DC_HPD1_SENSE_DELAYED);
+
+ dal_irq_service_ack_generic(irq_service, info);
+
+ value = dm_read_reg(irq_service->ctx, info->enable_reg);
+
+ set_reg_field_value(
+ value,
+ current_status ? 0 : 1,
+ DC_HPD1_INT_CONTROL,
+ DC_HPD1_INT_POLARITY);
+
+ dm_write_reg(irq_service->ctx, info->enable_reg, value);
+
+ return true;
+}
+
+static const struct irq_source_info_funcs hpd_irq_info_funcs = {
+ .set = NULL,
+ .ack = hpd_ack
+};
+
+static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
+ .set = NULL,
+ .ack = NULL
+};
+
+static const struct irq_source_info_funcs pflip_irq_info_funcs = {
+ .set = NULL,
+ .ack = NULL
+};
+
+static const struct irq_source_info_funcs vblank_irq_info_funcs = {
+ .set = dce110_vblank_set,
+ .ack = NULL
+};
+
+
+#define hpd_int_entry(reg_num)\
+ [DC_IRQ_SOURCE_INVALID + reg_num] = {\
+ .enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
+ .enable_mask =
[PATCH v2 06/10] drm/amd/display: dc/i2caux: add support for DCE6
DCE6 targets are added replicating existing DCE8 implementation.
---
.../gpu/drm/amd/display/dc/i2caux/Makefile| 12 +
.../dc/i2caux/dce60/i2c_hw_engine_dce60.c | 875 ++
.../dc/i2caux/dce60/i2c_hw_engine_dce60.h | 54 ++
.../dc/i2caux/dce60/i2c_sw_engine_dce60.c | 173
.../dc/i2caux/dce60/i2c_sw_engine_dce60.h | 43 +
.../display/dc/i2caux/dce60/i2caux_dce60.c| 284 ++
.../display/dc/i2caux/dce60/i2caux_dce60.h| 38 +
.../gpu/drm/amd/display/dc/i2caux/i2caux.c| 10 +
8 files changed, 1489 insertions(+)
create mode 100644
drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_hw_engine_dce60.c
create mode 100644
drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_hw_engine_dce60.h
create mode 100644
drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_sw_engine_dce60.c
create mode 100644
drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_sw_engine_dce60.h
create mode 100644 drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2caux_dce60.c
create mode 100644 drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2caux_dce60.h
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/Makefile
b/drivers/gpu/drm/amd/display/dc/i2caux/Makefile
index 352885cb4d07..80f58a357879 100644
--- a/drivers/gpu/drm/amd/display/dc/i2caux/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/Makefile
@@ -30,6 +30,18 @@ AMD_DAL_I2CAUX = $(addprefix
$(AMDDALPATH)/dc/i2caux/,$(I2CAUX))
AMD_DISPLAY_FILES += $(AMD_DAL_I2CAUX)
+###
+# DCE 6x family
+###
+ifdef CONFIG_DRM_AMD_DC_SI
+I2CAUX_DCE60 = i2caux_dce60.o i2c_hw_engine_dce60.o \
+ i2c_sw_engine_dce60.o
+
+AMD_DAL_I2CAUX_DCE60 = $(addprefix
$(AMDDALPATH)/dc/i2caux/dce60/,$(I2CAUX_DCE60))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_I2CAUX_DCE60)
+endif
+
###
# DCE 8x family
###
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_hw_engine_dce60.c
b/drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_hw_engine_dce60.c
new file mode 100644
index ..a945e00ce913
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_hw_engine_dce60.c
@@ -0,0 +1,875 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+
+/*
+ * Pre-requisites: headers required by header of this unit
+ */
+#include "include/i2caux_interface.h"
+#include "../engine.h"
+#include "../i2c_engine.h"
+#include "../i2c_hw_engine.h"
+#include "../i2c_generic_hw_engine.h"
+/*
+ * Header of this unit
+ */
+
+#include "i2c_hw_engine_dce60.h"
+
+/*
+ * Post-requisites: headers required by this unit
+ */
+
+#include "dce/dce_6_0_d.h"
+#include "dce/dce_6_0_sh_mask.h"
+/*
+ * This unit
+ */
+
+enum dc_i2c_status {
+ DC_I2C_STATUS__DC_I2C_STATUS_IDLE,
+ DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_SW,
+ DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_HW
+};
+
+enum dc_i2c_arbitration {
+ DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_NORMAL,
+ DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_HIGH
+};
+
+enum {
+ /* No timeout in HW
+* (timeout implemented in SW by querying status) */
+ I2C_SETUP_TIME_LIMIT = 255,
+ I2C_HW_BUFFER_SIZE = 144
+};
+
+/*
+ * @brief
+ * Cast 'struct i2c_hw_engine *'
+ * to 'struct i2c_hw_engine_dce60 *'
+ */
+#define FROM_I2C_HW_ENGINE(ptr) \
+ container_of((ptr), struct i2c_hw_engine_dce60, base)
+
+/*
+ * @brief
+ * Cast pointer to 'struct i2c_engine *'
+ * to pointer to 'struct i2c_hw_engine_dce60 *'
+ */
+#define FROM_I2C_ENGINE(ptr) \
+ FROM_I2C_HW_ENGINE(container_of((ptr), struct i2c_hw_engine, base))
+
+/*
+ * @brief
+ * Cast pointer to 'struct engine *'
+ *
[PATCH v2] drm/amd/display: add SI support to AMD DC
Sending PATCH v2 series rebase on amd-staging-drm-next
dce/dce60/dce60_resources.c and irq/dce60/irq_service_dce60.c
are still using dce_8_0_{d,sh_mask}.h headers
dpm is used for power management, a non fatal message is generated:
[drm:dm_pp_get_static_clocks: [amdgpu]]
*ERROR* DM_PPLIB: invalid powerlevel state: 0!
VBIOS parsing requires review about severity of generated Warning:
dce110_link_encoder_construct:
Failed to get encoder_cap_info from VBIOS with error code 4!
[PATCH v2 01/10] drm/amd/display: add asics info for SI parts
[PATCH v2 02/10] drm/amd/display: dc/dce: add DCE6 support (v2)
[PATCH v2 03/10] drm/amd/display: dc/core: add DCE6 support
[PATCH v2 04/10] drm/amd/display: dc/bios: add support for DCE6
[PATCH v2 05/10] drm/amd/display: dc/gpio: add support for DCE6
[PATCH v2 06/10] drm/amd/display: dc/i2caux: add support for DCE6
[PATCH v2 07/10] drm/amd/display: dc/irq: add support for DCE6
[PATCH v2 08/10] drm/amd/display: amdgpu_dm: add SI support (v2)
[PATCH v2 09/10] drm/amdgpu: enable DC support for SI parts (v2)
[PATCH v2 10/10] drm/amd/display: enable SI support in the Kconfig (v2)
___
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[PATCH v2 04/10] drm/amd/display: dc/bios: add support for DCE6
DCE6 targets are added replicating existing DCE8 implementation.
---
drivers/gpu/drm/amd/display/dc/bios/Makefile | 9 +
.../display/dc/bios/command_table_helper.c| 8 +
.../display/dc/bios/command_table_helper.h| 3 +
.../display/dc/bios/command_table_helper2.c | 8 +
.../display/dc/bios/command_table_helper2.h | 3 +
.../bios/dce60/command_table_helper_dce60.c | 354 ++
.../bios/dce60/command_table_helper_dce60.h | 33 ++
7 files changed, 418 insertions(+)
create mode 100644
drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c
create mode 100644
drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.h
diff --git a/drivers/gpu/drm/amd/display/dc/bios/Makefile
b/drivers/gpu/drm/amd/display/dc/bios/Makefile
index 239e86bbec5a..ed6b5e9763f6 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/bios/Makefile
@@ -31,6 +31,15 @@ AMD_DAL_BIOS = $(addprefix $(AMDDALPATH)/dc/bios/,$(BIOS))
AMD_DISPLAY_FILES += $(AMD_DAL_BIOS)
+###
+# DCE 6x
+###
+# All DCE6.x are derived from DCE6.0, so 6.0 MUST be defined if ANY of
+# DCE6.x is compiled.
+ifdef CONFIG_DRM_AMD_DC_SI
+AMD_DISPLAY_FILES += $(AMDDALPATH)/dc/bios/dce60/command_table_helper_dce60.o
+endif
+
###
# DCE 8x
###
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
index 253bbb1eea60..48b4ef03fc8f 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
@@ -36,6 +36,14 @@ bool dal_bios_parser_init_cmd_tbl_helper(
enum dce_version dce)
{
switch (dce) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+ case DCE_VERSION_6_0:
+ case DCE_VERSION_6_1:
+ case DCE_VERSION_6_4:
+ *h = dal_cmd_tbl_helper_dce60_get_table();
+ return true;
+#endif
+
case DCE_VERSION_8_0:
case DCE_VERSION_8_1:
case DCE_VERSION_8_3:
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h
b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h
index 4c3789df253d..dfd30aaf4032 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h
@@ -26,6 +26,9 @@
#ifndef __DAL_COMMAND_TABLE_HELPER_H__
#define __DAL_COMMAND_TABLE_HELPER_H__
+#if defined(CONFIG_DRM_AMD_DC_SI)
+#include "dce60/command_table_helper_dce60.h"
+#endif
#include "dce80/command_table_helper_dce80.h"
#include "dce110/command_table_helper_dce110.h"
#include "dce112/command_table_helper_dce112.h"
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
index 65b006ad372e..92288c582934 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
@@ -37,6 +37,14 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
enum dce_version dce)
{
switch (dce) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+ case DCE_VERSION_6_0:
+ case DCE_VERSION_6_1:
+ case DCE_VERSION_6_4:
+ *h = dal_cmd_tbl_helper_dce60_get_table();
+ return true;
+#endif
+
case DCE_VERSION_8_0:
case DCE_VERSION_8_1:
case DCE_VERSION_8_3:
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h
b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h
index 785fcb20a1b9..66e0a3e73768 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h
@@ -26,6 +26,9 @@
#ifndef __DAL_COMMAND_TABLE_HELPER2_H__
#define __DAL_COMMAND_TABLE_HELPER2_H__
+#if defined(CONFIG_DRM_AMD_DC_SI)
+#include "dce60/command_table_helper_dce60.h"
+#endif
#include "dce80/command_table_helper_dce80.h"
#include "dce110/command_table_helper_dce110.h"
#include "dce112/command_table_helper2_dce112.h"
diff --git
a/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c
b/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c
new file mode 100644
index ..552778ce9835
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c
@@ -0,0 +1,354 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the
[PATCH v2 01/10] drm/amd/display: add asics info for SI parts
Asics info retrieved from si_id.h in https://github.com/GPUOpen-Tools/CodeXL
Tree path:
./CodeXL/Components/ShaderAnalyzer/AMDTBackEnd/Include/Common/asic_reg/si_id.h
---
.../gpu/drm/amd/display/include/dal_asic_id.h | 40 +++
.../gpu/drm/amd/display/include/dal_types.h | 3 ++
2 files changed, 43 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
index 4f501ddcfb8d..5b600c9445bd 100644
--- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
@@ -30,6 +30,34 @@
* ASIC internal revision ID
*/
+/* DCE60 (based on si_id.h in GPUOpen-Tools CodeXL) */
+#define SI_TAHITI_P_A00x01
+#define SI_TAHITI_P_B00x05
+#define SI_TAHITI_P_B10x06
+#define SI_PITCAIRN_PM_A0 0x14
+#define SI_PITCAIRN_PM_A1 0x15
+#define SI_CAPEVERDE_M_A0 0x28
+#define SI_CAPEVERDE_M_A1 0x29
+#define SI_OLAND_M_A0 0x3C
+#define SI_HAINAN_V_A00x46
+
+#define SI_UNKNOWN0xFF
+
+#define ASIC_REV_IS_TAHITI_P(rev) \
+ ((rev >= SI_TAHITI_P_A0) && (rev < SI_PITCAIRN_PM_A0))
+
+#define ASIC_REV_IS_PITCAIRN_PM(rev) \
+ ((rev >= SI_PITCAIRN_PM_A0) && (rev < SI_CAPEVERDE_M_A0))
+
+#define ASIC_REV_IS_CAPEVERDE_M(rev) \
+ ((rev >= SI_CAPEVERDE_M_A0) && (rev < SI_OLAND_M_A0))
+
+#define ASIC_REV_IS_OLAND_M(rev) \
+ ((rev >= SI_OLAND_M_A0) && (rev < SI_HAINAN_V_A0))
+
+#define ASIC_REV_IS_HAINAN_V(rev) \
+ ((rev >= SI_HAINAN_V_A0) && (rev < SI_UNKNOWN))
+
/* DCE80 (based on ci_id.h in Perforce) */
#defineCI_BONAIRE_M_A0 0x14
#defineCI_BONAIRE_M_A1 0x15
@@ -150,12 +178,24 @@
/*
* ASIC chip ID
*/
+
+/* DCE60 */
+#define DEVICE_ID_SI_TAHITI_P_6780 0x6780
+#define DEVICE_ID_SI_PITCAIRN_PM_6800 0x6800
+#define DEVICE_ID_SI_PITCAIRN_PM_6808 0x6808
+#define DEVICE_ID_SI_CAPEVERDE_M_6820 0x6820
+#define DEVICE_ID_SI_CAPEVERDE_M_6828 0x6828
+#define DEVICE_ID_SI_OLAND_M_6600 0x6600
+#define DEVICE_ID_SI_OLAND_M_6608 0x6608
+#define DEVICE_ID_SI_HAINAN_V_6660 0x6660
+
/* DCE80 */
#define DEVICE_ID_KALINDI_9834 0x9834
#define DEVICE_ID_TEMASH_9839 0x9839
#define DEVICE_ID_TEMASH_983D 0x983D
/* Asic Family IDs for different asic family. */
+#define FAMILY_SI 110 /* Southern Islands: Tahiti (P), Pitcairn (PM), Cape
Verde (M), Oland (M), Hainan (V) */
#define FAMILY_CI 120 /* Sea Islands: Hawaii (P), Bonaire (M) */
#define FAMILY_KV 125 /* Fusion => Kaveri: Spectre, Spooky; Kabini: Kalindi */
#define FAMILY_VI 130 /* Volcanic Islands: Iceland (V), Tonga (M) */
diff --git a/drivers/gpu/drm/amd/display/include/dal_types.h
b/drivers/gpu/drm/amd/display/include/dal_types.h
index 89627133e188..c79f42544aae 100644
--- a/drivers/gpu/drm/amd/display/include/dal_types.h
+++ b/drivers/gpu/drm/amd/display/include/dal_types.h
@@ -34,6 +34,9 @@ struct dc_bios;
enum dce_version {
DCE_VERSION_UNKNOWN = (-1),
+ DCE_VERSION_6_0,
+ DCE_VERSION_6_1,
+ DCE_VERSION_6_4,
DCE_VERSION_8_0,
DCE_VERSION_8_1,
DCE_VERSION_8_3,
--
2.17.1
___
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[PATCH v2 02/10] drm/amd/display: dc/dce: add DCE6 support (v2)
DCE6 targets are added replicating existing DCE8 implementation.
NOTE: dce_8_0_{d,sh_mask}.h headers used instead of dce_6_0_{d,sh_mask}.h
only to build dce60_resource.c due to missing *_DCE60 macros/registers/masks
IMPORTANT: Coding of dce60_resource.c requires review to understand
if dce_6_0_{d,sh_mask}.h should be updated with macros/registers/masks
(v2) updated dce60_{hw_sequencer,resources}.c as per amd-staging-drm-next
removed dce_version cases in dc/dce/dce_clock_source.c
---
drivers/gpu/drm/amd/display/dc/Makefile |4 +
drivers/gpu/drm/amd/display/dc/dce60/Makefile | 34 +
.../amd/display/dc/dce60/dce60_hw_sequencer.c | 82 +
.../amd/display/dc/dce60/dce60_hw_sequencer.h | 36 +
.../drm/amd/display/dc/dce60/dce60_resource.c | 1458 +
.../drm/amd/display/dc/dce60/dce60_resource.h | 47 +
.../display/dc/dce60/dce60_timing_generator.c | 242 +++
.../display/dc/dce60/dce60_timing_generator.h | 39 +
.../include/asic_reg/dce/dce_6_0_sh_mask.h|4 +
9 files changed, 1946 insertions(+)
create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/Makefile
create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.h
create mode 100644
drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c
create mode 100644
drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.h
diff --git a/drivers/gpu/drm/amd/display/dc/Makefile
b/drivers/gpu/drm/amd/display/dc/Makefile
index aed538a4d1ba..d5d5acd57559 100644
--- a/drivers/gpu/drm/amd/display/dc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/Makefile
@@ -36,6 +36,10 @@ DC_LIBS += dce110
DC_LIBS += dce100
DC_LIBS += dce80
+ifdef CONFIG_DRM_AMD_DC_SI
+DC_LIBS += dce60
+endif
+
AMD_DC = $(addsuffix /Makefile, $(addprefix
$(FULL_AMD_DISPLAY_PATH)/dc/,$(DC_LIBS)))
include $(AMD_DC)
diff --git a/drivers/gpu/drm/amd/display/dc/dce60/Makefile
b/drivers/gpu/drm/amd/display/dc/dce60/Makefile
new file mode 100644
index ..39afd7c59a7c
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dce60/Makefile
@@ -0,0 +1,34 @@
+#
+# Copyright 2017 Advanced Micro Devices, Inc.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+# OTHER DEALINGS IN THE SOFTWARE.
+#
+#
+# Makefile for the 'controller' sub-component of DAL.
+# It provides the control and status of HW CRTC block.
+
+DCE60 = dce60_timing_generator.o dce60_hw_sequencer.o \
+ dce60_resource.o
+
+AMD_DAL_DCE60 = $(addprefix $(AMDDALPATH)/dc/dce60/,$(DCE60))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_DCE60)
+
+
+
diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c
new file mode 100644
index ..502172bf6097
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c
@@ -0,0 +1,82 @@
+/*
+ * Copyright 2015 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ *
[PATCH v2 03/10] drm/amd/display: dc/core: add DCE6 support
DCE6 targets are added as branching of existing DCE8 implementation.
---
.../gpu/drm/amd/display/dc/core/dc_resource.c | 29 +++
1 file changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index a5eb80aa3dd9..07bd4f72acc5 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -37,6 +37,9 @@
#include "virtual/virtual_stream_encoder.h"
#include "dpcd_defs.h"
+#if defined(CONFIG_DRM_AMD_DC_SI)
+#include "dce60/dce60_resource.h"
+#endif
#include "dce80/dce80_resource.h"
#include "dce100/dce100_resource.h"
#include "dce110/dce110_resource.h"
@@ -53,6 +56,18 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id
asic_id)
enum dce_version dc_version = DCE_VERSION_UNKNOWN;
switch (asic_id.chip_family) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+ case FAMILY_SI:
+ if (ASIC_REV_IS_TAHITI_P(asic_id.hw_internal_rev) ||
+ ASIC_REV_IS_PITCAIRN_PM(asic_id.hw_internal_rev) ||
+ ASIC_REV_IS_CAPEVERDE_M(asic_id.hw_internal_rev))
+ dc_version = DCE_VERSION_6_0;
+ else if (ASIC_REV_IS_OLAND_M(asic_id.hw_internal_rev))
+ dc_version = DCE_VERSION_6_4;
+ else
+ dc_version = DCE_VERSION_6_1;
+ break;
+#endif
case FAMILY_CI:
dc_version = DCE_VERSION_8_0;
break;
@@ -110,6 +125,20 @@ struct resource_pool *dc_create_resource_pool(
struct resource_pool *res_pool = NULL;
switch (dc_version) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+ case DCE_VERSION_6_0:
+ res_pool = dce60_create_resource_pool(
+ num_virtual_links, dc);
+ break;
+ case DCE_VERSION_6_1:
+ res_pool = dce61_create_resource_pool(
+ num_virtual_links, dc);
+ break;
+ case DCE_VERSION_6_4:
+ res_pool = dce64_create_resource_pool(
+ num_virtual_links, dc);
+ break;
+#endif
case DCE_VERSION_8_0:
res_pool = dce80_create_resource_pool(
num_virtual_links, dc);
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v2 05/10] drm/amd/display: dc/gpio: add support for DCE6
DCE6 targets are added replicating existing DCE8 implementation.
---
drivers/gpu/drm/amd/display/dc/gpio/Makefile | 12 +
.../display/dc/gpio/dce60/hw_factory_dce60.c | 174
.../display/dc/gpio/dce60/hw_factory_dce60.h | 32 ++
.../dc/gpio/dce60/hw_translate_dce60.c| 411 ++
.../dc/gpio/dce60/hw_translate_dce60.h| 32 ++
.../gpu/drm/amd/display/dc/gpio/hw_factory.c | 10 +
.../drm/amd/display/dc/gpio/hw_translate.c| 10 +
7 files changed, 681 insertions(+)
create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.c
create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.h
create mode 100644
drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c
create mode 100644
drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.h
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/Makefile
b/drivers/gpu/drm/amd/display/dc/gpio/Makefile
index 562ee189d780..122ca9991100 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/gpio/Makefile
@@ -30,6 +30,18 @@ AMD_DAL_GPIO = $(addprefix $(AMDDALPATH)/dc/gpio/,$(GPIO))
AMD_DISPLAY_FILES += $(AMD_DAL_GPIO)
+###
+# DCE 6x
+###
+# all DCE6.x are derived from DCE6.0
+ifdef CONFIG_DRM_AMD_DC_SI
+GPIO_DCE60 = hw_translate_dce60.o hw_factory_dce60.o
+
+AMD_DAL_GPIO_DCE60 = $(addprefix $(AMDDALPATH)/dc/gpio/dce60/,$(GPIO_DCE60))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCE60)
+endif
+
###
# DCE 8x
###
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.c
b/drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.c
new file mode 100644
index ..64afe9b48c5f
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.c
@@ -0,0 +1,174 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ * Copyright 2018 Mauro Rossi
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+#include "include/gpio_types.h"
+#include "../hw_factory.h"
+
+#include "hw_factory_dce60.h"
+
+#include "../hw_gpio.h"
+#include "../hw_ddc.h"
+#include "../hw_hpd.h"
+
+#include "dce/dce_6_0_d.h"
+#include "dce/dce_6_0_sh_mask.h"
+
+#define REG(reg_name)\
+ mm ## reg_name
+
+#include "reg_helper.h"
+#include "../hpd_regs.h"
+
+#define HPD_REG_LIST_DCE6(id) \
+ HPD_GPIO_REG_LIST(id), \
+ .int_status = mmDC_HPD ## id ## _INT_STATUS,\
+ .toggle_filt_cntl = mmDC_HPD ## id ## _TOGGLE_FILT_CNTL
+
+#define HPD_MASK_SH_LIST_DCE6(mask_sh) \
+ .DC_HPD_SENSE_DELAYED =
DC_HPD1_INT_STATUS__DC_HPD1_SENSE_DELAYED ## mask_sh,\
+ .DC_HPD_SENSE = DC_HPD1_INT_STATUS__DC_HPD1_SENSE ## mask_sh,\
+ .DC_HPD_CONNECT_INT_DELAY =
DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_CONNECT_INT_DELAY ## mask_sh,\
+ .DC_HPD_DISCONNECT_INT_DELAY =
DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_DISCONNECT_INT_DELAY ## mask_sh
+
+#define hpd_regs(id) \
+{\
+ HPD_REG_LIST_DCE6(id)\
+}
+
+static const struct hpd_registers hpd_regs[] = {
+ hpd_regs(1),
+ hpd_regs(2),
+ hpd_regs(3),
+ hpd_regs(4),
+ hpd_regs(5),
+ hpd_regs(6)
+};
+
+static const struct hpd_sh_mask hpd_shift = {
+ HPD_MASK_SH_LIST_DCE6(__SHIFT)
+};
+
+static const struct hpd_sh_mask hpd_mask = {
+ HPD_MASK_SH_LIST_DCE6(_MASK)
+};
+
+#include "../ddc_regs.h"
+
+ /* set field name */
+#define SF_DDC(reg_na
Re: [RFC] drm/amd/display: add SI support to AMD DC
Hi Harry,
thanks a lot for response,
On Mon, Oct 15, 2018 at 11:19 PM Harry Wentland wrote:
>
> On 2018-10-15 5:06 p.m., Harry Wentland wrote:
> > On 2018-10-14 5:47 p.m., Mauro Rossi wrote:
> >> Hi,
> >>
> >> reporting about some progress made during the weekend,
> >> thanks to Sylvain feedback & suggestions.
> >>
> >> I have rebased and updated the series on top of
> >> https://cgit.freedesktop.org/~agd5f/linux/?h=amd-staging-drm-next
> >>>> Here is the amd_dc_si branch:
> >> https://github.com/maurossi/linux/tree/amd_dc_si (uploading)
> >> NOTE: arch/x86/kernel/tsc.c changes for 4K display modes are not
> >> there, as they are not strictly needed for amd-gfx
> >>
>
>
> What updates do you have to your original series?
>
> If there are substantial updates can you send a v2 of your series?
The new v2 series is rebased on amd-staging-drm-next with following benefits:
- dce_clocks chipset families cases are not required anymore
- dcmu fw load for DCN1 has some SI cases added
- it is ready to be applied in amd-staging-drm-next
Not much changes compared to v1, but I'm about to submit v2 very soon.
>
> If not I'll go through the v1. The branch is great for review but email
> patches are easier for commenting.
This morning I've launched a build on v2 series, on
amd-staging-drm-next branch rebased on top of 4.19rc8
just to test it builds fine.
I'm sending the v2 series this evening and review may proceed on v2
amd-staging-drm-next context.
Mauro
>
>
> >> Copying also Harry, Alex, Christian and Mike in order to get some
> >> objective and infallible
> >> clues/feedbacks about blocking points and about "no care" items.
> >>
> >> Please, also big things I may have missed.
> >> M.
> >>
> >>> On Mon, Oct 8, 2018 at 11:23 PM wrote:
> >>>
> >>> Sylvain - I did hack a bit your patch set on amd-staging-drm-next to make
> >>> it go through the
> >>> asic init and I managed to get a x11 display with lines kind of garbled,
> >>> but
> >>> you can still understand easily what's on the screen.
> >>
> >> I forgot to mention that since I'm gorgeously trying AMD DC also on Mullins
> >> I have reverted d9fda24 (""drm/amdgpu: Don't default to DC support for
> >> Kaveri and older")
> >> because on Mullins I can boot with HDMI and HDMI-to-VGA converter
> >>
> >> I was hoping for AMD DC being re-enabled for Kaveri and older,
> >> but I'm available to submit new version of specific patch if required.
> >>
> >
> > I still need to find time to get through your patchset properly. Just a
> > quick note on this. There are Kabini/Kaveri ASICs with VGA connectors in
> > the market, which the DC code doesn't support. If someone writes it we can
> > re-enable it by default.
> >
> > Either way, you can revert that patch for your tree or use amdgpu.dc=0 as
> > long as you're aware that VGA won't work with amdgpu on such a kernel.
> >
> > Harry
> >
> >>> Sylvain - ... The lines may be garbled in your driver code because,
> >>> if I recall properly, "line buffer" programing in dce8 is not
> >>> the same than in dce6 (look for registers with the "LB" abbreviation). Or
> >>> some
> >>> slight differences in frame buffer tiling.
> >>
> >> So the problem could be related to some kind of scan line or tiling
> >> buffer issue,
> >> at the moment the dce_resouces model is grabbed "AS IS" from DCE8
> >> registers/masks
> >>
>
> We should probably update the DCE6 headers and use those. Sometimes register
> addresses change in subtle ways and cause problems later on that are hard to
> spot.
>
> >>>
> >>> Sylvain - I checked the kernel log, and like you said, I got errors in
> >>> DM_PPLIB due to an
> >>> invalid powerlevel and atombios/vbios table parsing regarding connectors.
> >>> general dpm is in amdgpu(no DC) for SI, it means the DCE related dpm part
> >>> in
> >>> current SI amdgpu code path should be "copied" in DC. It is related very
> >>> probably to the parsing of VBIOS/ATOMBIOS tables.
> >>
> >> 10-09 21:10:14.427 0 0 E :
> >> [drm:dm_pp_get_static_clocks [amdgpu]] *ERROR* DM_PPLIB: invalid
> >> powerlevel state: 0!
> >>
> >> NOTE: the error is the result of Powerplay dependency introduced by
> >> using AMD D
Re: [RFC] drm/amd/display: add SI support to AMD DC
Hi Harry,
in this thread some of the coding changes with open points,
as a checklist/track for review of upcoming (v2) patches.
M.
On Mon, Oct 15, 2018 at 11:06 PM Harry Wentland wrote:
>
> On 2018-10-14 5:47 p.m., Mauro Rossi wrote:
> > Hi,
> >
> > reporting about some progress made during the weekend,
> > thanks to Sylvain feedback & suggestions.
> >
> > I have rebased and updated the series on top of
> > https://cgit.freedesktop.org/~agd5f/linux/?h=amd-staging-drm-next
> >
> > Here is the amd_dc_si branch:
> > https://github.com/maurossi/linux/tree/amd_dc_si (uploading)
> > NOTE: arch/x86/kernel/tsc.c changes for 4K display modes are not
> > there, as they are not strictly needed for amd-gfx
> >
> > Copying also Harry, Alex, Christian and Mike in order to get some
> > objective and infallible
> > clues/feedbacks about blocking points and about "no care" items.
> >
> > Please, also big things I may have missed.
> > M.
> >
> >> On Mon, Oct 8, 2018 at 11:23 PM wrote:
> >>
> >> Sylvain - I did hack a bit your patch set on amd-staging-drm-next to make
> >> it go through the
> >> asic init and I managed to get a x11 display with lines kind of garbled,
> >> but
> >> you can still understand easily what's on the screen.
> >
> > I forgot to mention that since I'm gorgeously trying AMD DC also on Mullins
> > I have reverted d9fda24 (""drm/amdgpu: Don't default to DC support for
> > Kaveri and older")
> > because on Mullins I can boot with HDMI and HDMI-to-VGA converter
> >
> > I was hoping for AMD DC being re-enabled for Kaveri and older,
> > but I'm available to submit new version of specific patch if required.
> >
>
> I still need to find time to get through your patchset properly. Just a quick
> note on this. There are Kabini/Kaveri ASICs with VGA connectors in the
> market, which the DC code doesn't support. If someone writes it we can
> re-enable it by default.
>
> Either way, you can revert that patch for your tree or use amdgpu.dc=0 as
> long as you're aware that VGA won't work with amdgpu on such a kernel.
>
> Harry
At the moment I have reverted commit disabling DC for Kaveri, as I'm
using Acer ES1-521 which has HDMI output (with an HDMI-to-VGA
converter)
If it's not too complex, I could give it a try to have Kaveri working
for laptops with VGA output,
but from your judgment how complex is this task and which code paths
need to be touched?
If it is achievable by me, why not?
>
> >> Sylvain - ... The lines may be garbled in your driver code because,
> >> if I recall properly, "line buffer" programing in dce8 is not
> >> the same than in dce6 (look for registers with the "LB" abbreviation). Or
> >> some
> >> slight differences in frame buffer tiling.
> >
> > So the problem could be related to some kind of scan line or tiling
> > buffer issue,
> > at the moment the dce_resouces model is grabbed "AS IS" from DCE8
> > registers/masks
> >
I will check visually this evening the x11 line artifacts on HD7750 Cape Verde,
do you have any suggestion on top of Sylvain B. analysis?
> >>
> >> Sylvain - I checked the kernel log, and like you said, I got errors in
> >> DM_PPLIB due to an
> >> invalid powerlevel and atombios/vbios table parsing regarding connectors.
> >> general dpm is in amdgpu(no DC) for SI, it means the DCE related dpm part
> >> in
> >> current SI amdgpu code path should be "copied" in DC. It is related very
> >> probably to the parsing of VBIOS/ATOMBIOS tables.
> >
> > 10-09 21:10:14.427 0 0 E :
> > [drm:dm_pp_get_static_clocks [amdgpu]] *ERROR* DM_PPLIB: invalid
> > powerlevel state: 0!
> >
> > NOTE: the error is the result of Powerplay dependency introduced by
> > using AMD DC for SI
> > it's not fatal and it does not seem to affect performance in the Benchmarks
> >
> > DOUBT: I think that it would make sense to set "power level 0" i.e.
> > the "lower state" as safe default,
> > considering that powerplay smu6/hwmgr are not implemented for SI and
> > smu7 CIK functions do not work,
> > the AS-IS dpm is the only available option. (and it seams to be
> > working, looking at the framerates 250-280 in the V1 Vulkan benchmark)
> >
> >
> >
> >> 10-09 21:10:14.427 0 0 W [drm] dce110_link_encoder_construct:
> >> Failed to get encoder_cap_info from VBIOS with error code 4!
> >> 10-09 21:10:14.427 0 0 W [drm] dce1
[PATCH] WIP: drm/amd/display: dc/irq: use dce_6_0_{d,sh_mask}.h
Work In Progress for using DCE6 headers
vblank registers and masks where identified,
but using them gives a glipse with monitor screen active,
followed by monitor screen in standby
Please review to identify the problem
as the DCE6 vblank irq do not map exactlyto DC irq code,
it's not clear how to_dal_irq_source_dce60 should be defined and used
and it's not clear how to manage the DCE6 registers
in the following struct:
static const struct irq_source_info_funcs vblank_irq_info_funcs = {
.set = dce110_vblank_set,
.ack = NULL
};
---
.../display/dc/irq/dce60/irq_service_dce60.c | 116 +++---
.../display/dc/irq/dce60/irq_service_dce60.h | 5 +
.../drm/amd/include/asic_reg/dce/dce_6_0_d.h | 14 +++
.../include/asic_reg/dce/dce_6_0_sh_mask.h| 24
4 files changed, 145 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
b/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
index 107e0dcb5f80..c3befab49374 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
@@ -30,10 +30,17 @@
#include "irq_service_dce60.h"
#include "../dce110/irq_service_dce110.h"
-#include "dce/dce_8_0_d.h"
-#include "dce/dce_8_0_sh_mask.h"
-
+#include "dce/dce_6_0_d.h"
+#include "dce/dce_6_0_sh_mask.h"
+/* Q1: Are the DCE8 Interrupt Vector tables applicable to DCE6? */
#include "ivsrcid/ivsrcid_vislands30.h"
+/* See b10d51f8 ("drm/amd/display: Add interrupt entries for VBLANK isr.") */
+#define VISLANDS30_IV_SRCID_D1_VBLANK1
+#define VISLANDS30_IV_SRCID_D2_VBLANK2
+#define VISLANDS30_IV_SRCID_D3_VBLANK3
+#define VISLANDS30_IV_SRCID_D4_VBLANK4
+#define VISLANDS30_IV_SRCID_D5_VBLANK5
+#define VISLANDS30_IV_SRCID_D6_VBLANK6
#include "dc_types.h"
@@ -78,7 +85,7 @@ static const struct irq_source_info_funcs
pflip_irq_info_funcs = {
.set = NULL,
.ack = NULL
};
-
+ /* NOTE: .set = NULL in commit b10d51f8 Q2: Can dce110_vblank_set be used
here? */
static const struct irq_source_info_funcs vblank_irq_info_funcs = {
.set = dce110_vblank_set,
.ack = NULL
@@ -145,21 +152,21 @@ static const struct irq_source_info_funcs
vblank_irq_info_funcs = {
.funcs = _irq_info_funcs\
}
+/* NOTE: vblank_irq_info_funcs.set = dce110_vblank instead of NULL (see
b10d51f8) */
#define vblank_int_entry(reg_num)\
[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
- .enable_reg = mmCRTC ## reg_num ##
_CRTC_VERTICAL_INTERRUPT0_CONTROL,\
+ .enable_reg = mmLB ## reg_num ## _INT_MASK,\
.enable_mask =\
-
CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
+ INT_MASK__VBLANK_INT_MASK,\
.enable_value = {\
-
CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
-
~CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK},\
- .ack_reg = mmCRTC ## reg_num ##
_CRTC_VERTICAL_INTERRUPT0_CONTROL,\
+ INT_MASK__VBLANK_INT_MASK,\
+ ~INT_MASK__VBLANK_INT_MASK},\
+ .ack_reg = mmLB ## reg_num ## _VBLANK_STATUS,\
.ack_mask =\
-
CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\
+ VBLANK_STATUS__VBLANK_ACK_MASK,\
.ack_value =\
-
CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\
- .funcs = _irq_info_funcs,\
- .src_id = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 + reg_num\
+ VBLANK_STATUS__VBLANK_ACK_MASK,\
+ .funcs = _irq_info_funcs\
}
#define dummy_irq_entry() \
@@ -273,8 +280,89 @@ irq_source_info_dce60[DAL_IRQ_SOURCES_NUMBER] = {
vblank_int_entry(5),
};
+/* to_dal_irq_source_dce60 treats VBLANK differently from common dce110 one */
+enum dc_irq_source to_dal_irq_source_dce60(
+ struct irq_service *irq_service,
+ uint32_t src_id,
+ uint32_t ext_id)
+{
+ switch (src_id) {
+ case VISLANDS30_IV_SRCID_D1_VBLANK:
+ return DC_IRQ_SOURCE_VBLANK1;
+ case VISLANDS30_IV_SRCID_D2_VBLANK:
+ return DC_IRQ_SOURCE_VBLANK2;
+ case VISLANDS30_IV_SRCID_D3_VBLANK:
+ return DC_IRQ_SOURCE_VBLANK3;
+ case VISLANDS30_IV_SRCID_D4_VBLANK:
+ return DC_IRQ_SOURCE_VBLANK4;
+ case VISLANDS30_IV_SRCID_D5_VBLANK:
+ return DC_IRQ_SOURCE_VBLANK5;
+ case VISLANDS30_IV_SRCID_D6_VBLANK:
+ return DC_IRQ_SOURCE_VBLANK6;
+ case VISLANDS30_IV_SRCID_D1_V_UPDATE_INT:
+ return
Re: [PATCH] WIP: drm/amd/display: dc/irq: use dce_6_0_{d,sh_mask}.h
Hi,
just not to keep you engaged on this,
I've got the vblank irq handling working now.
I had exactly to replicate in dce60_irq_service.c the behavior of commit
b10d51f8 ("drm/amd/display: Add interrupt entries for VBLANK isr.")
and behavior of b57de80a ("drm/amd/display: Register on VLBLANK ISR.")
in amdgpu_dm.c
From functional point of view IRQ handling for DCE6 is complete,
I can proceed with other improvements, like Line Buffer/Watermark programming,
and VGA support for Kaveri and older.
Some suggestion those two areas by AMD developers would be very much
appreciated.
Kind regards
Mauro
On Wed, Jan 9, 2019 at 8:07 PM Mauro Rossi wrote:
>
> Ah-ha! (Meaning self-checking and trying to self-correct myself)
>
> I've seen that commit b10d51f8 ("drm/amd/display: Add interrupt
> entries for VBLANK isr.")
> required to be complemented by b57de80a ("drm/amd/display: Register on
> VLBLANK ISR.")
> which changed vblank irq control in dce110_register_irq_handlers() in file
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
>
> In this WIP I did not applied changes in amdgpu_dm_irq.c accordingly
> and this is the most probable root cause for screen being always blank
>
> I will specialize a dce60_register_irq_handlers()
> within braces #if defined(CONFIG_DRM_AMD_DC_SI)/#endif
> and replicate the behavior of b57de80a ("drm/amd/display: Register on
> VLBLANK ISR.")
>
> Please let me know if I'm at least going in the right direction
> and confirm that there is no other VBLANK Interrupt Register to be used in
> DCE6,
> if there is some other VBLANK Interrupt Register better than the one I found
> I'd like to know to implement directly the best solution.
>
> Mauro
>
> On Wed, Jan 2, 2019 at 1:12 AM Mauro Rossi wrote:
> >
> > Work In Progress for using DCE6 headers
> > vblank registers and masks where identified,
> > but using them gives a glipse with monitor screen active,
> > followed by monitor screen in standby
> >
> > Please review to identify the problem
> > as the DCE6 vblank irq do not map exactlyto DC irq code,
> > it's not clear how to_dal_irq_source_dce60 should be defined and used
> > and it's not clear how to manage the DCE6 registers
> > in the following struct:
> >
> > static const struct irq_source_info_funcs vblank_irq_info_funcs = {
> > .set = dce110_vblank_set,
> > .ack = NULL
> > };
> > ---
> > .../display/dc/irq/dce60/irq_service_dce60.c | 116 +++---
> > .../display/dc/irq/dce60/irq_service_dce60.h | 5 +
> > .../drm/amd/include/asic_reg/dce/dce_6_0_d.h | 14 +++
> > .../include/asic_reg/dce/dce_6_0_sh_mask.h| 24
> > 4 files changed, 145 insertions(+), 14 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
> > b/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
> > index 107e0dcb5f80..c3befab49374 100644
> > --- a/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
> > +++ b/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
> > @@ -30,10 +30,17 @@
> > #include "irq_service_dce60.h"
> > #include "../dce110/irq_service_dce110.h"
> >
> > -#include "dce/dce_8_0_d.h"
> > -#include "dce/dce_8_0_sh_mask.h"
> > -
> > +#include "dce/dce_6_0_d.h"
> > +#include "dce/dce_6_0_sh_mask.h"
> > +/* Q1: Are the DCE8 Interrupt Vector tables applicable to DCE6? */
> > #include "ivsrcid/ivsrcid_vislands30.h"
> > +/* See b10d51f8 ("drm/amd/display: Add interrupt entries for VBLANK isr.")
> > */
> > +#define VISLANDS30_IV_SRCID_D1_VBLANK1
> > +#define VISLANDS30_IV_SRCID_D2_VBLANK2
> > +#define VISLANDS30_IV_SRCID_D3_VBLANK3
> > +#define VISLANDS30_IV_SRCID_D4_VBLANK4
> > +#define VISLANDS30_IV_SRCID_D5_VBLANK5
> > +#define VISLANDS30_IV_SRCID_D6_VBLANK6
> >
> > #include "dc_types.h"
> >
> > @@ -78,7 +85,7 @@ static const struct irq_source_info_funcs
> > pflip_irq_info_funcs = {
> > .set = NULL,
> > .ack = NULL
> > };
> > -
> > + /* NOTE: .set = NULL in commit b10d51f8 Q2: Can dce110_vblank_set be used
> > here? */
> > static const struct irq_source_info_funcs vblank_irq_info_funcs = {
> > .set = dce110_vblank_set,
> > .ack = NULL
> > @@ -145,21 +152,21 @@ static const struct irq_so
Re: [PATCH] WIP: drm/amd/display: dc/irq: use dce_6_0_{d,sh_mask}.h
Ah-ha! (Meaning self-checking and trying to self-correct myself)
I've seen that commit b10d51f8 ("drm/amd/display: Add interrupt
entries for VBLANK isr.")
required to be complemented by b57de80a ("drm/amd/display: Register on
VLBLANK ISR.")
which changed vblank irq control in dce110_register_irq_handlers() in file
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
In this WIP I did not applied changes in amdgpu_dm_irq.c accordingly
and this is the most probable root cause for screen being always blank
I will specialize a dce60_register_irq_handlers()
within braces #if defined(CONFIG_DRM_AMD_DC_SI)/#endif
and replicate the behavior of b57de80a ("drm/amd/display: Register on
VLBLANK ISR.")
Please let me know if I'm at least going in the right direction
and confirm that there is no other VBLANK Interrupt Register to be used in DCE6,
if there is some other VBLANK Interrupt Register better than the one I found
I'd like to know to implement directly the best solution.
Mauro
On Wed, Jan 2, 2019 at 1:12 AM Mauro Rossi wrote:
>
> Work In Progress for using DCE6 headers
> vblank registers and masks where identified,
> but using them gives a glipse with monitor screen active,
> followed by monitor screen in standby
>
> Please review to identify the problem
> as the DCE6 vblank irq do not map exactlyto DC irq code,
> it's not clear how to_dal_irq_source_dce60 should be defined and used
> and it's not clear how to manage the DCE6 registers
> in the following struct:
>
> static const struct irq_source_info_funcs vblank_irq_info_funcs = {
> .set = dce110_vblank_set,
> .ack = NULL
> };
> ---
> .../display/dc/irq/dce60/irq_service_dce60.c | 116 +++---
> .../display/dc/irq/dce60/irq_service_dce60.h | 5 +
> .../drm/amd/include/asic_reg/dce/dce_6_0_d.h | 14 +++
> .../include/asic_reg/dce/dce_6_0_sh_mask.h| 24
> 4 files changed, 145 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
> b/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
> index 107e0dcb5f80..c3befab49374 100644
> --- a/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
> +++ b/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
> @@ -30,10 +30,17 @@
> #include "irq_service_dce60.h"
> #include "../dce110/irq_service_dce110.h"
>
> -#include "dce/dce_8_0_d.h"
> -#include "dce/dce_8_0_sh_mask.h"
> -
> +#include "dce/dce_6_0_d.h"
> +#include "dce/dce_6_0_sh_mask.h"
> +/* Q1: Are the DCE8 Interrupt Vector tables applicable to DCE6? */
> #include "ivsrcid/ivsrcid_vislands30.h"
> +/* See b10d51f8 ("drm/amd/display: Add interrupt entries for VBLANK isr.") */
> +#define VISLANDS30_IV_SRCID_D1_VBLANK1
> +#define VISLANDS30_IV_SRCID_D2_VBLANK2
> +#define VISLANDS30_IV_SRCID_D3_VBLANK3
> +#define VISLANDS30_IV_SRCID_D4_VBLANK4
> +#define VISLANDS30_IV_SRCID_D5_VBLANK5
> +#define VISLANDS30_IV_SRCID_D6_VBLANK6
>
> #include "dc_types.h"
>
> @@ -78,7 +85,7 @@ static const struct irq_source_info_funcs
> pflip_irq_info_funcs = {
> .set = NULL,
> .ack = NULL
> };
> -
> + /* NOTE: .set = NULL in commit b10d51f8 Q2: Can dce110_vblank_set be used
> here? */
> static const struct irq_source_info_funcs vblank_irq_info_funcs = {
> .set = dce110_vblank_set,
> .ack = NULL
> @@ -145,21 +152,21 @@ static const struct irq_source_info_funcs
> vblank_irq_info_funcs = {
> .funcs = _irq_info_funcs\
> }
>
> +/* NOTE: vblank_irq_info_funcs.set = dce110_vblank instead of NULL (see
> b10d51f8) */
> #define vblank_int_entry(reg_num)\
> [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
> - .enable_reg = mmCRTC ## reg_num ##
> _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
> + .enable_reg = mmLB ## reg_num ## _INT_MASK,\
> .enable_mask =\
> -
> CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
> + INT_MASK__VBLANK_INT_MASK,\
> .enable_value = {\
> -
> CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
> -
> ~CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK},\
> - .ack_reg = mmCRTC ## reg_num ##
> _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
> + INT_MASK__VBLANK_INT_MASK,\
> + ~INT_MASK__VBLANK_INT_MASK},\
> +
Re: [PATCH v2 02/10] drm/amd/display: dc/dce: add DCE6 support (v2)
Hi Harry,
On Wed, Oct 17, 2018 at 9:47 PM Wentland, Harry wrote:
>
> On 2018-10-17 4:35 a.m., Mauro Rossi wrote:
> > DCE6 targets are added replicating existing DCE8 implementation.
> >
> > NOTE: dce_8_0_{d,sh_mask}.h headers used instead of dce_6_0_{d,sh_mask}.h
> > only to build dce60_resource.c due to missing *_DCE60 macros/registers/masks
> >
> > IMPORTANT: Coding of dce60_resource.c requires review to understand
> > if dce_6_0_{d,sh_mask}.h should be updated with macros/registers/masks
> >
> > (v2) updated dce60_{hw_sequencer,resources}.c as per amd-staging-drm-next
> > removed dce_version cases in dc/dce/dce_clock_source.c
> > ---
> > drivers/gpu/drm/amd/display/dc/Makefile |4 +
> > drivers/gpu/drm/amd/display/dc/dce60/Makefile | 34 +
> > .../amd/display/dc/dce60/dce60_hw_sequencer.c | 82 +
> > .../amd/display/dc/dce60/dce60_hw_sequencer.h | 36 +
> > .../drm/amd/display/dc/dce60/dce60_resource.c | 1458 +
> > .../drm/amd/display/dc/dce60/dce60_resource.h | 47 +
> > .../display/dc/dce60/dce60_timing_generator.c | 242 +++
> > .../display/dc/dce60/dce60_timing_generator.h | 39 +
> > .../include/asic_reg/dce/dce_6_0_sh_mask.h|4 +
> > 9 files changed, 1946 insertions(+)
> > create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/Makefile
> > create mode 100644
> > drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c
> > create mode 100644
> > drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.h
> > create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c
> > create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.h
> > create mode 100644
> > drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c
> > create mode 100644
> > drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.h
> >
> > diff --git a/drivers/gpu/drm/amd/display/dc/Makefile
> > b/drivers/gpu/drm/amd/display/dc/Makefile
> > index aed538a4d1ba..d5d5acd57559 100644
> > --- a/drivers/gpu/drm/amd/display/dc/Makefile
> > +++ b/drivers/gpu/drm/amd/display/dc/Makefile
> > @@ -36,6 +36,10 @@ DC_LIBS += dce110
> > DC_LIBS += dce100
> > DC_LIBS += dce80
> >
> > +ifdef CONFIG_DRM_AMD_DC_SI
> > +DC_LIBS += dce60
> > +endif
> > +
> > AMD_DC = $(addsuffix /Makefile, $(addprefix
> > $(FULL_AMD_DISPLAY_PATH)/dc/,$(DC_LIBS)))
> >
> > include $(AMD_DC)
> > diff --git a/drivers/gpu/drm/amd/display/dc/dce60/Makefile
> > b/drivers/gpu/drm/amd/display/dc/dce60/Makefile
> > new file mode 100644
> > index ..39afd7c59a7c
> > --- /dev/null
> > +++ b/drivers/gpu/drm/amd/display/dc/dce60/Makefile
> > @@ -0,0 +1,34 @@
> > +#
> > +# Copyright 2017 Advanced Micro Devices, Inc.
> > +#
> > +# Permission is hereby granted, free of charge, to any person obtaining a
> > +# copy of this software and associated documentation files (the
> > "Software"),
> > +# to deal in the Software without restriction, including without limitation
> > +# the rights to use, copy, modify, merge, publish, distribute, sublicense,
> > +# and/or sell copies of the Software, and to permit persons to whom the
> > +# Software is furnished to do so, subject to the following conditions:
> > +#
> > +# The above copyright notice and this permission notice shall be included
> > in
> > +# all copies or substantial portions of the Software.
> > +#
> > +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
> > OR
> > +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> > +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> > +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> > +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > +# OTHER DEALINGS IN THE SOFTWARE.
> > +#
> > +#
> > +# Makefile for the 'controller' sub-component of DAL.
> > +# It provides the control and status of HW CRTC block.
> > +
> > +DCE60 = dce60_timing_generator.o dce60_hw_sequencer.o \
> > + dce60_resource.o
> > +
> > +AMD_DAL_DCE60 = $(addprefix $(AMDDALPATH)/dc/dce60/,$(DCE60))
> > +
> > +AMD_DISPLAY_FILES += $(AMD_DAL_DCE60)
> > +
> > +
> > +
> > diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c
> > b/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c
> > new
Raven: freeze at 'modprobe amdgpu' in early console with android-x86
Hello, I am having problem to load amdgpu module with Athlon 200GE, on a motherboard MSI B450M-A Pro Max with latest BIOS and a DVI-D monitor. The same HW setup boots Ubuntu 19.10 Gnome Desktop Environment with APU HW acceleration without any issue. When issueing the command 'modprobe amdgpu' in early console the screen just freezes, but I don't see any [drm] amdgpu output on the screen and the modesetting has clearly failed. I have tried with kernel 5.3, the same as the one used in Ubuntu 19.10, and replicated the %AMD% kernel config options extracted from Ubuntu. I have the same issue also with kernel 5.5rc7 and up to date linux-firmware. In case you have experienced or know about similar issues, could you please provide some info/suggestion for me to try to overcome the problem? Are there some implicit additional kernel config options required besides CONFIG_DRM_AMDGPU=m, CONFIG_AMD_DC=y, CONFIG_AMD_DC_DCN1_0=y, or some undocumented module dependencies, which are mandatory for the Raven APUs correct detection? Thanks for any info Mauro Rossi android-x86 team volunteer ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: Raven: freeze at 'modprobe amdgpu' in early console with android-x86
Hi Felix, On Mon, Jan 27, 2020 at 10:34 AM Felix Kuehling wrote: > > I've seen hangs on a Raven AM4 system after the Ubuntu upgrade to kernel > 5.3. I am able to work around it by disabling stutter mode with the > module parameter amdgpu.ppfeaturemask=0xfffdbfff. If that doesn't help, > you could also try disabling GFXOFF with amdgpu.ppfeaturemask=0xfffd3fff. > > Regards, >Felix I have tried with the grub kernel cmdline mentioned, but the freeze is still happening at 'modprobe amdgpu' Is there an explicit list of kernel module dependencies that I could check in our kernel defconfig? I have also added Qiang, in case he may have ever seen the issue in his former Android experience KR Mauro ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: Raven: freeze at 'modprobe amdgpu' in early console with android-x86
Hi, good news, 'modprobe amdgpu' is finally working with Athlon 200GE, on a motherboard MSI B450M-A Pro Max, with latest raven linux-firmware bundle for 19.50 Mauro On Tue, Feb 11, 2020 at 7:20 PM Mauro Rossi wrote: > Hi Felix, > > On Mon, Jan 27, 2020 at 10:34 AM Felix Kuehling > wrote: > > > > I've seen hangs on a Raven AM4 system after the Ubuntu upgrade to kernel > > 5.3. I am able to work around it by disabling stutter mode with the > > module parameter amdgpu.ppfeaturemask=0xfffdbfff. If that doesn't help, > > you could also try disabling GFXOFF with amdgpu.ppfeaturemask=0xfffd3fff. > > > > Regards, > >Felix > > I have tried with the grub kernel cmdline mentioned, but the freeze is > still happening at 'modprobe amdgpu' > > Is there an explicit list of kernel module dependencies that I could > check in our kernel defconfig? > > I have also added Qiang, in case he may have ever seen the issue in > his former Android experience > KR > > Mauro > ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amd/display: dc/clk_mgr: add support for SI parts (v3)
(v1) Changelog
[Why]
After commit c69dd2d "drm/amd/display: Refactor clk_mgr functions"
dc/clk_mgr requires these changes to add SI parts support
Necessary to avoid hitting default: ASSERT(0); /* Unknown Asic */
that would cause kernel freeze
[How]
Add case statement for FAMILY_SI chipsets
(v2) Changelog
[Why]
DCE6 has no DPREFCLK_CNTL register
[How]
Add DCE6 specific macros definitions for CLK registers and masks
Add DCE6 specific dce60/dce60_clk_mgr.c for DCE6 customization
Code style: reuse all the public functions in dce100/dce_clk_mgr.h header
Code style: use dce60_* static functions as per other DCE implementations
Add dce60_get_dp_ref_freq_khz() w/o using DPREFCLK_CNTL register
Use dce60_get_dp_ref_freq_khz() function in dce60_funcs
Add DCE6 specific dce60_clk_mgr_construct
dc/clk_mgr/dce_clk_mgr.c: use dce60_clk_mgr_construct for FAMILY_SI chipsets
Add Makefile rules for dce60_clk_mgr.o target conditional to
CONFIG_DRM_AMD_DC_SI
(v3) Changelog
[Why]
linux-next kernel test robot reported the following problem:
warning: no previous prototype for 'dce60_get_dp_ref_freq_khz'
[-Wmissing-prototypes]
[How]
mark dce60_get_dp_ref_freq_khz() as static
Fixes: 3ecb3b794e2 "drm/amd/display: dc/clk_mgr: add support for SI parts (v2)"
Reported-by: kernel test robot
Signed-off-by: Mauro Rossi
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
index c11c6b3a787d..0267644717b2 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
@@ -80,7 +80,7 @@ static const struct state_dependent_clocks
dce60_max_clks_by_state[] = {
/* ClocksStatePerformance */
{ .display_clk_khz = 60, .pixel_clk_khz = 40 } };
-int dce60_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)
+static int dce60_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)
{
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
int dprefclk_wdivider;
--
2.25.1
___
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re:
Hello, re-sending and copying full DL On Wed, Jul 22, 2020 at 4:51 AM Alex Deucher wrote: > On Mon, Jul 20, 2020 at 6:00 AM Mauro Rossi wrote: > > > > Hi Christian, > > > > On Mon, Jul 20, 2020 at 11:00 AM Christian König > > wrote: > > > > > > Hi Mauro, > > > > > > I'm not deep into the whole DC design, so just some general high level > > > comments on the cover letter: > > > > > > 1. Please add a subject line to the cover letter, my spam filter thinks > > > that this is suspicious otherwise. > > > > My mistake in the editing of covert letter with git send-email, > > I may have forgot to keep the Subject at the top > > > > > > > > 2. Then you should probably note how well (badly?) is that tested. > Since > > > you noted proof of concept it might not even work. > > > > The Changelog is to be read as: > > > > [RFC] was the initial Proof of concept was the RFC and [PATCH v2] was > > just a rebase onto amd-staging-drm-next > > > > this series [PATCH v3] has all the known changes required for DCE6 > specificity > > and based on a long offline thread with Alexander Deutcher and past > > dri-devel chats with Harry Wentland. > > > > It was tested for my possibilities of testing with HD7750 and HD7950, > > with checks in dmesg output for not getting "missing registers/masks" > > kernel WARNING > > and with kernel build on Ubuntu 20.04 and with android-x86 > > > > The proposal I made to Alex is that AMD testing systems will be used > > for further regression testing, > > as part of review and validation for eligibility to amd-staging-drm-next > > > > We will certainly test it once it lands, but presumably this is > working on the SI cards you have access to? > Yes, most of my testing was done with android-x86 Android CTS (EGL, GLES2, GLES3, VK) I am also in contact with a person with Firepro W5130M who is running a piglit session I had bought an HD7850 to test with Pitcairn, but it arrived as defective so I could not test with Pitcair > > > > > > 3. How feature complete (HDMI audio?, Freesync?) is it? > > > > All the changes in DC impacting DCE8 (dc/dce80 path) were ported to > > DCE6 (dc/dce60 path) in the last two years from initial submission > > > > > > > > Apart from that it looks like a rather impressive piece of work :) > > > > > > Cheers, > > > Christian. > > > > Thanks, > > please consider that most of the latest DCE6 specific parts were > > possible due to recent Alex support in getting the correct DCE6 > > headers, > > his suggestions and continuous feedback. > > > > I would suggest that Alex comments on the proposed next steps to follow. > > The code looks pretty good to me. I'd like to get some feedback from > the display team to see if they have any concerns, but beyond that I > think we can pull it into the tree and continue improving it there. > Do you have a link to a git tree I can pull directly that contains > these patches? Is this the right branch? > https://github.com/maurossi/linux/commits/kernel-5.8rc4_si_next > > Thanks! > > Alex > The following branch was pushed with the series on top of amd-staging-drm-next https://github.com/maurossi/linux/commits/kernel-5.6_si_drm-next > > > > > Mauro > > > > > > > > Am 16.07.20 um 23:22 schrieb Mauro Rossi: > > > > The series adds SI support to AMD DC > > > > > > > > Changelog: > > > > > > > > [RFC] > > > > Preliminar Proof Of Concept, with DCE8 headers still used in > dce60_resources.c > > > > > > > > [PATCH v2] > > > > Rebase on amd-staging-drm-next dated 17-Oct-2018 > > > > > > > > [PATCH v3] > > > > Add support for DCE6 specific headers, > > > > ad hoc DCE6 macros, funtions and fixes, > > > > rebase on current amd-staging-drm-next > > > > > > > > > > > > Commits [01/27]..[08/27] SI support added in various DC components > > > > > > > > [PATCH v3 01/27] drm/amdgpu: add some required DCE6 registers (v6) > > > > [PATCH v3 02/27] drm/amd/display: add asics info for SI parts > > > > [PATCH v3 03/27] drm/amd/display: dc/dce: add initial DCE6 support > (v9b) > > > > [PATCH v3 04/27] drm/amd/display: dc/core: add SI/DCE6 support (v2) > > > > [PATCH v3 05/27] drm/amd/display: dc/bios: add support for DCE6 > > > > [PATCH v3 06/27] drm/amd/display: d
Re:
On Mon, Jul 27, 2020 at 8:31 PM Alex Deucher wrote: > On Sun, Jul 26, 2020 at 11:31 AM Mauro Rossi > wrote: > > > > Hello, > > > > On Fri, Jul 24, 2020 at 8:31 PM Alex Deucher > wrote: > >> > >> On Wed, Jul 22, 2020 at 3:57 AM Mauro Rossi > wrote: > >> > > >> > Hello, > >> > re-sending and copying full DL > >> > > >> > On Wed, Jul 22, 2020 at 4:51 AM Alex Deucher > wrote: > >> >> > >> >> On Mon, Jul 20, 2020 at 6:00 AM Mauro Rossi > wrote: > >> >> > > >> >> > Hi Christian, > >> >> > > >> >> > On Mon, Jul 20, 2020 at 11:00 AM Christian König > >> >> > wrote: > >> >> > > > >> >> > > Hi Mauro, > >> >> > > > >> >> > > I'm not deep into the whole DC design, so just some general high > level > >> >> > > comments on the cover letter: > >> >> > > > >> >> > > 1. Please add a subject line to the cover letter, my spam filter > thinks > >> >> > > that this is suspicious otherwise. > >> >> > > >> >> > My mistake in the editing of covert letter with git send-email, > >> >> > I may have forgot to keep the Subject at the top > >> >> > > >> >> > > > >> >> > > 2. Then you should probably note how well (badly?) is that > tested. Since > >> >> > > you noted proof of concept it might not even work. > >> >> > > >> >> > The Changelog is to be read as: > >> >> > > >> >> > [RFC] was the initial Proof of concept was the RFC and [PATCH v2] > was > >> >> > just a rebase onto amd-staging-drm-next > >> >> > > >> >> > this series [PATCH v3] has all the known changes required for DCE6 > specificity > >> >> > and based on a long offline thread with Alexander Deutcher and past > >> >> > dri-devel chats with Harry Wentland. > >> >> > > >> >> > It was tested for my possibilities of testing with HD7750 and > HD7950, > >> >> > with checks in dmesg output for not getting "missing > registers/masks" > >> >> > kernel WARNING > >> >> > and with kernel build on Ubuntu 20.04 and with android-x86 > >> >> > > >> >> > The proposal I made to Alex is that AMD testing systems will be > used > >> >> > for further regression testing, > >> >> > as part of review and validation for eligibility to > amd-staging-drm-next > >> >> > > >> >> > >> >> We will certainly test it once it lands, but presumably this is > >> >> working on the SI cards you have access to? > >> > > >> > > >> > Yes, most of my testing was done with android-x86 Android CTS (EGL, > GLES2, GLES3, VK) > >> > > >> > I am also in contact with a person with Firepro W5130M who is running > a piglit session > >> > > >> > I had bought an HD7850 to test with Pitcairn, but it arrived as > defective so I could not test with Pitcair > >> > > >> > > >> >> > >> >> > > > >> >> > > 3. How feature complete (HDMI audio?, Freesync?) is it? > >> >> > > >> >> > All the changes in DC impacting DCE8 (dc/dce80 path) were ported to > >> >> > DCE6 (dc/dce60 path) in the last two years from initial submission > >> >> > > >> >> > > > >> >> > > Apart from that it looks like a rather impressive piece of work > :) > >> >> > > > >> >> > > Cheers, > >> >> > > Christian. > >> >> > > >> >> > Thanks, > >> >> > please consider that most of the latest DCE6 specific parts were > >> >> > possible due to recent Alex support in getting the correct DCE6 > >> >> > headers, > >> >> > his suggestions and continuous feedback. > >> >> > > >> >> > I would suggest that Alex comments on the proposed next steps to > follow. > >> >> > >> >> The code looks pretty good to me. I'd like to get some feedback from > >> >> the display team to see if they h
Re:
Hi Christian, On Mon, Jul 20, 2020 at 11:00 AM Christian König wrote: > > Hi Mauro, > > I'm not deep into the whole DC design, so just some general high level > comments on the cover letter: > > 1. Please add a subject line to the cover letter, my spam filter thinks > that this is suspicious otherwise. My mistake in the editing of covert letter with git send-email, I may have forgot to keep the Subject at the top > > 2. Then you should probably note how well (badly?) is that tested. Since > you noted proof of concept it might not even work. The Changelog is to be read as: [RFC] was the initial Proof of concept was the RFC and [PATCH v2] was just a rebase onto amd-staging-drm-next this series [PATCH v3] has all the known changes required for DCE6 specificity and based on a long offline thread with Alexander Deutcher and past dri-devel chats with Harry Wentland. It was tested for my possibilities of testing with HD7750 and HD7950, with checks in dmesg output for not getting "missing registers/masks" kernel WARNING and with kernel build on Ubuntu 20.04 and with android-x86 The proposal I made to Alex is that AMD testing systems will be used for further regression testing, as part of review and validation for eligibility to amd-staging-drm-next > > 3. How feature complete (HDMI audio?, Freesync?) is it? All the changes in DC impacting DCE8 (dc/dce80 path) were ported to DCE6 (dc/dce60 path) in the last two years from initial submission > > Apart from that it looks like a rather impressive piece of work :) > > Cheers, > Christian. Thanks, please consider that most of the latest DCE6 specific parts were possible due to recent Alex support in getting the correct DCE6 headers, his suggestions and continuous feedback. I would suggest that Alex comments on the proposed next steps to follow. Mauro > > Am 16.07.20 um 23:22 schrieb Mauro Rossi: > > The series adds SI support to AMD DC > > > > Changelog: > > > > [RFC] > > Preliminar Proof Of Concept, with DCE8 headers still used in > > dce60_resources.c > > > > [PATCH v2] > > Rebase on amd-staging-drm-next dated 17-Oct-2018 > > > > [PATCH v3] > > Add support for DCE6 specific headers, > > ad hoc DCE6 macros, funtions and fixes, > > rebase on current amd-staging-drm-next > > > > > > Commits [01/27]..[08/27] SI support added in various DC components > > > > [PATCH v3 01/27] drm/amdgpu: add some required DCE6 registers (v6) > > [PATCH v3 02/27] drm/amd/display: add asics info for SI parts > > [PATCH v3 03/27] drm/amd/display: dc/dce: add initial DCE6 support (v9b) > > [PATCH v3 04/27] drm/amd/display: dc/core: add SI/DCE6 support (v2) > > [PATCH v3 05/27] drm/amd/display: dc/bios: add support for DCE6 > > [PATCH v3 06/27] drm/amd/display: dc/gpio: add support for DCE6 (v2) > > [PATCH v3 07/27] drm/amd/display: dc/irq: add support for DCE6 (v4) > > [PATCH v3 08/27] drm/amd/display: amdgpu_dm: add SI support (v4) > > > > Commits [09/27]..[24/27] DCE6 specific code adaptions > > > > [PATCH v3 09/27] drm/amd/display: dc/clk_mgr: add support for SI parts (v2) > > [PATCH v3 10/27] drm/amd/display: dc/dce60: set max_cursor_size to 64 > > [PATCH v3 11/27] drm/amd/display: dce_audio: add DCE6 specific > > macros,functions > > [PATCH v3 12/27] drm/amd/display: dce_dmcu: add DCE6 specific macros > > [PATCH v3 13/27] drm/amd/display: dce_hwseq: add DCE6 specific > > macros,functions > > [PATCH v3 14/27] drm/amd/display: dce_ipp: add DCE6 specific > > macros,functions > > [PATCH v3 15/27] drm/amd/display: dce_link_encoder: add DCE6 specific > > macros,functions > > [PATCH v3 16/27] drm/amd/display: dce_mem_input: add DCE6 specific > > macros,functions > > [PATCH v3 17/27] drm/amd/display: dce_opp: add DCE6 specific > > macros,functions > > [PATCH v3 18/27] drm/amd/display: dce_transform: add DCE6 specific > > macros,functions > > [PATCH v3 19/27] drm/amdgpu: add some required DCE6 registers (v7) > > [PATCH v3 20/27] drm/amd/display: dce_transform: DCE6 Scaling Horizontal > > Filter Init > > [PATCH v3 21/27] drm/amd/display: dce60_hw_sequencer: add DCE6 > > macros,functions > > [PATCH v3 22/27] drm/amd/display: dce60_hw_sequencer: add DCE6 specific > > .cursor_lock > > [PATCH v3 23/27] drm/amd/display: dce60_timing_generator: add DCE6 specific > > functions > > [PATCH v3 24/27] drm/amd/display: dc/dce60: use DCE6 headers (v6) > > > > > > Commits [25/27]..[27/27] SI support final enablements > > > > [PATCH v3 25/27] drm/amd/display: create plane rotation property for > > Bonarie and later > > [PATCH
[PATCH v3 27/27] drm/amd/display: enable SI support in the Kconfig (v2)
[Why] All DCE6 specific code changes are guarded by CONFIG_DRM_AMD_DC_SI Kconfig option [How] (v1) CONFIG_DRM_AMD_DC_SI configuration option is added, default setting is disabled (v2) Hainan is not supported, description updated accordingly Tested with HD7750 (Cape Verde) and HD7950 (Tahiti) Signed-off-by: Mauro Rossi --- drivers/gpu/drm/amd/display/Kconfig | 8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig index 34ae4f3a32f4..77569097a480 100644 --- a/drivers/gpu/drm/amd/display/Kconfig +++ b/drivers/gpu/drm/amd/display/Kconfig @@ -31,6 +31,14 @@ config DRM_AMD_DC_HDCP help Choose this option if you want to support HDCP authentication. +config DRM_AMD_DC_SI + bool "AMD DC support for Southern Islands ASICs" + default n + help + Choose this option to enable new AMD DC support for SI asics + by default. This includes Tahiti, Pitcairn, Cape Verde, Oland. + Hainan is not supported by AMD DC and it has no physical DCE6. + config DEBUG_KERNEL_DC bool "Enable kgdb break in DC" depends on DRM_AMD_DC -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v3 22/27] drm/amd/display: dce60_hw_sequencer: add DCE6 specific .cursor_lock
[Why] kernel WARNING due to use of .cursor_lock = dce_pipe_control_lock inherited by dce110 [How] DCE6 set .cursor_lock = dce60_pipe_control_lock Signed-off-by: Mauro Rossi --- drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c index 37bd91883926..66e5a1ba2a58 100644 --- a/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c @@ -424,6 +424,7 @@ void dce60_hw_sequencer_construct(struct dc *dc) dc->hwseq->funcs.enable_display_power_gating = dce100_enable_display_power_gating; dc->hwss.apply_ctx_for_surface = dce60_apply_ctx_for_surface; + dc->hwss.cursor_lock = dce60_pipe_control_lock; dc->hwss.pipe_control_lock = dce60_pipe_control_lock; dc->hwss.prepare_bandwidth = dce100_prepare_bandwidth; dc->hwss.optimize_bandwidth = dce100_optimize_bandwidth; -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v3 14/27] drm/amd/display: dce_ipp: add DCE6 specific macros, functions
[Why]
DCE6 does not have CURSOR2_DEGAMMA_MODE bit in DEGAMMA_CONTROL register
[How]
Add DCE6 specific macros definitions for IPP masks
DCE6 IPP macros will avoid buiding errors when using DCE6 headers
Add dce60_ipp_set_degamma() function w/o Cursor2 Degamma programming
Use dce60_ipp_set_degamma() in ipp_funcs dce60_ipp_funcs
Add DCE6 specific dce60_ipp_construct
Signed-off-by: Mauro Rossi
---
drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c | 46 ++
drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h | 49
2 files changed, 95 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c
b/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c
index ce30dbf579d4..80569a2734eb 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c
@@ -231,6 +231,22 @@ static void dce_ipp_set_degamma(
CURSOR2_DEGAMMA_MODE, degamma_type);
}
+#if defined(CONFIG_DRM_AMD_DC_SI)
+static void dce60_ipp_set_degamma(
+ struct input_pixel_processor *ipp,
+ enum ipp_degamma_mode mode)
+{
+ struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp);
+ uint32_t degamma_type = (mode == IPP_DEGAMMA_MODE_HW_sRGB) ? 1 : 0;
+
+ ASSERT(mode == IPP_DEGAMMA_MODE_BYPASS || mode ==
IPP_DEGAMMA_MODE_HW_sRGB);
+ /* DCE6 does not have CURSOR2_DEGAMMA_MODE bit in DEGAMMA_CONTROL reg */
+ REG_SET_2(DEGAMMA_CONTROL, 0,
+ GRPH_DEGAMMA_MODE, degamma_type,
+ CURSOR_DEGAMMA_MODE, degamma_type);
+}
+#endif
+
static const struct ipp_funcs dce_ipp_funcs = {
.ipp_cursor_set_attributes = dce_ipp_cursor_set_attributes,
.ipp_cursor_set_position = dce_ipp_cursor_set_position,
@@ -239,6 +255,17 @@ static const struct ipp_funcs dce_ipp_funcs = {
.ipp_set_degamma = dce_ipp_set_degamma
};
+#if defined(CONFIG_DRM_AMD_DC_SI)
+static const struct ipp_funcs dce60_ipp_funcs = {
+ .ipp_cursor_set_attributes = dce_ipp_cursor_set_attributes,
+ .ipp_cursor_set_position = dce_ipp_cursor_set_position,
+ .ipp_program_prescale = dce_ipp_program_prescale,
+ .ipp_program_input_lut = dce_ipp_program_input_lut,
+ .ipp_set_degamma = dce60_ipp_set_degamma
+};
+#endif
+
+
/*/
/* Constructor, Destructor */
/*/
@@ -260,6 +287,25 @@ void dce_ipp_construct(
ipp_dce->ipp_mask = ipp_mask;
}
+#if defined(CONFIG_DRM_AMD_DC_SI)
+void dce60_ipp_construct(
+ struct dce_ipp *ipp_dce,
+ struct dc_context *ctx,
+ int inst,
+ const struct dce_ipp_registers *regs,
+ const struct dce_ipp_shift *ipp_shift,
+ const struct dce_ipp_mask *ipp_mask)
+{
+ ipp_dce->base.ctx = ctx;
+ ipp_dce->base.inst = inst;
+ ipp_dce->base.funcs = _ipp_funcs;
+
+ ipp_dce->regs = regs;
+ ipp_dce->ipp_shift = ipp_shift;
+ ipp_dce->ipp_mask = ipp_mask;
+}
+#endif
+
void dce_ipp_destroy(struct input_pixel_processor **ipp)
{
kfree(TO_DCE_IPP(*ipp));
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h
b/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h
index ca04e97d44c3..0028d4bdd81b 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h
@@ -147,6 +147,46 @@
IPP_SF(DCP0_DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, mask_sh), \
IPP_SF(DCP0_DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, mask_sh)
+#if defined(CONFIG_DRM_AMD_DC_SI)
+#define IPP_DCE60_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
+ IPP_SF(CUR_UPDATE, CURSOR_UPDATE_LOCK, mask_sh), \
+ IPP_SF(CUR_CONTROL, CURSOR_EN, mask_sh), \
+ IPP_SF(CUR_CONTROL, CURSOR_MODE, mask_sh), \
+ IPP_SF(CUR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \
+ IPP_SF(CUR_CONTROL, CUR_INV_TRANS_CLAMP, mask_sh), \
+ IPP_SF(CUR_POSITION, CURSOR_X_POSITION, mask_sh), \
+ IPP_SF(CUR_POSITION, CURSOR_Y_POSITION, mask_sh), \
+ IPP_SF(CUR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \
+ IPP_SF(CUR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
+ IPP_SF(CUR_COLOR1, CUR_COLOR1_BLUE, mask_sh), \
+ IPP_SF(CUR_COLOR1, CUR_COLOR1_GREEN, mask_sh), \
+ IPP_SF(CUR_COLOR1, CUR_COLOR1_RED, mask_sh), \
+ IPP_SF(CUR_COLOR2, CUR_COLOR2_BLUE, mask_sh), \
+ IPP_SF(CUR_COLOR2, CUR_COLOR2_GREEN, mask_sh), \
+ IPP_SF(CUR_COLOR2, CUR_COLOR2_RED, mask_sh), \
+ IPP_SF(CUR_SIZE, CURSOR_WIDTH, mask_sh), \
+ IPP_SF(CUR_SIZE, CURSOR_HEIGHT, mask_sh), \
+ IPP_SF(CUR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh),
\
+ IPP_SF(CUR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \
+ IPP_SF(PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, mask_sh), \
+ IPP_SF(PRESCALE_VALUES_GRPH_R, GRPH_PRESCALE_SCALE_R, mask_sh), \
+ IPP_SF(PRESCALE_VALUES_GRPH_R, GRPH_PRESCALE_BIAS_R, mask_sh), \
+ IPP_SF(PRESCALE_VALUES_GRPH_G, GRPH_PRES
[PATCH v3 06/27] drm/amd/display: dc/gpio: add support for DCE6 (v2)
[Why]
hw_factory.c requires changes for DCE6 support
[How]
DCE6 targets added replicating and adapting existing DCE8 implementation.
(v2) changes due to following commit:
91db931 ("drm/amd/display: refactor gpio to allocate hw_container in
constructor")
Signed-off-by: Mauro Rossi
---
drivers/gpu/drm/amd/display/dc/gpio/Makefile | 12 +
.../display/dc/gpio/dce60/hw_factory_dce60.c | 175
.../display/dc/gpio/dce60/hw_factory_dce60.h | 32 ++
.../dc/gpio/dce60/hw_translate_dce60.c| 411 ++
.../dc/gpio/dce60/hw_translate_dce60.h| 32 ++
.../gpu/drm/amd/display/dc/gpio/hw_factory.c | 10 +
.../drm/amd/display/dc/gpio/hw_translate.c| 10 +
7 files changed, 682 insertions(+)
create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.c
create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.h
create mode 100644
drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c
create mode 100644
drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.h
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/Makefile
b/drivers/gpu/drm/amd/display/dc/gpio/Makefile
index 0f2f4508e564..74c0943ed644 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/gpio/Makefile
@@ -30,6 +30,18 @@ AMD_DAL_GPIO = $(addprefix $(AMDDALPATH)/dc/gpio/,$(GPIO))
AMD_DISPLAY_FILES += $(AMD_DAL_GPIO)
+###
+# DCE 6x
+###
+# all DCE6.x are derived from DCE6.0
+ifdef CONFIG_DRM_AMD_DC_SI
+GPIO_DCE60 = hw_translate_dce60.o hw_factory_dce60.o
+
+AMD_DAL_GPIO_DCE60 = $(addprefix $(AMDDALPATH)/dc/gpio/dce60/,$(GPIO_DCE60))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCE60)
+endif
+
###
# DCE 8x
###
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.c
b/drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.c
new file mode 100644
index ..cc69acd8ada7
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.c
@@ -0,0 +1,175 @@
+/*
+ * Copyright 2020 Mauro Rossi
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+#include "include/gpio_types.h"
+#include "../hw_factory.h"
+
+#include "hw_factory_dce60.h"
+
+#include "../hw_gpio.h"
+#include "../hw_ddc.h"
+#include "../hw_hpd.h"
+#include "../hw_generic.h"
+
+#include "dce/dce_6_0_d.h"
+#include "dce/dce_6_0_sh_mask.h"
+
+
+#define REG(reg_name)\
+ mm ## reg_name
+
+#include "reg_helper.h"
+#include "../hpd_regs.h"
+
+#define HPD_REG_LIST_DCE6(id) \
+ HPD_GPIO_REG_LIST(id), \
+ .int_status = mmDC_HPD ## id ## _INT_STATUS,\
+ .toggle_filt_cntl = mmDC_HPD ## id ## _TOGGLE_FILT_CNTL
+
+#define HPD_MASK_SH_LIST_DCE6(mask_sh) \
+ .DC_HPD_SENSE_DELAYED =
DC_HPD1_INT_STATUS__DC_HPD1_SENSE_DELAYED ## mask_sh,\
+ .DC_HPD_SENSE = DC_HPD1_INT_STATUS__DC_HPD1_SENSE ## mask_sh,\
+ .DC_HPD_CONNECT_INT_DELAY =
DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_CONNECT_INT_DELAY ## mask_sh,\
+ .DC_HPD_DISCONNECT_INT_DELAY =
DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_DISCONNECT_INT_DELAY ## mask_sh
+
+#define hpd_regs(id) \
+{\
+ HPD_REG_LIST_DCE6(id)\
+}
+
+static const struct hpd_registers hpd_regs[] = {
+ hpd_regs(1),
+ hpd_regs(2),
+ hpd_regs(3),
+ hpd_regs(4),
+ hpd_regs(5),
+ hpd_regs(6)
+};
+
+static const struct hpd_sh_mask hpd_shift = {
+ HPD_MASK
[PATCH v3 02/27] drm/amd/display: add asics info for SI parts
[Why]
Asic info for SI parts need to be preliminarly added
[How]
Asics info retrieved from si_id.h in https://github.com/GPUOpen-Tools/CodeXL
Tree path:
./CodeXL/Components/ShaderAnalyzer/AMDTBackEnd/Include/Common/asic_reg/si_id.h
Signed-off-by: Mauro Rossi
---
.../gpu/drm/amd/display/include/dal_asic_id.h | 40 +++
.../gpu/drm/amd/display/include/dal_types.h | 3 ++
2 files changed, 43 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
index abeb58d544b1..b267987aed06 100644
--- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
@@ -30,6 +30,34 @@
* ASIC internal revision ID
*/
+/* DCE60 (based on si_id.h in GPUOpen-Tools CodeXL) */
+#define SI_TAHITI_P_A00x01
+#define SI_TAHITI_P_B00x05
+#define SI_TAHITI_P_B10x06
+#define SI_PITCAIRN_PM_A0 0x14
+#define SI_PITCAIRN_PM_A1 0x15
+#define SI_CAPEVERDE_M_A0 0x28
+#define SI_CAPEVERDE_M_A1 0x29
+#define SI_OLAND_M_A0 0x3C
+#define SI_HAINAN_V_A00x46
+
+#define SI_UNKNOWN0xFF
+
+#define ASIC_REV_IS_TAHITI_P(rev) \
+ ((rev >= SI_TAHITI_P_A0) && (rev < SI_PITCAIRN_PM_A0))
+
+#define ASIC_REV_IS_PITCAIRN_PM(rev) \
+ ((rev >= SI_PITCAIRN_PM_A0) && (rev < SI_CAPEVERDE_M_A0))
+
+#define ASIC_REV_IS_CAPEVERDE_M(rev) \
+ ((rev >= SI_CAPEVERDE_M_A0) && (rev < SI_OLAND_M_A0))
+
+#define ASIC_REV_IS_OLAND_M(rev) \
+ ((rev >= SI_OLAND_M_A0) && (rev < SI_HAINAN_V_A0))
+
+#define ASIC_REV_IS_HAINAN_V(rev) \
+ ((rev >= SI_HAINAN_V_A0) && (rev < SI_UNKNOWN))
+
/* DCE80 (based on ci_id.h in Perforce) */
#defineCI_BONAIRE_M_A0 0x14
#defineCI_BONAIRE_M_A1 0x15
@@ -181,6 +209,17 @@ enum {
/*
* ASIC chip ID
*/
+
+/* DCE60 */
+#define DEVICE_ID_SI_TAHITI_P_6780 0x6780
+#define DEVICE_ID_SI_PITCAIRN_PM_6800 0x6800
+#define DEVICE_ID_SI_PITCAIRN_PM_6808 0x6808
+#define DEVICE_ID_SI_CAPEVERDE_M_6820 0x6820
+#define DEVICE_ID_SI_CAPEVERDE_M_6828 0x6828
+#define DEVICE_ID_SI_OLAND_M_6600 0x6600
+#define DEVICE_ID_SI_OLAND_M_6608 0x6608
+#define DEVICE_ID_SI_HAINAN_V_6660 0x6660
+
/* DCE80 */
#define DEVICE_ID_KALINDI_9834 0x9834
#define DEVICE_ID_TEMASH_9839 0x9839
@@ -190,6 +229,7 @@ enum {
#define DEVICE_ID_RENOIR_1636 0x1636
/* Asic Family IDs for different asic family. */
+#define FAMILY_SI 110 /* Southern Islands: Tahiti (P), Pitcairn (PM), Cape
Verde (M), Oland (M), Hainan (V) */
#define FAMILY_CI 120 /* Sea Islands: Hawaii (P), Bonaire (M) */
#define FAMILY_KV 125 /* Fusion => Kaveri: Spectre, Spooky; Kabini: Kalindi */
#define FAMILY_VI 130 /* Volcanic Islands: Iceland (V), Tonga (M) */
diff --git a/drivers/gpu/drm/amd/display/include/dal_types.h
b/drivers/gpu/drm/amd/display/include/dal_types.h
index b67c9fa6b9cd..8aaa3af69202 100644
--- a/drivers/gpu/drm/amd/display/include/dal_types.h
+++ b/drivers/gpu/drm/amd/display/include/dal_types.h
@@ -34,6 +34,9 @@ struct dc_bios;
enum dce_version {
DCE_VERSION_UNKNOWN = (-1),
+ DCE_VERSION_6_0,
+ DCE_VERSION_6_1,
+ DCE_VERSION_6_4,
DCE_VERSION_8_0,
DCE_VERSION_8_1,
DCE_VERSION_8_3,
--
2.25.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v3 21/27] drm/amd/display: dce60_hw_sequencer: add DCE6 specific functions
[Why]
DCE6 has no bottom_pipe and no Blender HW
DCE6 needs 'blank_target' set to false in order to turn on the display
DCE6 has a specific dce60_pipe_control_lock() fuction that is a no op
[How]
Add DCE6 specific functions with needed private dce60_* dependent fuctions
Comment DCE6 specific CTRC program visibility implementation
Fix a typo in the initial header includes comment 's/DCE8/DCE6/g'
Use dce60_apply_ctx_for_surface() in dce60_hw_sequencer_construct
Use dce60_pipe_control_lock() in dce60_hw_sequencer_construct
Signed-off-by: Mauro Rossi
---
.../amd/display/dc/dce60/dce60_hw_sequencer.c | 381 +-
1 file changed, 379 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c
index e30e3510ec4a..37bd91883926 100644
--- a/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c
@@ -32,22 +32,399 @@
#include "dce110/dce110_hw_sequencer.h"
#include "dce100/dce100_hw_sequencer.h"
-/* include DCE8 register header files */
+/* include DCE6 register header files */
#include "dce/dce_6_0_d.h"
#include "dce/dce_6_0_sh_mask.h"
+#define DC_LOGGER_INIT()
+
/***
* Private definitions
**/
/***PIPE_CONTROL***/
+/*
+ * Check if FBC can be enabled
+ */
+static bool dce60_should_enable_fbc(struct dc *dc,
+ struct dc_state *context,
+ uint32_t *pipe_idx)
+{
+ uint32_t i;
+ struct pipe_ctx *pipe_ctx = NULL;
+ struct resource_context *res_ctx = >res_ctx;
+ unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
+
+
+ ASSERT(dc->fbc_compressor);
+
+ /* FBC memory should be allocated */
+ if (!dc->ctx->fbc_gpu_addr)
+ return false;
+
+ /* Only supports single display */
+ if (context->stream_count != 1)
+ return false;
+
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ if (res_ctx->pipe_ctx[i].stream) {
+
+ pipe_ctx = _ctx->pipe_ctx[i];
+
+ if (!pipe_ctx)
+ continue;
+
+ /* fbc not applicable on underlay pipe */
+ if (pipe_ctx->pipe_idx != underlay_idx) {
+ *pipe_idx = i;
+ break;
+ }
+ }
+ }
+
+ if (i == dc->res_pool->pipe_count)
+ return false;
+
+ if (!pipe_ctx->stream->link)
+ return false;
+
+ /* Only supports eDP */
+ if (pipe_ctx->stream->link->connector_signal != SIGNAL_TYPE_EDP)
+ return false;
+
+ /* PSR should not be enabled */
+ if (pipe_ctx->stream->link->psr_settings.psr_feature_enabled)
+ return false;
+
+ /* Nothing to compress */
+ if (!pipe_ctx->plane_state)
+ return false;
+
+ /* Only for non-linear tiling */
+ if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode ==
DC_ARRAY_LINEAR_GENERAL)
+ return false;
+
+ return true;
+}
+
+/*
+ * Enable FBC
+ */
+static void dce60_enable_fbc(
+ struct dc *dc,
+ struct dc_state *context)
+{
+ uint32_t pipe_idx = 0;
+
+ if (dce60_should_enable_fbc(dc, context, _idx)) {
+ /* Program GRPH COMPRESSED ADDRESS and PITCH */
+ struct compr_addr_and_pitch_params params = {0, 0, 0};
+ struct compressor *compr = dc->fbc_compressor;
+ struct pipe_ctx *pipe_ctx =
>res_ctx.pipe_ctx[pipe_idx];
+
+ params.source_view_width =
pipe_ctx->stream->timing.h_addressable;
+ params.source_view_height =
pipe_ctx->stream->timing.v_addressable;
+ params.inst = pipe_ctx->stream_res.tg->inst;
+ compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr;
+
+ compr->funcs->surface_address_and_pitch(compr, );
+ compr->funcs->set_fbc_invalidation_triggers(compr, 1);
+
+ compr->funcs->enable_fbc(compr, );
+ }
+}
+
+
+/***
+ * Front End programming
+
**/
+
+static void dce60_set_default_colors(struct pipe_ctx *pipe_ctx)
+{
+ struct default_adjustment default_adjust = { 0 };
+
+ default_adjust.force_hw_default = false;
+ default_adjust.i
[PATCH v3 16/27] drm/amd/display: dce_mem_input: add DCE6 specific macros, functions
[Why]
DCE6 has DPG_PIPE_ARBITRATION_CONTROL3 register for Line Buffer watermark
selection
DCE6 has STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK mask for Stutter watermark
selection
DCE6 has NB_PSTATE_CHANGE_WATERMARK_MASK mask for North Bridge watermark
selection
DCE6 has no GRPH_MICRO_TILE_MODE mask
DCE6 has no HW_ROTATION register
[How]
Add DCE6 specific macros definitions for MI registers and masks
Add DCE6 specific registers to dce_mem_input_registers struct
Add DCE6 specific masks to dce_mem_input_masks struct
DCE6 MI macros/structs changes will avoid buiding errors when using DCE6 headers
Add dce60_program_urgency_watermark() function
Add dce60_program_nbp_watermark() function
Add dce60_program_stutter_watermark() function
Add dce60_mi_program_display_marks() function w/ new DCE6 watermark programming
Add DCE6 specific tiling programming and modify DCE8 case
Add dce60_program_size() fuction w/o Rotation processing
Add dce60_mi_program_surface_config() fuction
Use dce60_mi_program_display_marks() in dce60_mi_funcs
Use dce60_mi_program_surface_config() in dce60_mi_funcs
Add DCE6 specific dce60_mem_input_construct
Signed-off-by: Mauro Rossi
---
.../drm/amd/display/dc/dce/dce_mem_input.c| 177 +-
.../drm/amd/display/dc/dce/dce_mem_input.h| 103 ++
2 files changed, 279 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
index 51481e922eb9..422a9fc61b71 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
@@ -174,6 +174,22 @@ static void program_urgency_watermark(
URGENCY_HIGH_WATERMARK, urgency_high_wm);
}
+#if defined(CONFIG_DRM_AMD_DC_SI)
+static void dce60_program_urgency_watermark(
+ struct dce_mem_input *dce_mi,
+ uint32_t wm_select,
+ uint32_t urgency_low_wm,
+ uint32_t urgency_high_wm)
+{
+ REG_UPDATE(DPG_PIPE_ARBITRATION_CONTROL3,
+ URGENCY_WATERMARK_MASK, wm_select);
+
+ REG_SET_2(DPG_PIPE_URGENCY_CONTROL, 0,
+ URGENCY_LOW_WATERMARK, urgency_low_wm,
+ URGENCY_HIGH_WATERMARK, urgency_high_wm);
+}
+#endif
+
static void dce120_program_urgency_watermark(
struct dce_mem_input *dce_mi,
uint32_t wm_select,
@@ -193,6 +209,25 @@ static void dce120_program_urgency_watermark(
}
+#if defined(CONFIG_DRM_AMD_DC_SI)
+static void dce60_program_nbp_watermark(
+ struct dce_mem_input *dce_mi,
+ uint32_t wm_select,
+ uint32_t nbp_wm)
+{
+ REG_UPDATE(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
+ NB_PSTATE_CHANGE_WATERMARK_MASK, wm_select);
+
+ REG_UPDATE_3(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
+ NB_PSTATE_CHANGE_ENABLE, 1,
+ NB_PSTATE_CHANGE_URGENT_DURING_REQUEST, 1,
+ NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST, 1);
+
+ REG_UPDATE(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
+ NB_PSTATE_CHANGE_WATERMARK, nbp_wm);
+}
+#endif
+
static void program_nbp_watermark(
struct dce_mem_input *dce_mi,
uint32_t wm_select,
@@ -225,6 +260,20 @@ static void program_nbp_watermark(
}
}
+#if defined(CONFIG_DRM_AMD_DC_SI)
+static void dce60_program_stutter_watermark(
+ struct dce_mem_input *dce_mi,
+ uint32_t wm_select,
+ uint32_t stutter_mark)
+{
+ REG_UPDATE(DPG_PIPE_STUTTER_CONTROL,
+ STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK, wm_select);
+
+ REG_UPDATE(DPG_PIPE_STUTTER_CONTROL,
+ STUTTER_EXIT_SELF_REFRESH_WATERMARK, stutter_mark);
+}
+#endif
+
static void dce120_program_stutter_watermark(
struct dce_mem_input *dce_mi,
uint32_t wm_select,
@@ -286,6 +335,34 @@ static void dce_mi_program_display_marks(
program_stutter_watermark(dce_mi, 1, stutter_exit.d_mark); /* set d */
}
+#if defined(CONFIG_DRM_AMD_DC_SI)
+static void dce60_mi_program_display_marks(
+ struct mem_input *mi,
+ struct dce_watermarks nbp,
+ struct dce_watermarks stutter_exit,
+ struct dce_watermarks stutter_enter,
+ struct dce_watermarks urgent,
+ uint32_t total_dest_line_time_ns)
+{
+ struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi);
+ uint32_t stutter_en = mi->ctx->dc->debug.disable_stutter ? 0 : 1;
+
+ dce60_program_urgency_watermark(dce_mi, 2, /* set a */
+ urgent.a_mark, total_dest_line_time_ns);
+ dce60_program_urgency_watermark(dce_mi, 1, /* set d */
+ urgent.d_mark, total_dest_line_time_ns);
+
+ REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL,
+ STUTTER_ENABLE, stutter_en,
+ STUTTER_IGNORE_FBC, 1);
+ dce60_program_nbp_watermark(dce_mi, 2, nbp.a_mark); /* set a */
+ dce60_program_nbp_watermark(dce_mi, 1, nbp.d_mark); /* set d */
+
+ dce60_program_stutter_watermark(dce_mi, 2, stutter_exit.a_mark
[PATCH v3 24/27] drm/amd/display: dc/dce60: use DCE6 headers (v6)
[Why]
With all DCE6 specific macros, register, masks in place
dce60_resource.c may use them and become independent from DCE8 headers
[How]
(v1) Changelog:
- use DCE6 headers for registers and masks, remove the DC8 headers
- remove 7th Display Controller/Encoder register instances (DCE6 has only 6)
- use DCE6 specific watermark programming registers
(DPG_PIPE_ARBITRATION_CONTROL3)
- use DCE6 specific input pixel processing registers shift/mask
- use DCE6 specific transform registers shift/mask
- use DCE6 specific link encoder registers shift/mask
- use DCE6 specific output pixel processing registers shift/mask
- use DCE6 specific audio registers shift/mask
- use DCE6 specific dmcu registers shift/mask
- use DCE6 specific hwseq registers shift/mask
- use DCE6 specific mem input registers shift/mask
(v2) Changelog:
- use DCE6 ad hoc dce60_mem_input_construct() function
- use DCE6 ad hoc dce60_transform_construct() function
(v3) Changelog:
- use DCE6 ad hoc dce60_ipp_construct() function
(v4) Changelog:
- use DCE6 ad hoc dce60_link_encoder_construct() function
(v5) Changelog:
- use DCE6 ad hoc dce60_opp_construct() function
(v6) Changelog:
- use DCE6 ad hoc dce60_audio_create() function
Signed-off-by: Mauro Rossi
---
.../drm/amd/display/dc/dce60/dce60_resource.c | 89 +--
1 file changed, 42 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c
b/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c
index 179f67ed7dbb..261333afc936 100644
--- a/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c
@@ -25,8 +25,8 @@
#include
-#include "dce/dce_8_0_d.h"
-#include "dce/dce_8_0_sh_mask.h"
+#include "dce/dce_6_0_d.h"
+#include "dce/dce_6_0_sh_mask.h"
#include "dm_services.h"
@@ -73,7 +73,6 @@
#define mmDP3_DP_DPHY_INTERNAL_CTRL 0x45DE
#define mmDP4_DP_DPHY_INTERNAL_CTRL 0x48DE
#define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4BDE
-#define mmDP6_DP_DPHY_INTERNAL_CTRL 0x4EDE
#endif
@@ -91,7 +90,6 @@
#define mmDP3_DP_DPHY_FAST_TRAINING 0x45CE
#define mmDP4_DP_DPHY_FAST_TRAINING 0x48CE
#define mmDP5_DP_DPHY_FAST_TRAINING 0x4BCE
- #define mmDP6_DP_DPHY_FAST_TRAINING 0x4ECE
#endif
@@ -113,38 +111,38 @@ static const struct dce110_timing_generator_offsets
dce60_tg_offsets[] = {
{
.crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
.dcp = (mmGRPH_CONTROL - mmGRPH_CONTROL),
- .dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL
- - mmDPG_WATERMARK_MASK_CONTROL),
+ .dmif = (mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL3
+ - mmDPG_PIPE_ARBITRATION_CONTROL3),
},
{
.crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
.dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
- .dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL
- - mmDPG_WATERMARK_MASK_CONTROL),
+ .dmif = (mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL3
+ - mmDPG_PIPE_ARBITRATION_CONTROL3),
},
{
.crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
.dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
- .dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL
- - mmDPG_WATERMARK_MASK_CONTROL),
+ .dmif = (mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL3
+ - mmDPG_PIPE_ARBITRATION_CONTROL3),
},
{
.crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
.dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
- .dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL
- - mmDPG_WATERMARK_MASK_CONTROL),
+ .dmif = (mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL3
+ - mmDPG_PIPE_ARBITRATION_CONTROL3),
},
{
.crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
.dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
- .dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL
- - mmDPG_WATERMARK_MASK_CONTROL),
+ .dmif = (mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL3
+ - mmDPG_PIPE_ARBITRATION_CONTROL3),
},
{
[PATCH v3 07/27] drm/amd/display: dc/irq: add support for DCE6 (v4)
[Why]
irq service requires changes for DCE6 support
[How]
(v1) DCE6 targets are added replicating existing DCE8 implementation.
due to missing CRTC_VERTICAL_INTERRUPT0_CONTROL registers/masks,
dce/dce_8_0_{d,sh_mask}.h used instead of dce/dce_6_0_{d,sh_mask}.h
(v2) DCE6 headers used adding the necessary vblank irq registers
(INT_MASK and VBLANK_STATUS) and vblank irq masks as implemented
in amdgpu driver.
Add vblank_irq_info_funcs_dce60 with .set and .ack as per commit
b10d51f ("drm/amd/display: Add interrupt entries for VBLANK isr.")
and use it in vblank_int_entry(reg_num) macro definition
(v3) updated due to following kernel 5.3 commit:
4fc4dca ("drm/amd: drop use of drmp.h in os_types.h")
(v4) updated due to following kernel 5.6 commit:
d9e3267 ("drm/amd/display: cleanup of construct and destruct funcs")
Signed-off-by: Mauro Rossi
---
drivers/gpu/drm/amd/display/dc/irq/Makefile | 11 +
.../display/dc/irq/dce60/irq_service_dce60.c | 395 ++
.../display/dc/irq/dce60/irq_service_dce60.h | 40 ++
.../gpu/drm/amd/display/dc/irq/irq_service.c | 3 +
4 files changed, 449 insertions(+)
create mode 100644 drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
create mode 100644 drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.h
diff --git a/drivers/gpu/drm/amd/display/dc/irq/Makefile
b/drivers/gpu/drm/amd/display/dc/irq/Makefile
index 3352b79fb1cb..405c25322607 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/irq/Makefile
@@ -30,6 +30,17 @@ AMD_DAL_IRQ = $(addprefix $(AMDDALPATH)/dc/irq/,$(IRQ))
AMD_DISPLAY_FILES += $(AMD_DAL_IRQ)
+###
+# DCE 6x
+###
+ifdef CONFIG_DRM_AMD_DC_SI
+IRQ_DCE60 = irq_service_dce60.o
+
+AMD_DAL_IRQ_DCE60 = $(addprefix $(AMDDALPATH)/dc/irq/dce60/,$(IRQ_DCE60))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCE60)
+endif
+
###
# DCE 8x
###
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
b/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
new file mode 100644
index ..524481885fd0
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
@@ -0,0 +1,395 @@
+/*
+ * Copyright 2020 Mauro Rossi
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include
+
+#include "dm_services.h"
+
+#include "include/logger_interface.h"
+
+#include "irq_service_dce60.h"
+#include "../dce110/irq_service_dce110.h"
+
+#include "dce/dce_6_0_d.h"
+#include "dce/dce_6_0_sh_mask.h"
+
+#include "ivsrcid/ivsrcid_vislands30.h"
+
+#define VISLANDS30_IV_SRCID_D1_VBLANK1
+#define VISLANDS30_IV_SRCID_D2_VBLANK2
+#define VISLANDS30_IV_SRCID_D3_VBLANK3
+#define VISLANDS30_IV_SRCID_D4_VBLANK4
+#define VISLANDS30_IV_SRCID_D5_VBLANK5
+#define VISLANDS30_IV_SRCID_D6_VBLANK6
+
+#include "dc_types.h"
+
+static bool hpd_ack(
+ struct irq_service *irq_service,
+ const struct irq_source_info *info)
+{
+ uint32_t addr = info->status_reg;
+ uint32_t value = dm_read_reg(irq_service->ctx, addr);
+ uint32_t current_status =
+ get_reg_field_value(
+ value,
+ DC_HPD1_INT_STATUS,
+ DC_HPD1_SENSE_DELAYED);
+
+ dal_irq_service_ack_generic(irq_service, info);
+
+ value = dm_re
[PATCH v3 03/27] drm/amd/display: dc/dce: add initial DCE6 support (v9b)
[Why]
DCE6 chipsets have a lot in common with DCE8, let's start from this
[How]
DCE6 targets are added replicating existing DCE8 implementation.
NOTE: dce_8_0_{d,sh_mask}.h headers used instead of dce_6_0_{d,sh_mask}.h
initial build prototype due to missing DCE6 macros/registers/masks
DCE6 specific macros/registers/masks will be added with later commits
(v2b) removed dce_version cases in dc/dce/dce_clock_source.c and
updated dce60 due to following kernel 5.0 commits:
24f7dd7 ("drm/amd/display: move pplib/smu notification to dccg block")
9566b67 ("drm/amd/display: remove safe_to_lower flag from dc, use 2
functions instead")
4244381 ("drm/amd/display: clean up base dccg struct")
4c5e8b5 ("drm/amd/display: split dccg clock manager into asic folders")
84e7fc0 ("drm/amd/display: rename dccg to clk_mgr")
77f6916 ("drm/amd/display: Remove duplicate header")
9f7ddbe ("drm/amd/display: fix optimize_bandwidth func pointer for dce80")
4ece61a ("drm/amd/display: set clocks to 0 on suspend on dce80")
(v3b) updated dce60 due to following kernel 5.1 commits:
380604e ("drm/amd/display: Use 100 Hz precision for pipe pixel clocks")
32e6136 ("drm/amd/display: Fix 64-bit division for 32-bit builds")
1877ccf ("drm/amd/display: Change from aux_engine to dce_aux")
c69dffa ("drm/amd/display: fix eDP fast bootup for pre-raven asic")
(v4b) updated dce60 due to following kernel 5.2 commits:
e5c4197 ("drm/amd/display: Add plane capabilities to dc_caps")
813d20d ("drm/amd/display: Fix multi-thread writing to 1 state")
ea36ad3 ("drm/amd/display: expand plane caps to include fp16 and scaling
capability")
afcd526 ("drm/amd/display: Add fast_validate parameter")
(v5b) updated dce60 due to following kernel 5.3 commits:
e7e10c4 ("drm/amd/display: stop external access to internal optc sync
params")
78cc70b ("drm/amd/display: Engine-specific encoder allocation")
dc88b4a ("drm/amd/display: make clk mgr soc specific")
4fc4dca ("drm/amd: drop use of drmp.h in os_types.h")
(v6b) updated dce60 due to following kernel 5.4 commits:
54a9bcb ("drm/amd/display: Fix a typo - dce_aduio_mask --> dce_audio_mask")
9adc805 ("drm/amd/display: make firmware info only load once during
dc_bios create")
(v7b) updated dce60 due to following kernel 5.5 commits:
cabe144 ("drm/amd/display: memory leak")
8276dd8 ("drm/amd/display: update register field access mechanism")
f6040a4 ("drm/amd/display: configurable aux timeout support")
bf7f5ac ("drm/amd/display: map TRANSMITTER_UNIPHY_x to LINK_REGS_x")
(v8b) updated dce60 due to following kernel 5.6 commits:
d9e3267 ("drm/amd/display: cleanup of construct and destruct funcs")
f42ea55 ("drm/amd/display: add separate of private hwss functions")
(v9b) updated dce60 due to following kernel 5.8 commits:
bba8289 ("drm/amd/display: code clean up in dce80_hw_sequencer.c")
904fb6e ("drm/amd/display: move panel power seq to new panel struct")
d4caa72 ("drm/amd/display: change from panel to panel cntl")
Signed-off-by: Mauro Rossi
---
drivers/gpu/drm/amd/display/dc/Makefile |4 +
drivers/gpu/drm/amd/display/dc/dce60/Makefile | 34 +
.../amd/display/dc/dce60/dce60_hw_sequencer.c | 54 +
.../amd/display/dc/dce60/dce60_hw_sequencer.h | 37 +
.../drm/amd/display/dc/dce60/dce60_resource.c | 1536 +
.../drm/amd/display/dc/dce60/dce60_resource.h | 47 +
.../display/dc/dce60/dce60_timing_generator.c | 247 +++
.../display/dc/dce60/dce60_timing_generator.h | 39 +
8 files changed, 1998 insertions(+)
create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/Makefile
create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.h
create mode 100644
drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c
create mode 100644
drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.h
diff --git a/drivers/gpu/drm/amd/display/dc/Makefile
b/drivers/gpu/drm/amd/display/dc/Makefile
index e0f4f1be1618..047b1e2dd8f1 100644
--- a/drivers/gpu/drm/amd/display/dc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/Makefile
@@ -43,6 +43,10 @@ DC_LIBS += dce110
DC_LIBS += dce100
DC_LIBS += dce80
+ifdef CONFIG_DRM_AMD_DC_SI
+DC_LIBS += dce60
+endif
+
ifdef CONFIG_DRM_AMD_DC_HDCP
DC_LIBS += hdcp
endif
diff --git a/drivers/gpu/drm/amd/display/dc/dce60/Makefile
b/drivers/gpu/drm/amd/d
[PATCH v3 15/27] drm/amd/display: dce_link_encoder: add DCE6 specific macros, functions
[Why]
DCE6 has no DP_DPHY_SCRAM_CNTL register
[How]
Add DCE6 specific macros definitions for LE registers
DCE6 LE macros will avoid buiding errors when using DCE6 headers
Add dce60_set_dp_phy_pattern_hbr2_compliance_cp2520_2() w/o Scramble Control
programming
Add dce60_set_dp_phy_pattern_passthrough_mode() w/o Scramble Control programming
Add dce60_configure_encoder() w/o Scramble Control programming
Add dce60_link_encoder_enable_dp_output() w/ dce60_configure_encoder
Add dce60_link_encoder_enable_dp_mst_output() w/ dce60_configure_encoder
Add dce60_link_encoder_dp_set_phy_pattern() w/
dce60_set_dp_phy_pattern_passthrough_mode
Use dce60_link_encoder_enable_dp_output() in dce60_lnk_enc_funcs
Use dce60_link_encoder_enable_dp_mst_output() in dce60_lnk_enc_funcs
Use dce60_link_encoder_dp_set_phy_pattern() in dce60_lnk_enc_funcs
Add DCE6 specific dce60_link_encoder_construct
Signed-off-by: Mauro Rossi
---
.../drm/amd/display/dc/dce/dce_link_encoder.c | 369 ++
.../drm/amd/display/dc/dce/dce_link_encoder.h | 38 ++
2 files changed, 407 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
index 8d8c84c81b34..b409f6b2bfd8 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
@@ -425,6 +425,59 @@ static void set_dp_phy_pattern_hbr2_compliance_cp2520_2(
enable_phy_bypass_mode(enc110, false);
}
+#if defined(CONFIG_DRM_AMD_DC_SI)
+static void dce60_set_dp_phy_pattern_hbr2_compliance_cp2520_2(
+ struct dce110_link_encoder *enc110,
+ unsigned int cp2520_pattern)
+{
+
+ /* previously there is a register DP_HBR2_EYE_PATTERN
+* that is enabled to get the pattern.
+* But it does not work with the latest spec change,
+* so we are programming the following registers manually.
+*
+* The following settings have been confirmed
+* by Nick Chorney and Sandra Liu */
+
+ /* Disable PHY Bypass mode to setup the test pattern */
+
+ enable_phy_bypass_mode(enc110, false);
+
+ /* Setup DIG encoder in DP SST mode */
+ enc110->base.funcs->setup(>base, SIGNAL_TYPE_DISPLAY_PORT);
+
+ /* ensure normal panel mode. */
+ setup_panel_mode(enc110, DP_PANEL_MODE_DEFAULT);
+
+ /* no vbid after BS (SR)
+* DP_LINK_FRAMING_CNTL changed history Sandra Liu
+* 11000260 / 11000104 / 11FC */
+ REG_UPDATE_3(DP_LINK_FRAMING_CNTL,
+ DP_IDLE_BS_INTERVAL, 0xFC,
+ DP_VBID_DISABLE, 1,
+ DP_VID_ENHANCED_FRAME_MODE, 1);
+
+ /* DCE6 has no DP_DPHY_SCRAM_CNTL register, skip swap BS with SR */
+
+ /* select cp2520 patterns */
+ if (REG(DP_DPHY_HBR2_PATTERN_CONTROL))
+ REG_UPDATE(DP_DPHY_HBR2_PATTERN_CONTROL,
+ DP_DPHY_HBR2_PATTERN_CONTROL, cp2520_pattern);
+ else
+ /* pre-DCE11 can only generate CP2520 pattern 2 */
+ ASSERT(cp2520_pattern == 2);
+
+ /* set link training complete */
+ set_link_training_complete(enc110, true);
+
+ /* disable video stream */
+ REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
+
+ /* Disable PHY Bypass mode to setup the test pattern */
+ enable_phy_bypass_mode(enc110, false);
+}
+#endif
+
static void set_dp_phy_pattern_passthrough_mode(
struct dce110_link_encoder *enc110,
enum dp_panel_mode panel_mode)
@@ -452,6 +505,35 @@ static void set_dp_phy_pattern_passthrough_mode(
disable_prbs_mode(enc110);
}
+#if defined(CONFIG_DRM_AMD_DC_SI)
+static void dce60_set_dp_phy_pattern_passthrough_mode(
+ struct dce110_link_encoder *enc110,
+ enum dp_panel_mode panel_mode)
+{
+ /* program correct panel mode */
+ setup_panel_mode(enc110, panel_mode);
+
+ /* restore LINK_FRAMING_CNTL
+* in case we were doing HBR2 compliance pattern before
+*/
+ REG_UPDATE_3(DP_LINK_FRAMING_CNTL,
+ DP_IDLE_BS_INTERVAL, 0x2000,
+ DP_VBID_DISABLE, 0,
+ DP_VID_ENHANCED_FRAME_MODE, 1);
+
+ /* DCE6 has no DP_DPHY_SCRAM_CNTL register, skip
DPHY_SCRAMBLER_BS_COUNT restore */
+
+ /* set link training complete */
+ set_link_training_complete(enc110, true);
+
+ /* Disable PHY Bypass mode to setup the test pattern */
+ enable_phy_bypass_mode(enc110, false);
+
+ /* Disable PRBS mode */
+ disable_prbs_mode(enc110);
+}
+#endif
+
/* return value is bit-vector */
static uint8_t get_frontend_source(
enum engine_id engine)
@@ -490,6 +572,20 @@ static void configure_encoder(
REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, 1);
}
+#if defined(CONFIG_DRM_AMD_DC_SI)
+static void dce60_configure_encoder(
+ struct dce110_link_encoder *enc110,
+
[PATCH v3 13/27] drm/amd/display: dce_hwseq: add DCE6 specific macros, functions
[Why]
DCE6 has no BLND_CONTROL register for Blender HW programming
DCE6 has no BLND_V_UPDATE_LOCK register for Pipe Locking
[How]
Add DCE6 specific macros definitions for HWSEQ registers and masks
DCE6 HWSEQ macros will avoid buiding errors when using DCE6 headers
Add dce60_pipe_control_lock() stub with no op
Signed-off-by: Mauro Rossi
---
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c | 9 +
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 18 ++
2 files changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
index e1c5839a80dc..4202fadb2c0e 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
@@ -85,6 +85,15 @@ void dce_pipe_control_lock(struct dc *dc,
}
}
+#if defined(CONFIG_DRM_AMD_DC_SI)
+void dce60_pipe_control_lock(struct dc *dc,
+ struct pipe_ctx *pipe,
+ bool lock)
+{
+ /* DCE6 has no BLND_V_UPDATE_LOCK register */
+}
+#endif
+
void dce_set_blender_mode(struct dce_hwseq *hws,
unsigned int blnd_inst,
enum blnd_mode mode)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index 66b88d6ba398..70bbc1311327 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -110,6 +110,12 @@
SR(BLNDV_CONTROL),\
HWSEQ_PIXEL_RATE_REG_LIST(CRTC)
+#if defined(CONFIG_DRM_AMD_DC_SI)
+#define HWSEQ_DCE6_REG_LIST() \
+ HWSEQ_DCEF_REG_LIST_DCE8(), \
+ HWSEQ_PIXEL_RATE_REG_LIST(CRTC)
+#endif
+
#define HWSEQ_DCE8_REG_LIST() \
HWSEQ_DCEF_REG_LIST_DCE8(), \
HWSEQ_BLND_REG_LIST(), \
@@ -488,6 +494,12 @@ struct dce_hwseq_registers {
HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE,
mask_sh),\
HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh)
+#if defined(CONFIG_DRM_AMD_DC_SI)
+#define HWSEQ_DCE6_MASK_SH_LIST(mask_sh)\
+ .DCFE_CLOCK_ENABLE = CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE ##
mask_sh, \
+ HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_)
+#endif
+
#define HWSEQ_DCE8_MASK_SH_LIST(mask_sh)\
.DCFE_CLOCK_ENABLE = CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE ##
mask_sh, \
HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\
@@ -836,6 +848,12 @@ void dce_pipe_control_lock(struct dc *dc,
void dce_set_blender_mode(struct dce_hwseq *hws,
unsigned int blnd_inst, enum blnd_mode mode);
+#if defined(CONFIG_DRM_AMD_DC_SI)
+void dce60_pipe_control_lock(struct dc *dc,
+ struct pipe_ctx *pipe,
+ bool lock);
+#endif
+
void dce_clock_gating_power_up(struct dce_hwseq *hws,
bool enable);
--
2.25.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v3 11/27] drm/amd/display: dce_audio: add DCE6 specific macros, functions
[Why]
DCE6 has no DCCG_AUDIO_DTO2_USE_512FBR_DTO mask in DCCG_AUDIO_DTO_SOURCE
register
[How]
Add DCE6 specific macros definitions for AUD masks
DCE6 AUD macros will avoid buiding errors when using DCE6 headers
Add dce60_aud_wall_dto_setup() w/o 512*Fs programming
Use dce60_aud_wall_dto_setup() in dce60_funcs
Add DCE specific dce60_audio_create
Signed-off-by: Mauro Rossi
---
.../gpu/drm/amd/display/dc/dce/dce_audio.c| 131 ++
.../gpu/drm/amd/display/dc/dce/dce_audio.h| 23 +++
2 files changed, 154 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
index 408046579712..2a2a0fdb9253 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
@@ -867,6 +867,98 @@ void dce_aud_wall_dto_setup(
}
}
+#if defined(CONFIG_DRM_AMD_DC_SI)
+void dce60_aud_wall_dto_setup(
+ struct audio *audio,
+ enum signal_type signal,
+ const struct audio_crtc_info *crtc_info,
+ const struct audio_pll_info *pll_info)
+{
+ struct dce_audio *aud = DCE_AUD(audio);
+
+ struct azalia_clock_info clock_info = { 0 };
+
+ if (dc_is_hdmi_signal(signal)) {
+ uint32_t src_sel;
+
+ /*DTO0 Programming goal:
+ -generate 24MHz, 128*Fs from 24MHz
+ -use DTO0 when an active HDMI port is connected
+ (optionally a DP is connected) */
+
+ /* calculate DTO settings */
+ get_azalia_clock_info_hdmi(
+ crtc_info->requested_pixel_clock_100Hz,
+ crtc_info->calculated_pixel_clock_100Hz,
+ _info);
+
+ DC_LOG_HW_AUDIO("\n%s:Input::requested_pixel_clock_100Hz = %d"\
+ "calculated_pixel_clock_100Hz =%d\n"\
+ "audio_dto_module = %d audio_dto_phase =%d
\n\n", __func__,\
+ crtc_info->requested_pixel_clock_100Hz,\
+ crtc_info->calculated_pixel_clock_100Hz,\
+ clock_info.audio_dto_module,\
+ clock_info.audio_dto_phase);
+
+ /* On TN/SI, Program DTO source select and DTO select before
+ programming DTO modulo and DTO phase. These bits must be
+ programmed first, otherwise there will be no HDMI audio at boot
+ up. This is a HW sequence change (different from old ASICs).
+ Caution when changing this programming sequence.
+
+ HDMI enabled, using DTO0
+ program master CRTC for DTO0 */
+ src_sel = pll_info->dto_source - DTO_SOURCE_ID0;
+ REG_UPDATE_2(DCCG_AUDIO_DTO_SOURCE,
+ DCCG_AUDIO_DTO0_SOURCE_SEL, src_sel,
+ DCCG_AUDIO_DTO_SEL, 0);
+
+ /* module */
+ REG_UPDATE(DCCG_AUDIO_DTO0_MODULE,
+ DCCG_AUDIO_DTO0_MODULE, clock_info.audio_dto_module);
+
+ /* phase */
+ REG_UPDATE(DCCG_AUDIO_DTO0_PHASE,
+ DCCG_AUDIO_DTO0_PHASE, clock_info.audio_dto_phase);
+ } else {
+ /*DTO1 Programming goal:
+ -generate 24MHz, 128*Fs from 24MHz (DCE6 does not support
512*Fs)
+ -default is to used DTO1, and switch to DTO0 when an audio
+ master HDMI port is connected
+ -use as default for DP
+
+ calculate DTO settings */
+ get_azalia_clock_info_dp(
+ crtc_info->requested_pixel_clock_100Hz,
+ pll_info,
+ _info);
+
+ /* Program DTO select before programming DTO modulo and DTO
+ phase. default to use DTO1 */
+
+ REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,
+ DCCG_AUDIO_DTO_SEL, 1);
+
+ /* DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1)
+* Cannot select 512fs for DP
+*
+* DCE6 has no DCCG_AUDIO_DTO2_USE_512FBR_DTO mask
+ */
+
+ /* module */
+ REG_UPDATE(DCCG_AUDIO_DTO1_MODULE,
+ DCCG_AUDIO_DTO1_MODULE,
clock_info.audio_dto_module);
+
+ /* phase */
+ REG_UPDATE(DCCG_AUDIO_DTO1_PHASE,
+ DCCG_AUDIO_DTO1_PHASE,
clock_info.audio_dto_phase);
+
+ /* DCE6 has no DCCG_AUDIO_DTO2_USE_512FBR_DTO mask in
DCCG_AUDIO_DTO_SOURCE reg */
+
+ }
+}
+#endif
+
static bool dce_aud_endpoint_valid(struct audio *audio)
{
uint32_t value;
@@ -926,6 +1018,19 @@ static const struct audio_funcs funcs = {
.az_configure = dce_aud_az_configure,
.destroy = dce_aud_destroy,
[PATCH v3 01/27] drm/amdgpu: add some required DCE6 registers (v6)
From: Alex Deucher To help with the DC port. v2: add missing masks, add additional registers v3: more updates v4: fix accidently dropped changes v5: add missing nb pstate mask v6: add vblank, vline masks Signed-off-by: Alex Deucher --- .../drm/amd/include/asic_reg/dce/dce_6_0_d.h | 62 - .../include/asic_reg/dce/dce_6_0_sh_mask.h| 92 +++ 2 files changed, 153 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h index ae798f768853..74897b046006 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h @@ -,14 +,74 @@ /* Registers that spilled out of sid.h */ #define mmDATA_FORMAT 0x1AC0 +#define mmLB0_DATA_FORMAT 0x1AC0 +#define mmLB1_DATA_FORMAT 0x1DC0 +#define mmLB2_DATA_FORMAT 0x40C0 +#define mmLB3_DATA_FORMAT 0x43C0 +#define mmLB4_DATA_FORMAT 0x46C0 +#define mmLB5_DATA_FORMAT 0x49C0 #define mmDESKTOP_HEIGHT 0x1AC1 +#define mmLB0_DESKTOP_HEIGHT0x1AC1 +#define mmLB1_DESKTOP_HEIGHT0x1DC1 +#define mmLB2_DESKTOP_HEIGHT0x40C1 +#define mmLB3_DESKTOP_HEIGHT0x43C1 +#define mmLB4_DESKTOP_HEIGHT0x46C1 +#define mmLB5_DESKTOP_HEIGHT0x49C1 #define mmDC_LB_MEMORY_SPLIT 0x1AC3 +#define mmLB0_DC_LB_MEMORY_SPLIT0x1AC3 +#define mmLB1_DC_LB_MEMORY_SPLIT0x1DC3 +#define mmLB2_DC_LB_MEMORY_SPLIT0x40C3 +#define mmLB3_DC_LB_MEMORY_SPLIT0x43C3 +#define mmLB4_DC_LB_MEMORY_SPLIT0x46C3 +#define mmLB5_DC_LB_MEMORY_SPLIT0x49C3 +#define mmDC_LB_MEM_SIZE0x1AC4 +#define mmLB0_DC_LB_MEM_SIZE0x1AC4 +#define mmLB1_DC_LB_MEM_SIZE0x1DC4 +#define mmLB2_DC_LB_MEM_SIZE0x40C4 +#define mmLB3_DC_LB_MEM_SIZE0x43C4 +#define mmLB4_DC_LB_MEM_SIZE0x46C4 +#define mmLB5_DC_LB_MEM_SIZE0x49C4 #define mmPRIORITY_A_CNT 0x1AC6 +#define mmLB0_PRIORITY_A_CNT0x1AC6 +#define mmLB1_PRIORITY_A_CNT0x1DC6 +#define mmLB2_PRIORITY_A_CNT0x40C6 +#define mmLB3_PRIORITY_A_CNT0x43C6 +#define mmLB4_PRIORITY_A_CNT0x46C6 +#define mmLB5_PRIORITY_A_CNT0x49C6 #define mmPRIORITY_B_CNT 0x1AC7 +#define mmLB0_PRIORITY_B_CNT0x1AC7 +#define mmLB1_PRIORITY_B_CNT0x1DC7 +#define mmLB2_PRIORITY_B_CNT0x40C7 +#define mmLB3_PRIORITY_B_CNT0x43C7 +#define mmLB4_PRIORITY_B_CNT0x46C7 +#define mmLB5_PRIORITY_B_CNT0x49C7 #define mmDPG_PIPE_ARBITRATION_CONTROL30x1B32 +#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL30x1B32 +#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL30x1E32 +#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL30x4132 +#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL30x4432 +#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL30x4732 +#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL30x4A32 #define mmINT_MASK 0x1AD0 +#define mmLB0_INT_MASK 0x1AD0 +#define mmLB1_INT_MASK 0x1DD0 +#define mmLB2_INT_MASK 0x40D0 +#define mmLB3_INT_MASK 0x43D0 +#define mmLB4_INT_MASK 0x46D0 +#define mmLB5_INT_MASK 0x49D0 #define mmVLINE_STATUS 0x1AEE +#define mmLB0_VLINE_STATUS 0x1AEE +#define mmLB1_VLINE_STATUS 0x1DEE +#define mmLB2_VLINE_STATUS 0x40EE +#define mmLB3_VLINE_STATUS 0x43EE +#define mmLB4_VLINE_STATUS 0x46EE +#define mmLB5_VLINE_STATUS 0x49EE #define mmVBLANK_STATUS0x1AEF - +#define mmLB0_VBLANK_STATUS 0x1AEF +#define mmLB1_VBLANK_STATUS 0x1DEF +#define mmLB2_VBLANK_STATUS
[PATCH v3 19/27] drm/amdgpu: add some required DCE6 registers (v7)
v7: add SCL_HORZ_FILTER_INIT regs --- .../gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h | 16 .../amd/include/asic_reg/dce/dce_6_0_sh_mask.h | 12 2 files changed, 28 insertions(+) diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h index 74897b046006..9de01ae574c0 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h @@ -4514,4 +4514,20 @@ #define mmLB4_VBLANK_STATUS 0x46EF #define mmLB5_VBLANK_STATUS 0x49EF +#define mmSCL_HORZ_FILTER_INIT_RGB_LUMA0x1B4C +#define mmSCL0_SCL_HORZ_FILTER_INIT_RGB_LUMA0x1B4C +#define mmSCL1_SCL_HORZ_FILTER_INIT_RGB_LUMA0x1E4C +#define mmSCL2_SCL_HORZ_FILTER_INIT_RGB_LUMA0x414C +#define mmSCL3_SCL_HORZ_FILTER_INIT_RGB_LUMA0x444C +#define mmSCL4_SCL_HORZ_FILTER_INIT_RGB_LUMA0x474C +#define mmSCL5_SCL_HORZ_FILTER_INIT_RGB_LUMA0x4A4C + +#define mmSCL_HORZ_FILTER_INIT_CHROMA 0x1B4D +#define mmSCL0_SCL_HORZ_FILTER_INIT_CHROMA 0x1B4D +#define mmSCL1_SCL_HORZ_FILTER_INIT_CHROMA 0x1E4D +#define mmSCL2_SCL_HORZ_FILTER_INIT_CHROMA 0x414D +#define mmSCL3_SCL_HORZ_FILTER_INIT_CHROMA 0x444D +#define mmSCL4_SCL_HORZ_FILTER_INIT_CHROMA 0x474D +#define mmSCL5_SCL_HORZ_FILTER_INIT_CHROMA 0x4A4D + #endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h index bf262460b0b9..41c4a46ce357 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h @@ -9926,5 +9926,17 @@ #define VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x0002L #defineVBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT0x0011 +// SCL_HORZ_FILTER_INIT_RGB_LUMA +#define SCL_HORZ_FILTER_INIT_RGB_LUMA__SCL_H_INIT_FRAC_RGB_Y_MASK 0xL +#defineSCL_HORZ_FILTER_INIT_RGB_LUMA__SCL_H_INIT_FRAC_RGB_Y__SHIFT 0x +#define SCL_HORZ_FILTER_INIT_RGB_LUMA__SCL_H_INIT_INT_RGB_Y_MASK 0x000fL +#defineSCL_HORZ_FILTER_INIT_RGB_LUMA__SCL_H_INIT_INT_RGB_Y__SHIFT 0x0010 + +// SCL_HORZ_FILTER_INIT_CHROMA +#define SCL_HORZ_FILTER_INIT_CHROMA__SCL_H_INIT_FRAC_CBCR_MASK 0xL +#defineSCL_HORZ_FILTER_INIT_CHROMA__SCL_H_INIT_FRAC_CBCR__SHIFT 0x +#define SCL_HORZ_FILTER_INIT_CHROMA__SCL_H_INIT_INT_CBCR_MASK 0x0007L +#defineSCL_HORZ_FILTER_INIT_CHROMA__SCL_H_INIT_INT_CBCR__SHIFT 0x0010 + #endif -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v3 08/27] drm/amd/display: amdgpu_dm: add SI support (v4)
[Why]
amdgpu_dm.c requires changes for SI chipsets init and irq handlers registration
[How]
SI support: load_dmcu_fw(), amdgpu_dm_initialize_drm_device(), dm_early_init()
Add DCE6 specific dce60_register_irq_handlers() function
(v1) NOTE: As per Kaveri and older amdgpu.dc=1 kernel cmdline is required
(v2) fix for bc011f9 ("drm/amdgpu: Change SI/CI gfx/sdma/smu init sequence")
remove CHIP_HAINAN support since it does not have physical DCE6 module
(v3) fix vblank irq support for DCE6 using ad hoc dce60_register_irq_handlers()
replicating for vblank irq the behavior of dce110_register_irq_handlers()
as per commit b57de80 ("drm/amd/display: Register on VLBLANK ISR.")
(v4) updated due to following kernel 5.2 commit:
b2fddb13 ("drm/amd/display: Drop underlay plane support")
Signed-off-by: Mauro Rossi
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 114 ++
1 file changed, 114 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 0bc333798cd6..df46cf7cb374 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1064,6 +1064,12 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
const struct dmcu_firmware_header_v1_0 *hdr;
switch(adev->asic_type) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+ case CHIP_TAHITI:
+ case CHIP_PITCAIRN:
+ case CHIP_VERDE:
+ case CHIP_OLAND:
+#endif
case CHIP_BONAIRE:
case CHIP_HAWAII:
case CHIP_KAVERI:
@@ -2472,6 +2478,89 @@ static void register_hpd_handlers(struct amdgpu_device
*adev)
}
}
+#if defined(CONFIG_DRM_AMD_DC_SI)
+/* Register IRQ sources and initialize IRQ callbacks */
+static int dce60_register_irq_handlers(struct amdgpu_device *adev)
+{
+ struct dc *dc = adev->dm.dc;
+ struct common_irq_params *c_irq_params;
+ struct dc_interrupt_params int_params = {0};
+ int r;
+ int i;
+ unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
+
+ int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
+ int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
+
+ /*
+* Actions of amdgpu_irq_add_id():
+* 1. Register a set() function with base driver.
+*Base driver will call set() function to enable/disable an
+*interrupt in DC hardware.
+* 2. Register amdgpu_dm_irq_handler().
+*Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
+*coming from DC hardware.
+*amdgpu_dm_irq_handler() will re-direct the interrupt to DC
+*for acknowledging and handling. */
+
+ /* Use VBLANK interrupt */
+ for (i = 0; i < adev->mode_info.num_crtc; i++) {
+ r = amdgpu_irq_add_id(adev, client_id, i+1 , >crtc_irq);
+ if (r) {
+ DRM_ERROR("Failed to add crtc irq id!\n");
+ return r;
+ }
+
+ int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
+ int_params.irq_source =
+ dc_interrupt_to_irq_source(dc, i+1 , 0);
+
+ c_irq_params = >dm.vblank_params[int_params.irq_source -
DC_IRQ_SOURCE_VBLANK1];
+
+ c_irq_params->adev = adev;
+ c_irq_params->irq_src = int_params.irq_source;
+
+ amdgpu_dm_irq_register_interrupt(adev, _params,
+ dm_crtc_high_irq, c_irq_params);
+ }
+
+ /* Use GRPH_PFLIP interrupt */
+ for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
+ i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
+ r = amdgpu_irq_add_id(adev, client_id, i, >pageflip_irq);
+ if (r) {
+ DRM_ERROR("Failed to add page flip irq id!\n");
+ return r;
+ }
+
+ int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
+ int_params.irq_source =
+ dc_interrupt_to_irq_source(dc, i, 0);
+
+ c_irq_params = >dm.pflip_params[int_params.irq_source -
DC_IRQ_SOURCE_PFLIP_FIRST];
+
+ c_irq_params->adev = adev;
+ c_irq_params->irq_src = int_params.irq_source;
+
+ amdgpu_dm_irq_register_interrupt(adev, _params,
+ dm_pflip_high_irq, c_irq_params);
+
+ }
+
+ /* HPD */
+ r = amdgpu_irq_add_id(adev, client_id,
+ VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, >hpd_irq);
+ if (r) {
+ DRM_ERROR("Failed to add hpd irq id!\n");
+ return r;
+ }
+
+ register_hpd_handlers(adev);
+
+ return 0;
+}
+#endif
+
/* Register IRQ sources and initialize IRQ callbacks */
st
[PATCH v3 18/27] drm/amd/display: dce_transform: add DCE6 specific macros, functions
[Why]
DCE6 has no SCL_MODE and no SCL_{HORZ,VERT}_FILTER_INIT registers
DCE6 has no SCL_BOUNDARY_MODE bit in SCL_CONTROL register
DCE6 has Line Buffer programming registers (DC_LB_MEMORY_SPLIT,DC_LB_MEM_SIZE)
DCE6 DATA_FORMAT register has only INTERLEAVE_EN bit
DCE6 has no Out Clamp Control programming registers (OUT_CLAMP_CONTROL_*)
[How]
Add DCE6 specific macros definitions for XFM registers and masks
Add DCE6 specific registers to dce_transform_registers struct
Add DCE6 specific masks to dce_transform_mask struct
DCE6 XFM macros/structs changes will avoid buiding errors when using DCE6
headers
Add dce60_setup_scaling_configuration() w/o missing Scaling registers/bit
programming
Add dce60_transform_set_scaler() using DCE6 Line Buffer programming registers
Add dce60_program_bit_depth_reduction() w/o Out Clamp Control programming
Add dce60_transform_set_pixel_storage_depth() use
dce60_program_bit_depth_reduction()
Use dce60_transform_set_scaler() in dce60_transform_funcs
Use dce60_transform_set_pixel_storage_depth() in dce60_transform_funcs
Add DCE6 specific dce60_transform_construct
Signed-off-by: Mauro Rossi
---
.../drm/amd/display/dc/dce/dce_transform.c| 268 ++
.../drm/amd/display/dc/dce/dce_transform.h| 150 ++
2 files changed, 418 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
index ab63d0d0304c..3303d01c1aae 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
@@ -146,6 +146,33 @@ static bool setup_scaling_configuration(
return true;
}
+#if defined(CONFIG_DRM_AMD_DC_SI)
+static bool dce60_setup_scaling_configuration(
+ struct dce_transform *xfm_dce,
+ const struct scaler_data *data)
+{
+ REG_SET(SCL_BYPASS_CONTROL, 0, SCL_BYPASS_MODE, 0);
+
+ if (data->taps.h_taps + data->taps.v_taps <= 2) {
+ /* Set bypass */
+
+ /* DCE6 has no SCL_MODE register, skip scale mode programming */
+
+ return false;
+ }
+
+ REG_SET_2(SCL_TAP_CONTROL, 0,
+ SCL_H_NUM_OF_TAPS, data->taps.h_taps - 1,
+ SCL_V_NUM_OF_TAPS, data->taps.v_taps - 1);
+
+ /* DCE6 has no SCL_MODE register, skip scale mode programming */
+
+ /* DCE6 has no SCL_BOUNDARY_MODE bit, skip replace out of bound pixels
*/
+
+ return true;
+}
+#endif
+
static void program_overscan(
struct dce_transform *xfm_dce,
const struct scaler_data *data)
@@ -399,6 +426,89 @@ static void dce_transform_set_scaler(
REG_UPDATE(LB_DATA_FORMAT, ALPHA_EN, data->lb_params.alpha_en);
}
+#if defined(CONFIG_DRM_AMD_DC_SI)
+static void dce60_transform_set_scaler(
+ struct transform *xfm,
+ const struct scaler_data *data)
+{
+ struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm);
+ bool is_scaling_required;
+ bool filter_updated = false;
+ const uint16_t *coeffs_v, *coeffs_h;
+
+ /*Use whole line buffer memory always*/
+ REG_SET(DC_LB_MEMORY_SPLIT, 0,
+ DC_LB_MEMORY_CONFIG, 0);
+
+ REG_SET(DC_LB_MEM_SIZE, 0,
+ DC_LB_MEM_SIZE, xfm_dce->lb_memory_size);
+
+ /* Clear SCL_F_SHARP_CONTROL value to 0 */
+ REG_WRITE(SCL_F_SHARP_CONTROL, 0);
+
+ /* 1. Program overscan */
+ program_overscan(xfm_dce, data);
+
+ /* 2. Program taps and configuration */
+ is_scaling_required = dce60_setup_scaling_configuration(xfm_dce, data);
+
+ if (is_scaling_required) {
+ /* 3. Calculate and program ratio, filter initialization */
+ struct scl_ratios_inits inits = { 0 };
+
+ calculate_inits(xfm_dce, data, );
+
+ program_scl_ratios_inits(xfm_dce, );
+
+ coeffs_v = get_filter_coeffs_16p(data->taps.v_taps,
data->ratios.vert);
+ coeffs_h = get_filter_coeffs_16p(data->taps.h_taps,
data->ratios.horz);
+
+ if (coeffs_v != xfm_dce->filter_v || coeffs_h !=
xfm_dce->filter_h) {
+ /* 4. Program vertical filters */
+ if (xfm_dce->filter_v == NULL)
+ REG_SET(SCL_VERT_FILTER_CONTROL, 0,
+ SCL_V_2TAP_HARDCODE_COEF_EN, 0);
+ program_multi_taps_filter(
+ xfm_dce,
+ data->taps.v_taps,
+ coeffs_v,
+ FILTER_TYPE_RGB_Y_VERTICAL);
+ program_multi_taps_filter(
+ xfm_dce,
+ data->taps.v_taps,
+ coeffs_v,
+ FILTER_TYPE
[PATCH v3 23/27] drm/amd/display: dce60_timing_generator: add DCE6 specific functions
[Why]
DCE6 has CRTC_PREFETCH_EN bit in CRTC_CONTROL register
DCE6 has no CRTC_LEGACY_REQUESTOR_EN bit in CRTC_START_LINE_CONTROL register
DCE6 has no CRTC_CRC_CNTL register
[How]
Modify dce60_timing_generator_enable_advanced_request() function
Add dce60_configure_crc() function and dce60_is_tg_enabled() kept as static
Use dce60_configure_crc() function in dce60_tg_funcs
Signed-off-by: Mauro Rossi
---
.../display/dc/dce60/dce60_timing_generator.c | 57 +--
.../amd/display/dc/inc/hw/clk_mgr_internal.h | 11
2 files changed, 50 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c
b/drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c
index eb9705e9d40a..4a5b7a0940c6 100644
--- a/drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c
@@ -128,20 +128,12 @@ static void
dce60_timing_generator_enable_advanced_request(
struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
uint32_t addr = CRTC_REG(mmCRTC_START_LINE_CONTROL);
uint32_t value = dm_read_reg(tg->ctx, addr);
+ /* DCE6 has CRTC_PREFETCH_EN bit in CRTC_CONTROL register */
+ uint32_t addr2 = CRTC_REG(mmCRTC_CONTROL);
+ uint32_t value2 = dm_read_reg(tg->ctx, addr2);
- if (enable) {
- set_reg_field_value(
- value,
- 0,
- CRTC_START_LINE_CONTROL,
- CRTC_LEGACY_REQUESTOR_EN);
- } else {
- set_reg_field_value(
- value,
- 1,
- CRTC_START_LINE_CONTROL,
- CRTC_LEGACY_REQUESTOR_EN);
- }
+ /* DCE6 does not support CRTC_LEGACY_REQUESTOR_EN bit
+ so here is not possible to set bit based on enable argument */
if ((timing->v_sync_width + timing->v_front_porch) <= 3) {
set_reg_field_value(
@@ -150,9 +142,9 @@ static void dce60_timing_generator_enable_advanced_request(
CRTC_START_LINE_CONTROL,
CRTC_ADVANCED_START_LINE_POSITION);
set_reg_field_value(
- value,
+ value2,
0,
- CRTC_START_LINE_CONTROL,
+ CRTC_CONTROL,
CRTC_PREFETCH_EN);
} else {
set_reg_field_value(
@@ -161,9 +153,9 @@ static void dce60_timing_generator_enable_advanced_request(
CRTC_START_LINE_CONTROL,
CRTC_ADVANCED_START_LINE_POSITION);
set_reg_field_value(
- value,
+ value2,
1,
- CRTC_START_LINE_CONTROL,
+ CRTC_CONTROL,
CRTC_PREFETCH_EN);
}
@@ -180,6 +172,35 @@ static void dce60_timing_generator_enable_advanced_request(
CRTC_INTERLACE_START_LINE_EARLY);
dm_write_reg(tg->ctx, addr, value);
+ dm_write_reg(tg->ctx, addr2, value2);
+}
+
+static bool dce60_is_tg_enabled(struct timing_generator *tg)
+{
+ uint32_t addr = 0;
+ uint32_t value = 0;
+ uint32_t field = 0;
+ struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
+
+ addr = CRTC_REG(mmCRTC_CONTROL);
+ value = dm_read_reg(tg->ctx, addr);
+ field = get_reg_field_value(value, CRTC_CONTROL,
+ CRTC_CURRENT_MASTER_EN_STATE);
+ return field == 1;
+}
+
+bool dce60_configure_crc(struct timing_generator *tg,
+ const struct crc_params *params)
+{
+ struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
+
+ /* Cannot configure crc on a CRTC that is disabled */
+ if (!dce60_is_tg_enabled(tg))
+ return false;
+
+ /* DCE6 has no CRTC_CRC_CNTL register, nothing to do */
+
+ return true;
}
static const struct timing_generator_funcs dce60_tg_funcs = {
@@ -217,7 +238,7 @@ static const struct timing_generator_funcs dce60_tg_funcs =
{
/* DCE6.0 overrides */
.enable_advanced_request =
dce60_timing_generator_enable_advanced_request,
- .configure_crc = dce110_configure_crc,
+ .configure_crc = dce60_configure_crc,
.get_crc = dce110_get_crc,
};
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
index 4e6e18bbef5d..ca9eedb643f2 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
@@ -88,6 +88,11 @@ enum dentist_divider_range {
.DPREFCLK_CNTL = mmDPREFCLK_CNTL, \
.DENTIST_DISPCLK_CNTL
[PATCH v3 17/27] drm/amd/display: dce_opp: add DCE6 specific macros, functions
[Why]
DCE6 has no FMT_TRUNCATE_MODE bit in FMT_BIT_DEPTH_CONTROL register
DCE6 has no FMT_CLAMP_COMPONENT_{R,G,B} registers
DCE6 has no FMT_SUBSAMPLING_{MODE,ORDER} bits in FMT_CONTROL register
[How]
Add DCE6 specific macros definitions for OPP registers and masks
DCE6 OPP macros will avoid buiding errors when using DCE6 headers
Add dce60_set_truncation() w/o FMT_TRUNCATE_MODE bit programming
Add dce60_opp_set_clamping() w/o Format Clamp Component programming
Add dce60_opp_program_fmt() w/o Format Subsampling bits programming
Add dce60_opp_program_bit_depth_reduction() with dce60_set_truncation
Use dce60_opp_program_fmt() in dce60_opp_funcs
Use dce60_opp_program_bit_depth_reduction() in dce60_opp_funcs
Add DCE6 specific dce60_opp_construct
Signed-off-by: Mauro Rossi
---
drivers/gpu/drm/amd/display/dc/dce/dce_opp.c | 205 +++
drivers/gpu/drm/amd/display/dc/dce/dce_opp.h | 49 +
2 files changed, 254 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
index 51081d9ae3fb..e459ae65aaf7 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
@@ -141,6 +141,47 @@ static void set_truncation(
params->flags.TRUNCATE_MODE);
}
+#if defined(CONFIG_DRM_AMD_DC_SI)
+/**
+ * dce60_set_truncation
+ * 1) set truncation depth: 0 for 18 bpp or 1 for 24 bpp
+ * 2) enable truncation
+ * 3) HW remove 12bit FMT support for DCE11 power saving reason.
+ */
+static void dce60_set_truncation(
+ struct dce110_opp *opp110,
+ const struct bit_depth_reduction_params *params)
+{
+ /* DCE6 has no FMT_TRUNCATE_MODE bit in FMT_BIT_DEPTH_CONTROL reg */
+
+ /*Disable truncation*/
+ REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL,
+ FMT_TRUNCATE_EN, 0,
+ FMT_TRUNCATE_DEPTH, 0);
+
+ if (params->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
+ /* 8bpc trunc on YCbCr422*/
+ if (params->flags.TRUNCATE_DEPTH == 1)
+ REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL,
+ FMT_TRUNCATE_EN, 1,
+ FMT_TRUNCATE_DEPTH, 1);
+ else if (params->flags.TRUNCATE_DEPTH == 2)
+ /* 10bpc trunc on YCbCr422*/
+ REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL,
+ FMT_TRUNCATE_EN, 1,
+ FMT_TRUNCATE_DEPTH, 2);
+ return;
+ }
+ /* on other format-to do */
+ if (params->flags.TRUNCATE_ENABLED == 0)
+ return;
+ /*Set truncation depth and Enable truncation*/
+ REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL,
+ FMT_TRUNCATE_EN, 1,
+ FMT_TRUNCATE_DEPTH,
+ params->flags.TRUNCATE_DEPTH);
+}
+#endif
/**
* set_spatial_dither
@@ -373,6 +414,57 @@ void dce110_opp_set_clamping(
}
}
+#if defined(CONFIG_DRM_AMD_DC_SI)
+/**
+ * Set Clamping for DCE6 parts
+ * 1) Set clamping format based on bpc - 0 for 6bpc (No clamping)
+ * 1 for 8 bpc
+ * 2 for 10 bpc
+ * 3 for 12 bpc
+ * 7 for programable
+ * 2) Enable clamp if Limited range requested
+ */
+void dce60_opp_set_clamping(
+ struct dce110_opp *opp110,
+ const struct clamping_and_pixel_encoding_params *params)
+{
+ REG_SET_2(FMT_CLAMP_CNTL, 0,
+ FMT_CLAMP_DATA_EN, 0,
+ FMT_CLAMP_COLOR_FORMAT, 0);
+
+ switch (params->clamping_level) {
+ case CLAMPING_FULL_RANGE:
+ break;
+ case CLAMPING_LIMITED_RANGE_8BPC:
+ REG_SET_2(FMT_CLAMP_CNTL, 0,
+ FMT_CLAMP_DATA_EN, 1,
+ FMT_CLAMP_COLOR_FORMAT, 1);
+ break;
+ case CLAMPING_LIMITED_RANGE_10BPC:
+ REG_SET_2(FMT_CLAMP_CNTL, 0,
+ FMT_CLAMP_DATA_EN, 1,
+ FMT_CLAMP_COLOR_FORMAT, 2);
+ break;
+ case CLAMPING_LIMITED_RANGE_12BPC:
+ REG_SET_2(FMT_CLAMP_CNTL, 0,
+ FMT_CLAMP_DATA_EN, 1,
+ FMT_CLAMP_COLOR_FORMAT, 3);
+ break;
+ case CLAMPING_LIMITED_RANGE_PROGRAMMABLE:
+ /*Set clamp control*/
+ REG_SET_2(FMT_CLAMP_CNTL, 0,
+ FMT_CLAMP_DATA_EN, 1,
+ FMT_CLAMP_COLOR_FORMAT, 7);
+
+ /* DCE6 does have FMT_CLAMP_COMPONENT_{R,G,B} registers */
+
+ break;
+ default:
+ break;
+ }
+}
+#endif
+
/**
* set_pixel_encoding
*
@@ -408,6 +500,39 @@ static void set_pixel_encoding(
}
+#if defined(CONFIG_DRM_AMD_DC_SI)
+/**
+ * dce60_set_pixel_enco
[PATCH v3 25/27] drm/amd/display: create plane rotation property for Bonaire and later
[Why] DCE6 chipsets do not support HW rotation [How] rotation property is created for Bonaire and later Signed-off-by: Mauro Rossi --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index df46cf7cb374..25ffa89d5657 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -6103,8 +6103,9 @@ static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270; - drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0, - supported_rotations); + if (dm->adev->asic_type >= CHIP_BONAIRE) + drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0, + supported_rotations); drm_plane_helper_add(plane, _plane_helper_funcs); -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v3 04/27] drm/amd/display: dc/core: add SI/DCE6 support (v2)
[Why]
resource_parse_asic_id() and dc_create_resource_pool() are missing SI/DCE6 cases
[How]
SI/DCE6 cases support added using existing DCE8 implementation as a reference
(v2) updated due to following kernel 5.2 commit:
d9673c9 ("drm/amd/display: Pass init_data into DCN resource creation")
Signed-off-by: Mauro Rossi
---
.../gpu/drm/amd/display/dc/core/dc_resource.c | 29 +++
1 file changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 7b5f90ebb133..ca26714c800e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -42,6 +42,9 @@
#include "virtual/virtual_stream_encoder.h"
#include "dpcd_defs.h"
+#if defined(CONFIG_DRM_AMD_DC_SI)
+#include "dce60/dce60_resource.h"
+#endif
#include "dce80/dce80_resource.h"
#include "dce100/dce100_resource.h"
#include "dce110/dce110_resource.h"
@@ -63,6 +66,18 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id
asic_id)
enum dce_version dc_version = DCE_VERSION_UNKNOWN;
switch (asic_id.chip_family) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+ case FAMILY_SI:
+ if (ASIC_REV_IS_TAHITI_P(asic_id.hw_internal_rev) ||
+ ASIC_REV_IS_PITCAIRN_PM(asic_id.hw_internal_rev) ||
+ ASIC_REV_IS_CAPEVERDE_M(asic_id.hw_internal_rev))
+ dc_version = DCE_VERSION_6_0;
+ else if (ASIC_REV_IS_OLAND_M(asic_id.hw_internal_rev))
+ dc_version = DCE_VERSION_6_4;
+ else
+ dc_version = DCE_VERSION_6_1;
+ break;
+#endif
case FAMILY_CI:
dc_version = DCE_VERSION_8_0;
break;
@@ -129,6 +144,20 @@ struct resource_pool *dc_create_resource_pool(struct dc
*dc,
struct resource_pool *res_pool = NULL;
switch (dc_version) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+ case DCE_VERSION_6_0:
+ res_pool = dce60_create_resource_pool(
+ init_data->num_virtual_links, dc);
+ break;
+ case DCE_VERSION_6_1:
+ res_pool = dce61_create_resource_pool(
+ init_data->num_virtual_links, dc);
+ break;
+ case DCE_VERSION_6_4:
+ res_pool = dce64_create_resource_pool(
+ init_data->num_virtual_links, dc);
+ break;
+#endif
case DCE_VERSION_8_0:
res_pool = dce80_create_resource_pool(
init_data->num_virtual_links, dc);
--
2.25.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v3 09/27] drm/amd/display: dc/clk_mgr: add support for SI parts (v2)
(v1) Changelog
[Why]
After commit c69dd2d "drm/amd/display: Refactor clk_mgr functions"
dc/clk_mgr requires these changes to add SI parts support
Necessary to avoid hitting default: ASSERT(0); /* Unknown Asic */
that would cause kernel freeze
[How]
Add case statement for FAMILY_SI chipsets
(v2) Changelog
[Why]
DCE6 has no DPREFCLK_CNTL register
[How]
Add DCE6 specific macros definitions for CLK registers and masks
Add DCE6 specific dce60/dce60_clk_mgr.c for DCE6 customization
Code style: reuse all the public functions in dce100/dce_clk_mgr.h header
Code style: use dce60_* static functions as per other DCE implementations
Add dce60_get_dp_ref_freq_khz() w/o using DPREFCLK_CNTL register
Use dce60_get_dp_ref_freq_khz() function in dce60_funcs
Add DCE6 specific dce60_clk_mgr_construct
dc/clk_mgr/dce_clk_mgr.c: use dce60_clk_mgr_construct for FAMILY_SI chipsets
Add Makefile rules for dce60_clk_mgr.o target conditional to
CONFIG_DRM_AMD_DC_SI
Signed-off-by: Mauro Rossi
---
.../gpu/drm/amd/display/dc/clk_mgr/Makefile | 11 ++
.../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 6 +
.../display/dc/clk_mgr/dce60/dce60_clk_mgr.c | 174 ++
.../display/dc/clk_mgr/dce60/dce60_clk_mgr.h | 36
4 files changed, 227 insertions(+)
create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.h
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
index 6874276bb2a1..52b1ce775a1e 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
@@ -30,6 +30,17 @@ AMD_DAL_CLK_MGR = $(addprefix
$(AMDDALPATH)/dc/clk_mgr/,$(CLK_MGR))
AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR)
+ifdef CONFIG_DRM_AMD_DC_SI
+###
+# DCE 60
+###
+CLK_MGR_DCE60 = dce60_clk_mgr.o
+
+AMD_DAL_CLK_MGR_DCE60 = $(addprefix
$(AMDDALPATH)/dc/clk_mgr/dce60/,$(CLK_MGR_DCE60))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCE60)
+endif
+
###
# DCE 100 and DCE8x
###
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
index 6a345d43028c..efb909ef7a0f 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
@@ -34,6 +34,7 @@
#include "dce110/dce110_clk_mgr.h"
#include "dce112/dce112_clk_mgr.h"
#include "dce120/dce120_clk_mgr.h"
+#include "dce60/dce60_clk_mgr.h"
#include "dcn10/rv1_clk_mgr.h"
#include "dcn10/rv2_clk_mgr.h"
#include "dcn20/dcn20_clk_mgr.h"
@@ -123,6 +124,11 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx,
struct pp_smu_funcs *p
}
switch (asic_id.chip_family) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+ case FAMILY_SI:
+ dce60_clk_mgr_construct(ctx, clk_mgr);
+ break;
+#endif
case FAMILY_CI:
case FAMILY_KV:
dce_clk_mgr_construct(ctx, clk_mgr);
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
new file mode 100644
index ..c11c6b3a787d
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
@@ -0,0 +1,174 @@
+/*
+ * Copyright 2020 Mauro Rossi
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+
+#include "dccg.h"
+#include "clk_mgr_internal.h"
+#include "dce100/dce_clk_mgr.h"
+#include &q
[PATCH v3 05/27] drm/amd/display: dc/bios: add support for DCE6
[Why]
command_table_helper.c requires changes for DCE6 support
[How]
DCE6 targets added replicating and adapting the existing DCE8 implementation.
Signed-off-by: Mauro Rossi
---
drivers/gpu/drm/amd/display/dc/bios/Makefile | 9 +
.../display/dc/bios/command_table_helper.c| 8 +
.../display/dc/bios/command_table_helper.h| 3 +
.../display/dc/bios/command_table_helper2.c | 8 +
.../display/dc/bios/command_table_helper2.h | 3 +
.../bios/dce60/command_table_helper_dce60.c | 354 ++
.../bios/dce60/command_table_helper_dce60.h | 33 ++
7 files changed, 418 insertions(+)
create mode 100644
drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c
create mode 100644
drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.h
diff --git a/drivers/gpu/drm/amd/display/dc/bios/Makefile
b/drivers/gpu/drm/amd/display/dc/bios/Makefile
index 239e86bbec5a..ed6b5e9763f6 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/bios/Makefile
@@ -31,6 +31,15 @@ AMD_DAL_BIOS = $(addprefix $(AMDDALPATH)/dc/bios/,$(BIOS))
AMD_DISPLAY_FILES += $(AMD_DAL_BIOS)
+###
+# DCE 6x
+###
+# All DCE6.x are derived from DCE6.0, so 6.0 MUST be defined if ANY of
+# DCE6.x is compiled.
+ifdef CONFIG_DRM_AMD_DC_SI
+AMD_DISPLAY_FILES += $(AMDDALPATH)/dc/bios/dce60/command_table_helper_dce60.o
+endif
+
###
# DCE 8x
###
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
index 253bbb1eea60..48b4ef03fc8f 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
@@ -36,6 +36,14 @@ bool dal_bios_parser_init_cmd_tbl_helper(
enum dce_version dce)
{
switch (dce) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+ case DCE_VERSION_6_0:
+ case DCE_VERSION_6_1:
+ case DCE_VERSION_6_4:
+ *h = dal_cmd_tbl_helper_dce60_get_table();
+ return true;
+#endif
+
case DCE_VERSION_8_0:
case DCE_VERSION_8_1:
case DCE_VERSION_8_3:
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h
b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h
index 4c3789df253d..dfd30aaf4032 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h
@@ -26,6 +26,9 @@
#ifndef __DAL_COMMAND_TABLE_HELPER_H__
#define __DAL_COMMAND_TABLE_HELPER_H__
+#if defined(CONFIG_DRM_AMD_DC_SI)
+#include "dce60/command_table_helper_dce60.h"
+#endif
#include "dce80/command_table_helper_dce80.h"
#include "dce110/command_table_helper_dce110.h"
#include "dce112/command_table_helper_dce112.h"
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
index 21ff6b686f5f..74c498b6774d 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
@@ -37,6 +37,14 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
enum dce_version dce)
{
switch (dce) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+ case DCE_VERSION_6_0:
+ case DCE_VERSION_6_1:
+ case DCE_VERSION_6_4:
+ *h = dal_cmd_tbl_helper_dce60_get_table();
+ return true;
+#endif
+
case DCE_VERSION_8_0:
case DCE_VERSION_8_1:
case DCE_VERSION_8_3:
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h
b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h
index 785fcb20a1b9..66e0a3e73768 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h
@@ -26,6 +26,9 @@
#ifndef __DAL_COMMAND_TABLE_HELPER2_H__
#define __DAL_COMMAND_TABLE_HELPER2_H__
+#if defined(CONFIG_DRM_AMD_DC_SI)
+#include "dce60/command_table_helper_dce60.h"
+#endif
#include "dce80/command_table_helper_dce80.h"
#include "dce110/command_table_helper_dce110.h"
#include "dce112/command_table_helper2_dce112.h"
diff --git
a/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c
b/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c
new file mode 100644
index ..710221b4f5c5
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c
@@ -0,0 +1,354 @@
+/*
+ * Copyright 2020 Mauro Rossi
+ *
+ * Permission is hereby granted, free of charge, to any
[PATCH v3 26/27] drm/amdgpu: enable DC support for SI parts (v2)
[Why]
amdgpu_device.c requires changes for SI chipsets support
si.c require changes for Display Manager IP block enabling
[How]
amdgpu_device.c: add SI families in amdgpu_device_asic_has_dc_support()
si.c: changes in si_set_ip_blocks() for Display Manager IP blocks enablement
(v1) NOTE: As per Kaveri and older amdgpu.dc=1 kernel cmdline is required
(v2) fix for bc011f9350 ("drm/amdgpu: Change SI/CI gfx/sdma/smu init sequence")
remove CHIP_HAINAN support since it does not have physical DCE6 module
Signed-off-by: Mauro Rossi
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 ++
drivers/gpu/drm/amd/amdgpu/si.c| 10 ++
2 files changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index aa5b54e5a1d7..cd5efa6c1c18 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2775,6 +2775,12 @@ bool amdgpu_device_asic_has_dc_support(enum
amd_asic_type asic_type)
{
switch (asic_type) {
#if defined(CONFIG_DRM_AMD_DC)
+#if defined(CONFIG_DRM_AMD_DC_SI)
+ case CHIP_TAHITI:
+ case CHIP_PITCAIRN:
+ case CHIP_VERDE:
+ case CHIP_OLAND:
+#endif
case CHIP_BONAIRE:
case CHIP_KAVERI:
case CHIP_KABINI:
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index 1b449291f068..5a112c7a35ca 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -52,6 +52,8 @@
#include "bif/bif_3_0_d.h"
#include "bif/bif_3_0_sh_mask.h"
+#include "amdgpu_dm.h"
+
static const u32 tahiti_golden_registers[] =
{
mmAZALIA_SCLK_CONTROL, 0x0030, 0x0011,
@@ -2546,6 +2548,10 @@ int si_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, _smu_ip_block);
if (adev->enable_virtual_display)
amdgpu_device_ip_block_add(adev, _virtual_ip_block);
+#if defined(CONFIG_DRM_AMD_DC) && defined(CONFIG_DRM_AMD_DC_SI)
+ else if (amdgpu_device_has_dc_support(adev))
+ amdgpu_device_ip_block_add(adev, _ip_block);
+#endif
else
amdgpu_device_ip_block_add(adev, _v6_0_ip_block);
amdgpu_device_ip_block_add(adev, _v3_1_ip_block);
@@ -2560,6 +2566,10 @@ int si_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, _smu_ip_block);
if (adev->enable_virtual_display)
amdgpu_device_ip_block_add(adev, _virtual_ip_block);
+#if defined(CONFIG_DRM_AMD_DC) && defined(CONFIG_DRM_AMD_DC_SI)
+ else if (amdgpu_device_has_dc_support(adev))
+ amdgpu_device_ip_block_add(adev, _ip_block);
+#endif
else
amdgpu_device_ip_block_add(adev, _v6_4_ip_block);
amdgpu_device_ip_block_add(adev, _v3_1_ip_block);
--
2.25.1
___
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v3 12/27] drm/amd/display: dce_dmcu: add DCE6 specific macros, functions
[Why] DCE6 has no SMU_INTERRUPT_CONTROL register, but it's used for DCN10 and later [How] Add DCE6 specific macros definitions for DMCU registers and masks DCE6 DMCU macros will avoid buiding errors when using DCE6 headers There is no other change needed in dce_dcmu Signed-off-by: Mauro Rossi --- drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h | 37 +++ 1 file changed, 37 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h index 5e044c2d3d6d..93e7f34d4775 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h @@ -46,6 +46,24 @@ SR(SMU_INTERRUPT_CONTROL), \ SR(DC_DMCU_SCRATCH) +#if defined(CONFIG_DRM_AMD_DC_SI) +#define DMCU_DCE60_REG_LIST() \ + SR(DMCU_CTRL), \ + SR(DMCU_STATUS), \ + SR(DMCU_RAM_ACCESS_CTRL), \ + SR(DMCU_IRAM_WR_CTRL), \ + SR(DMCU_IRAM_WR_DATA), \ + SR(MASTER_COMM_DATA_REG1), \ + SR(MASTER_COMM_DATA_REG2), \ + SR(MASTER_COMM_DATA_REG3), \ + SR(MASTER_COMM_CMD_REG), \ + SR(MASTER_COMM_CNTL_REG), \ + SR(DMCU_IRAM_RD_CTRL), \ + SR(DMCU_IRAM_RD_DATA), \ + SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \ + SR(DC_DMCU_SCRATCH) +#endif + #define DMCU_DCE80_REG_LIST() \ SR(DMCU_CTRL), \ SR(DMCU_STATUS), \ @@ -104,6 +122,25 @@ STATIC_SCREEN4_INT_TO_UC_EN, mask_sh), \ DMCU_SF(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, mask_sh) +#if defined(CONFIG_DRM_AMD_DC_SI) +#define DMCU_MASK_SH_LIST_DCE60(mask_sh) \ + DMCU_SF(DMCU_CTRL, \ + DMCU_ENABLE, mask_sh), \ + DMCU_SF(DMCU_STATUS, \ + UC_IN_STOP_MODE, mask_sh), \ + DMCU_SF(DMCU_STATUS, \ + UC_IN_RESET, mask_sh), \ + DMCU_SF(DMCU_RAM_ACCESS_CTRL, \ + IRAM_HOST_ACCESS_EN, mask_sh), \ + DMCU_SF(DMCU_RAM_ACCESS_CTRL, \ + IRAM_WR_ADDR_AUTO_INC, mask_sh), \ + DMCU_SF(DMCU_RAM_ACCESS_CTRL, \ + IRAM_RD_ADDR_AUTO_INC, mask_sh), \ + DMCU_SF(MASTER_COMM_CMD_REG, \ + MASTER_COMM_CMD_REG_BYTE0, mask_sh), \ + DMCU_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh) +#endif + #define DMCU_MASK_SH_LIST_DCE80(mask_sh) \ DMCU_SF(DMCU_CTRL, \ DMCU_ENABLE, mask_sh), \ -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v3 20/27] drm/amd/display: dce_transform: DCE6 Scaling Horizontal Filter Init
[Why]
DCE6 has specific SCL_HORZ_FILTER_INIT_{LUMA_RGB,CHROMA} registers
In DCE6 h_init_luma and h_init_chroma initialization is required
Some DCE6 specific SCL_{HORZ,VERT}_FILTER_CONTROL masks were not listed
[How]
Add the registers and masks in dce_transform.h
Add DCE6 specific struct sclh_ratios_inits in dce_transform.h
Add dce60_calculate_inits() function
Add dce60_program_scl_ratios_inits() function
Fix dce60_transform_set_scaler() function
Signed-off-by: Mauro Rossi
---
.../drm/amd/display/dc/dce/dce_transform.c| 73 +--
.../drm/amd/display/dc/dce/dce_transform.h| 28 +++
2 files changed, 96 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
index 3303d01c1aae..51ad48e36a8a 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
@@ -306,6 +306,37 @@ static void calculate_inits(
inits->v_init.fraction = dc_fixpt_u0d19(v_init) << 5;
}
+#if defined(CONFIG_DRM_AMD_DC_SI)
+static void dce60_calculate_inits(
+ struct dce_transform *xfm_dce,
+ const struct scaler_data *data,
+ struct sclh_ratios_inits *inits)
+{
+ struct fixed31_32 h_init;
+ struct fixed31_32 v_init;
+
+ inits->h_int_scale_ratio =
+ dc_fixpt_u2d19(data->ratios.horz) << 5;
+ inits->v_int_scale_ratio =
+ dc_fixpt_u2d19(data->ratios.vert) << 5;
+
+ /* DCE6 h_init_luma setting inspired by DCE110 */
+ inits->h_init_luma.integer = 1;
+
+ /* DCE6 h_init_chroma setting inspired by DCE110 */
+ inits->h_init_chroma.integer = 1;
+
+ v_init =
+ dc_fixpt_div_int(
+ dc_fixpt_add(
+ data->ratios.vert,
+ dc_fixpt_from_int(data->taps.v_taps + 1)),
+ 2);
+ inits->v_init.integer = dc_fixpt_floor(v_init);
+ inits->v_init.fraction = dc_fixpt_u0d19(v_init) << 5;
+}
+#endif
+
static void program_scl_ratios_inits(
struct dce_transform *xfm_dce,
struct scl_ratios_inits *inits)
@@ -328,6 +359,36 @@ static void program_scl_ratios_inits(
REG_WRITE(SCL_AUTOMATIC_MODE_CONTROL, 0);
}
+#if defined(CONFIG_DRM_AMD_DC_SI)
+static void dce60_program_scl_ratios_inits(
+ struct dce_transform *xfm_dce,
+ struct sclh_ratios_inits *inits)
+{
+
+ REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0,
+ SCL_H_SCALE_RATIO, inits->h_int_scale_ratio);
+
+ REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0,
+ SCL_V_SCALE_RATIO, inits->v_int_scale_ratio);
+
+ /* DCE6 has SCL_HORZ_FILTER_INIT_RGB_LUMA register */
+ REG_SET_2(SCL_HORZ_FILTER_INIT_RGB_LUMA, 0,
+ SCL_H_INIT_INT_RGB_Y, inits->h_init_luma.integer,
+ SCL_H_INIT_FRAC_RGB_Y, inits->h_init_luma.fraction);
+
+ /* DCE6 has SCL_HORZ_FILTER_INIT_CHROMA register */
+ REG_SET_2(SCL_HORZ_FILTER_INIT_CHROMA, 0,
+ SCL_H_INIT_INT_CBCR, inits->h_init_chroma.integer,
+ SCL_H_INIT_FRAC_CBCR, inits->h_init_chroma.fraction);
+
+ REG_SET_2(SCL_VERT_FILTER_INIT, 0,
+ SCL_V_INIT_INT, inits->v_init.integer,
+ SCL_V_INIT_FRAC, inits->v_init.fraction);
+
+ REG_WRITE(SCL_AUTOMATIC_MODE_CONTROL, 0);
+}
+#endif
+
static const uint16_t *get_filter_coeffs_16p(int taps, struct fixed31_32 ratio)
{
if (taps == 4)
@@ -453,12 +514,14 @@ static void dce60_transform_set_scaler(
is_scaling_required = dce60_setup_scaling_configuration(xfm_dce, data);
if (is_scaling_required) {
- /* 3. Calculate and program ratio, filter initialization */
- struct scl_ratios_inits inits = { 0 };
+ /* 3. Calculate and program ratio, DCE6 filter initialization */
+ struct sclh_ratios_inits inits = { 0 };
- calculate_inits(xfm_dce, data, );
+ /* DCE6 has specific calculate_inits() function */
+ dce60_calculate_inits(xfm_dce, data, );
- program_scl_ratios_inits(xfm_dce, );
+ /* DCE6 has specific program_scl_ratios_inits() function */
+ dce60_program_scl_ratios_inits(xfm_dce, );
coeffs_v = get_filter_coeffs_16p(data->taps.v_taps,
data->ratios.vert);
coeffs_h = get_filter_coeffs_16p(data->taps.h_taps,
data->ratios.horz);
@@ -503,7 +566,7 @@ static void dce60_transform_set_scaler(
/* 6. Program the viewport */
program_viewport(xfm_dce, >viewport);
- /* DCE6 does not have bit to flip to new coefficient memory */
+ /* DCE6 has no SCL_COEF_UPDATE_COMPLETE bit to flip to new coefficient
memory */
[PATCH v3 10/27] drm/amd/display: dc/dce60: set max_cursor_size to 64
[Why] Issue in the Mouse cursor size in Linux Desktop Environments [How] In DCE6 dc->caps.max_cursor_size need to be set as 64 instead of 128 Signed-off-by: Mauro Rossi --- drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c b/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c index 9d21cfba6009..179f67ed7dbb 100644 --- a/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c @@ -970,7 +970,7 @@ static bool dce60_construct( pool->base.timing_generator_count = res_cap.num_timing_generator; dc->caps.max_downscale_ratio = 200; dc->caps.i2c_speed_in_khz = 40; - dc->caps.max_cursor_size = 128; + dc->caps.max_cursor_size = 64; dc->caps.dual_link_dvi = true; dc->caps.extended_aux_timeout_support = false; @@ -1168,7 +1168,7 @@ static bool dce61_construct( pool->base.timing_generator_count = res_cap_61.num_timing_generator; dc->caps.max_downscale_ratio = 200; dc->caps.i2c_speed_in_khz = 40; - dc->caps.max_cursor_size = 128; + dc->caps.max_cursor_size = 64; dc->caps.is_apu = true; /* @@ -1365,7 +1365,7 @@ static bool dce64_construct( pool->base.timing_generator_count = res_cap_64.num_timing_generator; dc->caps.max_downscale_ratio = 200; dc->caps.i2c_speed_in_khz = 40; - dc->caps.max_cursor_size = 128; + dc->caps.max_cursor_size = 64; dc->caps.is_apu = true; /* -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[no subject]
The series adds SI support to AMD DC Changelog: [RFC] Preliminar Proof Of Concept, with DCE8 headers still used in dce60_resources.c [PATCH v2] Rebase on amd-staging-drm-next dated 17-Oct-2018 [PATCH v3] Add support for DCE6 specific headers, ad hoc DCE6 macros, funtions and fixes, rebase on current amd-staging-drm-next Commits [01/27]..[08/27] SI support added in various DC components [PATCH v3 01/27] drm/amdgpu: add some required DCE6 registers (v6) [PATCH v3 02/27] drm/amd/display: add asics info for SI parts [PATCH v3 03/27] drm/amd/display: dc/dce: add initial DCE6 support (v9b) [PATCH v3 04/27] drm/amd/display: dc/core: add SI/DCE6 support (v2) [PATCH v3 05/27] drm/amd/display: dc/bios: add support for DCE6 [PATCH v3 06/27] drm/amd/display: dc/gpio: add support for DCE6 (v2) [PATCH v3 07/27] drm/amd/display: dc/irq: add support for DCE6 (v4) [PATCH v3 08/27] drm/amd/display: amdgpu_dm: add SI support (v4) Commits [09/27]..[24/27] DCE6 specific code adaptions [PATCH v3 09/27] drm/amd/display: dc/clk_mgr: add support for SI parts (v2) [PATCH v3 10/27] drm/amd/display: dc/dce60: set max_cursor_size to 64 [PATCH v3 11/27] drm/amd/display: dce_audio: add DCE6 specific macros,functions [PATCH v3 12/27] drm/amd/display: dce_dmcu: add DCE6 specific macros [PATCH v3 13/27] drm/amd/display: dce_hwseq: add DCE6 specific macros,functions [PATCH v3 14/27] drm/amd/display: dce_ipp: add DCE6 specific macros,functions [PATCH v3 15/27] drm/amd/display: dce_link_encoder: add DCE6 specific macros,functions [PATCH v3 16/27] drm/amd/display: dce_mem_input: add DCE6 specific macros,functions [PATCH v3 17/27] drm/amd/display: dce_opp: add DCE6 specific macros,functions [PATCH v3 18/27] drm/amd/display: dce_transform: add DCE6 specific macros,functions [PATCH v3 19/27] drm/amdgpu: add some required DCE6 registers (v7) [PATCH v3 20/27] drm/amd/display: dce_transform: DCE6 Scaling Horizontal Filter Init [PATCH v3 21/27] drm/amd/display: dce60_hw_sequencer: add DCE6 macros,functions [PATCH v3 22/27] drm/amd/display: dce60_hw_sequencer: add DCE6 specific .cursor_lock [PATCH v3 23/27] drm/amd/display: dce60_timing_generator: add DCE6 specific functions [PATCH v3 24/27] drm/amd/display: dc/dce60: use DCE6 headers (v6) Commits [25/27]..[27/27] SI support final enablements [PATCH v3 25/27] drm/amd/display: create plane rotation property for Bonarie and later [PATCH v3 26/27] drm/amdgpu: enable DC support for SI parts (v2) [PATCH v3 27/27] drm/amd/display: enable SI support in the Kconfig (v2) Signed-off-by: Mauro Rossi ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: Request for Information on the current drm radeon Atomic Mode Settings
Cc: correct email address of Lee Jones, just For Your Information Updated [2] link URL because HWC3 in Celadon was moved to project Celadon drm-hwcomposer local branch on yesterday The request for information on drm radeon atomic modesettings is confirmed Mauro On Fri, May 17, 2024 at 8:31 AM Mauro Rossi wrote: > Hi all, > > with Android 14 QPR2 there were substantial changes in graphic stack's > Android HAL (Hardware Abstraction Layer), > essentially it became mandatory that hwcomposer HAL module supports AIDL > Android Interface Definition Language, > > at the moment drm_hwcomposer does not support AIDL [1] > > Project Celadon has an HWC3 AIDL implemented [2], as a patch on top of > hardware/interface AOSP project, there is an opportunity to use it also for > non Intel GPUs. > > drm amdpu in kernel already supports ADF Atomic Display Framework, I would > like to ask the current status of Atomic Display Framework in drm radeon, > because Atomic Mode Settings seems partially implemented since 2010-2012, > but ADF capabilities are not exposed to user space. > > Please, I also need some basic (high level) information about the > outstanding changes that would be required to support it, in order to be > able to use HWC3 -> drm_hwcomposer with r600, r300 chipsets. > > Thanks for your informations > > Mauro > android-x86 team/Bliss-OS community > > [1] > https://gitlab.freedesktop.org/drm-hwcomposer/drm-hwcomposer/-/issues/80 > [2] > https://github.com/projectceladon/vendor-intel-utils/blob/master/aosp_diff/preliminary/hardware/interfaces/11_0001-Enable-graphics.composer3-AIDL-HAL-service.patch > [2] https://github.com/projectceladon/drm-hwcomposer/commit/1160cdfb53daebf59f3704ec9586c66385e63747
Request for Information on the current drm radeon Atomic Mode Settings
Hi all, with Android 14 QPR2 there were substantial changes in graphic stack's Android HAL (Hardware Abstraction Layer), essentially it became mandatory that hwcomposer HAL module supports AIDL Android Interface Definition Language, at the moment drm_hwcomposer does not support AIDL [1] Project Celadon has an HWC3 AIDL implemented [2], as a patch on top of hardware/interface AOSP project, there is an opportunity to use it also for non Intel GPUs. drm amdpu in kernel already supports ADF Atomic Display Framework, I would like to ask the current status of Atomic Display Framework in drm radeon, because Atomic Mode Settings seems partially implemented since 2010-2012, but ADF capabilities are not exposed to user space. Please, I also need some basic (high level) information about the outstanding changes that would be required to support it, in order to be able to use HWC3 -> drm_hwcomposer with r600, r300 chipsets. Thanks for your informations Mauro android-x86 team/Bliss-OS community [1] https://gitlab.freedesktop.org/drm-hwcomposer/drm-hwcomposer/-/issues/80 [2] https://github.com/projectceladon/vendor-intel-utils/blob/master/aosp_diff/preliminary/hardware/interfaces/11_0001-Enable-graphics.composer3-AIDL-HAL-service.patch
