[arch-commits] Commit in verilator/trunk (PKGBUILD)
Date: Tuesday, December 8, 2020 @ 19:19:30 Author: ffy00 Revision: 772022 upgpkg: verilator 4.106-1 Modified: verilator/trunk/PKGBUILD --+ PKGBUILD |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) Modified: PKGBUILD === --- PKGBUILD2020-12-08 19:19:09 UTC (rev 772021) +++ PKGBUILD2020-12-08 19:19:30 UTC (rev 772022) @@ -3,7 +3,7 @@ # Contributor: Jeffrey Tolar pkgname=verilator -pkgver=4.102 +pkgver=4.106 pkgrel=1 pkgdesc='The fastest free Verilog HDL simulator' url='https://www.veripool.org/projects/verilator/wiki/Intro' @@ -12,7 +12,7 @@ depends=('perl') makedepends=('gcc') source=("https://www.veripool.org/ftp/verilator-$pkgver.tgz";) -sha512sums=('e0030b3b0172c404f2ad5c6c5888c2c23bf17b3f54cc5830449325f6a61fedebc742f9241281c82ee85e8bb2582269c21a81af4fa30d035af01d7394062fad43') +sha512sums=('003663961bbbe6d043b5fbdcee324c7a80c79e04c0c3fb51219b8246f0af00570d2bc4ee5371be01df86c051917ef51f26fc8cad235f0523b9bb0871f7b5431d') build() { cd verilator-$pkgver
[arch-commits] Commit in verilator/trunk (PKGBUILD)
Date: Saturday, October 24, 2020 @ 16:39:14 Author: ffy00 Revision: 731444 upgpkg: verilator 4.102-1 Modified: verilator/trunk/PKGBUILD --+ PKGBUILD |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) Modified: PKGBUILD === --- PKGBUILD2020-10-24 15:41:44 UTC (rev 731443) +++ PKGBUILD2020-10-24 16:39:14 UTC (rev 731444) @@ -3,7 +3,7 @@ # Contributor: Jeffrey Tolar pkgname=verilator -pkgver=4.036 +pkgver=4.102 pkgrel=1 pkgdesc='The fastest free Verilog HDL simulator' url='https://www.veripool.org/projects/verilator/wiki/Intro' @@ -12,7 +12,7 @@ depends=('perl') makedepends=('gcc') source=("https://www.veripool.org/ftp/verilator-$pkgver.tgz";) -sha512sums=('298dfb3f0e9d2f01e139ba6bf8bc31c5c9a491029fb9eadad77af8be0dae6c7b270c6e29b88a3b267b78e9370106b33a6933ea5041cb4fd754dfd2f98189875a') +sha512sums=('e0030b3b0172c404f2ad5c6c5888c2c23bf17b3f54cc5830449325f6a61fedebc742f9241281c82ee85e8bb2582269c21a81af4fa30d035af01d7394062fad43') build() { cd verilator-$pkgver
[arch-commits] Commit in verilator/trunk (PKGBUILD)
Date: Thursday, June 18, 2020 @ 07:02:59 Author: felixonmars Revision: 646741 upgpkg: verilator 4.036-1 Modified: verilator/trunk/PKGBUILD --+ PKGBUILD |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) Modified: PKGBUILD === --- PKGBUILD2020-06-18 06:53:49 UTC (rev 646740) +++ PKGBUILD2020-06-18 07:02:59 UTC (rev 646741) @@ -3,7 +3,7 @@ # Contributor: Jeffrey Tolar pkgname=verilator -pkgver=4.034 +pkgver=4.036 pkgrel=1 pkgdesc='The fastest free Verilog HDL simulator' url='https://www.veripool.org/projects/verilator/wiki/Intro' @@ -12,7 +12,7 @@ depends=('perl') makedepends=('gcc') source=("https://www.veripool.org/ftp/verilator-$pkgver.tgz";) -sha512sums=('04c9c0f51c5c8262cd8e8338204ed6729a3f5be399e012252dd2c102f6474a9abcfdb693bc13eb4fcf7e74e0a6dfa375c3b6592fbc5b5ad2ed07f852a4a06646') +sha512sums=('298dfb3f0e9d2f01e139ba6bf8bc31c5c9a491029fb9eadad77af8be0dae6c7b270c6e29b88a3b267b78e9370106b33a6933ea5041cb4fd754dfd2f98189875a') build() { cd verilator-$pkgver
[arch-commits] Commit in verilator/trunk (PKGBUILD)
Date: Sunday, May 24, 2020 @ 15:54:50 Author: felixonmars Revision: 632952 upgpkg: verilator 4.034-1 Modified: verilator/trunk/PKGBUILD --+ PKGBUILD |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) Modified: PKGBUILD === --- PKGBUILD2020-05-24 15:54:41 UTC (rev 632951) +++ PKGBUILD2020-05-24 15:54:50 UTC (rev 632952) @@ -3,7 +3,7 @@ # Contributor: Jeffrey Tolar pkgname=verilator -pkgver=4.032 +pkgver=4.034 pkgrel=1 pkgdesc='The fastest free Verilog HDL simulator' url='https://www.veripool.org/projects/verilator/wiki/Intro' @@ -12,7 +12,7 @@ depends=('perl') makedepends=('gcc') source=("https://www.veripool.org/ftp/verilator-$pkgver.tgz";) -sha512sums=('2b34d0b6d94babb74b443b3f3ae4e6c9f15423a0b078df72930c4f75b4a831843a4d4b901dc586725a67a49c6f5308402fef4c9ca72b88b13b01746b36d2fb20') +sha512sums=('04c9c0f51c5c8262cd8e8338204ed6729a3f5be399e012252dd2c102f6474a9abcfdb693bc13eb4fcf7e74e0a6dfa375c3b6592fbc5b5ad2ed07f852a4a06646') build() { cd verilator-$pkgver
[arch-commits] Commit in verilator/trunk (PKGBUILD)
Date: Sunday, May 3, 2020 @ 02:21:05 Author: felixonmars Revision: 624536 remove redundant gcc-libs dep Modified: verilator/trunk/PKGBUILD --+ PKGBUILD |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Modified: PKGBUILD === --- PKGBUILD2020-05-03 02:21:05 UTC (rev 624535) +++ PKGBUILD2020-05-03 02:21:05 UTC (rev 624536) @@ -9,7 +9,7 @@ url='https://www.veripool.org/projects/verilator/wiki/Intro' arch=('x86_64') license=('LGPL') -depends=('gcc-libs' 'perl') +depends=('perl') makedepends=('gcc') source=("https://www.veripool.org/ftp/verilator-$pkgver.tgz";) sha512sums=('2b34d0b6d94babb74b443b3f3ae4e6c9f15423a0b078df72930c4f75b4a831843a4d4b901dc586725a67a49c6f5308402fef4c9ca72b88b13b01746b36d2fb20')
[arch-commits] Commit in verilator/trunk (PKGBUILD)
Date: Sunday, May 3, 2020 @ 02:20:31 Author: felixonmars Revision: 624532 upgpkg: verilator 4.032-1 Modified: verilator/trunk/PKGBUILD --+ PKGBUILD |6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) Modified: PKGBUILD === --- PKGBUILD2020-05-03 02:16:26 UTC (rev 624531) +++ PKGBUILD2020-05-03 02:20:31 UTC (rev 624532) @@ -3,16 +3,16 @@ # Contributor: Jeffrey Tolar pkgname=verilator -pkgver=4.030 +pkgver=4.032 pkgrel=1 pkgdesc='The fastest free Verilog HDL simulator' url='https://www.veripool.org/projects/verilator/wiki/Intro' arch=('x86_64') license=('LGPL') -depends=('gcc-libs') +depends=('gcc-libs' 'perl') makedepends=('gcc') source=("https://www.veripool.org/ftp/verilator-$pkgver.tgz";) -sha512sums=('5e1ab57a8ed51b04f6c97798c13f2f3ae24aa1ec2a2b8c9ae98099b16b2f7e9b21171412391832239464d3ad71f8f89b685a20eaa77c005b386a1db6eae02da7') +sha512sums=('2b34d0b6d94babb74b443b3f3ae4e6c9f15423a0b078df72930c4f75b4a831843a4d4b901dc586725a67a49c6f5308402fef4c9ca72b88b13b01746b36d2fb20') build() { cd verilator-$pkgver
[arch-commits] Commit in verilator/trunk (PKGBUILD)
Date: Saturday, March 28, 2020 @ 01:25:32 Author: ffy00 Revision: 605057 upgpkg: verilator 4.030-1 Modified: verilator/trunk/PKGBUILD --+ PKGBUILD |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) Modified: PKGBUILD === --- PKGBUILD2020-03-28 00:41:49 UTC (rev 605056) +++ PKGBUILD2020-03-28 01:25:32 UTC (rev 605057) @@ -3,7 +3,7 @@ # Contributor: Jeffrey Tolar pkgname=verilator -pkgver=4.024 +pkgver=4.030 pkgrel=1 pkgdesc='The fastest free Verilog HDL simulator' url='https://www.veripool.org/projects/verilator/wiki/Intro' @@ -12,7 +12,7 @@ depends=('gcc-libs') makedepends=('gcc') source=("https://www.veripool.org/ftp/verilator-$pkgver.tgz";) -sha512sums=('85aa05af69f30f27e4407cb868218c8cb5050b35861511265bca5058a7a67860b1146fced41553b17e7f316fce8cea362caf5bc9bec9cc06fb9e093f80460d5a') +sha512sums=('5e1ab57a8ed51b04f6c97798c13f2f3ae24aa1ec2a2b8c9ae98099b16b2f7e9b21171412391832239464d3ad71f8f89b685a20eaa77c005b386a1db6eae02da7') build() { cd verilator-$pkgver
[arch-commits] Commit in verilator/trunk (PKGBUILD)
Date: Wednesday, January 22, 2020 @ 16:11:11 Author: felixonmars Revision: 554287 upgpkg: verilator 4.024-1 Modified: verilator/trunk/PKGBUILD --+ PKGBUILD |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) Modified: PKGBUILD === --- PKGBUILD2020-01-22 15:54:53 UTC (rev 554286) +++ PKGBUILD2020-01-22 16:11:11 UTC (rev 554287) @@ -3,7 +3,7 @@ # Contributor: Jeffrey Tolar pkgname=verilator -pkgver=4.022 +pkgver=4.024 pkgrel=1 pkgdesc='The fastest free Verilog HDL simulator' url='https://www.veripool.org/projects/verilator/wiki/Intro' @@ -12,7 +12,7 @@ depends=('gcc-libs') makedepends=('gcc') source=("https://www.veripool.org/ftp/verilator-$pkgver.tgz";) -sha512sums=('fd0334fb07765dfff44c9ee1f1d762427ae46b7169bfa7bd1bb4673c472fbdb1f10afdc8ae366636ad0ea5844435ed5452ad958dc0d8bd79fceaabe2d7f2fdf5') +sha512sums=('85aa05af69f30f27e4407cb868218c8cb5050b35861511265bca5058a7a67860b1146fced41553b17e7f316fce8cea362caf5bc9bec9cc06fb9e093f80460d5a') build() { cd verilator-$pkgver
[arch-commits] Commit in verilator/trunk (PKGBUILD)
Date: Tuesday, November 26, 2019 @ 12:19:39 Author: felixonmars Revision: 533461 upgpkg: verilator 4.022-1 Modified: verilator/trunk/PKGBUILD --+ PKGBUILD |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) Modified: PKGBUILD === --- PKGBUILD2019-11-26 11:38:20 UTC (rev 533460) +++ PKGBUILD2019-11-26 12:19:39 UTC (rev 533461) @@ -3,7 +3,7 @@ # Contributor: Jeffrey Tolar pkgname=verilator -pkgver=4.020 +pkgver=4.022 pkgrel=1 pkgdesc='The fastest free Verilog HDL simulator' url='https://www.veripool.org/projects/verilator/wiki/Intro' @@ -12,7 +12,7 @@ depends=('gcc-libs') makedepends=('gcc') source=("https://www.veripool.org/ftp/verilator-$pkgver.tgz";) -sha512sums=('d80200f38dbda761a2d76fa917fbddbb2c7f4d2b7795377ab8ca2f71c428f9c866ac0c157dbaca0d89b7664d7ad7fd6b4b96ba84583958eedfecabcac020cdd6') +sha512sums=('fd0334fb07765dfff44c9ee1f1d762427ae46b7169bfa7bd1bb4673c472fbdb1f10afdc8ae366636ad0ea5844435ed5452ad958dc0d8bd79fceaabe2d7f2fdf5') build() { cd verilator-$pkgver
[arch-commits] Commit in verilator/trunk (PKGBUILD)
Date: Monday, October 14, 2019 @ 17:06:09 Author: felixonmars Revision: 515766 upgpkg: verilator 4.020-1 Modified: verilator/trunk/PKGBUILD --+ PKGBUILD |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) Modified: PKGBUILD === --- PKGBUILD2019-10-14 17:04:11 UTC (rev 515765) +++ PKGBUILD2019-10-14 17:06:09 UTC (rev 515766) @@ -3,7 +3,7 @@ # Contributor: Jeffrey Tolar pkgname=verilator -pkgver=4.018 +pkgver=4.020 pkgrel=1 pkgdesc='The fastest free Verilog HDL simulator' url='https://www.veripool.org/projects/verilator/wiki/Intro' @@ -12,7 +12,7 @@ depends=('gcc-libs') makedepends=('gcc') source=("https://www.veripool.org/ftp/verilator-$pkgver.tgz";) -sha512sums=('62b74659dc3dc1c7eb0cca08cf6a514d4416ca24cff15f8ca315d5d106c2a978c077050602525cb17bb6d522e1f84b2711cd67d11d282dc29f65cb416ae98e46') +sha512sums=('d80200f38dbda761a2d76fa917fbddbb2c7f4d2b7795377ab8ca2f71c428f9c866ac0c157dbaca0d89b7664d7ad7fd6b4b96ba84583958eedfecabcac020cdd6') build() { cd verilator-$pkgver
[arch-commits] Commit in verilator/trunk (PKGBUILD)
Date: Thursday, September 26, 2019 @ 20:04:25 Author: arojas Revision: 511879 https Modified: verilator/trunk/PKGBUILD --+ PKGBUILD |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Modified: PKGBUILD === --- PKGBUILD2019-09-26 20:03:56 UTC (rev 511878) +++ PKGBUILD2019-09-26 20:04:25 UTC (rev 511879) @@ -11,7 +11,7 @@ license=('LGPL') depends=('gcc-libs') makedepends=('gcc') -source=("http://www.veripool.org/ftp/verilator-$pkgver.tgz";) +source=("https://www.veripool.org/ftp/verilator-$pkgver.tgz";) sha512sums=('62b74659dc3dc1c7eb0cca08cf6a514d4416ca24cff15f8ca315d5d106c2a978c077050602525cb17bb6d522e1f84b2711cd67d11d282dc29f65cb416ae98e46') build() {
[arch-commits] Commit in verilator/trunk (PKGBUILD)
Date: Sunday, September 1, 2019 @ 09:35:53 Author: felixonmars Revision: 505948 upgpkg: verilator 4.018-1 Modified: verilator/trunk/PKGBUILD --+ PKGBUILD |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) Modified: PKGBUILD === --- PKGBUILD2019-09-01 09:34:47 UTC (rev 505947) +++ PKGBUILD2019-09-01 09:35:53 UTC (rev 505948) @@ -3,7 +3,7 @@ # Contributor: Jeffrey Tolar pkgname=verilator -pkgver=4.016 +pkgver=4.018 pkgrel=1 pkgdesc='The fastest free Verilog HDL simulator' url='https://www.veripool.org/projects/verilator/wiki/Intro' @@ -12,7 +12,7 @@ depends=('gcc-libs') makedepends=('gcc') source=("http://www.veripool.org/ftp/verilator-$pkgver.tgz";) -sha512sums=('14bb1d0493103e702b1cbe0ea7c639c04cafa87f204952f88e629012dde1fcecf8e1e51569ff7a422b4dcb0566d0fae35acc681b2e47ae88fac6937362ff3254') +sha512sums=('62b74659dc3dc1c7eb0cca08cf6a514d4416ca24cff15f8ca315d5d106c2a978c077050602525cb17bb6d522e1f84b2711cd67d11d282dc29f65cb416ae98e46') build() { cd verilator-$pkgver
[arch-commits] Commit in verilator/trunk (PKGBUILD)
Date: Monday, June 24, 2019 @ 17:24:24 Author: felixonmars Revision: 483597 upgpkg: verilator 4.016-1 Modified: verilator/trunk/PKGBUILD --+ PKGBUILD |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) Modified: PKGBUILD === --- PKGBUILD2019-06-24 17:24:21 UTC (rev 483596) +++ PKGBUILD2019-06-24 17:24:24 UTC (rev 483597) @@ -3,7 +3,7 @@ # Contributor: Jeffrey Tolar pkgname=verilator -pkgver=4.014 +pkgver=4.016 pkgrel=1 pkgdesc='The fastest free Verilog HDL simulator' url='http://www.veripool.org/projects/verilator/wiki/Intro' @@ -12,7 +12,7 @@ depends=('gcc-libs') makedepends=('gcc') source=("http://www.veripool.org/ftp/verilator-$pkgver.tgz";) -sha512sums=('41378150b409aa40dc8cf76157bd922c9e9f3134d4b27a53877f5974592a07220b8ae235ef9c9a33fda3ef54bb1d55804accc4a4e491a5147afc119ac1ff0e08') +sha512sums=('14bb1d0493103e702b1cbe0ea7c639c04cafa87f204952f88e629012dde1fcecf8e1e51569ff7a422b4dcb0566d0fae35acc681b2e47ae88fac6937362ff3254') build() { cd verilator-$pkgver
[arch-commits] Commit in verilator/trunk (PKGBUILD)
Date: Saturday, June 8, 2019 @ 21:54:47 Author: felixonmars Revision: 478404 upgpkg: verilator 4.014-1 Modified: verilator/trunk/PKGBUILD --+ PKGBUILD |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) Modified: PKGBUILD === --- PKGBUILD2019-06-08 21:53:24 UTC (rev 478403) +++ PKGBUILD2019-06-08 21:54:47 UTC (rev 478404) @@ -3,7 +3,7 @@ # Contributor: Jeffrey Tolar pkgname=verilator -pkgver=4.012 +pkgver=4.014 pkgrel=1 pkgdesc='The fastest free Verilog HDL simulator' url='http://www.veripool.org/projects/verilator/wiki/Intro' @@ -12,7 +12,7 @@ depends=('gcc-libs') makedepends=('gcc') source=("http://www.veripool.org/ftp/verilator-$pkgver.tgz";) -sha512sums=('b2ebe685e5801eb25e76cc9820def7586324b4854651756e0df4c4e21b218ebc2bafd3ef8157d22d90cf6f940089d6d4ac9981e26abf602a5b47f58d878c05ea') +sha512sums=('41378150b409aa40dc8cf76157bd922c9e9f3134d4b27a53877f5974592a07220b8ae235ef9c9a33fda3ef54bb1d55804accc4a4e491a5147afc119ac1ff0e08') build() { cd verilator-$pkgver
[arch-commits] Commit in verilator/trunk (PKGBUILD)
Date: Wednesday, April 24, 2019 @ 21:00:41 Author: felixonmars Revision: 453482 upgpkg: verilator 4.012-1 Modified: verilator/trunk/PKGBUILD --+ PKGBUILD |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) Modified: PKGBUILD === --- PKGBUILD2019-04-24 21:00:29 UTC (rev 453481) +++ PKGBUILD2019-04-24 21:00:41 UTC (rev 453482) @@ -3,7 +3,7 @@ # Contributor: Jeffrey Tolar pkgname=verilator -pkgver=4.010 +pkgver=4.012 pkgrel=1 pkgdesc='The fastest free Verilog HDL simulator' url='http://www.veripool.org/projects/verilator/wiki/Intro' @@ -12,7 +12,7 @@ depends=('gcc-libs') makedepends=('gcc') source=("http://www.veripool.org/ftp/verilator-$pkgver.tgz";) -sha512sums=('7e6915b48207cb54d7c6a3ad2e03c8da078e63f6a25dd9edf64853294c0985bda0d9893e6ca2a81f3cd9bc107a7fba32664eb62edddaa5bbc51633f56a581652') +sha512sums=('b2ebe685e5801eb25e76cc9820def7586324b4854651756e0df4c4e21b218ebc2bafd3ef8157d22d90cf6f940089d6d4ac9981e26abf602a5b47f58d878c05ea') build() { cd verilator-$pkgver
[arch-commits] Commit in verilator/trunk (PKGBUILD)
Date: Friday, March 8, 2019 @ 16:36:23 Author: felixonmars Revision: 438110 upgpkg: verilator 4.010-1 Modified: verilator/trunk/PKGBUILD --+ PKGBUILD |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) Modified: PKGBUILD === --- PKGBUILD2019-03-08 16:32:10 UTC (rev 438109) +++ PKGBUILD2019-03-08 16:36:23 UTC (rev 438110) @@ -3,7 +3,7 @@ # Contributor: Jeffrey Tolar pkgname=verilator -pkgver=4.004 +pkgver=4.010 pkgrel=1 pkgdesc='The fastest free Verilog HDL simulator' url='http://www.veripool.org/projects/verilator/wiki/Intro' @@ -12,7 +12,7 @@ depends=('gcc-libs') makedepends=('gcc') source=("http://www.veripool.org/ftp/verilator-$pkgver.tgz";) -sha512sums=('f8aa345826cfb2045af54026dc17a90a8f33735399e582e43252bd5bd1766615c2ab049236bda78c917628ac54e303bd2412d442fac2789c0fcc4f38770ecff5') +sha512sums=('7e6915b48207cb54d7c6a3ad2e03c8da078e63f6a25dd9edf64853294c0985bda0d9893e6ca2a81f3cd9bc107a7fba32664eb62edddaa5bbc51633f56a581652') build() { cd verilator-$pkgver
[arch-commits] Commit in verilator/trunk (PKGBUILD)
Date: Saturday, October 6, 2018 @ 17:17:43 Author: felixonmars Revision: 390890 upgpkg: verilator 4.004-1 Modified: verilator/trunk/PKGBUILD --+ PKGBUILD |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) Modified: PKGBUILD === --- PKGBUILD2018-10-06 15:59:08 UTC (rev 390889) +++ PKGBUILD2018-10-06 17:17:43 UTC (rev 390890) @@ -3,7 +3,7 @@ # Contributor: Jeffrey Tolar pkgname=verilator -pkgver=4.002 +pkgver=4.004 pkgrel=1 pkgdesc='The fastest free Verilog HDL simulator' url='http://www.veripool.org/projects/verilator/wiki/Intro' @@ -12,7 +12,7 @@ depends=('gcc-libs') makedepends=('gcc') source=("http://www.veripool.org/ftp/verilator-$pkgver.tgz";) -sha512sums=('6d9f6f93e81f99aca90cb1c5ca0da5c1a8495eb9c38c147b06ec6229c24d3b47fd005d3106d422a0cff6798168c04bb2dca8c30f7e83675bfacefb6dbafaf9e3') +sha512sums=('f8aa345826cfb2045af54026dc17a90a8f33735399e582e43252bd5bd1766615c2ab049236bda78c917628ac54e303bd2412d442fac2789c0fcc4f38770ecff5') build() { cd verilator-$pkgver
[arch-commits] Commit in verilator/trunk (PKGBUILD)
Date: Tuesday, September 18, 2018 @ 13:20:04 Author: felixonmars Revision: 383048 upgpkg: verilator 4.002-1 Modified: verilator/trunk/PKGBUILD --+ PKGBUILD |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) Modified: PKGBUILD === --- PKGBUILD2018-09-18 13:19:36 UTC (rev 383047) +++ PKGBUILD2018-09-18 13:20:04 UTC (rev 383048) @@ -3,7 +3,7 @@ # Contributor: Jeffrey Tolar pkgname=verilator -pkgver=3.926 +pkgver=4.002 pkgrel=1 pkgdesc='The fastest free Verilog HDL simulator' url='http://www.veripool.org/projects/verilator/wiki/Intro' @@ -12,7 +12,7 @@ depends=('gcc-libs') makedepends=('gcc') source=("http://www.veripool.org/ftp/verilator-$pkgver.tgz";) -sha512sums=('e1d83f6f2f5250b91567405fa24adcbd0a3d604024c70345a3521698c0e51a9e4bba0ed417444ed793bbb9c25da94551f366264580530fe2516906c0f3626051') +sha512sums=('6d9f6f93e81f99aca90cb1c5ca0da5c1a8495eb9c38c147b06ec6229c24d3b47fd005d3106d422a0cff6798168c04bb2dca8c30f7e83675bfacefb6dbafaf9e3') build() { cd verilator-$pkgver
[arch-commits] Commit in verilator/trunk (PKGBUILD)
Date: Wednesday, September 12, 2018 @ 19:22:46 Author: felixonmars Revision: 379883 upgpkg: verilator 3.926-1 Modified: verilator/trunk/PKGBUILD --+ PKGBUILD |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) Modified: PKGBUILD === --- PKGBUILD2018-09-12 19:18:02 UTC (rev 379882) +++ PKGBUILD2018-09-12 19:22:46 UTC (rev 379883) @@ -3,7 +3,7 @@ # Contributor: Jeffrey Tolar pkgname=verilator -pkgver=3.924 +pkgver=3.926 pkgrel=1 pkgdesc='The fastest free Verilog HDL simulator' url='http://www.veripool.org/projects/verilator/wiki/Intro' @@ -12,7 +12,7 @@ depends=('gcc-libs') makedepends=('gcc') source=("http://www.veripool.org/ftp/verilator-$pkgver.tgz";) -sha512sums=('30e6a744485c6a6d76eb3e09f2aa54cc1b439e86421bfb4974148ffa13b9179aad825d9980ad61d3324583868bcdf18b57d950f47ea29ae4809696254cf5949a') +sha512sums=('e1d83f6f2f5250b91567405fa24adcbd0a3d604024c70345a3521698c0e51a9e4bba0ed417444ed793bbb9c25da94551f366264580530fe2516906c0f3626051') build() { cd verilator-$pkgver
[arch-commits] Commit in verilator/trunk (PKGBUILD)
Date: Wednesday, June 27, 2018 @ 15:29:28 Author: felixonmars Revision: 346420 upgpkg: verilator 3.924-1 Modified: verilator/trunk/PKGBUILD --+ PKGBUILD |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) Modified: PKGBUILD === --- PKGBUILD2018-06-27 15:24:20 UTC (rev 346419) +++ PKGBUILD2018-06-27 15:29:28 UTC (rev 346420) @@ -4,7 +4,7 @@ # Contributor: Jeffrey Tolar pkgname=verilator -pkgver=3.922 +pkgver=3.924 pkgrel=1 pkgdesc='The fastest free Verilog HDL simulator' url='http://www.veripool.org/projects/verilator/wiki/Intro' @@ -13,7 +13,7 @@ depends=('gcc-libs') makedepends=('gcc') source=("http://www.veripool.org/ftp/verilator-$pkgver.tgz";) -sha256sums=('8fba8da6d4fc0044180a1d75ea671b11a5c7757683dadfbca38bd7c143433beb') +sha512sums=('30e6a744485c6a6d76eb3e09f2aa54cc1b439e86421bfb4974148ffa13b9179aad825d9980ad61d3324583868bcdf18b57d950f47ea29ae4809696254cf5949a') build() { cd verilator-$pkgver