Hi,
On Monday, July 11, 2016 05:27 PM, Peter Jansweijer wrote:
Both sides of the the tx and rx fifos are clocked with the same
frequency so there are no under- or overflows.
Yes, I understand this.
For high speed devices the region where you would hit a jump point is
extremely small, you would be very (un)lucky to hit it. To my knowledge,
this has not been observed or reported up to now.
A rough estimation is ~3% of the designs would exhibit the problem
(assuming 8ns data clock, 150ps setup+hold times, 100ps of jitter, and
each design has a random phase relationship between the clocks on each
side of the elastic buffer).
And yes, we would like the highest accuracy we can reasonably get.
This will also be our goal, now that WR has matured. The (restart)
jitter behaviour of the transceivers should be part of a more detailed
study on jitter contributions (an awareness that became clear due to our
fruitful email conversation).
Cheers,
Sébastien
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