Re: [ARTIQ] ARTIQ implementation

[Sébastien Bourdeauducq]

Hi,

On Wednesday, October 05, 2016 12:17 PM, Cornelius Hempel wrote:

At this stage, we are just trying to get an understanding of the size and 
functional requirements (FPGA space and features) at the verilog level - which 
both Trung, our FPGA engineer, and Moglabs speak.


you can simply look at the synthesis logs on our buildserver, e.g.
http://buildbot.m-labs.hk/builders/artiq-board/builds/66/steps/conda_build/logs/stdio
http://buildbot.m-labs.hk/waterfall?show=artiq-board

Note that most of our builds are for the KC705, which uses significantly 
more resources than the Pipistrello target.


Sébastien
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Re: [ARTIQ] ARTIQ implementation

[Cornelius Hempel]

Hi,

At this stage, we are just trying to get an understanding of the size and 
functional requirements (FPGA space and features) at the verilog level - which 
both Trung, our FPGA engineer, and Moglabs speak. 
So just the pre-bitstream verilog code would be sufficient to get a feel for 
it. 

If anyone could spare a copy just of these, that would be very helpful. 

Porting Migen/MiSoC to a new target is likely the way to go eventually.

Thanks & best regards from Sydney!
Cornelius

> On 5 Oct 2016, at 14:10, Sébastien Bourdeauducq  wrote:
> 
> Hi,
> 
> On Wednesday, October 05, 2016 09:49 AM, Trung Nguyen wrote:
>> My goal is to extract the Verilog comprising that gets compiled into the
>> FPGA bitstream in order to establish how and if we can deploy it on
>> another SPARTAN 6 board (= the pipistrello FPGA) made commercially by
>> moglabs here in Australia.
>> 
>> It appears that I need to intercept the output of both Migen and MiSoC
>> as they build the gateway bitstream, BIOS and runtime.
> 
> Better port Migen/MiSoC to your board, otherwise you will have to take 
> apart/reinvent the ARTIQ build system.
> 
>> I have tried two ways to install ARTIQ, (1) via Anaconda and (2) from
>> source.
>> (1) fails as Migen and MiSoC are not part of the distribution and I
>> presume this branch is just to compile user control commands to send to
>> the FPGA, correct?
> 
> Migen and MiSoC are packaged for conda and it is possible to build a 
> bitstream using only the conda packages. But since you are intending to 
> develop I recommend you use (and learn) git.
> 
>> Trying Artiq 2.0, as pointed out in your previous email,
>> I tried to build gateware bitstream but I got this error:
>> 
>> 
>>AttributeError: type object 'BaseSoC' has no attribute 'csr_map'
> 
> https://github.com/m-labs/artiq/issues/565
> If you use MiSoC from Git (not conda), "git checkout 0.3" also gives you the 
> correct version.
> 
> Sébastien
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—
Dr. Cornelius Hempel
Quantum Control Laboratory
The University of Sydney
School of Physics | Faculty of Science
Sydney Nanoscience Hub
Building A31, room 3011
NSW 2006, Australia
phone: +61 2 8627 5037

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Re: [ARTIQ] ARTIQ implementation

[Sébastien Bourdeauducq]

Hi,

On Wednesday, October 05, 2016 09:49 AM, Trung Nguyen wrote:

My goal is to extract the Verilog comprising that gets compiled into the
FPGA bitstream in order to establish how and if we can deploy it on
another SPARTAN 6 board (= the pipistrello FPGA) made commercially by
moglabs here in Australia.

It appears that I need to intercept the output of both Migen and MiSoC
as they build the gateway bitstream, BIOS and runtime.


Better port Migen/MiSoC to your board, otherwise you will have to take 
apart/reinvent the ARTIQ build system.



I have tried two ways to install ARTIQ, (1) via Anaconda and (2) from
source.
(1) fails as Migen and MiSoC are not part of the distribution and I
presume this branch is just to compile user control commands to send to
the FPGA, correct?


Migen and MiSoC are packaged for conda and it is possible to build a 
bitstream using only the conda packages. But since you are intending to 
develop I recommend you use (and learn) git.



Trying Artiq 2.0, as pointed out in your previous email,
I tried to build gateware bitstream but I got this error:


AttributeError: type object 'BaseSoC' has no attribute 'csr_map'


https://github.com/m-labs/artiq/issues/565
If you use MiSoC from Git (not conda), "git checkout 0.3" also gives you 
the correct version.


Sébastien
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Re: [ARTIQ] ARTIQ implementation

[Trung Nguyen]

Dear ARTIQ users,

I'm still trying to set up the Artiq environment in order to be able to
compile the FPGA bitstream code, but I am getting stuck both with ARTIQ 3.0
and 2.0.

My goal is to extract the Verilog comprising that gets compiled into the
FPGA bitstream in order to establish how and if we can deploy it on another
SPARTAN 6 board (= the pipistrello FPGA) made commercially by moglabs here
in Australia.

It appears that I need to intercept the output of both Migen and MiSoC as
they build the gateway bitstream, BIOS and runtime.

I have tried two ways to install ARTIQ, (1) via Anaconda and (2) from
source.
(1) fails as Migen and MiSoC are not part of the distribution and I presume
this branch is just to compile user control commands to send to the FPGA,
correct?
Therefore, I went with (2), both trying ARTIQ 3.0 and 2.0, but still get
stuck.

With Artiq 3.0, I can't install rustc successfully, I got this error:

> configure: configuring submodules
>
> configure:
>
> configure:
>
> configure: looking at LLVM
>
> configure:
>
> configure: not reconfiguring LLVM, external LLVM root
>
> configure: error: program '/usr/local/llvm-or1k/bin/llvm-config/bin/FileCheck'
>> is missing, please install it
>
> When executing this command:

> ../configure --prefix=/usr/local/rust-or1k 
> --llvm-root=/usr/local/llvm-or1k/bin/llvm-config
> --disable-manage-submodules

given on

>  https://m-labs.hk/artiq/manual-master/installing_from_source.html


 I found "FileCheck” in the following directory:

> /home/trungnguyen/artiq-dev-3.0/llvm-or1k/build/bin/FileCheck
>
and changed  to --llvm-root=/home/trungnguyen/artiq-dev-3.0/llvm-or1k/build.
It ran successfully but I'm not sure if it's the solution or not.

Trying Artiq 2.0, as pointed out in your previous email, I downloaded it
from
https://github.com/m-labs/artiq/releases/tag/2.0
And followed the instructions on:
https://m-labs.hk/artiq/manual-release-2/installing_from_source.html

I tried to build gateware bitstream but I got this error:

> (artiq-main) trungnguyen@trungnguyen:~/artiq-dev$ python3.5 -m
>> artiq.gateware.targets.pipistrello
>
> Traceback (most recent call last):
>
>   File "/home/trungnguyen/anaconda3/envs/artiq-main/lib/python3.5/runpy.py",
>> line 184, in _run_module_as_main
>
> "__main__", mod_spec)
>
>   File "/home/trungnguyen/anaconda3/envs/artiq-main/lib/python3.5/runpy.py",
>> line 85, in _run_code
>
> exec(code, run_globals)
>
>   File 
> "/home/trungnguyen/artiq-dev/artiq/artiq/gateware/targets/pipistrello.py",
>> line 127, in 
>
> class NIST_QC1(BaseSoC, AMPSoC):
>
>   File 
> "/home/trungnguyen/artiq-dev/artiq/artiq/gateware/targets/pipistrello.py",
>> line 136, in NIST_QC1
>
> csr_map.update(BaseSoC.csr_map)
>
> AttributeError: type object 'BaseSoC' has no attribute 'csr_map'
>
>
I commented out this attribute. I know this is not a good way to solve
problem but I have no knowledge of the script file.
Then I tried again and received error messages, please refer to the
attached files (logfile and errorfile) for more information.

I would be grateful if you could point me in the right direction.

Thank you very much,
Trung

Best Regards,
Trung Vu Nguyen

On 29 September 2016 at 20:31, Trung Nguyen 
wrote:

> Hi,
>
> the mailing list I was referring to is the ARTIQ list (
>> https://ssl.serverraum.org/lists/listinfo/artiq).
>>
>> You need to use a modified Rust:
>> https://github.com/m-labs/rust
>>
>> Full compilation instructions for the upcoming ARTIQ 3.0 are here:
>> https://m-labs.hk/artiq/manual-master/installing_from_source
>> .html#preparing-the-build-environment-for-the-core-device
>>
>> Alternatively you can use the already released ARTIQ 2.0 which does not
>> require Rust.
>
>
> Thank you for your reply. I will try it.
>
> The note about using the or1k-linux target only refers to building
>> binutils,
>> as it is a workaround to its undesirable behavior. Everything else uses
>> the target
>> or1k-unknown as it is the correct one.
>
>
> Hi Peter, "or1k-unknown" is default target it in the script and I tried it
> first but I got the error. Then I changed it to "or1k-linux" but it's not
> solved.
> Thank you.
>
> Best Regards,
> Trung Vu Nguyen
>
> On 29 September 2016 at 12:28, Sébastien Bourdeauducq 
> wrote:
>
>> Hi,
>>
>> the mailing list I was referring to is the ARTIQ list (
>> https://ssl.serverraum.org/lists/listinfo/artiq).
>>
>> You need to use a modified Rust:
>> https://github.com/m-labs/rust
>>
>> Full compilation instructions for the upcoming ARTIQ 3.0 are here:
>> https://m-labs.hk/artiq/manual-master/installing_from_source
>> .html#preparing-the-build-environment-for-the-core-device
>>
>> Alternatively you can use the already released ARTIQ 2.0 which does not
>> require Rust.
>>
>> Sébastien
>>
>>
>>
>> On Thursday, September 29, 2016 10:28 AM, Trung Nguyen wrote:
>>
>>> Hi Developers,
>>>
>>> I'm trying to run the Artiq environment to compile the gateware file.