On Wednesday, June 28, 2017 04:52 PM, Thomas Harty wrote:
Have we settled on the 50T as the FPGA for the first version of Kasli,
and what speed grade?
I would advocate for the 50T in -2 speed grade for two main reasons:
a) I don't think we need that much FPGA resources for the 100T to be needed.
b) -2 speed grade transceivers go to 6.25Gbps whereas -1 speed grade
ones go to 3.75Gbps. In addition to a significant increase in bandwidth,
the -2 transceivers can use the same configuration on the Metlino/Sayma
side which is used for the backplane (5Gbps). Otherwise we would have to
generate another set of Ultrascale transceiver settings (and shave a
yak) and potentially deal with weird RTIO frequency ratios in a hybrid
MTCA/Eurocard Sinara system.
Sébastien
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