Re: [ARTIQ] Instantiating tri-state buffer in migen
Hi Sebastien
Thank you for the quick reply. Will try that and let you know.
Regards
Arpit Agrawal
On Fri, Oct 6, 2017 at 9:29 PM, Sébastien Bourdeauducq via ARTIQ <
artiq@lists.m-labs.hk> wrote:
> On Saturday, October 07, 2017 09:13 AM, Arpit Agrawal via ARTIQ wrote:
>
>> return Instance("IOBUFDS",
>> i_I=self.i, o_O=self.o, i_T=self.oe,
>>
>
> OE means "output enable". T means "tristate", i.e. not driving. You need
> to invert that signal.
>
> Sébastien
>
> ___
> ARTIQ mailing list
> https://ssl.serverraum.org/lists/listinfo/artiq
>
___
ARTIQ mailing list
https://ssl.serverraum.org/lists/listinfo/artiq
[ARTIQ] Instantiating tri-state buffer in migen
Hello
I've written simple code to instantiate buffer and generate a square wave.
The code is working fine for OBUFDS, but for tri-state buffers (OBUFTDS &
IOBUFDS), there is nothing on the output. All 3 files are attached. Would
you please let me know what could be wrong? Do we need to do something more
to use tri-state buffers?
Note: In kc705 platform file, I changed output standard of user_sma_gpio_p
and user_sma_gpio_n pins to LVDS25 (a quick hack basically).
Regards
Arpit Agrawal
#!/usr/bin/env python3
from migen import *
from migen.build.platforms import kc705
class DifferentialTristate(TSTriple):
def get_tristate(self, pad, pad_n):
return Instance("IOBUFDS",
i_I=self.i, o_O=self.o, i_T=self.oe,
io_IO=pad, io_IOB=pad_n)
if __name__ == "__main__":
plat = kc705.Platform()
m = Module()
signal1 = Signal(reset=0)
count1 = Signal(max=1000, reset=0)
diff1 = DifferentialTristate()
m.specials += diff1.get_tristate(plat.request("user_sma_gpio_p"),
plat.request("user_sma_gpio_n"))
m.comb += [
diff1.oe.eq(1),
diff1.i.eq(signal1)
]
m.sync += [
If(count1 < 999,
count1.eq(count1 + 1)
).Else(
count1.eq(0),
signal1.eq(~signal1)
)
]
plat.build(m, run=True, build_dir="differential", build_name="differential")
plat.create_programmer().flash(0, "differential.bin")
#!/usr/bin/env python3
from migen import *
from migen.build.platforms import kc705
class DifferentialTristate(TSTriple):
def get_tristate(self, pad, pad_n):
return Instance("OBUFDS",
i_I=self.i,
o_O=pad, o_OB=pad_n)
if __name__ == "__main__":
plat = kc705.Platform()
m = Module()
signal1 = Signal(reset=0)
count1 = Signal(max=1000, reset=0)
diff1 = DifferentialTristate()
m.specials += diff1.get_tristate(plat.request("user_sma_gpio_p"),
plat.request("user_sma_gpio_n"))
m.comb += [
# diff1.oe.eq(1),
diff1.i.eq(signal1)
]
m.sync += [
If(count1 < 999,
count1.eq(count1 + 1)
).Else(
count1.eq(0),
signal1.eq(~signal1)
)
]
plat.build(m, run=True, build_dir="differential", build_name="differential")
plat.create_programmer().flash(0, "differential.bin")
#!/usr/bin/env python3
from migen import *
from migen.build.platforms import kc705
class DifferentialTristate(TSTriple):
def get_tristate(self, pad, pad_n):
return Instance("OBUFTDS",
i_I=self.i, i_T=self.oe,
o_O=pad, o_OB=pad_n)
if __name__ == "__main__":
plat = kc705.Platform()
m = Module()
signal1 = Signal(reset=0)
count1 = Signal(max=1000, reset=0)
diff1 = DifferentialTristate()
m.specials += diff1.get_tristate(plat.request("user_sma_gpio_p"),
plat.request("user_sma_gpio_n"))
m.comb += [
diff1.oe.eq(1),
diff1.i.eq(signal1)
]
m.sync += [
If(count1 < 999,
count1.eq(count1 + 1)
).Else(
count1.eq(0),
signal1.eq(~signal1)
)
]
plat.build(m, run=True, build_dir="differential", build_name="differential")
plat.create_programmer().flash(0, "differential.bin")
___
ARTIQ mailing list
https://ssl.serverraum.org/lists/listinfo/artiq
Re: [ARTIQ] ARTIQ SPI PHY, differential driving
Hello Dr. Chris
Thank you so much, this is exactly what we were looking for.
Regards
Arpit Agrawal
On Thu, Sep 21, 2017 at 7:58 PM, Chris Ballance via ARTIQ <
artiq@lists.m-labs.hk> wrote:
> Joe,
>
> Attached is a patch I hacked up a while ago that adds differential IOs to
> the SPIMaster. It is ugly, but hopefully transparent. I don't think I have
> tested this on hardware, and this will only work with a single chip-select
> line.
>
> Instantiate it like:
> phy = spi.SPIMaster(self.platform.request("spi", 0), differential=True)
>
> where the pins are defined like:
> ("spi", 0,
> Subsignal("miso_p", Pins("LA00_CC_P")),
> Subsignal("miso_n", Pins("LA00_CC_N")),
> Subsignal("clk_p", Pins("LA08_P")),
> Subsignal("clk_n", Pins("LA08_N")),
> Subsignal("mosi_p", Pins("LA03_P")),
> Subsignal("mosi_n", Pins("LA03_N")),
> Subsignal("cs_n_n", Pins("LA02_P")),
> Subsignal("cs_n_p", Pins("LA02_N")),
> IOStandard("LVDS_25")
> )
>
> (Possibly turning on some termination, depending on your hardware).
>
> Hope this helps move you in the right direction -
> Chris
>
>
> On 21/09/2017 19:43, Joe Britton via ARTIQ wrote:
>
>> This was discussed on IRC too...
>>
>> https://irclog.whitequark.org/m-labs/2017-09-13
>> https://irclog.whitequark.org/m-labs/2017-09-15
>> https://irclog.whitequark.org/m-labs/2017-09-16
>> https://irclog.whitequark.org/m-labs/2017-09-17
>>
>> The Q is much appreciated but we still don't have a solution that
>> works. It looks like rather greater knowledge of MIGEN is required.
>> M-Labs, please provide code so Arpit can contribute at the ARTIQ
>> Python level and steer clear of not-yet fully documented aspects of
>> Migen. AFACT this is needed for integration of any of the EEM modules
>> with VHDCI_carrier. Arpit can't contribute to testing and driver
>> writing for Zotino if he remains stuck on this bump. -Joe
>>
>> On Wed, Sep 13, 2017 at 1:35 PM, Joe Britton
>> wrote:
>>
>>> Thanks Arpit and Daniel for email responses. Catching up the mailing
>>> list...
>>>
>>> The path Metlino/Sayma -> FMC -> VHDCI uses LVDS which are driven as
>>> _p and _n pin pairs from the FPGA for each EEM IO line. Each EEM board
>>> has an LVDS receiver that generates local single-ended IO.
>>>
>>> If that is the case, you need to dig into Migen to figure out how to
express the
subsignals with two pins using an LVDS standard (I haven’t done this
myself, you might ask Robert
or Sebastien).
>>> We've already figure out how to do get Migen to express subsignals
>>> using a pair of pins. For example,
>>>
>>> ("clk", 0,
>>> Subsignal("p", Pins("Y23")),
>>> Subsignal("n", Pins("Y24")),
>>> IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE")
>>> )
>>>
>>> Does Migen supports sub-subsignals or is a change needed to SPIMaster?
>>> This is what the NIST_clock Migen subsignal definition looks like for
>>> spi when driven single-ended by the FPGA.
>>>
>>> ("spi", 0,
>>> Subsignal("clk", Pins("LPC:LA13_N")),
>>> Subsignal("cs_n", Pins("LPC:LA14_N")),
>>> Subsignal("mosi", Pins("LPC:LA17_CC_P")),
>>> Subsignal("miso", Pins("LPC:LA17_CC_N")),
>>> IOStandard("LVTTL")),
>>>
>>>
>>> On Wed, Sep 13, 2017 at 11:21 AM, Joe Britton
>>> wrote:
>>>
What's the right way to use ARTIQ to drive SPI devices across the VHDCI
bus?
The SPIMaster interface appears to take only a single signal for each of
clk, cs_n, mosi and miso.
Has anybody yet interfaced with an SPI device using VHCDI? -Joe
>>> ___
>> ARTIQ mailing list
>> https://ssl.serverraum.org/lists/listinfo/artiq
>>
>
>
> ___
> ARTIQ mailing list
> https://ssl.serverraum.org/lists/listinfo/artiq
>
>
___
ARTIQ mailing list
https://ssl.serverraum.org/lists/listinfo/artiq
