Re: [ARTIQ] TTL + slow DACs

[Slichter, Daniel H. (Fed)]

> Since this is another piece of hardware and the processing constraints as well
> as the electrical constraints are so different, it seems prudent to account 
> for
> these differences. Consider doing proper galvanic isolation with a fiber:
> ground potential differences easily
> -- and even in well controlled labs -- exceed the common mode tolerances of
> lvds if the devices are a few tens of meters apart.
> 
> This is why we would like to consider a very low barrier, non-rack form factor
> that is connected by fiber plus a simple power supply and provides a good
> number of analog voltages and a good number of ttls.
> That obsoletes the LVDS breakout board which also doesn't help with the
> galvanic isolation for the high density low speed DAC that we would like to
> bundle with that box.

OK, fiber is superior for galvanic isolation, but at the end of the day this 
would be a solution with just a few TTL lines per board, and you would then 
sprinkle these around the lab, correct?  And clock/timing transfer can be done 
over the fiber in a suitable way?
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Re: [ARTIQ] TTL + slow DACs

[Robert Jördens]

On Thu, Mar 31, 2016 at 5:29 PM, Slichter, Daniel H. (Fed)
 wrote:
>> We'll probably want a few dozen TTLs, broken out on SMA, so the FMC panel
>> is not an option there.
>>
>> We can remove PCIe indeed, but keeping the WR oscillators is probably a
>> good idea as they can be used for clock synchronization with the master.
>
> For the purpose of a TTL card, I would recommend that the TTL be broken out 
> to LVDS over cat5/cat6 using RJ45 connectors, as is currently done in the 
> ARTIQ hardware.  It would be possible to send 64 TTL lines out of a single 
> AMC card of 6 HP width in this manner, much more than you could ever do with 
> SMA, and with vastly cheaper cabling and excellent signal integrity for long 
> cabling runs (tested to work fine with 30 m cable, for example).  We have 
> existing breakout boards that convert between 4 TTL signals on SMA and 4 LVDS 
> signals on Ethernet cables.
>
> This card would not have an FMC mezzanine, but would rather just break things 
> out directly from the FPGA.  I would recommend using a similar architecture 
> on the AMC board to our existing TTL riser card that interfaces between TTL 
> at the FPGA and LVDS.  I know we could directly drive LVDS to/from the FPGA, 
> but then we don't have any isolation between the FPGA user IO and the end 
> user application, which makes me nervous that users could more easily fry the 
> FPGA.
>
> One could use a very inexpensive FPGA for this particular task, although it 
> might be nice to have a hard processor if it is driving so many TTL lines.

Since this is another piece of hardware and the processing constraints
as well as the electrical constraints are so different, it seems
prudent to account for these differences. Consider doing proper
galvanic isolation with a fiber: ground potential differences easily
-- and even in well controlled labs -- exceed the common mode
tolerances of lvds if the devices are a few tens of meters apart.

This is why we would like to consider a very low barrier, non-rack
form factor that is connected by fiber plus a simple power supply and
provides a good number of analog voltages and a good number of ttls.
That obsoletes the LVDS breakout board which also doesn't help with
the galvanic isolation for the high density low speed DAC that we
would like to bundle with that box.

Robert.
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Re: [ARTIQ] TTL + slow DACs

[Slichter, Daniel H. (Fed)]

> We'll probably want a few dozen TTLs, broken out on SMA, so the FMC panel
> is not an option there.
> 
> We can remove PCIe indeed, but keeping the WR oscillators is probably a
> good idea as they can be used for clock synchronization with the master.

For the purpose of a TTL card, I would recommend that the TTL be broken out to 
LVDS over cat5/cat6 using RJ45 connectors, as is currently done in the ARTIQ 
hardware.  It would be possible to send 64 TTL lines out of a single AMC card 
of 6 HP width in this manner, much more than you could ever do with SMA, and 
with vastly cheaper cabling and excellent signal integrity for long cabling 
runs (tested to work fine with 30 m cable, for example).  We have existing 
breakout boards that convert between 4 TTL signals on SMA and 4 LVDS signals on 
Ethernet cables.  

This card would not have an FMC mezzanine, but would rather just break things 
out directly from the FPGA.  I would recommend using a similar architecture on 
the AMC board to our existing TTL riser card that interfaces between TTL at the 
FPGA and LVDS.  I know we could directly drive LVDS to/from the FPGA, but then 
we don't have any isolation between the FPGA user IO and the end user 
application, which makes me nervous that users could more easily fry the FPGA.  

One could use a very inexpensive FPGA for this particular task, although it 
might be nice to have a hard processor if it is driving so many TTL lines.  
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Re: [ARTIQ] TTL + slow DACs

[Grzegorz Kasprowicz]

for this purpose one can use this board
http://www.ohwr.org/projects/spec/wiki
there is available also stand-alone aluminium box.The cost can be lowered
by factor of two when WR oscillators, PCie chip and memory is not mounted.
Just leave FPGA,supply and FMC connector.
Greg

On 31 March 2016 at 14:48, Grzegorz Kasprowicz <kaspr...@gmail.com> wrote:

> Well, yes, providing that you find charger that won't fail after 500 hours
> :)
>
>
> -Original Message-
> From: Sébastien Bourdeauducq [mailto:s...@m-labs.hk]
> Sent: Thursday, March 31, 2016 12:42 PM
> To: Grzegorz Kasprowicz <kaspr...@gmail.com>
> Cc: Slichter, Daniel H. (Fed) <daniel.slich...@nist.gov>; Robert Jördens
> <r...@m-labs.hk>; Grzegorz Kasprowicz <gkasp...@elka.pw.edu.pl>; Leibrandt,
> David R. (Fed) <david.leibra...@nist.gov>; artiq@lists.m-labs.hk
> Subject: Re: [ARTIQ] TTL + slow DACs
>
> On Thursday, 31 March 2016 12:40:55 PM HKT Grzegorz Kasprowicz wrote:
> > Well, we can use in this case the AMC board plugged into dual AMC box
> > which has 4 SFPs.
> > In some cases this could be an overkill, but it is working solution.
> > http://www.ohwr.org/projects/amc-ubackplane-sfp/wiki
>
> A Spartan-6 FPGA powered by a mobile phone charger is sufficient.
>
>
>
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Re: [ARTIQ] TTL + slow DACs

[Grzegorz Kasprowicz]

Well, yes, providing that you find charger that won't fail after 500 hours
:)


-Original Message-
From: Sébastien Bourdeauducq [mailto:s...@m-labs.hk] 
Sent: Thursday, March 31, 2016 12:42 PM
To: Grzegorz Kasprowicz <kaspr...@gmail.com>
Cc: Slichter, Daniel H. (Fed) <daniel.slich...@nist.gov>; Robert Jördens
<r...@m-labs.hk>; Grzegorz Kasprowicz <gkasp...@elka.pw.edu.pl>; Leibrandt,
David R. (Fed) <david.leibra...@nist.gov>; artiq@lists.m-labs.hk
Subject: Re: [ARTIQ] TTL + slow DACs

On Thursday, 31 March 2016 12:40:55 PM HKT Grzegorz Kasprowicz wrote:
> Well, we can use in this case the AMC board plugged into dual AMC box 
> which has 4 SFPs.
> In some cases this could be an overkill, but it is working solution.
> http://www.ohwr.org/projects/amc-ubackplane-sfp/wiki

A Spartan-6 FPGA powered by a mobile phone charger is sufficient.


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Re: [ARTIQ] TTL + slow DACs

[Grzegorz Kasprowicz]

Well, we can use in this case the AMC board plugged into dual AMC box which
has 4 SFPs.
In some cases this could be an overkill, but it is working solution.
http://www.ohwr.org/projects/amc-ubackplane-sfp/wiki

On 31 March 2016 at 12:05, Sébastien Bourdeauducq  wrote:

> On Wednesday, 30 March 2016 11:45:16 PM HKT Slichter, Daniel H. (Fed)
> wrote:
> > One further question: is there a plan to make a “TTL” card or a
> multichannel
> > “slow” DAC card (e.g. for trap voltages), using a Centronics or d-sub
> type
> > connector?  These could both be more readily accomplished with their own
> > FMC modules if we go with this architecture.
>
> No. They will need breakout boxes anyway, and better put an FPGA in that
> box
> and connect it to the root master with a fiber.
>
> Sébastien
>
>
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