Re: [avr-gcc-list] Optimiser bloats code
Paulo Marques schreef:
Not really a better idea for 3 bits, but it would be for 4:
prog_uint8_t inv_table[8]={0,4,2,6,1,5,3,7};
unsigned char inv_test(void)
{
return pgm_read_byte(inv_table[PORTB 0x3]);
}
Ah yes, of course a table!
The output from gcc 4.2.0:
byte inv_test(void)
{
return pgm_read_byte(inv_table[PORTB 0x3]);
96: e8 b3 in r30, 0x18 ; 24
98: ff 27 eor r31, r31
9a: e3 70 andir30, 0x03 ; 3
9c: f0 70 andir31, 0x00 ; 0
9e: ec 5a subir30, 0xAC ; 172
a0: ff 4f sbcir31, 0xFF ; 255
a2: e4 91 lpm r30, Z
}
a4: 8e 2f mov r24, r30
a6: 99 27 eor r25, r25
a8: 08 95 ret
If not for the redundant andi r31, 0x00 (when r31 has just been zeroed
by the eor r31,r31) it would give the same number of instructions as
your code.
The nice thing about this approach is that it works the same for 4 or
more bits (up to 8).
Yes but the table would grow large on 8 bits inversion :D. And I'm more
afraid of running out of space, then running out of time.
Thanks for the help,
Wouter
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Re: [avr-gcc-list] Inversion of logic improves size speed
Anatoly Sokolov schreef: Hi, Bug #11259 [avr] gcc Double 'andi' missed optimization: http://gcc.gnu.org/bugzilla/show_bug.cgi?id=11259 Bug #29560 Poor optimization for character shifts on Atmel AVR: http://gcc.gnu.org/bugzilla/show_bug.cgi?id=29560 Bug #29560 seems to be a little different. The bug report is on shifting with a variable shift count. And the loop for doing this shift is non optimal (high byte shift because of int promotion or something alike). While my example works with fixed shifts. Actually, it's bit extraction implemented as shifting. My concern is that when rewriting/inverting my logic I get much better (optimal in most cases) results. So it seems the compiler has not chosen the most optimal path. It seems like he has two ways of doing the shifting? Mabye it's some hidden 8-bit/16-bit variable difference? Testcase: snip There are two 'and' insn (#24 and #12), but them are not optimized yet. Why? Probably reason, 'lshiftrt' insn is splited in 'rotate' and 'and' insns in 'pass_split_after_reload' pass of the compiler, but optimization passes (combine and cse) of which two 'and' insns can merge are run earlier. I see, to bad... It is possible to add peephole for merge two 'and' insns. But I do not think that this decision optimum. Why not? I agree it's not solving the roots of the problem but it helps anyway. I am a total noob on GCC internals so this might be a stupid question... Thanks for all the explantions! Really interresting stuff. Greetings, Wouter ___ AVR-GCC-list mailing list AVR-GCC-list@nongnu.org http://lists.nongnu.org/mailman/listinfo/avr-gcc-list
Re: [avr-gcc-list] Inserting code before context save in an ISR (fornested interrupts)
Thanks for the help guys. I waded through the interrupt header files
and figured out how to use __attribute__ just about the same time Joerg
posted this... ahh well.
I really is nice to be able to tap into such knowledgeable people.
-David Carr
Joerg Wunsch wrote:
Eric Weddington [EMAIL PROTECTED] wrote:
And to do this using avr-libc, is to use the INTERRUPT() macro
(instead of ISR()):
which has been deprecated, due to its confusing name.
So the official solution is:
void YOUR_VECTOR_vect(void) __attribute__((interrupt));
void
YOUR_VECTOR_vect(void)
{
/* your ISR goes here */
}
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RE: [avr-gcc-list] Inserting code before context save in an ISR(fornested interrupts)
-Original Message-
From:
[EMAIL PROTECTED]
[mailto:[EMAIL PROTECTED]
org] On Behalf Of Joerg Wunsch
Sent: Monday, August 06, 2007 11:21 PM
To: avr-gcc-list@nongnu.org
Subject: Re: [avr-gcc-list] Inserting code before context
save in an ISR(fornested interrupts)
Eric Weddington [EMAIL PROTECTED] wrote:
And to do this using avr-libc, is to use the INTERRUPT() macro
(instead of ISR()):
which has been deprecated, due to its confusing name.
So the official solution is:
void YOUR_VECTOR_vect(void) __attribute__((interrupt));
void
YOUR_VECTOR_vect(void)
{
/* your ISR goes here */
}
True, good point. Thanks for the correction.
Eric
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