[PATCH 2/3] OMAP4460: ram init changes
configure Memory Adapter for 4460
Signed-off-by: Jan Weitzel j.weit...@phytec.de
---
arch/arm/mach-omap/include/mach/omap4-silicon.h |4
arch/arm/mach-omap/omap4_generic.c | 21 +++--
2 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap/include/mach/omap4-silicon.h
b/arch/arm/mach-omap/include/mach/omap4-silicon.h
index d5517c5..4082bac 100644
--- a/arch/arm/mach-omap/include/mach/omap4-silicon.h
+++ b/arch/arm/mach-omap/include/mach/omap4-silicon.h
@@ -101,6 +101,10 @@
#define DMM_LISA_MAP_SYS_SIZE_MASK (7 20)
#define DMM_LISA_MAP_SYS_SIZE_SHIFT20
#define DMM_LISA_MAP_SYS_ADDR_MASK (0xFF 24)
+
+/* Memory Adapter (4460 onwards) */
+#define OMAP44XX_MA_BASE 0x482AF000
+
/*
* Hardware Register Details
*/
diff --git a/arch/arm/mach-omap/omap4_generic.c
b/arch/arm/mach-omap/omap4_generic.c
index 3f6865a..617d786 100644
--- a/arch/arm/mach-omap/omap4_generic.c
+++ b/arch/arm/mach-omap/omap4_generic.c
@@ -29,6 +29,10 @@
#define OMAP4460_CONTROL_ID_CODE_ES1_0 0x0B94E02F
#define OMAP4460_CONTROL_ID_CODE_ES1_1 0x2B94E02F
+/* EMIF_L3_CONFIG register value */
+#define EMIF_L3_CONFIG_VAL_SYS_10_LL_0 0x0AFF
+#define EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0 0x0A30
+
void __noreturn reset_cpu(unsigned long addr)
{
writel(PRM_RSTCTRL_RESET, PRM_RSTCTRL);
@@ -272,8 +276,7 @@ static void reset_phy(unsigned int base)
void omap4_ddr_init(const struct ddr_regs *ddr_regs,
const struct dpll_param *core)
{
- unsigned int rev;
- rev = omap4_revision();
+ unsigned int rev = omap4_revision();
if (rev == OMAP4430_ES2_0) {
writel(0x9e9e9e9e, 0x4A100638);
@@ -296,6 +299,13 @@ void omap4_ddr_init(const struct ddr_regs *ddr_regs,
writel(0x, OMAP44XX_DMM_BASE + DMM_LISA_MAP_2);
writel(0xFF020100, OMAP44XX_DMM_BASE + DMM_LISA_MAP_3);
+ if (rev = OMAP4460_ES1_0) {
+ writel(0x80640300, OMAP44XX_MA_BASE + DMM_LISA_MAP_0);
+
+ writel(0x, OMAP44XX_MA_BASE + DMM_LISA_MAP_2);
+ writel(0xFF020100, OMAP44XX_MA_BASE + DMM_LISA_MAP_3);
+ }
+
/* DDR needs to be initialised @ 19.2 MHz
* So put core DPLL in bypass mode
* Configure the Core DPLL but don't lock it
@@ -338,6 +348,13 @@ void omap4_ddr_init(const struct ddr_regs *ddr_regs,
writel(0x8000, OMAP44XX_EMIF1_BASE + EMIF_PWR_MGMT_CTRL);
writel(0x8000, OMAP44XX_EMIF2_BASE + EMIF_PWR_MGMT_CTRL);
+ if (rev = OMAP4460_ES1_0) {
+ writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0,
+ OMAP44XX_EMIF1_BASE + EMIF_L3_CONFIG);
+ writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0,
+ OMAP44XX_EMIF2_BASE + EMIF_L3_CONFIG);
+ }
+
/*
* DMM : DMM_LISA_MAP_0(Section_0)
* [31:24] SYS_ADDR 0x80
--
1.7.0.4
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[PATCH 0/3 v2] omap: 4460 support
Add support for OMAP4460 cpu on top of ed358834 (next) v2: merge usage of omap4_scale_vcores to 1/3 avoid volatile int* Jan Weitzel (3): Add support for OMAP4460 TPS62361 OMAP4460: ram init changes OMAP4460: clock init arch/arm/boards/panda/lowlevel.c|4 +- arch/arm/boards/panda/mux.c |8 +++ arch/arm/boards/pcm049/lowlevel.c | 15 -- arch/arm/boards/pcm049/mux.c|8 +++ arch/arm/boards/phycard-a-xl2/lowlevel.c| 13 - arch/arm/boards/phycard-a-xl2/mux.c |8 +++ arch/arm/mach-omap/include/mach/omap4-clock.h | 19 +++ arch/arm/mach-omap/include/mach/omap4-silicon.h | 13 +- arch/arm/mach-omap/omap4_clock.c| 58 +- arch/arm/mach-omap/omap4_generic.c | 60 +-- 10 files changed, 181 insertions(+), 25 deletions(-) ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH 3/3] OMAP4460: clock init
Change clock init to allow early gpio access. Add support for 4460 clocks.
Signed-off-by: Jan Weitzel j.weit...@phytec.de
---
arch/arm/boards/panda/mux.c |8 +
arch/arm/boards/pcm049/lowlevel.c | 11 +--
arch/arm/boards/pcm049/mux.c |8 +
arch/arm/boards/phycard-a-xl2/lowlevel.c |9 -
arch/arm/boards/phycard-a-xl2/mux.c |8 +
arch/arm/mach-omap/include/mach/omap4-clock.h |4 ++
arch/arm/mach-omap/omap4_clock.c | 39 +---
7 files changed, 70 insertions(+), 17 deletions(-)
diff --git a/arch/arm/boards/panda/mux.c b/arch/arm/boards/panda/mux.c
index 310e433..3783006 100644
--- a/arch/arm/boards/panda/mux.c
+++ b/arch/arm/boards/panda/mux.c
@@ -3,6 +3,7 @@
#include io.h
#include mach/omap4-silicon.h
#include mach/omap4-mux.h
+#include mach/omap4-clock.h
static const struct pad_conf_entry core_padconf_array[] = {
{ GPMC_AD0, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* sdmmc2_dat0
*/ },
@@ -245,4 +246,11 @@ void set_muxconf_regs(void)
omap4_do_set_mux(OMAP44XX_CONTROL_PADCONF_WKUP, wkup_padconf_array,
ARRAY_SIZE(wkup_padconf_array));
+
+ /* gpio_wk7 is used for controlling TPS on 4460 */
+ if (omap4_revision() = OMAP4460_ES1_0) {
+ writew(M3, OMAP44XX_CONTROL_PADCONF_WKUP + PAD1_FREF_CLK4_REQ);
+ /* Enable GPIO-1 clocks before TPS initialization */
+ omap4_enable_gpio1_wup_clocks();
+ }
}
diff --git a/arch/arm/boards/pcm049/lowlevel.c
b/arch/arm/boards/pcm049/lowlevel.c
index 5e591fa..65a29ec 100644
--- a/arch/arm/boards/pcm049/lowlevel.c
+++ b/arch/arm/boards/pcm049/lowlevel.c
@@ -48,7 +48,8 @@ static const struct ddr_regs ddr_regs_mt42L64M64_25_400_mhz =
{
static void noinline pcm049_init_lowlevel(void)
{
struct dpll_param core = OMAP4_CORE_DPLL_PARAM_19M2_DDR400;
- struct dpll_param mpu = OMAP4_MPU_DPLL_PARAM_19M2_MPU1000;
+ struct dpll_param mpu44xx = OMAP4_MPU_DPLL_PARAM_19M2_MPU1000;
+ struct dpll_param mpu4460 = OMAP4_MPU_DPLL_PARAM_19M2_MPU920;
struct dpll_param iva = OMAP4_IVA_DPLL_PARAM_19M2;
struct dpll_param per = OMAP4_PER_DPLL_PARAM_19M2;
struct dpll_param abe = OMAP4_ABE_DPLL_PARAM_19M2;
@@ -64,7 +65,11 @@ static void noinline pcm049_init_lowlevel(void)
writel(CM_SYS_CLKSEL_19M2, CM_SYS_CLKSEL);
/* Configure all DPLL's at 100% OPP */
- omap4_configure_mpu_dpll(mpu);
+ if (omap4_revision() OMAP4460_ES1_0)
+ omap4_configure_mpu_dpll(mpu44xx);
+ else
+ omap4_configure_mpu_dpll(mpu4460);
+
omap4_configure_iva_dpll(iva);
omap4_configure_per_dpll(per);
omap4_configure_abe_dpll(abe);
@@ -90,7 +95,7 @@ void board_init_lowlevel(void)
return;
r = 0x4030d000;
-__asm__ __volatile__(mov sp, %0 : : r(r));
+ __asm__ __volatile__(mov sp, %0 : : r(r));
pcm049_init_lowlevel();
}
diff --git a/arch/arm/boards/pcm049/mux.c b/arch/arm/boards/pcm049/mux.c
index a7a77b5..04e1d67 100644
--- a/arch/arm/boards/pcm049/mux.c
+++ b/arch/arm/boards/pcm049/mux.c
@@ -3,6 +3,7 @@
#include io.h
#include mach/omap4-silicon.h
#include mach/omap4-mux.h
+#include mach/omap4-clock.h
static const struct pad_conf_entry core_padconf_array[] = {
{GPMC_AD0, (IEN | PTD | DIS | M0)}, /*
gpmc_ad0 */
@@ -242,4 +243,11 @@ void set_muxconf_regs(void)
omap4_do_set_mux(OMAP44XX_CONTROL_PADCONF_WKUP, wkup_padconf_array,
ARRAY_SIZE(wkup_padconf_array));
+
+ /* gpio_182 is used for controlling TPS on 4460 */
+ if (omap4_revision() = OMAP4460_ES1_0) {
+ writew(M3, OMAP44XX_CONTROL_PADCONF_CORE + FREF_CLK2_OUT);
+ /* Enable GPIO-1 clocks before TPS initialization */
+ omap4_enable_gpio_clocks();
+ }
}
diff --git a/arch/arm/boards/phycard-a-xl2/lowlevel.c
b/arch/arm/boards/phycard-a-xl2/lowlevel.c
index 2aa79a8..38f80c9 100644
--- a/arch/arm/boards/phycard-a-xl2/lowlevel.c
+++ b/arch/arm/boards/phycard-a-xl2/lowlevel.c
@@ -48,7 +48,8 @@ static const struct ddr_regs ddr_regs_mt42L64M64_25_400_mhz =
{
static noinline void pcaaxl2_init_lowlevel(void)
{
struct dpll_param core = OMAP4_CORE_DPLL_PARAM_19M2_DDR400;
- struct dpll_param mpu = OMAP4_MPU_DPLL_PARAM_19M2_MPU1000;
+ struct dpll_param mpu44xx = OMAP4_MPU_DPLL_PARAM_19M2_MPU1000;
+ struct dpll_param mpu4460 = OMAP4_MPU_DPLL_PARAM_19M2_MPU920;
struct dpll_param iva = OMAP4_IVA_DPLL_PARAM_19M2;
struct dpll_param per = OMAP4_PER_DPLL_PARAM_19M2;
struct dpll_param abe = OMAP4_ABE_DPLL_PARAM_19M2;
@@ -64,7 +65,11 @@ static noinline void pcaaxl2_init_lowlevel(void)
writel(CM_SYS_CLKSEL_19M2, CM_SYS_CLKSEL);
/* Configure all DPLL's at 100% OPP */
-
[for master PATCH 2/2] calao: at91 qil/tny/usb auto detect the phy addr
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD plagn...@jcrosoft.com
---
arch/arm/boards/qil-a9260/init.c |2 +-
arch/arm/boards/tny-a926x/init.c |2 +-
arch/arm/boards/usb-a926x/init.c |2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boards/qil-a9260/init.c b/arch/arm/boards/qil-a9260/init.c
index ee204fb..92aea97 100644
--- a/arch/arm/boards/qil-a9260/init.c
+++ b/arch/arm/boards/qil-a9260/init.c
@@ -80,7 +80,7 @@ static void qil_a9260_add_device_mci(void) {}
#ifdef CONFIG_CALAO_MB_QIL_A9260
static struct at91_ether_platform_data macb_pdata = {
.flags = AT91SAM_ETHER_RMII,
- .phy_addr = 0,
+ .phy_addr = -1,
};
static void qil_a9260_phy_reset(void)
diff --git a/arch/arm/boards/tny-a926x/init.c b/arch/arm/boards/tny-a926x/init.c
index d58132a..556e633 100644
--- a/arch/arm/boards/tny-a926x/init.c
+++ b/arch/arm/boards/tny-a926x/init.c
@@ -118,7 +118,7 @@ static void tny_a9260_add_device_nand(void)
#ifdef CONFIG_DRIVER_NET_MACB
static struct at91_ether_platform_data macb_pdata = {
.flags = AT91SAM_ETHER_RMII,
- .phy_addr = 0,
+ .phy_addr = -1,
};
static void __init ek_add_device_macb(void)
diff --git a/arch/arm/boards/usb-a926x/init.c b/arch/arm/boards/usb-a926x/init.c
index 52444e1..7b19fa4 100644
--- a/arch/arm/boards/usb-a926x/init.c
+++ b/arch/arm/boards/usb-a926x/init.c
@@ -122,7 +122,7 @@ static void usb_a9260_add_device_nand(void) {}
#if defined(CONFIG_DRIVER_NET_MACB)
static struct at91_ether_platform_data macb_pdata = {
.flags = AT91SAM_ETHER_RMII,
- .phy_addr = 0,
+ .phy_addr = -1,
};
static void usb_a9260_phy_reset(void)
--
1.7.10.4
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[PATCH 0/7] smsc911x: runtime configuration improvement
Hi, please pull The following changes since commit 3f96b4938c4046590be8a38fb114148c4bf1ca8e: Merge tag 'bootm_fix' of git://git.jcrosoft.org/barebox (2012-08-13 20:37:53 +0200) are available in the git repository at: git://git.jcrosoft.org/barebox.git tags/smc911x_improve for you to fetch changes up to 865ba468b906292c0158b8734dee5a31688e332b: smm911x: check if the device is ready before using it (2012-08-15 01:19:54 +0800) smsc911x: runtime configuration improvement This patch series allow to detect and configure the drivers at the runtime - Check if the device is ready before using it - Update chip detection (take from the kernel 3.5) - improve detection handle to detect bus configuration and swap - add support to pass the shift via platform data - add 16bit bus width support - introduce read/write ops - move register define to smc911x.h Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD plagn...@jcrosoft.com Jean-Christophe PLAGNIOL-VILLARD (7): smc911x: move register define to smc911x.h smc911x: introduce read/write ops smc911x: add 16bit bus width support smc911x: add support to pass the shift via platform data smc911x: improve detection handle smc911x: update chip detection smm911x: check if the device is ready before using it arch/blackfin/boards/ipe337/ipe337.c |7 +- drivers/net/Kconfig |6 -- drivers/net/smc911x.c| 569 - drivers/net/smc911x.h| 364 ++ include/smc911x.h| 18 + 5 files changed, 567 insertions(+), 397 deletions(-) create mode 100644 drivers/net/smc911x.h create mode 100644 include/smc911x.h Best Regards, J. ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH 5/7] smc911x: improve detection handle
detect if the bus is swapped and report a 32bit drivers is used on a 16bit bus
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD plagn...@jcrosoft.com
---
drivers/net/smc911x.c | 20 +++-
drivers/net/smc911x.h |2 ++
2 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index de2f388..67d82df 100644
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -450,9 +450,27 @@ static int smc911x_probe(struct device_d *dev)
}
val = smc911x_reg_read(priv, BYTE_TEST);
- if(val != 0x87654321) {
+ if (val == 0x43218765) {
+ dev_info(dev, BYTE_TEST looks swapped,
+ applying WORD_SWAP);
+ smc911x_reg_write(priv, WORD_SWAP, 0x);
+
+ /* 1 dummy read of BYTE_TEST is needed after a write to
+* WORD_SWAP before its contents are valid */
+ val = smc911x_reg_read(priv, BYTE_TEST);
+
+ val = smc911x_reg_read(priv, BYTE_TEST);
+ }
+
+ if (val != 0x87654321) {
dev_err(dev, no smc911x found on 0x%p (byte_test=0x%08x)\n,
priv-base, val);
+ if (((val 16) 0x) == (val 0x)) {
+ dev_err(dev, top 16 bits equal to bottom 16 bits\n);
+ dev_err(dev,
+ This may mean the chip is set
+ for 32 bit while the bus is reading 16
bit\n);
+ }
return -ENODEV;
}
diff --git a/drivers/net/smc911x.h b/drivers/net/smc911x.h
index baf3598..d409247 100644
--- a/drivers/net/smc911x.h
+++ b/drivers/net/smc911x.h
@@ -26,6 +26,8 @@
* of the Lan911x memory space
*/
+#define WORD_SWAP 0x98
+
#define RX_DATA_FIFO0x00
#define TX_DATA_FIFO0x20
--
1.7.10.4
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[PATCH 6/7] smc911x: update chip detection
Use linux kernel chip detection from 3.5
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD plagn...@jcrosoft.com
---
drivers/net/smc911x.c | 59 +++--
drivers/net/smc911x.h | 33 +--
2 files changed, 54 insertions(+), 38 deletions(-)
diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index 67d82df..021a194 100644
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -48,29 +48,12 @@ struct smc911x_priv {
u32 width;
int shift;
+ int generation;
u32 (*reg_read)(struct smc911x_priv *priv, u32 reg);
void (*reg_write)(struct smc911x_priv *priv, u32 reg, u32 val);
};
-struct chip_id {
- u16 id;
- char *name;
-};
-
-static const struct chip_id chip_ids[] = {
- { CHIP_9115, LAN9115 },
- { CHIP_9116, LAN9116 },
- { CHIP_9117, LAN9117 },
- { CHIP_9118, LAN9118 },
- { CHIP_9215, LAN9215 },
- { CHIP_9216, LAN9216 },
- { CHIP_9217, LAN9217 },
- { CHIP_9218, LAN9218 },
- { CHIP_9221, LAN9221 },
- { 0, NULL },
-};
-
#define DRIVERNAME smc911x
#define __smc_shift(priv, reg) ((reg) ((priv)-shift))
@@ -429,7 +412,6 @@ static int smc911x_probe(struct device_d *dev)
struct eth_device *edev;
struct smc911x_priv *priv;
uint32_t val;
- int i;
struct smc911x_plat *pdata = dev-platform_data;
priv = xzalloc(sizeof(*priv));
@@ -474,16 +456,41 @@ static int smc911x_probe(struct device_d *dev)
return -ENODEV;
}
- val = smc911x_reg_read(priv, ID_REV) 16;
- for(i = 0; chip_ids[i].id != 0; i++) {
- if (chip_ids[i].id == val) break;
- }
- if (!chip_ids[i].id) {
- dev_err(dev, Unknown chip ID %04x\n, val);
+ val = smc911x_reg_read(priv, ID_REV);
+ switch (val 0x) {
+ case 0x0118:
+ case 0x0117:
+ case 0x0116:
+ case 0x0115:
+ case 0x218A:
+ /* LAN911[5678] family */
+ priv-generation = val 0x;
+ break;
+
+ case 0x118A:
+ case 0x117A:
+ case 0x116A:
+ case 0x115A:
+ /* LAN921[5678] family */
+ priv-generation = 3;
+ break;
+
+ case 0x9210:
+ case 0x9211:
+ case 0x9220:
+ case 0x9221:
+ /* LAN9210/LAN9211/LAN9220/LAN9221 */
+ priv-generation = 4;
+ break;
+
+ default:
+ dev_err(dev, LAN911x not identified, idrev: 0x%08X\n,
+ val);
return -ENODEV;
}
- dev_info(dev, detected %s controller\n, chip_ids[i].name);
+ dev_info(dev, LAN911x identified, idrev: 0x%08X, generation: %d\n,
+ val, priv-generation);
edev = priv-edev;
edev-priv = priv;
diff --git a/drivers/net/smc911x.h b/drivers/net/smc911x.h
index d409247..623e192 100644
--- a/drivers/net/smc911x.h
+++ b/drivers/net/smc911x.h
@@ -341,15 +341,24 @@
#define WUCSR_WAKE_EN 0x0004
#define WUCSR_MPEN 0x0002
-/* Chip ID values */
-#define CHIP_9115 0x115
-#define CHIP_9116 0x116
-#define CHIP_9117 0x117
-#define CHIP_9118 0x118
-#define CHIP_9215 0x115a
-#define CHIP_9216 0x116a
-#define CHIP_9217 0x117a
-#define CHIP_9218 0x118a
-#define CHIP_9221 0x9221
-
-
+/* SMSC PHY */
+#define MII_LAN83C185_ISF 29 /* Interrupt Source Flags */
+#define MII_LAN83C185_IM 30 /* Interrupt Mask */
+#define MII_LAN83C185_CTRL_STATUS 17 /* Mode/Status Register */
+
+#define MII_LAN83C185_ISF_INT1 (11) /* Auto-Negotiation Page Received */
+#define MII_LAN83C185_ISF_INT2 (12) /* Parallel Detection Fault */
+#define MII_LAN83C185_ISF_INT3 (13) /* Auto-Negotiation LP Ack */
+#define MII_LAN83C185_ISF_INT4 (14) /* Link Down */
+#define MII_LAN83C185_ISF_INT5 (15) /* Remote Fault Detected */
+#define MII_LAN83C185_ISF_INT6 (16) /* Auto-Negotiation complete */
+#define MII_LAN83C185_ISF_INT7 (17) /* ENERGYON */
+
+#define MII_LAN83C185_ISF_INT_ALL (0x0e)
+
+#define MII_LAN83C185_ISF_INT_PHYLIB_EVENTS \
+ (MII_LAN83C185_ISF_INT6 | MII_LAN83C185_ISF_INT4 | \
+MII_LAN83C185_ISF_INT7)
+
+#define MII_LAN83C185_EDPWRDOWN (1 13) /* EDPWRDOWN */
+#define MII_LAN83C185_ENERGYON (1 1) /* ENERGYON */
--
1.7.10.4
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[PATCH 3/7] smc911x: add 16bit bus width support
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD plagn...@jcrosoft.com
---
drivers/net/smc911x.c | 20 ++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index 2583235..c74ed52 100644
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -47,6 +47,8 @@ struct smc911x_priv {
struct mii_device miidev;
void __iomem *base;
+ u32 width;
+
u32 (*reg_read)(struct smc911x_priv *priv, u32 reg);
void (*reg_write)(struct smc911x_priv *priv, u32 reg, u32 val);
};
@@ -78,7 +80,11 @@ static inline u32 smc911x_reg_read(struct smc911x_priv
*priv, u32 reg)
static inline u32 __smc911x_reg_read(struct smc911x_priv *priv, u32 reg)
{
- return readl(priv-base + reg);
+ if (priv-width)
+ return readl(priv-base + reg);
+ else
+ return ((readw(priv-base + reg) 0x) |
+ ((readw(priv-base + reg + 2) 0x) 16));
}
static inline void smc911x_reg_write(struct smc911x_priv *priv, u32 reg,
@@ -90,7 +96,12 @@ static inline void smc911x_reg_write(struct smc911x_priv
*priv, u32 reg,
static inline void __smc911x_reg_write(struct smc911x_priv *priv, u32 reg,
u32 val)
{
- writel(val, priv-base + reg);
+ if (priv-width) {
+ writel(val, priv-base + reg);
+ } else {
+ writew(val 0x, priv-base + reg);
+ writew((val 16) 0x, priv-base + reg + 2);
+ }
}
static int smc911x_mac_wait_busy(struct smc911x_priv *priv)
@@ -393,6 +404,11 @@ static int smc911x_probe(struct device_d *dev)
int i;
priv = xzalloc(sizeof(*priv));
+ priv-width = dev-resource[0].flags IORESOURCE_MEM_TYPE_MASK;
+ if (!priv-width)
+ priv-width = 1;
+ else
+ priv-width = priv-width == IORESOURCE_MEM_32BIT;
priv-base = dev_request_mem_region(dev, 0);
priv-reg_read = __smc911x_reg_read;
priv-reg_write = __smc911x_reg_write;
--
1.7.10.4
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Re: [for master PATCH 1/2] miidev: add phy_addr detection support
On Tue, Aug 14, 2012 at 05:48:55PM +0200, Jean-Christophe PLAGNIOL-VILLARD
wrote:
export via param the phy_addr and the phy_id detected
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD plagn...@jcrosoft.com
---
Hi,
this is need to fix the calao board support since the introduction of
the gigabit phy detection support
Can you explain what this has to do with gigabit support?
Sascha
Best Regards,
J.
drivers/net/miidev.c | 76
++
include/miidev.h |2 ++
2 files changed, 72 insertions(+), 6 deletions(-)
diff --git a/drivers/net/miidev.c b/drivers/net/miidev.c
index b49944b..ab1811d 100644
--- a/drivers/net/miidev.c
+++ b/drivers/net/miidev.c
@@ -236,18 +236,82 @@ static struct file_operations miidev_ops = {
.lseek = dev_lseek_default,
};
+static int get_phy_id(struct mii_device *mdev, int phy_addr,
+ uint32_t *phy_id)
+{
+ int val;
+
+ val = mii_read(mdev, phy_addr, MII_PHYSID1);
+ if (val 0)
+ return -EIO;
+ *phy_id = (val 0x) 16;
+ val = mii_read(mdev, phy_addr, MII_PHYSID2);
+ if (val 0)
+ return -EIO;
+ *phy_id |= (val 0x);
+
+ return 0;
+}
+
+static int phy_detect_one(struct mii_device *mdev, int phy_addr,
+ uint32_t *phy_id)
+{
+ uint32_t _phy_id;
+ int ret;
+
+ ret = get_phy_id(mdev, phy_addr, _phy_id);
+
+ if (ret)
+ return ret;
+
+ /* If the phy_id is mostly Fs, there is no device there */
+ if ((_phy_id 0x1fff) == 0x1fff)
+ return -EIO;
+
+ *phy_id = _phy_id;
+
+ return 0;
+}
+
+static int phy_detect(struct mii_device *mdev)
+{
+ int phy_addr;
+
+ for (phy_addr = 0; phy_addr = 0x1f; phy_addr++) {
+ if (!phy_detect_one(mdev, phy_addr, mdev-phy_id))
+ return phy_addr;
+ }
+
+ return -EIO;
+}
+
static int miidev_probe(struct device_d *dev)
{
struct mii_device *mdev = dev-priv;
int val;
int caps = 0;
+ char str[11];
+
+ if (mdev-address 0) {
+ int phy_addr;
+
+ phy_addr = phy_detect(mdev);
+
+ if (phy_addr 0) {
+ dev_err(dev, cannot detect PHY\n);
+ return -ENODEV;
+ }
+ mdev-address = phy_addr;
+ } else {
+ if (phy_detect_one(mdev, mdev-address, mdev-phy_id) 0)
+ goto err_out;
+ }
+
+ sprintf(str, %u, mdev-address);
+ dev_add_param_fixed(dev, phy_addr, str);
+ sprintf(str, 0x%08x, mdev-phy_id);
+ dev_add_param_fixed(dev, phy_id, str);
- val = mii_read(mdev, mdev-address, MII_PHYSID1);
- if (val 0 || val == 0x)
- goto err_out;
- val = mii_read(mdev, mdev-address, MII_PHYSID2);
- if (val 0 || val == 0x)
- goto err_out;
val = mii_read(mdev, mdev-address, MII_BMSR);
if (val 0)
goto err_out;
diff --git a/include/miidev.h b/include/miidev.h
index 4bbf94c..2f39234 100644
--- a/include/miidev.h
+++ b/include/miidev.h
@@ -38,6 +38,8 @@ struct mii_device {
struct device_d *parent;
int address;/* The address the phy has on the bus */
+ uint32_t phy_id;/* The phy id */
+
int (*read) (struct mii_device *dev, int addr, int reg);
int (*write) (struct mii_device *dev, int addr, int reg, int value);
--
1.7.10.4
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Re: [PATCH 0/3 v2] omap: 4460 support
On Tue, Aug 14, 2012 at 09:04:30AM +0200, Jan Weitzel wrote: Add support for OMAP4460 cpu on top of ed358834 (next) v2: merge usage of omap4_scale_vcores to 1/3 avoid volatile int* Applied, thanks Sascha Jan Weitzel (3): Add support for OMAP4460 TPS62361 OMAP4460: ram init changes OMAP4460: clock init arch/arm/boards/panda/lowlevel.c|4 +- arch/arm/boards/panda/mux.c |8 +++ arch/arm/boards/pcm049/lowlevel.c | 15 -- arch/arm/boards/pcm049/mux.c|8 +++ arch/arm/boards/phycard-a-xl2/lowlevel.c| 13 - arch/arm/boards/phycard-a-xl2/mux.c |8 +++ arch/arm/mach-omap/include/mach/omap4-clock.h | 19 +++ arch/arm/mach-omap/include/mach/omap4-silicon.h | 13 +- arch/arm/mach-omap/omap4_clock.c| 58 +- arch/arm/mach-omap/omap4_generic.c | 60 +-- 10 files changed, 181 insertions(+), 25 deletions(-) ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH 1/7] smc911x: move register define to smc911x.h
On Tue, Aug 14, 2012 at 07:32:14PM +0200, Jean-Christophe PLAGNIOL-VILLARD
wrote:
this make the driver more readable
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD plagn...@jcrosoft.com
---
drivers/net/smc911x.c| 329 +--
drivers/net/{smc911x.c = smc911x.h} | 406
--
2 files changed, 2 insertions(+), 733 deletions(-)
copy drivers/net/{smc911x.c = smc911x.h} (60%)
This is only churn. Please drop.
Sascha
diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index 7dddbbc..9c488c7 100644
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -38,334 +38,9 @@
#include clock.h
#include io.h
-#define AS CONFIG_DRIVER_NET_SMC911X_ADDRESS_SHIFT
-/* Below are the register offsets and bit definitions
- * of the Lan911x memory space
- */
-#define RX_DATA_FIFO (0x00 AS)
-
-#define TX_DATA_FIFO (0x20 AS)
-#define TX_CMD_A_INT_ON_COMP0x8000
-#define TX_CMD_A_INT_BUF_END_ALGN 0x0300
-#define TX_CMD_A_INT_4_BYTE_ALGN0x
-#define TX_CMD_A_INT_16_BYTE_ALGN 0x0100
-#define TX_CMD_A_INT_32_BYTE_ALGN 0x0200
-#define TX_CMD_A_INT_DATA_OFFSET0x001F
-#define TX_CMD_A_INT_FIRST_SEG 0x2000
-#define TX_CMD_A_INT_LAST_SEG 0x1000
-#define TX_CMD_A_BUF_SIZE 0x07FF
-#define TX_CMD_B_PKT_TAG0x
-#define TX_CMD_B_ADD_CRC_DISABLE0x2000
-#define TX_CMD_B_DISABLE_PADDING0x1000
-#define TX_CMD_B_PKT_BYTE_LENGTH0x07FF
-
-#define RX_STATUS_FIFO (0x40 AS)
-#define RX_STS_PKT_LEN 0x3FFF
-#define RX_STS_ES 0x8000
-#define RX_STS_BCST 0x2000
-#define RX_STS_LEN_ERR 0x1000
-#define RX_STS_RUNT_ERR 0x0800
-#define RX_STS_MCAST0x0400
-#define RX_STS_TOO_LONG 0x0080
-#define RX_STS_COLL 0x0040
-#define RX_STS_ETH_TYPE 0x0020
-#define RX_STS_WDOG_TMT 0x0010
-#define RX_STS_MII_ERR 0x0008
-#define RX_STS_DRIBBLING0x0004
-#define RX_STS_CRC_ERR 0x0002
-#define RX_STATUS_FIFO_PEEK (0x44 AS)
-#define TX_STATUS_FIFO (0x48 AS)
-#define TX_STS_TAG 0x
-#define TX_STS_ES 0x8000
-#define TX_STS_LOC 0x0800
-#define TX_STS_NO_CARR 0x0400
-#define TX_STS_LATE_COLL0x0200
-#define TX_STS_MANY_COLL0x0100
-#define TX_STS_COLL_CNT 0x0078
-#define TX_STS_MANY_DEFER 0x0004
-#define TX_STS_UNDERRUN 0x0002
-#define TX_STS_DEFERRED 0x0001
-#define TX_STATUS_FIFO_PEEK (0x4C AS)
-#define ID_REV (0x50 AS)
-#define ID_REV_CHIP_ID 0x /* RO */
-#define ID_REV_REV_ID 0x /* RO */
-
-#define INT_CFG (0x54 AS)
-#define INT_CFG_INT_DEAS0xFF00 /* R/W */
-#define INT_CFG_INT_DEAS_CLR0x4000
-#define INT_CFG_INT_DEAS_STS0x2000
-#define INT_CFG_IRQ_INT 0x1000 /* RO */
-#define INT_CFG_IRQ_EN 0x0100 /* R/W */
-#define INT_CFG_IRQ_POL 0x0010 /* R/W Not
Affected by SW Reset */
-#define INT_CFG_IRQ_TYPE0x0001 /* R/W Not
Affected by SW Reset */
-
-#define INT_STS (0x58 AS)
-#define INT_STS_SW_INT 0x8000 /* R/WC */
-#define INT_STS_TXSTOP_INT 0x0200 /* R/WC */
-#define INT_STS_RXSTOP_INT 0x0100 /* R/WC */
-#define INT_STS_RXDFH_INT 0x0080 /* R/WC */
-#define INT_STS_RXDF_INT0x0040 /* R/WC */
-#define INT_STS_TX_IOC 0x0020 /* R/WC */
-#define INT_STS_RXD_INT 0x0010 /* R/WC */
-#define INT_STS_GPT_INT
Re: [PATCH 3/7] smc911x: add 16bit bus width support
On Tue, Aug 14, 2012 at 07:32:16PM +0200, Jean-Christophe PLAGNIOL-VILLARD
wrote:
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD plagn...@jcrosoft.com
---
drivers/net/smc911x.c | 20 ++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index 2583235..c74ed52 100644
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -47,6 +47,8 @@ struct smc911x_priv {
struct mii_device miidev;
void __iomem *base;
+ u32 width;
+
u32 (*reg_read)(struct smc911x_priv *priv, u32 reg);
void (*reg_write)(struct smc911x_priv *priv, u32 reg, u32 val);
};
@@ -78,7 +80,11 @@ static inline u32 smc911x_reg_read(struct smc911x_priv
*priv, u32 reg)
static inline u32 __smc911x_reg_read(struct smc911x_priv *priv, u32 reg)
{
- return readl(priv-base + reg);
+ if (priv-width)
+ return readl(priv-base + reg);
+ else
+ return ((readw(priv-base + reg) 0x) |
+ ((readw(priv-base + reg + 2) 0x) 16));
}
If you introduce function pointers for the read/write functions, then
please use them to implement 16bit support.
Sascha
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vacation
Hi all, I am on vacation for the next week and won't have internet connection until August 24. Have fun! Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH 3/7] smc911x: add 16bit bus width support
On 22:21 Tue 14 Aug , Sascha Hauer wrote:
On Tue, Aug 14, 2012 at 07:32:16PM +0200, Jean-Christophe PLAGNIOL-VILLARD
wrote:
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD plagn...@jcrosoft.com
---
drivers/net/smc911x.c | 20 ++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index 2583235..c74ed52 100644
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -47,6 +47,8 @@ struct smc911x_priv {
struct mii_device miidev;
void __iomem *base;
+ u32 width;
+
u32 (*reg_read)(struct smc911x_priv *priv, u32 reg);
void (*reg_write)(struct smc911x_priv *priv, u32 reg, u32 val);
};
@@ -78,7 +80,11 @@ static inline u32 smc911x_reg_read(struct smc911x_priv
*priv, u32 reg)
static inline u32 __smc911x_reg_read(struct smc911x_priv *priv, u32 reg)
{
- return readl(priv-base + reg);
+ if (priv-width)
+ return readl(priv-base + reg);
+ else
+ return ((readw(priv-base + reg) 0x) |
+ ((readw(priv-base + reg + 2) 0x) 16));
}
If you introduce function pointers for the read/write functions, then
please use them to implement 16bit support.
this what this patch do
Best Regards,
J.
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Re: [PATCH 1/7] smc911x: move register define to smc911x.h
On 22:19 Tue 14 Aug , Sascha Hauer wrote:
On Tue, Aug 14, 2012 at 07:32:14PM +0200, Jean-Christophe PLAGNIOL-VILLARD
wrote:
this make the driver more readable
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD plagn...@jcrosoft.com
---
drivers/net/smc911x.c| 329 +--
drivers/net/{smc911x.c = smc911x.h} | 406
--
2 files changed, 2 insertions(+), 733 deletions(-)
copy drivers/net/{smc911x.c = smc911x.h} (60%)
This is only churn. Please drop.
I'm going to use the linux one and sync both of them
in a second patch series with more improvement so this help
Best Regards,
J.
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