Re: [RFC v4 01/10] Add initial RISC-V architecture support
On Mon, 2 Oct 2017 12:08:58 +0200 Daniel Schultzwrote: > Hi, > > > On 09/29/2017 02:07 PM, Oleksij Rempel wrote: > > Hi, > > > > hm... mostly looks identical with existing arch > > > > Am 29.09.2017 um 01:12 schrieb Antony Pavlov: > >> Signed-off-by: Antony Pavlov > >> -- > >> TODOs: > >> > >>* split patch; > >> --- > >> arch/riscv/Kconfig | 73 + > >> arch/riscv/Makefile | 68 +++ > >> arch/riscv/boot/Makefile | 2 + > >> arch/riscv/boot/main_entry.c | 40 > >> arch/riscv/boot/start.S | 74 ++ > >> arch/riscv/dts/.gitignore| > arch/riscv/dts/Makefile > >>| 9 > >> arch/riscv/dts/skeleton.dtsi | 13 ++ > >> arch/riscv/include/asm/barebox.h | 1 + > >> arch/riscv/include/asm/bitops.h | 35 ++ > >> arch/riscv/include/asm/bitsperlong.h | 10 > >> arch/riscv/include/asm/byteorder.h | 10 > >> arch/riscv/include/asm/common.h | 6 +++ > >> arch/riscv/include/asm/elf.h | 11 + > >> arch/riscv/include/asm/io.h | 8 > >> arch/riscv/include/asm/mmu.h | 6 +++ > >> arch/riscv/include/asm/posix_types.h | 1 + > >> arch/riscv/include/asm/sections.h| 1 + > >> arch/riscv/include/asm/string.h | 1 + > >> arch/riscv/include/asm/swab.h| 6 +++ > >> arch/riscv/include/asm/types.h | 60 > >> arch/riscv/include/asm/unaligned.h | 19 > >> arch/riscv/lib/.gitignore| 1 + > >> arch/riscv/lib/Makefile | 9 > >> arch/riscv/lib/ashldi3.c | 28 > >> arch/riscv/lib/ashrdi3.c | 30 > >> arch/riscv/lib/asm-offsets.c | 12 + > >> arch/riscv/lib/barebox.lds.S | 89 > >> > >> arch/riscv/lib/dtb.c | 41 + > >> arch/riscv/lib/libgcc.h | 29 > >> arch/riscv/lib/lshrdi3.c | 28 > >> arch/riscv/lib/riscv_timer.c | 68 +++ > >> drivers/of/Kconfig | 2 +- > >> 33 files changed, 791 insertions(+), 1 deletion(-) > >> > >> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > >> new file mode 100644 > >> index 0..b2f0817ef > >> --- /dev/null > >> +++ b/arch/riscv/Kconfig > >> @@ -0,0 +1,73 @@ > >> +config RISCV > >> + bool > >> + select GENERIC_FIND_NEXT_BIT > >> + select HAVE_CONFIGURABLE_MEMORY_LAYOUT > >> + select HAVE_CONFIGURABLE_TEXT_BASE > >> + select GPIOLIB > >> + select OFTREE > >> + select COMMON_CLK > >> + select COMMON_CLK_OF_PROVIDER > >> + select CLKDEV_LOOKUP > >> + default y > >> + > >> +config ARCH_TEXT_BASE > >> + hex > >> + default 0x0 > >> + > >> +config GENERIC_LINKER_SCRIPT > >> + bool > >> + default y > >> + > >> +menu "Machine selection" > >> + > >> +choice > >> + prompt "CPU selection" > >> + default CPU_RV_GENERIC > >> + > >> +config CPU_RV_GENERIC > >> + bool "Generic RISC-V" > >> + select CPU_SUPPORTS_32BIT_KERNEL > >> + select CPU_SUPPORTS_64BIT_KERNEL > >> + > >> +endchoice > >> + > >> +config CPU_SUPPORTS_32BIT_KERNEL > >> + bool > >> +config CPU_SUPPORTS_64BIT_KERNEL > >> + bool > >> + > >> +choice > >> + prompt "barebox code model" > >> + default 64BIT > >> + > >> +config 32BIT > >> + bool "32-bit barebox" > >> + depends on CPU_SUPPORTS_32BIT_KERNEL > >> + help > >> +Select this option to build a 32-bit barebox. > >> + > >> +config 64BIT > >> + bool "64-bit barebox" > >> + depends on CPU_SUPPORTS_64BIT_KERNEL > >> + help > >> +Select this option to build a 64-bit barebox. > >> + > >> +endchoice > >> + > >> +config BUILTIN_DTB > >> + bool "link a DTB into the barebox image" > >> + depends on OFTREE > >> + > >> +config BUILTIN_DTB_NAME > >> + string "DTB to build into the barebox image" > >> + depends on BUILTIN_DTB > >> + > >> +endmenu > >> + > >> +source common/Kconfig > >> +source commands/Kconfig > >> +source net/Kconfig > >> +source drivers/Kconfig > >> +source fs/Kconfig > >> +source lib/Kconfig > >> +source crypto/Kconfig > >> diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile > >> new file mode 100644 > >> index 0..4e3318cf1 > >> --- /dev/null > >> +++ b/arch/riscv/Makefile > >> @@ -0,0 +1,68 @@ > >> +CPPFLAGS += -fno-strict-aliasing > >> + > >> +cflags-y += -fno-pic -pipe > >> +cflags-y += -Wall -Wmissing-prototypes -Wstrict-prototypes \ > >> + -Wno-uninitialized -Wno-format -Wno-main -mcmodel=medany > >> + > >> +LDFLAGS += $(ldflags-y) > >> +LDFLAGS_barebox += -nostdlib > >> + > >> +TEXT_BASE = $(CONFIG_TEXT_BASE) > >> +CPPFLAGS += -DTEXT_BASE=$(CONFIG_TEXT_BASE) > >> + > >> +ifndef CONFIG_MODULES > >> +# Add cleanup flags > >> +CPPFLAGS +=
Re: [RFC v4 01/10] Add initial RISC-V architecture support
On Mon, 2 Oct 2017 12:04:30 +0200 Daniel Schultzwrote: > Hi, > > > On 09/30/2017 01:57 PM, Antony Pavlov wrote: > > On Fri, 29 Sep 2017 14:07:09 +0200 > > Oleksij Rempel wrote: > > > >> Hi, > >> > >> hm... mostly looks identical with existing arch > > What do you mean when you say "existing arch"? > > > > ... > > > >> Am 29.09.2017 um 01:12 schrieb Antony Pavlov: > > ... > >>> diff --git a/arch/riscv/boot/start.S b/arch/riscv/boot/start.S > >>> new file mode 100644 > >>> index 0..2fd00f63d > >>> --- /dev/null > >>> +++ b/arch/riscv/boot/start.S > >>> @@ -0,0 +1,74 @@ > >>> +/* > >>> + * Startup Code for MIPS CPU > >>> + * > >>> + * based on coreboot/src/arch/riscv/bootblock.S > >>> + * > >>> + * Copyright (C) 2016 Antony Pavlov > >>> + * > >>> + * This file is part of barebox. > >>> + * See file CREDITS for list of people who contributed to this project. > >>> + * > >>> + * This program is free software; you can redistribute it and/or modify > >>> + * it under the terms of the GNU General Public License version 2 > >>> + * as published by the Free Software Foundation. > >>> + * > >>> + * This program is distributed in the hope that it will be useful, > >>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of > >>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > >>> + * GNU General Public License for more details. > >>> + * > >>> + */ > >>> + > >>> +#include > >>> + > >>> + .text > >>> + .section ".text_entry" > >>> + .align 2 > >>> + > >>> +.globl _start > >>> +_start: > >>> + li sp, STACK_BASE + STACK_SIZE > >>> + > >>> + # make room for HLS and initialize it > >>> + addi sp, sp, -64 /* MENTRY_FRAME_SIZE */ > >>> + > >>> + # poison the stack > >>> + li t1, STACK_BASE > >>> + li t0, 0xdeadbeef > >>> + sw t0, 0(t1) > >>> + > >>> + # clear any pending interrupts > >>> + //csrwi mip, 0 > >> should be removed. > > Actually not! > > > > I have imported this code from coreboot. > > > > I have commented this line because csrwi does not worked in some cases. > > > > But I have to make additional investigations on csrwi. > > > CSRRWI is part of the base integer instruction set and the machine mode > is mandatory. If there are troubles with this instruction, the core has > a faulty design. So executing this line should be okay even if there is > no interrupt controller. > It's not a bug, it's a feature :) At the moment I use picorv32 core. Here is a quote from https://github.com/cliffordwolf/picorv32#custom-instructions-for-irq-handling The IRQ handling features in PicoRV32 do not follow the RISC-V Privileged ISA specification. Instead a small set of very simple custom instructions is used to implement IRQ handling with minimal hardware overhead. I'm planning to make it possible to use another core instead of picorv32 in Eriso SoC, so I can introduce something like SYS_HAS_PICORV32_CPU Kconfig macro. > -- > Mit freundlichen Grüßen, > With best regards, >Daniel Schultz > > > ___ > barebox mailing list > barebox@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/barebox -- Best regards, Antony Pavlov ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: [RFC v4 01/10] Add initial RISC-V architecture support
On Mon, 2 Oct 2017 09:43:02 +0200 Oleksij Rempelwrote: > Hi, > > Am 30.09.2017 um 13:57 schrieb Antony Pavlov: > > On Fri, 29 Sep 2017 14:07:09 +0200 > > Oleksij Rempel wrote: > > > >> Hi, > >> > >> hm... mostly looks identical with existing arch > > > > What do you mean when you say "existing arch"? > > it is a note for me. I just compared it with MIPS > > ... > > > >> Am 29.09.2017 um 01:12 schrieb Antony Pavlov: > > ... > >>> diff --git a/arch/riscv/boot/start.S b/arch/riscv/boot/start.S > >>> new file mode 100644 > >>> index 0..2fd00f63d > >>> --- /dev/null > >>> +++ b/arch/riscv/boot/start.S > >>> @@ -0,0 +1,74 @@ > >>> +/* > >>> + * Startup Code for MIPS CPU > > Beside here is a copy paste ^^^ artefact :) Thanks! I have just fixed this. > > >>> + * based on coreboot/src/arch/riscv/bootblock.S > >>> + * > >>> + * Copyright (C) 2016 Antony Pavlov > >>> + * -- Best regards, Antony Pavlov ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: [RFC v4 01/10] Add initial RISC-V architecture support
Hi, On 09/29/2017 02:07 PM, Oleksij Rempel wrote: Hi, hm... mostly looks identical with existing arch Am 29.09.2017 um 01:12 schrieb Antony Pavlov: Signed-off-by: Antony Pavlov-- TODOs: * split patch; --- arch/riscv/Kconfig | 73 + arch/riscv/Makefile | 68 +++ arch/riscv/boot/Makefile | 2 + arch/riscv/boot/main_entry.c | 40 arch/riscv/boot/start.S | 74 ++ arch/riscv/dts/.gitignore| > arch/riscv/dts/Makefile | 9 arch/riscv/dts/skeleton.dtsi | 13 ++ arch/riscv/include/asm/barebox.h | 1 + arch/riscv/include/asm/bitops.h | 35 ++ arch/riscv/include/asm/bitsperlong.h | 10 arch/riscv/include/asm/byteorder.h | 10 arch/riscv/include/asm/common.h | 6 +++ arch/riscv/include/asm/elf.h | 11 + arch/riscv/include/asm/io.h | 8 arch/riscv/include/asm/mmu.h | 6 +++ arch/riscv/include/asm/posix_types.h | 1 + arch/riscv/include/asm/sections.h| 1 + arch/riscv/include/asm/string.h | 1 + arch/riscv/include/asm/swab.h| 6 +++ arch/riscv/include/asm/types.h | 60 arch/riscv/include/asm/unaligned.h | 19 arch/riscv/lib/.gitignore| 1 + arch/riscv/lib/Makefile | 9 arch/riscv/lib/ashldi3.c | 28 arch/riscv/lib/ashrdi3.c | 30 arch/riscv/lib/asm-offsets.c | 12 + arch/riscv/lib/barebox.lds.S | 89 arch/riscv/lib/dtb.c | 41 + arch/riscv/lib/libgcc.h | 29 arch/riscv/lib/lshrdi3.c | 28 arch/riscv/lib/riscv_timer.c | 68 +++ drivers/of/Kconfig | 2 +- 33 files changed, 791 insertions(+), 1 deletion(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig new file mode 100644 index 0..b2f0817ef --- /dev/null +++ b/arch/riscv/Kconfig @@ -0,0 +1,73 @@ +config RISCV + bool + select GENERIC_FIND_NEXT_BIT + select HAVE_CONFIGURABLE_MEMORY_LAYOUT + select HAVE_CONFIGURABLE_TEXT_BASE + select GPIOLIB + select OFTREE + select COMMON_CLK + select COMMON_CLK_OF_PROVIDER + select CLKDEV_LOOKUP + default y + +config ARCH_TEXT_BASE + hex + default 0x0 + +config GENERIC_LINKER_SCRIPT + bool + default y + +menu "Machine selection" + +choice + prompt "CPU selection" + default CPU_RV_GENERIC + +config CPU_RV_GENERIC + bool "Generic RISC-V" + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_64BIT_KERNEL + +endchoice + +config CPU_SUPPORTS_32BIT_KERNEL + bool +config CPU_SUPPORTS_64BIT_KERNEL + bool + +choice + prompt "barebox code model" + default 64BIT + +config 32BIT + bool "32-bit barebox" + depends on CPU_SUPPORTS_32BIT_KERNEL + help + Select this option to build a 32-bit barebox. + +config 64BIT + bool "64-bit barebox" + depends on CPU_SUPPORTS_64BIT_KERNEL + help + Select this option to build a 64-bit barebox. + +endchoice + +config BUILTIN_DTB + bool "link a DTB into the barebox image" + depends on OFTREE + +config BUILTIN_DTB_NAME + string "DTB to build into the barebox image" + depends on BUILTIN_DTB + +endmenu + +source common/Kconfig +source commands/Kconfig +source net/Kconfig +source drivers/Kconfig +source fs/Kconfig +source lib/Kconfig +source crypto/Kconfig diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile new file mode 100644 index 0..4e3318cf1 --- /dev/null +++ b/arch/riscv/Makefile @@ -0,0 +1,68 @@ +CPPFLAGS += -fno-strict-aliasing + +cflags-y += -fno-pic -pipe +cflags-y += -Wall -Wmissing-prototypes -Wstrict-prototypes \ + -Wno-uninitialized -Wno-format -Wno-main -mcmodel=medany + +LDFLAGS += $(ldflags-y) +LDFLAGS_barebox += -nostdlib + +TEXT_BASE = $(CONFIG_TEXT_BASE) +CPPFLAGS += -DTEXT_BASE=$(CONFIG_TEXT_BASE) + +ifndef CONFIG_MODULES +# Add cleanup flags +CPPFLAGS += -fdata-sections -ffunction-sections +LDFLAGS_barebox += -static --gc-sections +endif + +KBUILD_BINARY := barebox.bin + +machdirs := $(patsubst %,arch/riscv/mach-%/,$(machine-y)) + +ifneq ($(board-y),) +BOARD := arch/riscv/boards/$(board-y)/ +else +BOARD := +endif + +ifeq ($(KBUILD_SRC),) +CPPFLAGS += -I$(BOARD)/include +else +CPPFLAGS += -I$(srctree)/$(BOARD)/include +endif + +ifeq ($(KBUILD_SRC),) +CPPFLAGS += $(patsubst %,-I%include,$(machdirs)) +else +CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs)) +endif + +archprepare: maketools + +PHONY += maketools + +ifneq ($(machine-y),) +MACH :=
Re: [RFC v4 01/10] Add initial RISC-V architecture support
Hi, On 09/30/2017 01:57 PM, Antony Pavlov wrote: On Fri, 29 Sep 2017 14:07:09 +0200 Oleksij Rempelwrote: Hi, hm... mostly looks identical with existing arch What do you mean when you say "existing arch"? ... Am 29.09.2017 um 01:12 schrieb Antony Pavlov: ... diff --git a/arch/riscv/boot/start.S b/arch/riscv/boot/start.S new file mode 100644 index 0..2fd00f63d --- /dev/null +++ b/arch/riscv/boot/start.S @@ -0,0 +1,74 @@ +/* + * Startup Code for MIPS CPU + * + * based on coreboot/src/arch/riscv/bootblock.S + * + * Copyright (C) 2016 Antony Pavlov + * + * This file is part of barebox. + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include + + .text + .section ".text_entry" + .align 2 + +.globl _start +_start: + li sp, STACK_BASE + STACK_SIZE + + # make room for HLS and initialize it + addi sp, sp, -64 /* MENTRY_FRAME_SIZE */ + + # poison the stack + li t1, STACK_BASE + li t0, 0xdeadbeef + sw t0, 0(t1) + + # clear any pending interrupts + //csrwi mip, 0 should be removed. Actually not! I have imported this code from coreboot. I have commented this line because csrwi does not worked in some cases. But I have to make additional investigations on csrwi. CSRRWI is part of the base integer instruction set and the machine mode is mandatory. If there are troubles with this instruction, the core has a faulty design. So executing this line should be okay even if there is no interrupt controller. -- Mit freundlichen Grüßen, With best regards, Daniel Schultz ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: [RFC v4 01/10] Add initial RISC-V architecture support
Hi, Am 30.09.2017 um 13:57 schrieb Antony Pavlov: > On Fri, 29 Sep 2017 14:07:09 +0200 > Oleksij Rempelwrote: > >> Hi, >> >> hm... mostly looks identical with existing arch > > What do you mean when you say "existing arch"? it is a note for me. I just compared it with MIPS > ... > >> Am 29.09.2017 um 01:12 schrieb Antony Pavlov: > ... >>> diff --git a/arch/riscv/boot/start.S b/arch/riscv/boot/start.S >>> new file mode 100644 >>> index 0..2fd00f63d >>> --- /dev/null >>> +++ b/arch/riscv/boot/start.S >>> @@ -0,0 +1,74 @@ >>> +/* >>> + * Startup Code for MIPS CPU Beside here is a copy paste ^^^ artefact :) >>> + * based on coreboot/src/arch/riscv/bootblock.S >>> + * >>> + * Copyright (C) 2016 Antony Pavlov >>> + * -- Regards, Oleksij signature.asc Description: OpenPGP digital signature ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox