[PATCH 4/4] ARM: socfpga_defconfig: enable Altera firmware stuff
Signed-off-by: Antony Pavlov --- arch/arm/configs/socfpga_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/configs/socfpga_defconfig b/arch/arm/configs/socfpga_defconfig index 6883b5f526..3a50bae8f2 100644 --- a/arch/arm/configs/socfpga_defconfig +++ b/arch/arm/configs/socfpga_defconfig @@ -60,6 +60,7 @@ CONFIG_CMD_LED=y CONFIG_CMD_SPI=y CONFIG_CMD_LED_TRIGGER=y CONFIG_CMD_BAREBOX_UPDATE=y +CONFIG_CMD_FIRMWARELOAD=y CONFIG_CMD_OF_NODE=y CONFIG_CMD_OF_PROPERTY=y CONFIG_CMD_OFTREE=y @@ -82,6 +83,7 @@ CONFIG_LED_TRIGGERS=y CONFIG_EEPROM_AT25=y CONFIG_KEYBOARD_GPIO=y CONFIG_GPIO_DESIGNWARE=y +CONFIG_FIRMWARE_ALTERA_SOCFPGA=y CONFIG_FS_EXT4=y CONFIG_FS_TFTP=y CONFIG_FS_NFS=y -- 2.17.0 ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH 2/4] ARM: socfpga: boards: pll_config.h: remove duplicate macros
Signed-off-by: Antony Pavlov --- arch/arm/boards/ebv-socrates/pll_config.h | 6 -- arch/arm/boards/terasic-sockit/pll_config.h | 6 -- 2 files changed, 12 deletions(-) diff --git a/arch/arm/boards/ebv-socrates/pll_config.h b/arch/arm/boards/ebv-socrates/pll_config.h index 083ebd4a87..e912912c9a 100644 --- a/arch/arm/boards/ebv-socrates/pll_config.h +++ b/arch/arm/boards/ebv-socrates/pll_config.h @@ -87,12 +87,6 @@ #define CONFIG_HPS_CLK_MAINVCO_HZ (16) #define CONFIG_HPS_CLK_PERVCO_HZ (10) #define CONFIG_HPS_CLK_SDRVCO_HZ (6) -#define CONFIG_HPS_CLK_OSC1_HZ (2500) -#define CONFIG_HPS_CLK_OSC2_HZ (2500) -#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ (0) -#define CONFIG_HPS_CLK_F2S_PER_REF_HZ (0) -#define CONFIG_HPS_CLK_MAINVCO_HZ (16) -#define CONFIG_HPS_CLK_PERVCO_HZ (10) #define CONFIG_HPS_CLK_EMAC0_HZ (1953125) #define CONFIG_HPS_CLK_EMAC1_HZ (25000) #define CONFIG_HPS_CLK_USBCLK_HZ (2) diff --git a/arch/arm/boards/terasic-sockit/pll_config.h b/arch/arm/boards/terasic-sockit/pll_config.h index e064e2b2b2..ef4a59a611 100644 --- a/arch/arm/boards/terasic-sockit/pll_config.h +++ b/arch/arm/boards/terasic-sockit/pll_config.h @@ -87,12 +87,6 @@ #define CONFIG_HPS_CLK_MAINVCO_HZ (16) #define CONFIG_HPS_CLK_PERVCO_HZ (10) #define CONFIG_HPS_CLK_SDRVCO_HZ (8) -#define CONFIG_HPS_CLK_OSC1_HZ (2500) -#define CONFIG_HPS_CLK_OSC2_HZ (2500) -#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ (0) -#define CONFIG_HPS_CLK_F2S_PER_REF_HZ (0) -#define CONFIG_HPS_CLK_MAINVCO_HZ (16) -#define CONFIG_HPS_CLK_PERVCO_HZ (10) #define CONFIG_HPS_CLK_EMAC0_HZ (1953125) #define CONFIG_HPS_CLK_EMAC1_HZ (25000) #define CONFIG_HPS_CLK_USBCLK_HZ (2) -- 2.17.0 ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH 0/4] ARM: socfpga: misc fixes
Antony Pavlov (4): net: make SoCFPGA-specific designware driver work again ARM: socfpga: boards: pll_config.h: remove duplicate macros ARM: socfpga: mach/pll_config.h: add guard macro ARM: socfpga_defconfig: enable Altera firmware stuff arch/arm/boards/ebv-socrates/pll_config.h | 6 -- arch/arm/boards/terasic-sockit/pll_config.h | 6 -- arch/arm/configs/socfpga_defconfig | 3 +++ arch/arm/mach-socfpga/include/mach/pll_config.h | 4 drivers/net/Kconfig | 1 + 5 files changed, 8 insertions(+), 12 deletions(-) -- 2.17.0 ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH 1/4] net: make SoCFPGA-specific designware driver work again
If MFD_SYSCON is disabled in .config then socfpga_designware_eth probe fails with this message: socfpga_designware_eth ff702000.ethernet: Could not get sysmgr-syscon node Thanks to Steffen for hint! Cc: Steffen Trumtrar Signed-off-by: Antony Pavlov --- arch/arm/configs/socfpga_defconfig | 1 + drivers/net/Kconfig| 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/configs/socfpga_defconfig b/arch/arm/configs/socfpga_defconfig index dbc33f952f..6883b5f526 100644 --- a/arch/arm/configs/socfpga_defconfig +++ b/arch/arm/configs/socfpga_defconfig @@ -71,6 +71,7 @@ CONFIG_OF_BAREBOX_DRIVERS=y CONFIG_OF_BAREBOX_ENV_IN_FS=y CONFIG_DRIVER_SERIAL_NS16550=y CONFIG_DRIVER_NET_DESIGNWARE=y +CONFIG_DRIVER_NET_DESIGNWARE_SOCFPGA=y CONFIG_MCI=y CONFIG_MCI_DW=y CONFIG_MFD_MC13XXX=y diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 09676b3d60..b633a3ac4d 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -82,6 +82,7 @@ config DRIVER_NET_DESIGNWARE_GENERIC config DRIVER_NET_DESIGNWARE_SOCFPGA bool "Designware Universal MAC ethernet driver for SoCFPGA platforms" depends on ARCH_SOCFPGA + select MFD_SYSCON help This option enables support for the Synopsys Designware Core Univesal MAC 10M/100M/1G ethernet IP on SoCFPGA. -- 2.17.0 ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH 3/4] ARM: socfpga: mach/pll_config.h: add guard macro
Signed-off-by: Antony Pavlov
---
arch/arm/mach-socfpga/include/mach/pll_config.h | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/mach-socfpga/include/mach/pll_config.h
b/arch/arm/mach-socfpga/include/mach/pll_config.h
index 1a7e851eda..d6fb60dd24 100644
--- a/arch/arm/mach-socfpga/include/mach/pll_config.h
+++ b/arch/arm/mach-socfpga/include/mach/pll_config.h
@@ -1,3 +1,5 @@
+#ifndef _MACH_SOCFPGA_PRELOADER_PLL_CONFIG_H_
+#define _MACH_SOCFPGA_PRELOADER_PLL_CONFIG_H_
#include
@@ -54,3 +56,5 @@ static struct socfpga_cm_config cm_default_cfg = {
.alteragrp_mpu = CONFIG_HPS_ALTERAGRP_MPUCLK,
.alteregrp_main = CONFIG_HPS_ALTERAGRP_MAINCLK,
};
+
+#endif /* _MACH_SOCFPGA_PRELOADER_PLL_CONFIG_H_ */
--
2.17.0
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[PATCH 3/4] ARM: i.MX6: Add cpu type for 'plus' variants
We need to distinguish between the i.MX6d/q and the i.MX6d/q plus SoC
variants. Add a cpu type for them to make that possible in the next
steps.
Signed-off-by: Sascha Hauer
---
arch/arm/boards/phytec-som-imx6/board.c | 2 +-
arch/arm/boards/zii-imx6q-rdu2/lowlevel.c | 4 ++--
arch/arm/mach-imx/imx6.c | 16
arch/arm/mach-imx/include/mach/imx6.h | 8
4 files changed, 19 insertions(+), 11 deletions(-)
diff --git a/arch/arm/boards/phytec-som-imx6/board.c
b/arch/arm/boards/phytec-som-imx6/board.c
index 717a22963a..7b63ee0e0c 100644
--- a/arch/arm/boards/phytec-som-imx6/board.c
+++ b/arch/arm/boards/phytec-som-imx6/board.c
@@ -66,7 +66,7 @@ static void phyflex_err006282_workaround(void)
mdelay(2);
gpio_set_value(MX6_PHYFLEX_ERR006282, 0);
- if (cpu_is_mx6q() || cpu_is_mx6d())
+ if (cpu_is_mx6q() || cpu_is_mx6d() || cpu_is_mx6qp() || cpu_is_mx6dp())
mxc_iomux_v3_setup_pad(MX6Q_PAD_SD4_DAT3__GPIO_2_11_PD);
else if (cpu_is_mx6dl() || cpu_is_mx6s())
mxc_iomux_v3_setup_pad(MX6DL_PAD_SD4_DAT3__GPIO_2_11);
diff --git a/arch/arm/boards/zii-imx6q-rdu2/lowlevel.c
b/arch/arm/boards/zii-imx6q-rdu2/lowlevel.c
index c9ef16ae05..48d02ce645 100644
--- a/arch/arm/boards/zii-imx6q-rdu2/lowlevel.c
+++ b/arch/arm/boards/zii-imx6q-rdu2/lowlevel.c
@@ -284,7 +284,7 @@ static noinline void rdu2_sram_setup(void)
relocate_to_current_adr();
setup_c();
- if (__imx6_cpu_revision() == IMX_CHIP_REV_2_0)
+ if (__imx6_cpu_type() == IMX6_CPUTYPE_IMX6QP)
write_regs(imx6qp_dcd, ARRAY_SIZE(imx6qp_dcd));
else
write_regs(imx6q_dcd, ARRAY_SIZE(imx6q_dcd));
@@ -307,7 +307,7 @@ ENTRY_FUNCTION(start_imx6_zii_rdu2, r0, r1, r2)
if (get_pc() < MX6_MMDC_PORT01_BASE_ADDR)
rdu2_sram_setup();
- if (__imx6_cpu_revision() == IMX_CHIP_REV_2_0)
+ if (__imx6_cpu_type() == IMX6_CPUTYPE_IMX6QP)
imx6q_barebox_entry(__dtb_imx6qp_zii_rdu2_start +
get_runtime_offset());
else
diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
index 5a7cb7f8bc..88165adee3 100644
--- a/arch/arm/mach-imx/imx6.c
+++ b/arch/arm/mach-imx/imx6.c
@@ -186,16 +186,16 @@ int imx6_init(void)
switch (imx6_cpu_type()) {
case IMX6_CPUTYPE_IMX6Q:
- if (mx6_silicon_revision >= IMX_CHIP_REV_2_0)
- cputypestr = "i.MX6 Quad Plus";
- else
- cputypestr = "i.MX6 Quad";
+ cputypestr = "i.MX6 Quad";
+ break;
+ case IMX6_CPUTYPE_IMX6QP:
+ cputypestr = "i.MX6 Quad Plus";
break;
case IMX6_CPUTYPE_IMX6D:
- if (mx6_silicon_revision >= IMX_CHIP_REV_2_0)
- cputypestr = "i.MX6 Dual Plus";
- else
- cputypestr = "i.MX6 Dual";
+ cputypestr = "i.MX6 Dual";
+ break;
+ case IMX6_CPUTYPE_IMX6DP:
+ cputypestr = "i.MX6 Dual Plus";
break;
case IMX6_CPUTYPE_IMX6DL:
cputypestr = "i.MX6 DualLite";
diff --git a/arch/arm/mach-imx/include/mach/imx6.h
b/arch/arm/mach-imx/include/mach/imx6.h
index 9b538db2ea..e06ca4e235 100644
--- a/arch/arm/mach-imx/include/mach/imx6.h
+++ b/arch/arm/mach-imx/include/mach/imx6.h
@@ -16,7 +16,9 @@ void __noreturn imx6_pm_stby_poweroff(void);
#define IMX6_CPUTYPE_IMX6DL0x261
#define IMX6_CPUTYPE_IMX6SX0x462
#define IMX6_CPUTYPE_IMX6D 0x263
+#define IMX6_CPUTYPE_IMX6DP0x1263
#define IMX6_CPUTYPE_IMX6Q 0x463
+#define IMX6_CPUTYPE_IMX6QP0x1463
#define IMX6_CPUTYPE_IMX6UL0x164
#define IMX6_CPUTYPE_IMX6ULL 0x165
@@ -69,6 +71,10 @@ static inline int __imx6_cpu_type(void)
cpu_type |= scu_get_core_count() << 8;
+ if ((cpu_type == IMX6_CPUTYPE_IMX6D || cpu_type == IMX6_CPUTYPE_IMX6Q)
&&
+ SI_REV_MAJOR(si_rev) >= 1)
+ cpu_type |= 0x1000;
+
return cpu_type;
}
@@ -90,7 +96,9 @@ int imx6_cpu_type(void);
DEFINE_MX6_CPU_TYPE(mx6s, IMX6_CPUTYPE_IMX6S);
DEFINE_MX6_CPU_TYPE(mx6dl, IMX6_CPUTYPE_IMX6DL);
DEFINE_MX6_CPU_TYPE(mx6q, IMX6_CPUTYPE_IMX6Q);
+DEFINE_MX6_CPU_TYPE(mx6qp, IMX6_CPUTYPE_IMX6QP);
DEFINE_MX6_CPU_TYPE(mx6d, IMX6_CPUTYPE_IMX6D);
+DEFINE_MX6_CPU_TYPE(mx6dp, IMX6_CPUTYPE_IMX6DP);
DEFINE_MX6_CPU_TYPE(mx6sx, IMX6_CPUTYPE_IMX6SX);
DEFINE_MX6_CPU_TYPE(mx6sl, IMX6_CPUTYPE_IMX6SL);
DEFINE_MX6_CPU_TYPE(mx6ul, IMX6_CPUTYPE_IMX6UL);
--
2.16.1
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[PATCH 4/4] clk: i.MX6: Fix enfc_sel for i.MX6dqp
The plus SoC variants have some differences in the clock controller.
For now fix the NAND controller clock. There are more differences
that might be relevant, but for now are left for a future excercise.
Signed-off-by: Sascha Hauer
---
drivers/clk/imx/clk-imx6.c | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-imx6.c b/drivers/clk/imx/clk-imx6.c
index c48ab7f76a..7f1af12571 100644
--- a/drivers/clk/imx/clk-imx6.c
+++ b/drivers/clk/imx/clk-imx6.c
@@ -59,6 +59,11 @@
static struct clk *clks[IMX6QDL_CLK_END];
static struct clk_onecell_data clk_data;
+static inline int cpu_is_plus(void)
+{
+ return cpu_is_mx6qp() || cpu_is_mx6dp();
+}
+
static const char *step_sels[] = {
"osc",
"pll2_pfd2_396m",
@@ -109,6 +114,15 @@ static const char *enfc_sels[] = {
"pll2_pfd2_396m",
};
+static const char *enfc_sels_plus[] = {
+ "pll2_pfd0_352m",
+ "pll2_bus",
+ "pll3_usb_otg",
+ "pll2_pfd2_396m",
+ "pll3_pfd3_454m",
+ "dummy",
+};
+
static const char *eim_sels[] = {
"axi",
"pll3_usb_otg",
@@ -404,7 +418,10 @@ static int imx6_ccm_probe(struct device_d *dev)
clks[IMX6QDL_CLK_USDHC2_SEL] = imx_clk_mux("usdhc2_sel",
base + 0x1c, 17, 1, usdhc_sels,ARRAY_SIZE(usdhc_sels));
clks[IMX6QDL_CLK_USDHC3_SEL] = imx_clk_mux("usdhc3_sel",
base + 0x1c, 18, 1, usdhc_sels,ARRAY_SIZE(usdhc_sels));
clks[IMX6QDL_CLK_USDHC4_SEL] = imx_clk_mux("usdhc4_sel",
base + 0x1c, 19, 1, usdhc_sels,ARRAY_SIZE(usdhc_sels));
- clks[IMX6QDL_CLK_ENFC_SEL] = imx_clk_mux("enfc_sel",
base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels));
+ if (cpu_is_plus())
+ clks[IMX6QDL_CLK_ENFC_SEL] = imx_clk_mux("enfc_sel",
base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels));
+ else
+ clks[IMX6QDL_CLK_ENFC_SEL] = imx_clk_mux("enfc_sel",
base + 0x2c, 16, 2, enfc_sels_plus,ARRAY_SIZE(enfc_sels_plus));
clks[IMX6QDL_CLK_EIM_SEL] = imx_clk_mux("eim_sel",
base + 0x1c, 27, 2, eim_sels, ARRAY_SIZE(eim_sels));
clks[IMX6QDL_CLK_EIM_SLOW_SEL] = imx_clk_mux("eim_slow_sel",
base + 0x1c, 29, 2, eim_sels, ARRAY_SIZE(eim_sels));
clks[IMX6QDL_CLK_VDO_AXI_SEL] = imx_clk_mux("vdo_axi_sel",
base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels));
--
2.16.1
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[PATCH 2/4] ARM: i.MX6: factor out function to read si_rev
The i.MX6sl has another silicon revision register offset than the
other i.MX6 SoCs. Finding the register is done twice. Factor out
a function to get a common place to find the register.
Signed-off-by: Sascha Hauer
---
arch/arm/mach-imx/include/mach/imx6.h | 61 +--
1 file changed, 36 insertions(+), 25 deletions(-)
diff --git a/arch/arm/mach-imx/include/mach/imx6.h
b/arch/arm/mach-imx/include/mach/imx6.h
index 436f8fc31b..9b538db2ea 100644
--- a/arch/arm/mach-imx/include/mach/imx6.h
+++ b/arch/arm/mach-imx/include/mach/imx6.h
@@ -33,26 +33,43 @@ static inline int scu_get_core_count(void)
return (ncores & 0x03) + 1;
}
+#define SI_REV_CPUTYPE(s) (((s) >> 16) & 0xff)
+#define SI_REV_MAJOR(s)(((s) >> 8) & 0xf)
+#define SI_REV_MINOR(s)((s) & 0xf)
+
+static inline uint32_t __imx6_read_si_rev(void)
+{
+ uint32_t si_rev;
+ uint32_t cpu_type;
+
+ si_rev = readl(MX6_ANATOP_BASE_ADDR + IMX6_ANATOP_SI_REV);
+ cpu_type = SI_REV_CPUTYPE(si_rev);
+
+ if (cpu_type >= 0x61 && cpu_type <= 0x65)
+ return si_rev;
+
+ /* try non-MX6-standard SI_REV reg offset for MX6SL */
+ si_rev = readl(MX6_ANATOP_BASE_ADDR + IMX6SL_ANATOP_SI_REV);
+ cpu_type = SI_REV_CPUTYPE(si_rev);
+
+ if (si_rev == 0x60)
+ return si_rev;
+
+ return 0;
+}
+
static inline int __imx6_cpu_type(void)
{
- uint32_t val;
-
- val = readl(MX6_ANATOP_BASE_ADDR + IMX6_ANATOP_SI_REV);
- val = (val >> 16) & 0xff;
- /* non-MX6-standard SI_REV reg offset for MX6SL */
- if (IS_ENABLED(CONFIG_ARCH_IMX6SL) &&
- val < (IMX6_CPUTYPE_IMX6S & 0xff)) {
- uint32_t tmp;
- tmp = readl(MX6_ANATOP_BASE_ADDR + IMX6SL_ANATOP_SI_REV);
- tmp = (tmp >> 16) & 0xff;
- if ((IMX6_CPUTYPE_IMX6SL & 0xff) == tmp)
- /* intentionally skip scu_get_core_count() for MX6SL */
- return IMX6_CPUTYPE_IMX6SL;
- }
+ uint32_t si_rev = __imx6_read_si_rev();
+ uint32_t cpu_type = SI_REV_CPUTYPE(si_rev);
- val |= scu_get_core_count() << 8;
+ /* intentionally skip scu_get_core_count() for MX6SL */
+ if (cpu_type == IMX6_CPUTYPE_IMX6SL)
+ return IMX6_CPUTYPE_IMX6SL;
- return val;
+ cpu_type |= scu_get_core_count() << 8;
+
+ return cpu_type;
}
int imx6_cpu_type(void);
@@ -81,17 +98,11 @@ DEFINE_MX6_CPU_TYPE(mx6ull, IMX6_CPUTYPE_IMX6ULL);
static inline int __imx6_cpu_revision(void)
{
- uint32_t rev;
- uint32_t si_rev_offset = IMX6_ANATOP_SI_REV;
+ uint32_t si_rev = __imx6_read_si_rev();
u8 major_part, minor_part;
- if (IS_ENABLED(CONFIG_ARCH_IMX6SL) && cpu_mx6_is_mx6sl())
- si_rev_offset = IMX6SL_ANATOP_SI_REV;
-
- rev = readl(MX6_ANATOP_BASE_ADDR + si_rev_offset);
-
- major_part = (rev >> 8) & 0xf;
- minor_part = rev & 0xf;
+ major_part = (si_rev >> 8) & 0xf;
+ minor_part = si_rev & 0xf;
return ((major_part + 1) << 4) | minor_part;
}
--
2.16.1
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[PATCH 1/4] ARM: i.MX6: de-inline i.MX6 type detection
Having the i.MX6 type detection completely inline is less then optimal
in terms of binary size. Make the detection functions non-inline. While
at it ask the registers only once and store the result in a variable as
the i.MX6 type is unlikely to change during runtime.
Signed-off-by: Sascha Hauer
---
arch/arm/mach-imx/imx6.c | 26 ++
arch/arm/mach-imx/include/mach/imx6.h | 16 ++--
2 files changed, 28 insertions(+), 14 deletions(-)
diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
index 14a1cba5a4..5a7cb7f8bc 100644
--- a/arch/arm/mach-imx/imx6.c
+++ b/arch/arm/mach-imx/imx6.c
@@ -147,6 +147,32 @@ static void imx6ul_enet_clk_init(void)
writel(val, gprbase + IOMUXC_GPR1);
}
+int imx6_cpu_type(void)
+{
+ static int cpu_type = -1;
+
+ if (!cpu_is_mx6())
+ return 0;
+
+ if (cpu_type < 0)
+ cpu_type = __imx6_cpu_type();
+
+ return cpu_type;
+}
+
+int imx6_cpu_revision(void)
+{
+ static int soc_revision = -1;
+
+ if (!cpu_is_mx6())
+ return 0;
+
+ if (soc_revision < 0)
+ soc_revision = __imx6_cpu_revision();
+
+ return soc_revision;
+}
+
int imx6_init(void)
{
const char *cputypestr;
diff --git a/arch/arm/mach-imx/include/mach/imx6.h
b/arch/arm/mach-imx/include/mach/imx6.h
index 6b08e6a521..436f8fc31b 100644
--- a/arch/arm/mach-imx/include/mach/imx6.h
+++ b/arch/arm/mach-imx/include/mach/imx6.h
@@ -55,13 +55,7 @@ static inline int __imx6_cpu_type(void)
return val;
}
-static inline int imx6_cpu_type(void)
-{
- if (!cpu_is_mx6())
- return 0;
-
- return __imx6_cpu_type();
-}
+int imx6_cpu_type(void);
#define DEFINE_MX6_CPU_TYPE(str, type) \
static inline int cpu_mx6_is_##str(void)\
@@ -102,12 +96,6 @@ static inline int __imx6_cpu_revision(void)
return ((major_part + 1) << 4) | minor_part;
}
-static inline int imx6_cpu_revision(void)
-{
- if (!cpu_is_mx6())
- return 0;
-
- return __imx6_cpu_revision();
-}
+int imx6_cpu_revision(void);
#endif /* __MACH_IMX6_H */
--
2.16.1
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[PATCH 0/4] Fix NAND controller clock for i.MX6plus
The i.MX6 plus SoC variants have some changes in the clock controller, start integrating them beginning with the NAND controller clock. Before doing so we have to add proper detection code for the i.MX6 plus. Sascha Hauer (4): ARM: i.MX6: de-inline i.MX6 type detection ARM: i.MX6: factor out function to read si_rev ARM: i.MX6: Add cpu type for 'plus' variants clk: i.MX6: Fix enfc_sel for i.MX6dqp arch/arm/boards/phytec-som-imx6/board.c | 2 +- arch/arm/boards/zii-imx6q-rdu2/lowlevel.c | 4 +- arch/arm/mach-imx/imx6.c | 42 +--- arch/arm/mach-imx/include/mach/imx6.h | 81 +-- drivers/clk/imx/clk-imx6.c| 19 +++- 5 files changed, 99 insertions(+), 49 deletions(-) -- 2.16.1 ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH] ARM: i.MX53 TX53: remove duplicate _imx53
The pblx-y variables for the TX53 have _imx53 twice in their names. With this the names do not match the names in the FILE_* variables. This results in the make system removing the pblx files as intermediate files. Fix the names. Signed-off-by: Sascha Hauer --- images/Makefile.imx | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/images/Makefile.imx b/images/Makefile.imx index ac46d51c59..90da95d4d0 100644 --- a/images/Makefile.imx +++ b/images/Makefile.imx @@ -139,17 +139,17 @@ CFG_start_imx53_mba53_1gib.pblx.imximg = $(board)/tqma53/flash-header-tq-tqma53- FILE_barebox-tq-mba53-1gib.img = start_imx53_mba53_1gib.pblx.imximg image-$(CONFIG_MACH_TQMA53) += barebox-tq-mba53-1gib.img -pblx-$(CONFIG_MACH_TX53) += start_imx53_imx53_tx53_xx30_samsung +pblx-$(CONFIG_MACH_TX53) += start_imx53_tx53_xx30_samsung CFG_start_imx53_tx53_xx30_samsung.pblx.imximg = $(board)/karo-tx53/flash-header-tx53-revxx30-samsung.imxcfg FILE_barebox-tx53-xx30-samsung.img = start_imx53_tx53_xx30_samsung.pblx.imximg image-$(CONFIG_MACH_TX53) += barebox-tx53-xx30-samsung.img -pblx-$(CONFIG_MACH_TX53) += start_imx53_imx53_tx53_xx30 +pblx-$(CONFIG_MACH_TX53) += start_imx53_tx53_xx30 CFG_start_imx53_tx53_xx30.pblx.imximg = $(board)/karo-tx53/flash-header-tx53-revxx30.imxcfg FILE_barebox-tx53-xx30.img = start_imx53_tx53_xx30.pblx.imximg image-$(CONFIG_MACH_TX53) += barebox-tx53-xx30.img -pblx-$(CONFIG_MACH_TX53) += start_imx53_imx53_tx53_1011 +pblx-$(CONFIG_MACH_TX53) += start_imx53_tx53_1011 CFG_start_imx53_tx53_1011.pblx.imximg = $(board)/karo-tx53/flash-header-tx53-rev1011.imxcfg FILE_barebox-tx53-1011.img = start_imx53_tx53_1011.pblx.imximg image-$(CONFIG_MACH_TX53) += barebox-tx53-1011.img -- 2.16.1 ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH] ARM: i.MX6: phycore: Enable usbotg
The i.MX6 phyCORE boards have USBOTG support. Enable it.
Signed-off-by: Sascha Hauer
---
arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi
b/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi
index b10530cbcf..2ce22b9880 100644
--- a/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi
+++ b/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi
@@ -252,6 +252,10 @@
status = "okay";
};
+&usbotg {
+ status = "okay";
+};
+
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
--
2.16.1
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[PATCH] clk: i.MX6: Adjust GPMI parent clock
Based on the corresponding Kernel code: The gpmi needs 100MHz frequency in the EDO/Sync mode, We can not get the 100MHz from the pll2_pfd0_352m. So choose pll2_pfd2_396m as enfc_sel's parent. Signed-off-by: Sascha Hauer --- drivers/clk/imx/clk-imx6.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/drivers/clk/imx/clk-imx6.c b/drivers/clk/imx/clk-imx6.c index d0571bce5e..c48ab7f76a 100644 --- a/drivers/clk/imx/clk-imx6.c +++ b/drivers/clk/imx/clk-imx6.c @@ -514,6 +514,13 @@ static int imx6_ccm_probe(struct device_d *dev) clk_set_parent(clks[IMX6QDL_CLK_LVDS1_SEL], clks[IMX6QDL_CLK_SATA_REF_100M]); + /* +* The gpmi needs 100MHz frequency in the EDO/Sync mode, +* We can not get the 100MHz from the pll2_pfd0_352m. +* So choose pll2_pfd2_396m as enfc_sel's parent. +*/ + clk_set_parent(clks[IMX6QDL_CLK_ENFC_SEL], clks[IMX6QDL_CLK_PLL2_PFD2_396M]); + return 0; } -- 2.16.1 ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH 00/10] Vybrid MMDC support and misc ESDCTL fixes
On Tue, Apr 10, 2018 at 04:53:13PM -0700, Andrey Smirnov wrote: > Everyone: > > This series is a bit of code I developed to support automatic > configured DRAM size detection on Vybrid platform as well as some > small fixes/cleanup I made while looking at esdctl.c. > > All feedback is wellcome! Not much to comment, looks all good. Applied, thanks Sascha > > Thanks, > Andrey Smirnov > > Andrey Smirnov (10): > ARM: i.MX: esdctl: Use IOMEM instead of (void *) > ARM: i.MX51: esdctl: Replace magic value with ESDMISC_DDR2_8_BANK > ARM: i.MX6: esdctl: Share memory size calculation code > ARM: i.MX6: esdctl: Factor out common code in imx6*_barebox_entry() > ARM: i.MX6: esdctl: Use symbolic constants for RAM base address > ARM: i.MX: esdctl: Make use of min_t() > ARM: i.MX: esdctl: Introduce memory_sdram_size() > ARM: i.MX: esdctl: Add support for Vybrid's memory controller > i.MX: vf610-twr: Make use of vf610_barebox_entry() > i.MX: zii-vf610-dev: Make use of vf610_barebox_entry() > > arch/arm/boards/freescale-vf610-twr/lowlevel.c | 5 +- > arch/arm/boards/zii-imx6q-rdu2/lowlevel.c | 2 +- > arch/arm/boards/zii-vf610-dev/lowlevel.c | 3 +- > arch/arm/dts/vf610-ddrmc.dtsi | 15 +++ > arch/arm/dts/vf610-twr.dts | 1 + > arch/arm/dts/vf610-zii-dev.dtsi| 4 +- > arch/arm/mach-imx/esdctl.c | 144 > ++--- > arch/arm/mach-imx/include/mach/esdctl.h| 2 + > arch/arm/mach-imx/include/mach/imx6-regs.h | 4 +- > arch/arm/mach-imx/include/mach/vf610-ddrmc.h | 18 > arch/arm/mach-imx/include/mach/vf610-regs.h| 2 + > include/memory.h | 8 ++ > 12 files changed, 141 insertions(+), 67 deletions(-) > create mode 100644 arch/arm/dts/vf610-ddrmc.dtsi > create mode 100644 arch/arm/mach-imx/include/mach/vf610-ddrmc.h > > -- > 2.14.3 > > > ___ > barebox mailing list > barebox@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/barebox > -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH] ARM: start: Avoid calling arm_mem_barebox_image() twice
On Tue, Apr 10, 2018 at 04:45:36PM -0700, Andrey Smirnov wrote:
> Avoid calling arm_mem_barebox_image() twice by making barebox_base
> function-wide in scope
>
> Signed-off-by: Andrey Smirnov
> ---
> arch/arm/cpu/start.c | 13 +
> 1 file changed, 5 insertions(+), 8 deletions(-)
Applied, thanks
Sascha
>
> diff --git a/arch/arm/cpu/start.c b/arch/arm/cpu/start.c
> index 68fff892e..64bd942ad 100644
> --- a/arch/arm/cpu/start.c
> +++ b/arch/arm/cpu/start.c
> @@ -144,13 +144,11 @@ __noreturn void barebox_non_pbl_start(unsigned long
> membase,
> unsigned long endmem = membase + memsize;
> unsigned long malloc_start, malloc_end;
> unsigned long barebox_size = barebox_image_size + MAX_BSS_SIZE;
> -
> - if (IS_ENABLED(CONFIG_RELOCATABLE)) {
> - unsigned long barebox_base = arm_mem_barebox_image(membase,
> -endmem,
> -
> barebox_size);
> + unsigned long barebox_base = arm_mem_barebox_image(membase,
> +endmem,
> +barebox_size);
> + if (IS_ENABLED(CONFIG_RELOCATABLE))
> relocate_to_adr(barebox_base);
> - }
>
> setup_c();
>
> @@ -160,8 +158,7 @@ __noreturn void barebox_non_pbl_start(unsigned long
> membase,
>
> arm_stack_top = arm_mem_stack_top(membase, endmem);
> arm_barebox_size = barebox_size;
> - malloc_end = arm_mem_barebox_image(membase, endmem,
> - arm_barebox_size);
> + malloc_end = barebox_base;
>
> if (IS_ENABLED(CONFIG_MMU_EARLY)) {
> unsigned long ttb = arm_mem_ttb(membase, endmem);
> --
> 2.14.3
>
>
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Re: [PATCH 1/2] i.MX: vf610-twr: Print '>' when DEBUG_LL is enabled
On Tue, Apr 10, 2018 at 04:40:37PM -0700, Andrey Smirnov wrote:
> Majority of others boards prints '>' as soon as DEBUG_LL related
> configuration is done, so do so for VF610-TWR as well.
>
> Signed-off-by: Andrey Smirnov
> ---
> arch/arm/boards/freescale-vf610-twr/lowlevel.c | 2 ++
> 1 file changed, 2 insertions(+)
Applied, thanks
Sascha
>
> diff --git a/arch/arm/boards/freescale-vf610-twr/lowlevel.c
> b/arch/arm/boards/freescale-vf610-twr/lowlevel.c
> index a043dd421..65956fdd2 100644
> --- a/arch/arm/boards/freescale-vf610-twr/lowlevel.c
> +++ b/arch/arm/boards/freescale-vf610-twr/lowlevel.c
> @@ -22,6 +22,8 @@ static inline void setup_uart(void)
> writel(0, iomuxbase + 0x0380);
>
> vf610_uart_setup_ll();
> +
> + putc_ll('>');
> }
>
> extern char __dtb_vf610_twr_start[];
> --
> 2.14.3
>
>
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Re: [PATCH] pinctrl-vf610: Make use of BIT macro
On Tue, Apr 10, 2018 at 04:39:43PM -0700, Andrey Smirnov wrote:
> Signed-off-by: Andrey Smirnov
> ---
> drivers/pinctrl/pinctrl-vf610.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
Applied, thanks
Sascha
>
> diff --git a/drivers/pinctrl/pinctrl-vf610.c b/drivers/pinctrl/pinctrl-vf610.c
> index 4234263d3..a46b0e2ca 100644
> --- a/drivers/pinctrl/pinctrl-vf610.c
> +++ b/drivers/pinctrl/pinctrl-vf610.c
> @@ -29,9 +29,9 @@
> enum {
> PINCTRL_VF610_MUX_LINE_SIZE = 20,
>
> - PINCTRL_VF610_IBE = 1 << 0,
> - PINCTRL_VF610_OBE = 1 << 1,
> - PINCTRL_VF610_xBE = 0b11,
> + PINCTRL_VF610_IBE = BIT(0),
> + PINCTRL_VF610_OBE = BIT(1),
> + PINCTRL_VF610_xBE = PINCTRL_VF610_OBE | PINCTRL_VF610_IBE,
> };
>
> struct pinctrl_vf610 {
> --
> 2.14.3
>
>
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Re: [PATCH] ARM: Make use of ALIGN_DOWN macro in barebox-arm.h
On Tue, Apr 10, 2018 at 04:38:05PM -0700, Andrey Smirnov wrote:
> Signed-off-by: Andrey Smirnov
> ---
> arch/arm/include/asm/barebox-arm.h | 9 +++--
> 1 file changed, 3 insertions(+), 6 deletions(-)
Applied, thanks
Sascha
>
> diff --git a/arch/arm/include/asm/barebox-arm.h
> b/arch/arm/include/asm/barebox-arm.h
> index 4b270e7de..67e4d964d 100644
> --- a/arch/arm/include/asm/barebox-arm.h
> +++ b/arch/arm/include/asm/barebox-arm.h
> @@ -114,8 +114,7 @@ static inline unsigned long arm_mem_ttb(unsigned long
> membase,
> unsigned long endmem)
> {
> endmem = arm_mem_stack(membase, endmem);
> - endmem &= ~(SZ_16K - 1);
> - endmem -= SZ_16K;
> + endmem = ALIGN_DOWN(endmem, SZ_16K) - SZ_16K;
>
> return endmem;
> }
> @@ -138,7 +137,7 @@ static inline unsigned long arm_mem_ramoops(unsigned long
> membase,
> endmem = arm_mem_ttb(membase, endmem);
> #ifdef CONFIG_FS_PSTORE_RAMOOPS
> endmem -= CONFIG_FS_PSTORE_RAMOOPS_SIZE;
> - endmem &= ~(SZ_4K - 1); /* Align to 4K */
> + endmem = ALIGN_DOWN(endmem, SZ_4K);
> #endif
>
> return endmem;
> @@ -151,9 +150,7 @@ static inline unsigned long
> arm_mem_barebox_image(unsigned long membase,
> endmem = arm_mem_ramoops(membase, endmem);
>
> if (IS_ENABLED(CONFIG_RELOCATABLE)) {
> - endmem -= size;
> - endmem &= ~(SZ_1M - 1);
> - return endmem;
> + return ALIGN_DOWN(endmem - size, SZ_1M);
> } else {
> if (TEXT_BASE >= membase && TEXT_BASE < endmem)
> return TEXT_BASE;
> --
> 2.14.3
>
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Re: [PATCH v3 04/10] ARM: add file for HYP mode related setup
On Tue, Apr 10, 2018 at 12:53:32PM +0200, Lucas Stach wrote: > Am Donnerstag, den 05.04.2018, 09:54 +0200 schrieb Sascha Hauer: > > On Mon, Mar 26, 2018 at 09:20:19PM +0200, Lucas Stach wrote: > > > This adds routines to add hyp mode vectors and switch back to HYP > > > mode from SVC. This is needed in both the PBL and Barebox proper. > > > > > > > > Signed-off-by: Lucas Stach > > > > > Tested-by: Roland Hieber > > > --- > > > v3: > > > - fix whitespace > > > - use __BARE_INIT > > > --- > > > arch/arm/cpu/Makefile | 4 ++ > > > arch/arm/cpu/hyp.S| 116 > > > ++ > > > arch/arm/cpu/sm_as.S | 11 > > > arch/arm/include/asm/secure.h | 8 +++ > > > 4 files changed, 128 insertions(+), 11 deletions(-) > > > create mode 100644 arch/arm/cpu/hyp.S > > > > > > diff --git a/arch/arm/cpu/Makefile b/arch/arm/cpu/Makefile > > > index 13fe12c31f6f..f86dff975bb4 100644 > > > --- a/arch/arm/cpu/Makefile > > > +++ b/arch/arm/cpu/Makefile > > > @@ -9,6 +9,10 @@ obj-$(CONFIG_ARM_EXCEPTIONS) += exceptions.o > > > obj-$(CONFIG_MMU) += mmu.o mmu-early.o > > > pbl-$(CONFIG_MMU) += mmu-early.o > > > lwl-y += lowlevel.o > > > +obj-y += hyp.o > > > +AFLAGS_hyp.o :=-Wa,-march=armv7-a -Wa,-mcpu=all > > > +pbl-y += hyp.o > > > +AFLAGS_pbl-hyp.o :=-Wa,-march=armv7-a -Wa,-mcpu=all > > > endif > > > > > > obj-$(CONFIG_ARM_EXCEPTIONS) += interrupts.o > > > diff --git a/arch/arm/cpu/hyp.S b/arch/arm/cpu/hyp.S > > > new file mode 100644 > > > index ..1314b56eab25 > > > --- /dev/null > > > +++ b/arch/arm/cpu/hyp.S > > > @@ -0,0 +1,116 @@ > > > +#include > > > +#include > > > +#include > > > +#include > > > + > > > +.arch_extension sec > > > +.arch_extension virt > > > + > > > +__BARE_INIT > > > + > > > +.data > > > > > + .align 2 > > > +ENTRY(__boot_cpu_mode) > > > > > + .long 0 > > > +.text > > > + > > > +ENTRY(__hyp_install) > > > > > > > + mrs r12, cpsr > > > > > > > + and r12, r12, #MODE_MASK > > > + > > > > > + @ Save the initial CPU state > > > > > > > + adr r0, .L__boot_cpu_mode_offset > > > > > > > + ldr r1, [r0] > > > + str r12, [r0, r1] > > > > Naa, this won't work. You save the cpsr value in __boot_cpu_mode, but > > this variable exists both in PBL and regular barebox, __hyp_install > > is called multiple times and cpsr is modified right after saving it. > > It does. ;) > > I guess its non-obvious from the code flow, but what we do is to drop > down to SVC in the PBL, then jump back to HYP before starting barebox > proper and the dropping down to SVC again on barebox entry. > All in all this is less-than-pretty, but IMHO it's the lesser evil than > trying to implement some communication channel from PBL to barebox > proper to pass information like this. > > So I guess this code needs some more comments... Yep ;) Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH 2/3] console: Add simplified 'serdev' framework from Linux kernel
On Mon, Apr 09, 2018 at 09:40:46AM -0700, Andrey Smirnov wrote:
> On Mon, Apr 2, 2018 at 11:54 PM, Sascha Hauer wrote:
> > Hi Andrey,
> >
> > Some comments inside.
> >
> >
> > On Mon, Mar 26, 2018 at 06:09:14AM -0700, Andrey Smirnov wrote:
> >> Port 'serdev' UART-slave deivce framework found in recent Linux
> >> kernels (post 4.13) in order to be able to port 'serdev' slave drivers
> >> from Linux.
> >>
> >> Signed-off-by: Andrey Smirnov
> >> @@ -323,6 +324,17 @@ int console_register(struct console_device *newcdev)
> >> dev->parent = newcdev->dev;
> >> platform_device_register(dev);
> >>
> >> + newcdev->open_count = 0;
> >> +
> >> + /*
> >> + * If our console deive is a serdev, we skip the creation of
> >
> > s/deive/device/
>
> Will fix in v2.
>
> >
> >> + * corresponding entry in /dev as well as registration in
> >> + * console_list and just go straigh to populating child
> >
> > s/straigh/straight/
>
> Ditto.
>
> >
> >> + * devices.
> >> + */
> >> + if (serdev_node)
> >> + return of_platform_populate(serdev_node, NULL, dev);
> >
> > How is this going to be used? A serdev driver binds to the serdev_node
> > and then it probably needs to get a pointer to the console device,
> > right? How does the driver accomplish this?
> >
>
> Serdev slave driver doesn't hold explicit pointer to console device,
> instead accessing it via point to serdev_device. The latter could
> obtained by calling to_serdev_device(dev->parent), where dev is
> device_d given to slave driver's probe function.
>
>
> >> +/**
> >> + * struct serdev_device - Basic representation of an serdev device
> >> + *
> >> + * @dev: Corresponding device
> >> + * @fifo:Circular buffer used for console draining
> >> + * @buf: Buffer used to pass Rx data to consumers
> >> + * @poller Async poller used to poll this serdev
> >> + * @polling_interval:Async poller periodicity
> >> + * @polling_window: Duration of a single busy loop poll
> >> + * @receive_buf: Function called with data received from device;
> >> + * returns number of bytes accepted;
> >> + */
> >> +struct serdev_device {
> >> + struct device_d *dev;
> >> + struct kfifo *fifo;
> >> + unsigned char *buf;
> >> + struct poller_async poller;
> >> + uint64_t polling_interval;
> >> + uint64_t polling_window;
> >> +
> >> + int (*receive_buf)(struct serdev_device *, const unsigned char *,
> >> +size_t);
> >> +};
> >> +
> >> +int serdev_device_open(struct serdev_device *);
> >> +unsigned int serdev_device_set_baudrate(struct serdev_device *, unsigned
> >> int);
> >> +int serdev_device_write(struct serdev_device *, const unsigned char *,
> >> + size_t, unsigned long);
> >
> > So a serdev driver uses serdev_device_write() to send characters out. To
> > receive characters it has to implement serdev_device->receive_buf,
> > right?
>
> Right. I tried to implement exactly the same API that Linux's serdev
> API provides.
>
> > What kind of devices did you implement this for?
>
> I ported serdev in support of porting the driver for RAVE SP which is
> a small microcontroller device found many ZII board including RDU2. It
> implement a whole bunch of various functionality including watchdog,
> parameter EEPROM, sensor access, backlight control, button input event
> generation, etc.
>
> > For devices which send data without request (GPS?) this seems the way to
> > go. For
> > others a synchronous receive function might be good, no?
> >
>
> I didn't implement anything like that mostly because Linux serdev API
> doesn't and any ported driver wouldn't have any need for those
> functions. But in general, I am not sure how useful synchronous
> receive function would be. In my experience, devices like that usually
> implement some binary transport protocol with packetization/escape
> sequences on top of UART, which usually requires a state machine
> operating with byte granularity as the data comes in to parse
> responses correctly and synchronous APIs are not extremely useful for
> that kind of a use-case.
>
> FWIW, since serdev API is integrated into poller infrastructure it is
> pretty trivial to write blocking code with it. Here's how I use it in
> my driver to implement request-response type of a function:
>
> rave_sp_write(sp, data, data_size);
> /*
> * is_timeout will implicitly poll serdev via poller
> * infrastructure
> */
> while (!is_timeout(start, SECOND) && !reply.received)
>;
I understand that synchronous receiving might not be that useful. Given
how simple it is we could add a synchronous receive wrapper function
just for the sake of completeness, even if it only provides an example
how the code can be used.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Re: [PATCH 3/3] serial: Check result of console_unregister()
Hi Andrey, On Mon, Apr 09, 2018 at 09:00:52AM -0700, Andrey Smirnov wrote: > On Tue, Apr 3, 2018 at 12:04 AM, Sascha Hauer wrote: > > On Mon, Mar 26, 2018 at 06:09:15AM -0700, Andrey Smirnov wrote: > >> In order to allow 'serdev' devices to prevent parent console device > >> removal and correspondign memory deallocation add code to all serial > >> driver to check result of console_unregister() and bail out early if > >> it is unsuccessful. > >> > >> One example of a use-case for this would be a reset handler relying on > >> a serdev device for transport. Without this patch underlying console > >> device would be removed and de-allocated before reset handler is even > >> run thus leading to unpredictable behaviour and crashes. > > > > Can't we make this sure at driver core level? > > I need to be able to prevent serial driver's "remove" function from > ever executing to prevent any de-initialization/memory freeing from > happening. The simplest way to solve this in driver core that comes to > my mind is implementing simple reference counting API that children > could use to force driver core to bail out on removing parents if they > are still in use. Does that sound like a reasonable idea? > > > So if a device decides not > > to return -EBUSY in the remove callback then the parent devices won't be > > removed? > > Remove callback currently returns void, we could change it to return > int and use it to implement a sort of implicit refcounting, but doing > so would result in quite a bit of code churn since all of the current > drivers would have to be converted to return int in their .remove > callbacks. Would you rather I do this or explicit refcounting? Normally it helps looking at the Linux kernel to see how a problem is solved there. Not so this time it seems. Linux distinguishes between "remove" and "shutdown". "shutdown" is what we want during barebox shutdown. I found a Linux driver that is similar to your situation: It registers a restart_handler while being a i2c device itself. There seems to be no way to prevent a device from being shutdown, it's only that the i2c bus drivers simply do not implement it. Where do we go from here? I think reference counting is a bit over the top. At the moment I would opt for a *very* simple solution: Let's drop the call to console_unregister() and the freeing of resources entirely as it gives us nothing. The only console driver I can see where removing is valid is drivers/usb/gadget/u_serial.c and you won't use this for restarting a SoC ;) Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH 1/2] i.MX53/TX53: Adjust to latest get_runtime_offset()
On Mon, Apr 09, 2018 at 06:36:36PM -0700, Andrey Smirnov wrote: > Latest version of get_runtime_offset() returns positive offset that > needs to be added to rather than substracted from original pointer. > > Cc: Michael Grzeschik > Signed-off-by: Andrey Smirnov > --- > > Sascha: > > This one obviously needs to go into master as well. Sorry for the > noise if this has already been fixed. Applied to master, thanks Sascha > > Thanks, > Andrey Smirnov > > arch/arm/boards/karo-tx53/lowlevel.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm/boards/karo-tx53/lowlevel.c > b/arch/arm/boards/karo-tx53/lowlevel.c > index cb324b200..a0bce8a78 100644 > --- a/arch/arm/boards/karo-tx53/lowlevel.c > +++ b/arch/arm/boards/karo-tx53/lowlevel.c > @@ -47,7 +47,7 @@ static void __imx53_tx53_init(int is_xx30) > if (IS_ENABLED(CONFIG_DEBUG_LL)) > setup_uart(); > > - fdt = fdt_blob_fixed_offset - get_runtime_offset(); > + fdt = fdt_blob_fixed_offset + get_runtime_offset(); > > imx53_barebox_entry(fdt); > } > -- > 2.14.3 > > > ___ > barebox mailing list > barebox@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/barebox > -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH v2] ARM: Add Advantech imx6 board support
On Mon, Apr 09, 2018 at 01:53:59PM +0200, Christoph Fritz wrote:
> Add support for Advantech i.MX6 SOM named ROM-7421.
>
> Signed-off-by: Christoph Fritz
> ---
> Changes since v0:
> - distinguish between MMC environment names in pr_notice() board.c
> - rework eMMC partition layout and don't use its hw-bootpartition for now
> - purge writing clock registers
> - rework and simplify lowlevel.c init and use imx6q_barebox_entry(fdt)
> - s/linux,stdout-path/stdout-path in dts
> - rework and simplify spi nor partition layout
> - remove additional pinctrl subnode from dts
> - remove setting of explicit ARCH_TEXT_BASE in Kconfig
> - use bitop Macro for ar8035_phy_fixup()
> - use imx_setup_pad() for early debug uart
> ---
Applied, thanks
Sascha
> arch/arm/boards/Makefile | 1 +
> arch/arm/boards/advantech-mx6/Makefile | 2 +
> arch/arm/boards/advantech-mx6/board.c | 101 +
> .../flash-header-advantech-rom-7421.imxcfg | 66 ++
> arch/arm/boards/advantech-mx6/lowlevel.c | 56 +
> arch/arm/configs/imx_v7_defconfig | 1 +
> arch/arm/dts/Makefile | 1 +
> arch/arm/dts/imx6dl-advantech-rom-7421.dts | 225
> +
> arch/arm/mach-imx/Kconfig | 5 +
> images/Makefile.imx| 5 +
> 10 files changed, 463 insertions(+)
> create mode 100644 arch/arm/boards/advantech-mx6/Makefile
> create mode 100644 arch/arm/boards/advantech-mx6/board.c
> create mode 100644
> arch/arm/boards/advantech-mx6/flash-header-advantech-rom-7421.imxcfg
> create mode 100644 arch/arm/boards/advantech-mx6/lowlevel.c
> create mode 100755 arch/arm/dts/imx6dl-advantech-rom-7421.dts
>
> diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
> index ca187cc..521f37d 100644
> --- a/arch/arm/boards/Makefile
> +++ b/arch/arm/boards/Makefile
> @@ -1,4 +1,5 @@
> # keep sorted by CONFIG_* macro name.
> +obj-$(CONFIG_MACH_ADVANTECH_ROM_742X)+= advantech-mx6/
> obj-$(CONFIG_MACH_AFI_GF)+= afi-gf/
> obj-$(CONFIG_MACH_ANIMEO_IP) += animeo_ip/
> obj-$(CONFIG_MACH_ARCHOSG9) += archosg9/
> diff --git a/arch/arm/boards/advantech-mx6/Makefile
> b/arch/arm/boards/advantech-mx6/Makefile
> new file mode 100644
> index 000..01c7a25
> --- /dev/null
> +++ b/arch/arm/boards/advantech-mx6/Makefile
> @@ -0,0 +1,2 @@
> +obj-y += board.o
> +lwl-y += lowlevel.o
> diff --git a/arch/arm/boards/advantech-mx6/board.c
> b/arch/arm/boards/advantech-mx6/board.c
> new file mode 100644
> index 000..4a30a84
> --- /dev/null
> +++ b/arch/arm/boards/advantech-mx6/board.c
> @@ -0,0 +1,101 @@
> +/*
> + * Copyright (C) 2018 Christoph Fritz
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +static int ar8035_phy_fixup(struct phy_device *dev)
> +{
> + u16 val;
> +
> + /* Ar803x phy SmartEEE feature cause link status generates glitch,
> + * which cause ethernet link down/up issue, so disable SmartEEE
> + */
> + phy_write(dev, 0xd, 0x3);
> + phy_write(dev, 0xe, 0x805d);
> + phy_write(dev, 0xd, 0x4003);
> +
> + val = phy_read(dev, 0xe);
> + phy_write(dev, 0xe, val & ~BIT(8));
> +
> + /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
> + phy_write(dev, 0xd, 0x7);
> + phy_write(dev, 0xe, 0x8016);
> + phy_write(dev, 0xd, 0x4007);
> +
> + val = phy_read(dev, 0xe);
> + val &= 0xffe3;
> + val |= 0x18;
> + phy_write(dev, 0xe, val);
> +
> + /* introduce tx clock delay */
> + phy_write(dev, 0x1d, 0x5);
> + val = phy_read(dev, 0x1e);
> + val |= 0x0100;
> + phy_write(dev, 0x1e, val);
> +
> + return 0;
> +}
> +
> +static int advantech_mx6_devices_init(void)
> +{
> + int ret;
> + char *environment_path, *envdev;
> +
> + if (!of_machine_is_compatible("advantech,imx6dl-rom-7421"))
> + return 0;
> +
> + phy_register_fixup_for_uid(0x004dd072, 0xffef, ar8035_phy_fixup);
> +
> + switch (bootsource_get()) {
> + case BOOTSOURCE_MMC:
> + environment_path = basprintf("/chosen/environment-sd%d",
> + bootsource_get_instance() + 1);
> + if (bootsource_get_instance() + 1 == 4)
> + envdev = "eMMC";
> + else
