v2022.09.0
Hi All, I am happy to announce barebox-2022.09.0. This time we have a few new board supports: Support for the 96Boards Meerkat96 board is added as well as support for the Enclustra AA1 (SoCFPGA). Also worth noting is that we now have ROMAPI support for the i.MX8MP and i.MX8MN. This allows us to bootstrap barebox via USB on these SoCs. Another nice detail has been added by Ahmad. The of_dump command now has an option to limit the data size for each property to be printed. This makes it particularly useful for showing FIT images. A lot of other small fixes and improvements went into this release, see below. Have Fun! Sascha -8<-- Ahmad Fatoum (75): ARM: i.MX8M: select ARM_USE_COMPRESSED_DTB for all boards ARM: i.MX8M: use compressed DTBs partitions: efi: register guid device parameter for disk GUID commands: implement devlookup to find device behind device file block: efi: allow disabling /dev/usbdiskX renaming ARM: i.MX8MN: pass along correct DT depending on variant regulator: fixed: remove duplicate always-on handling aiodev: add ST L3GD20 Gyroscope and temperature sensor support pinctrl: stm32: keep GPIO bank clocks enabled throughout spi: stm32: fix reads for sizes bigger than SZ_64K-1 common: don't allow compressing in-barebox binaries again pbl: make USE_COMPRESSED_DTB a PBL-only feature pbl: remove redundant select UNCOMRPESS kbuild: gen-dtb-s: use Makefile.lib instead of duplicating cmd_lzo pbl: compressed-dtb: use flexible array member to access data kbuild: pbl: use same compression algo for both barebox and DTB lib: zstd: sync with Linux decompressor: define macros for non-PBL case as well of: base: factor out duplication for property formatting commands: of_dump: support limiting size of printed properties string: implement str_has_prefix booti: add debug prints for kernel header parsing reset: Fix of_reset_control_get() for consistent return values reset: implement reset_control_get_optional() reset: implement reset_control_get_count() ARM: i.MX8M: move TF-A chainload functions in ARM: i.MX8M: imx8mn-evk: use generic imx8mn_load_and_start_image_via_tfa ARM: i.MX8MN: add SDPS barebox-side support ARM: i.MX8MN: evk: simplify DDR4/LPDDR4 selection code ddr: imx8m: rename type to more fitting ddrc|dram_type ARM: i.MX8M: remove struct dram_timing_info::dram_type again pbl: generalize fsl i2c_early API into pbl_i2c i2c: add for PBL use ARM: i.MX8M: use new pbl/pmic.h API mci: imx-esdhc-pbl: fix warning about unused static function gitignore: add device tree blobs to top-level .gitignore defaultenv: ikconfig: add generated directory to .gitignore pbl: factor out pbl_bio API into pbl/bio.h scripts: imx-usb-loader: add i.MX8MN support RISC-V: asm: factor relocation related functions into asm/reloc.h ARM: asm: factor relocation related functions in asm/reloc.h MIPS: asm: add get_runtime_offset stub ARM: i.MX8MP: remove select for unused ARC PBL USB gadget driver driver: probe: report power domain attach failure commands: boot: support preselecting boot entry in menu mfd: implement mfd_add_devices regmap: implement regmap_init_i2c_smbus regulator: consult min_uv, max_uv for regulator_get_voltage blspec: refactor to prepare for booting by file path blspec: iterate over entries in lexical order boot: allow booting by bootspec absolute path mci: add hint on how to resolve warning about vmmc-supply test: self: add simple environment variable test test: self: include new tests in CONFIG_SELFTEST_ENABLE_ALL bootsource: rename existing bootsource_set to bootsource_set_raw bootsource: allow DT aliases and bootrom numbering to differ ARM: dts: rk356x: align bootsource_instance numbering and MMC DT aliases net: designware: rework Kconfig text and menu structure net: designware: eqos: stm32: remove duplicate error message net: designware: eqos: replace double accounting of interface up status net: designware: eqos: remove undefined eqos_reset prototype FIT: add first support for compressed images of: implement of_append_property test: self: add tests for of_append_property power: reset: reboot-mode: refactor to allow other mode- prefixes power: reset: reboot-mode: parse barebox,mode-* properties ARM: dts: stm32mp: reuse now upstream tamp node ARM: dts: stm32mp: add bootrom serial (DFU) reboot mode regulator: recursively enable/disable regulator dependency tree regulator: fixed: request vin-supply as needed regulator: add Rockchip rk808 support ARM: dts: imx6: marsboard: fix flash node after upstream rename ARM: i.MX8M: HABv4:
[PATCH 2/6] RISC-V: add riscv_vendor_id() support
Add the support to query the vendorid which is stored within the
mvendorid register. This register is only accessible from M-Mode so we
need to use the sbi interface if we are running from S-Mode.
Signed-off-by: Marco Felsch
---
arch/riscv/include/asm/system.h | 31 +++
1 file changed, 31 insertions(+)
diff --git a/arch/riscv/include/asm/system.h b/arch/riscv/include/asm/system.h
index adf856f9e9..3eb50f63fd 100644
--- a/arch/riscv/include/asm/system.h
+++ b/arch/riscv/include/asm/system.h
@@ -5,6 +5,8 @@
#ifndef __ASSEMBLY__
+#include
+
#define RISCV_MODE_MASK 0x3
enum riscv_mode {
RISCV_U_MODE = 0,
@@ -42,6 +44,30 @@ static inline long __riscv_hartid(u32 flags)
return hartid;
}
+static inline long __riscv_vendor_id(u32 flags)
+{
+ struct sbiret ret = { .error = -1 };
+ long id;
+
+ switch (__riscv_mode(flags)) {
+ case RISCV_M_MODE:
+ __asm__ volatile("csrr %0, mvendorid\n" : "=r"(id));
+ return id;
+ case RISCV_S_MODE:
+ /*
+* We need to use the sbi_ecall() since it can be that we got
+* called without a working stack
+*/
+ ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_MVENDORID,
+ 0, 0, 0, 0, 0, 0);
+ if (!ret.error)
+ return ret.value;
+ default:
+ }
+
+ return ret.error;
+}
+
#ifndef __PBL__
extern unsigned barebox_riscv_pbl_flags;
@@ -54,6 +80,11 @@ static inline long riscv_hartid(void)
{
return __riscv_hartid(barebox_riscv_pbl_flags);
}
+
+static inline long riscv_vendor_id(void)
+{
+ return __riscv_vendor_id(barebox_riscv_pbl_flags);
+}
#endif
#endif
--
2.30.2
[PATCH 0/6] RISC-V Allwinner D1 Support 2nd Stage Support
Hi, this small series adds the basic support for the Allwinner sun20i D1 Nezsha board. It is very limited only serial is supported right now. Patches 1-4 can be applied independently. Patch 5 may need some more attention since Ahmad told me in person that not all softcores implementing the vendorid register. Please see the patch notes on this patch. Patch 6 adds the support for the D1 board and a detailed description how to build and flash a bootable image. Marco Felsch (6): RISC-V: cache: fix local_flush_icache_all enabling RISC-V: add riscv_vendor_id() support RISC-V: import vendorid list from linux RISC-V: use m/sscratch registers for barebox_riscv_pbl_flags RISC-V: implement cache-management errata for T-Head SoCs RISC-V: add Allwinner Sun20i D1 Nezha support Documentation/boards/riscv.rst| 102 + arch/riscv/Kconfig.socs | 16 +++ arch/riscv/boards/Makefile| 1 + arch/riscv/boards/allwinner-d1/Makefile | 3 + arch/riscv/boards/allwinner-d1/lowlevel.c | 12 ++ arch/riscv/boot/entry.c | 3 +- arch/riscv/boot/entry.h | 6 +- arch/riscv/boot/start.c | 13 +-- arch/riscv/boot/uncompress.c | 8 +- arch/riscv/configs/sun20i_defconfig | 130 ++ arch/riscv/include/asm/cache.h| 23 +++- arch/riscv/include/asm/debug_ll.h | 5 + arch/riscv/include/asm/system.h | 71 +--- arch/riscv/include/asm/vendorid_list.h| 11 ++ common/Kconfig| 5 + images/Makefile.riscv | 4 + 16 files changed, 380 insertions(+), 33 deletions(-) create mode 100644 arch/riscv/boards/allwinner-d1/Makefile create mode 100644 arch/riscv/boards/allwinner-d1/lowlevel.c create mode 100644 arch/riscv/configs/sun20i_defconfig create mode 100644 arch/riscv/include/asm/vendorid_list.h -- 2.30.2
[PATCH 5/6] RISC-V: implement cache-management errata for T-Head SoCs
Since riscv_vendor_id() can be used from pbl and non-pbl context as well
as from relocated and non-relocated code, we are able to query the
vendor id and add special vendor handlings. This is required since the
T-Head C906 and C910 implement a scheme for handling cache operations
different from the generic Zicbom extension.
While on it replace the 'asm' statement by '__asm__' so we are not
relying on GNU extension.
Signed-off-by: Marco Felsch
---
Hi,
please note that I'm aware of the fact that not all RISC-V cores
implementing the vendorid register, which is quirky according the
"privileged architecture" documentation. For such cores I would propose
to extend the pbl-flags by adding a quirks field. Platforms not
supporting the vendorid register can set the quirk within th
lowlevel/pbl code e.g.:
barebox_riscv_supervisor_entry(DRAM_BASE, SZ_1G, hartid, fdt,
RISCV_QUIRK_NO_VENDORID);
This can be parsed by riscv_vendor_id() so in such case the vendorid 0
which is:
3.1.2 Machine Vendor ID Register mvendorid
The mvendorid CSR is a 32-bit read-only register providing the JEDEC
manufacturer ID of the provider of the core. This register must be
readable in any implementation, but a value of 0 can be returned to
indicate the field is not implemented or that this is a non-commercial
implementation.
Regards,
Marco
arch/riscv/include/asm/cache.h | 21 -
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h
index 6d69ed49bd..c787f89001 100644
--- a/arch/riscv/include/asm/cache.h
+++ b/arch/riscv/include/asm/cache.h
@@ -6,10 +6,29 @@
#ifndef _ASM_RISCV_CACHE_H
#define _ASM_RISCV_CACHE_H
+#include
+
+static inline void thead_local_flush_icache_all(void)
+{
+ /*
+* According [1] "13.3 Example of cache settings"
+* [1]: https://github.com/T-head-Semi/openc906/blob/main/ \
+* doc/openc906%20datasheet.pd
+*/
+ __asm__ volatile (".long 0x010b" ::: "memory"); /* th.icache.iall */
+ __asm__ volatile (".long 0x01bb" ::: "memory"); /* th.sync.is */
+}
+
static inline void local_flush_icache_all(void)
{
#ifdef CONFIG_HAS_CACHE
- asm volatile ("fence.i" ::: "memory");
+ switch(riscv_vendor_id()) {
+ case THEAD_VENDOR_ID:
+ thead_local_flush_icache_all();
+ break;
+ default:
+ __asm__ volatile ("fence.i" ::: "memory");
+ }
#endif
}
--
2.30.2
[PATCH 6/6] RISC-V: add Allwinner Sun20i D1 Nezha support
Add Allwinner sun20i SoC and D1-Nezha board support. Signed-off-by: Marco Felsch --- Documentation/boards/riscv.rst| 102 + arch/riscv/Kconfig.socs | 16 +++ arch/riscv/boards/Makefile| 1 + arch/riscv/boards/allwinner-d1/Makefile | 3 + arch/riscv/boards/allwinner-d1/lowlevel.c | 12 ++ arch/riscv/configs/sun20i_defconfig | 130 ++ arch/riscv/include/asm/debug_ll.h | 5 + common/Kconfig| 5 + images/Makefile.riscv | 4 + 9 files changed, 278 insertions(+) create mode 100644 arch/riscv/boards/allwinner-d1/Makefile create mode 100644 arch/riscv/boards/allwinner-d1/lowlevel.c create mode 100644 arch/riscv/configs/sun20i_defconfig diff --git a/Documentation/boards/riscv.rst b/Documentation/boards/riscv.rst index b7a3a95f0f..4c31c4316b 100644 --- a/Documentation/boards/riscv.rst +++ b/Documentation/boards/riscv.rst @@ -188,3 +188,105 @@ Next, start barebox from DRAM:: running /env/bin/init... /env/bin/init not found barebox:/ + +Allwinner D1 Nezha +-- + +Barebox has limited second-stage support for the Allwinner D1 Nezha (sun20i):: + + ARCH=riscv make sun20i_defconfig + ARCH=riscv CROSS_COMPILE=riscv64-linux-gnu- make + +The resulting ``./images/barebox-allwinner-d1.img`` can be used as 2nd stage +image which gets called by opensbi:: + + git clone https://github.com/tekkamanninja/opensbi -b allwinner_d1 + cd opensbi + CROSS_COMPILE=riscv64-linux-gnu- PLATFORM=generic FW_PIC=y make + +The resulting ``./build/platform/generic/firmware/fw_dynamic.bin`` is loaded +by the 1st stage (spl) loader, which is basically a u-boot spl:: + + git clone https://github.com/smaeul/sun20i_d1_spl -b mainline + cd sun20i_d1_spl + CROSS_COMPILE=riscv64-linux-gnu- make p=sun20iw1p1 mmc + +The resulting ``./nboot/boot0_sdcard_sun20iw1p1.bin`` image used as 1st stage +bootloader which loads all necessary binaries: dtb, opensbi and barebox to the +dedicated places in DRAM. After loading it jumps to the opensbi image. The +initial dtb can be taken from u-boot:: + + git clone https://github.com/smaeul/u-boot.git -b d1-wip + cd u-boot + ARCH=riscv make nezha_defconfig + ARCH=riscv CROSS_COMPILE=riscv64-linux-gnu- make + +Make will print two warnings at the end of this command but those can be ignored +since we only want the devicetree blob which can be found under ``./u-boot.dtb``. + +The final image is build by mkimage. It is some sort of a self-defined toc1 +format. So we need to compile the mkimage with the toc1 format support as +first:: + + cd u-boot + make tools-only + +The resulting ``tools/mkimage`` is used to build the toc1 image which is loaded +by the 1st stage bootloader from the mmc interface. To build the final toc1 image +we need to specify a toc1.cfg like:: + + [opensbi] + file = /opensbi/build/platform/generic/firmware/fw_dynamic.bin + addr = 0x4000 + [dtb] + file = /u-boot/u-boot.dtb + addr = 0x4400 + [u-boot] + file = /barebox/images/barebox-allwinner-d1.img + addr = 0x4a00 + +Then we need to call:: + + mkimage -T sunxi_toc1 -d toc1.cfg boot.toc1 + +The last part is to place the 1st stage bootloader and the ``boot.toc1`` image +onto the correct places. So the ROM loader can find the 1st stage bootloader +and the 1st bootloader can find the ``boot.toc1`` image. This is done by:: + + dd if=boot0_sdcard_sun20iw1p1.bin of=/dev/sd bs=512 seek=16 + dd if=boot.toc1 of=/dev/sd bs=512 seek=32800 + +Now plug in the sdcard and power device and you will see:: + + [309]HELLO! BOOT0 is starting! + [312]BOOT0 commit : 882671f-dirty + [315]set pll start + [317]periph0 has been enabled + [320]set pll end + [322]board init ok + + ... + + OpenSBI v0.9-204-gc9024b5 + _ _ +/ __ \ / | _ \_ _| + | | | |_ __ ___ _ __ | (___ | |_) || | + | | | | '_ \ / _ \ '_ \ \___ \| _ < | | + | |__| | |_) | __/ | | |) | |_) || |_ +\/| .__/ \___|_| |_|_/|/_| + | | + |_| + + Platform Name : Allwinner D1 Nezha + Platform Features : medeleg + + ... + + barebox 2022.08.0-00262-g38678340903b #1 Tue Sep 13 12:54:29 CEST 2022 + + + Board: Allwinner D1 Nezha + + ... + + barebox@Allwinner D1 Nezha:/ diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 828b65a0c1..0f03637a66 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -110,6 +110,22 @@ config BOARD_BEAGLEV_BETA endif +config SOC_ALLWINNER_SUN20I + bool "Allwinner Sun20i SoCs" + depends on ARCH_RV64I + select HAS_ASM_DEBUG_LL + select HAS_CACHE + +if SOC_ALLWINNER_SUN20I + +config BOARD_ALLWINNER_D1 + bool "Allwinner D1 Nezha" + select RISCV_S_MODE + select RISCV_M_MODE + def_bool y + +endif + comment "CPU features" config SIFIVE_L2 diff
[PATCH 4/6] RISC-V: use m/sscratch registers for barebox_riscv_pbl_flags
Use the dedicated scratch register for setting the pbl flags. Each mode
has it's own scratch register so we are not conflicting with M-mode
running firmware e.g. OpenSBI. Using the scratch register has two main
advantages:
1st) It can be used in PBL and non-PBL use-case.
2nd) It is not affected by the relocation code.
This commit prepares barebox to add support for the special cache ops
used by several T-Head CPUs.
Signed-off-by: Marco Felsch
---
arch/riscv/boot/entry.c | 3 +-
arch/riscv/boot/entry.h | 6 ++--
arch/riscv/boot/start.c | 13 +++
arch/riscv/boot/uncompress.c| 8 ++---
arch/riscv/include/asm/system.h | 62 -
5 files changed, 50 insertions(+), 42 deletions(-)
diff --git a/arch/riscv/boot/entry.c b/arch/riscv/boot/entry.c
index e4a5c2208d..f5a536fc78 100644
--- a/arch/riscv/boot/entry.c
+++ b/arch/riscv/boot/entry.c
@@ -25,6 +25,7 @@ void __noreturn __naked barebox_riscv_entry(unsigned long
membase,
{
unsigned long stack_top = riscv_mem_stack_top(membase, membase +
memsize);
asm volatile ("move sp, %0" : : "r"(stack_top));
- barebox_pbl_start(membase, memsize, boarddata, flags);
+ riscv_set_flags(flags);
+ barebox_pbl_start(membase, memsize, boarddata);
}
diff --git a/arch/riscv/boot/entry.h b/arch/riscv/boot/entry.h
index fb4af5eae5..b3a24d2783 100644
--- a/arch/riscv/boot/entry.h
+++ b/arch/riscv/boot/entry.h
@@ -6,12 +6,10 @@
void __noreturn barebox_non_pbl_start(unsigned long membase,
unsigned long memsize,
- void *boarddata,
- unsigned flags);
+ void *boarddata);
void __noreturn barebox_pbl_start(unsigned long membase,
unsigned long memsize,
- void *boarddata,
- unsigned flags);
+ void *boarddata);
#endif
diff --git a/arch/riscv/boot/start.c b/arch/riscv/boot/start.c
index 8b4c8bb2f0..27d9066243 100644
--- a/arch/riscv/boot/start.c
+++ b/arch/riscv/boot/start.c
@@ -27,7 +27,6 @@ static unsigned long riscv_barebox_size;
static unsigned long riscv_endmem;
static void *barebox_boarddata;
static unsigned long barebox_boarddata_size;
-unsigned barebox_riscv_pbl_flags;
void *barebox_riscv_boot_dtb(void)
{
@@ -108,7 +107,7 @@ device_initcall(barebox_memory_areas_init);
*/
__noreturn __no_sanitize_address __section(.text_entry)
void barebox_non_pbl_start(unsigned long membase, unsigned long memsize,
- void *boarddata, unsigned flags)
+ void *boarddata)
{
unsigned long endmem = membase + memsize;
unsigned long malloc_start, malloc_end;
@@ -121,7 +120,7 @@ void barebox_non_pbl_start(unsigned long membase, unsigned
long memsize,
barrier();
- irq_init_vector(__riscv_mode(flags));
+ irq_init_vector(riscv_mode());
pr_debug("memory at 0x%08lx, size 0x%08lx\n", membase, memsize);
@@ -171,20 +170,18 @@ void barebox_non_pbl_start(unsigned long membase,
unsigned long memsize,
mem_malloc_init((void *)malloc_start, (void *)malloc_end - 1);
- barebox_riscv_pbl_flags = flags;
-
pr_debug("starting barebox...\n");
start_barebox();
}
-void start(unsigned long membase, unsigned long memsize, void *boarddata,
unsigned flags);
+void start(unsigned long membase, unsigned long memsize, void *boarddata);
/*
* First function in the uncompressed image. We get here from
* the pbl. The stack already has been set up by the pbl.
*/
void __no_sanitize_address __section(.text_entry) start(unsigned long membase,
- unsigned long memsize, void *boarddata, unsigned flags)
+ unsigned long memsize, void *boarddata)
{
- barebox_non_pbl_start(membase, memsize, boarddata, flags);
+ barebox_non_pbl_start(membase, memsize, boarddata);
}
diff --git a/arch/riscv/boot/uncompress.c b/arch/riscv/boot/uncompress.c
index 4ed9b4d371..ee24f81e01 100644
--- a/arch/riscv/boot/uncompress.c
+++ b/arch/riscv/boot/uncompress.c
@@ -24,16 +24,16 @@ unsigned long free_mem_ptr;
unsigned long free_mem_end_ptr;
void __noreturn barebox_pbl_start(unsigned long membase, unsigned long memsize,
- void *fdt, unsigned flags)
+ void *fdt)
{
uint32_t pg_len, uncompressed_len;
- void __noreturn (*barebox)(unsigned long, unsigned long, void *,
unsigned);
+ void __noreturn (*barebox)(unsigned long, unsigned long, void *);
unsigned long endmem = membase + memsize;
unsigned long barebox_base;
void *pg_start, *pg_end;
unsigned long pc = get_pc();
- irq_init_vector(__riscv_mode(flags));
+ irq_init_vector(riscv_mode());
/* piggy data is
[PATCH 1/6] RISC-V: cache: fix local_flush_icache_all enabling
Commit fe181ffda9 ("RISC-V: support incoherent I-Cache") added the
support to handle non-coherent caches and introduced the HAS_CACHE
Kconfig symbol. The symbol must be used with CONFIG_ prefixed since this
is the final Kconfig symbol which can be used within the code.
Fixes: fe181ffda9 ("RISC-V: support incoherent I-Cache")
Signed-off-by: Marco Felsch
---
arch/riscv/include/asm/cache.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h
index 9a0b9326b2..6d69ed49bd 100644
--- a/arch/riscv/include/asm/cache.h
+++ b/arch/riscv/include/asm/cache.h
@@ -8,7 +8,7 @@
static inline void local_flush_icache_all(void)
{
-#ifdef HAS_CACHE
+#ifdef CONFIG_HAS_CACHE
asm volatile ("fence.i" ::: "memory");
#endif
}
--
2.30.2
[PATCH 3/6] RISC-V: import vendorid list from linux
Import the vendor id list from upstream linux. Signed-off-by: Marco Felsch --- arch/riscv/include/asm/vendorid_list.h | 11 +++ 1 file changed, 11 insertions(+) create mode 100644 arch/riscv/include/asm/vendorid_list.h diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/asm/vendorid_list.h new file mode 100644 index 00..cb89af3f07 --- /dev/null +++ b/arch/riscv/include/asm/vendorid_list.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2021 SiFive + */ +#ifndef ASM_VENDOR_LIST_H +#define ASM_VENDOR_LIST_H + +#define SIFIVE_VENDOR_ID 0x489 +#define THEAD_VENDOR_ID0x5b7 + +#endif -- 2.30.2
Re: [PATCH next] Documentation: filesystems: tftp: fix code blocks
On Tue, Sep 13, 2022 at 12:54:11PM +0300, Antony Pavlov wrote: > On Tue, 13 Sep 2022 10:08:37 +0200 > Sascha Hauer wrote: > > Hi Sascha! > > > On Mon, Sep 12, 2022 at 11:50:47AM +0300, Antony Pavlov wrote: > > > The patch fixes these sphinx errors: > > > > > > Documentation/filesystems/tftp.rst:44: ERROR: Error in "code-block" > > > directive: > > > maximum 1 argument(s) allowed, 3 supplied. > > > Documentation/filesystems/tftp.rst:53: ERROR: Error in "code-block" > > > directive: > > > maximum 1 argument(s) allowed, 4 supplied. > > > > > > Signed-off-by: Antony Pavlov > > > --- > > > Documentation/filesystems/tftp.rst | 2 ++ > > > 1 file changed, 2 insertions(+) > > > > Applied, thanks > > I thought that this patch is for ammend. My bad! I shell add "for > ammend" or "fixup" tag to the message subject next time. Ah, ok, I didn't realize that. When the to-be-fixed-up patch sits in next you could just commit with --fixup=, this makes it very easy to fix it up on my side. Sascha -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
[PATCH] ubifs: Fix pointer type mismatch in gzip decompressor
deflate_decompress() takes a unsigned int * for the out_len argument
whereas ubifs passes a size_t * argument. Adjust the argument type
accordingly.
Signed-off-by: Sascha Hauer
---
fs/ubifs/ubifs.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/fs/ubifs/ubifs.c b/fs/ubifs/ubifs.c
index 0b4f3de773..71ccd2c0e7 100644
--- a/fs/ubifs/ubifs.c
+++ b/fs/ubifs/ubifs.c
@@ -46,7 +46,14 @@ static ZSTD_DCtx *ubifs_zstd_cctx;
static int gzip_decompress(const unsigned char *in, size_t in_len,
unsigned char *out, size_t *out_len)
{
- return deflate_decompress(_zlib_stream, in, in_len, out, out_len);
+ unsigned int olen;
+ int ret;
+
+ ret = deflate_decompress(_zlib_stream, in, in_len, out, );
+
+ *out_len = olen;
+
+ return ret;
}
#endif
--
2.30.2
Re: [PATCH next] Documentation: filesystems: tftp: fix code blocks
On Tue, 13 Sep 2022 10:08:37 +0200 Sascha Hauer wrote: Hi Sascha! > On Mon, Sep 12, 2022 at 11:50:47AM +0300, Antony Pavlov wrote: > > The patch fixes these sphinx errors: > > > > Documentation/filesystems/tftp.rst:44: ERROR: Error in "code-block" > > directive: > > maximum 1 argument(s) allowed, 3 supplied. > > Documentation/filesystems/tftp.rst:53: ERROR: Error in "code-block" > > directive: > > maximum 1 argument(s) allowed, 4 supplied. > > > > Signed-off-by: Antony Pavlov > > --- > > Documentation/filesystems/tftp.rst | 2 ++ > > 1 file changed, 2 insertions(+) > > Applied, thanks I thought that this patch is for ammend. My bad! I shell add "for ammend" or "fixup" tag to the message subject next time. > > > > diff --git a/Documentation/filesystems/tftp.rst > > b/Documentation/filesystems/tftp.rst > > index 8929213d3c4..e88ad3dd4c8 100644 > > --- a/Documentation/filesystems/tftp.rst > > +++ b/Documentation/filesystems/tftp.rst > > @@ -42,6 +42,7 @@ the opposite effect. Performance depends on: > > 100 Mb/s) it had to be reduced to > > > > .. code-block:: console > > + > > global tftp.windowsize=26 > > > > for example. > > @@ -51,6 +52,7 @@ the opposite effect. Performance depends on: > > example, the `fec-imx` driver reserves place for > > > > .. code-block:: c > > + > > #define FEC_RBD_NUM 64 > > > > packets before they are dropped > > -- > > 2.37.2 > > > > > > -- > Pengutronix e.K. | | > Steuerwalder Str. 21 | http://www.pengutronix.de/ | > 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | -- Best regards, Antony Pavlov
[PATCH 1/2] ARM: rdu2: Drop redundant of graph link
The link is also present in the upstream dtsi file in the same way, so
remove it from the barebox overlay.
Signed-off-by: Sascha Hauer
---
arch/arm/dts/imx6qdl-zii-rdu2.dtsi | 10 --
1 file changed, 10 deletions(-)
diff --git a/arch/arm/dts/imx6qdl-zii-rdu2.dtsi
b/arch/arm/dts/imx6qdl-zii-rdu2.dtsi
index b593545ffe..59f7656139 100644
--- a/arch/arm/dts/imx6qdl-zii-rdu2.dtsi
+++ b/arch/arm/dts/imx6qdl-zii-rdu2.dtsi
@@ -234,16 +234,6 @@
{
edp-bridge@68 {
pinctrl-0 = <_tc358767>, <_disp0>;
-
- ports {
- port@1 {
- reg = <1>;
-
- tc358767_in: endpoint {
- remote-endpoint = <_out>;
- };
- };
- };
};
};
--
2.30.2
[PATCH 2/2] ARM: rdu2: fix dtc warning
This fixes:
dts/src/arm/imx6qdl.dtsi:1332.32-1334.7: Warning (graph_endpoint):
/soc/ipu@240/port@2/endpoint@0: graph connection to node
'/soc/bus@210/i2c@21a/edp-bridge@68/ports/port@1/endpoint' is not
bidirectional
also defined at dts/src/arm/imx6qdl-zii-rdu2.dtsi:647.17-649.3
also defined at arch/arm/dts/imx6qdl-zii-rdu2.dtsi:246.17-248.3
dts/src/arm/imx6qdl-zii-rdu2.dtsi:186.25-188.6: Warning (graph_endpoint):
/disp0/port@0/endpoint: graph connection to node
'/soc/ipu@240/port@2/endpoint@0' is not bidirectional
dts/src/arm/imx6qdl.dtsi:1332.32-1334.7: Warning (graph_endpoint):
/soc/ipu@240/port@2/endpoint@0: graph connection to node
'/soc/bus@210/i2c@21a/edp-bridge@68/ports/port@1/endpoint' is not
bidirectional
also defined at dts/src/arm/imx6qdl-zii-rdu2.dtsi:647.17-649.3
also defined at arch/arm/dts/imx6qdl-zii-rdu2.dtsi:246.17-248.3
dts/src/arm/imx6qdl-zii-rdu2.dtsi:186.25-188.6: Warning (graph_endpoint):
/disp0/port@0/endpoint: graph connection to node
'/soc/ipu@240/port@2/endpoint@0' is not bidirectional
I don't know if the link is non biderectional intentionally, it might
have something to do with the runtime dts adjustments. The warning
is around for a long time now without anybody caring, so just get
rid of it and see if somebody can explain the backgrounds or provide
a proper solution for it.
Signed-off-by: Sascha Hauer
---
arch/arm/dts/imx6qdl-zii-rdu2.dtsi | 4
1 file changed, 4 deletions(-)
diff --git a/arch/arm/dts/imx6qdl-zii-rdu2.dtsi
b/arch/arm/dts/imx6qdl-zii-rdu2.dtsi
index 59f7656139..714ba8e755 100644
--- a/arch/arm/dts/imx6qdl-zii-rdu2.dtsi
+++ b/arch/arm/dts/imx6qdl-zii-rdu2.dtsi
@@ -243,10 +243,6 @@
};
};
-_di0_disp0 {
- remote-endpoint = <_in>;
-};
-
{
lvds-channel@0 {
fsl,data-width = <24>;
--
2.30.2
TFTP RFC7440 windowsize support
Hi All, As you might have noticed Enrico added RFC7440 support to our TFTP support. This greatly improves the speed for TFTP transfers when the server also has RFC7440 support. RFC7440 support has just appeared in the latest atftpd release (version 0.8.0), so you can give this a try without locally patched TFTP demons. This release is also available in debian backports. Unfortunately there's no light without shadow. On i.MX6 the FEC ethernet controller is too slow to catch up with a gigabit link. Up to now this hasn't been a problem on barebox, as we only ever had a single packet in flight. Now with windowsize support the controller can get overwhelmed with so many TFTP packets that RX overruns occur. I changed the imx_v7_defconfig to limit the windowsize to a smaller value that seems to work here. Similar problems might exist on other ethernet controllers, so we might have to generally switch to more conservative default window sizes. Sascha -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
[PATCH] ARM: imx_v7_defconfig: Limit TFTP window size
The FEC ethernet controller is too slow to catch up with a gigabit link. This hasn't been a problem until now, because the protocols we use in barebox only have a single packet in flight. With TFTP window size support and a gigabit link though we get receive buffer overruns resulting in messages like: WARNING: eth0: error frame: 0x2feca098 0x0806 The resulting speed is slower than without TFTP windowsize support due to the necessary retransmits. Limit the window size to a value that seems to be working on i.MX6 boards. Signed-off-by: Sascha Hauer --- arch/arm/configs/imx_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/imx_v7_defconfig b/arch/arm/configs/imx_v7_defconfig index df2304eae9..d07abe28ae 100644 --- a/arch/arm/configs/imx_v7_defconfig +++ b/arch/arm/configs/imx_v7_defconfig @@ -210,6 +210,7 @@ CONFIG_GENERIC_PHY=y CONFIG_USB_NOP_XCEIV=y CONFIG_FS_EXT4=y CONFIG_FS_TFTP=y +CONFIG_FS_TFTP_MAX_WINDOW_SIZE=8 CONFIG_FS_NFS=y CONFIG_FS_FAT=y CONFIG_FS_FAT_WRITE=y -- 2.30.2
Re: [PATCH] fs: ubifs: remove always-false check
On 13.09.22 10:37, Sascha Hauer wrote:
> On Thu, Aug 11, 2022 at 03:58:04PM +0200, Ahmad Fatoum wrote:
>> GCC correctly warns that two bit wide compr_type can't
>> exceed or be equal to UBIFS_COMPR_TYPES_CNT (== 4).
>>
>> Remove the check. The check is there in the kernel as well,
>> but the warning is disabled there.
>>
>> Signed-off-by: Ahmad Fatoum
>> ---
>> fs/ubifs/super.c | 5 -
>> 1 file changed, 5 deletions(-)
>>
>> diff --git a/fs/ubifs/super.c b/fs/ubifs/super.c
>> index b48e21fae636..6a0074bd1a5c 100644
>> --- a/fs/ubifs/super.c
>> +++ b/fs/ubifs/super.c
>> @@ -86,11 +86,6 @@ static int validate_inode(struct ubifs_info *c, const
>> struct inode *inode)
>> return 1;
>> }
>>
>> -if (ui->compr_type >= UBIFS_COMPR_TYPES_CNT) {
>> -ubifs_err(c, "unknown compression type %d", ui->compr_type);
>> -return 2;
>> -}
>> -
>
> Although Richard decided for the Kernel to keep the check I decided to
> take this patch for barebox. The warning is annoying and doesn't tell us
> anything. Once this is solved in the Kernel we'll get the solution with
> the next UBIFS sync.
My thoughts exactly.
Cheers,
Ahmad
>
> Sascha
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0|
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
Re: [PATCH master] ARM: sync_caches_for_execution: don't flush disabled data cache
On Thu, Sep 01, 2022 at 12:41:36PM +0200, Ahmad Fatoum wrote:
> We unconditionally clean and then invalidate D-cache entries in
> sync_caches_for_execution by calling arm_early_mmu_cache_flush().
>
> The function afterwards takes care to invalidate the I-cache.
>
> This misbehaves though when the D-Cache contains stale dirty
> entries for currently executing code. Most boards avoid this
> pitfall, because barebox_arm_entry calls
> arm_early_mmu_cache_invalidate() and sync_caches_for_execution()
> is only called afterwards. But for some boards,
> relocate_to_current_adr() is called before barebox_arm_entry and
> various board code works around this by calling
> arm_early_mmu_cache_invalidate() first.
>
> Make this unnecessary by not flushing the data cache when it's disabled
> and instead only invalidate the I-Cache.
>
> This fixes a hang observed on a serial-booted i.MX6Q rev 1.5
> executing relocate_to_current_adr() -> sync_caches_for_execution()
> from On-Chip SRAM.
>
> Signed-off-by: Ahmad Fatoum
> ---
> arch/arm/cpu/common.c | 6 ++
> 1 file changed, 6 insertions(+)
Applied, thanks
Sascha
>
> diff --git a/arch/arm/cpu/common.c b/arch/arm/cpu/common.c
> index 8cfcc8f6ce7a..5ccacf204751 100644
> --- a/arch/arm/cpu/common.c
> +++ b/arch/arm/cpu/common.c
> @@ -23,6 +23,12 @@
> */
> void sync_caches_for_execution(void)
> {
> + /* if caches are disabled, don't do data cache maintenance */
> + if (!(get_cr() & CR_C)) {
> + icache_invalidate();
> + return;
> + }
> +
> /*
>* Despite the name arm_early_mmu_cache_flush not only flushes the
>* data cache, but also invalidates the instruction cache.
> --
> 2.30.2
>
>
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0|
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
Re: [PATCH] fs: ubifs: remove always-false check
On Thu, Aug 11, 2022 at 03:58:04PM +0200, Ahmad Fatoum wrote:
> GCC correctly warns that two bit wide compr_type can't
> exceed or be equal to UBIFS_COMPR_TYPES_CNT (== 4).
>
> Remove the check. The check is there in the kernel as well,
> but the warning is disabled there.
>
> Signed-off-by: Ahmad Fatoum
> ---
> fs/ubifs/super.c | 5 -
> 1 file changed, 5 deletions(-)
>
> diff --git a/fs/ubifs/super.c b/fs/ubifs/super.c
> index b48e21fae636..6a0074bd1a5c 100644
> --- a/fs/ubifs/super.c
> +++ b/fs/ubifs/super.c
> @@ -86,11 +86,6 @@ static int validate_inode(struct ubifs_info *c, const
> struct inode *inode)
> return 1;
> }
>
> - if (ui->compr_type >= UBIFS_COMPR_TYPES_CNT) {
> - ubifs_err(c, "unknown compression type %d", ui->compr_type);
> - return 2;
> - }
> -
Although Richard decided for the Kernel to keep the check I decided to
take this patch for barebox. The warning is annoying and doesn't tell us
anything. Once this is solved in the Kernel we'll get the solution with
the next UBIFS sync.
Sascha
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0|
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
Re: [PATCH] of: of_probe: create board's machine device at the earliest
On Mon, Sep 05, 2022 at 09:02:08AM +0200, Ahmad Fatoum wrote: > We currently create devices for matching reserved memory entries and > firmware before creating the machine device. In a deep probe system, the > machine driver would be probed directly at registration and as such > needs to be probed before other devices are created, so it can disable > other devices if needed. Move the machine device registration to the > top, so board drivers can disabled reserved memory entries and firmware > if they need to. > > Signed-off-by: Ahmad Fatoum > --- > drivers/of/base.c | 8 ++-- > 1 file changed, 6 insertions(+), 2 deletions(-) Applied, thanks Sascha > > diff --git a/drivers/of/base.c b/drivers/of/base.c > index 52e6a9294e11..6a51dd71793d 100644 > --- a/drivers/of/base.c > +++ b/drivers/of/base.c > @@ -2503,6 +2503,12 @@ int of_probe(void) > if(!root_node) > return -ENODEV; > > + /* > + * We do this first thing, so board drivers can patch the device > + * tree prior to device creation if needed. > + */ > + of_platform_device_create_root(root_node); > + > /* >* Handle certain compatibles explicitly, since we don't want to create >* platform_devices for every node in /reserved-memory with a > @@ -2515,8 +2521,6 @@ int of_probe(void) > if (node) > of_platform_populate(node, NULL, NULL); > > - of_platform_device_create_root(root_node); > - > of_platform_populate(root_node, of_default_bus_match_table, NULL); > > return 0; > -- > 2.30.2 > > > -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
Re: [PATCH] soc: imx: gpcv2: make available to all i.MX8M
On Mon, Sep 05, 2022 at 09:04:06AM +0200, Ahmad Fatoum wrote: > Now that the driver supports i.MX8M Mini, Nano and Plus, we should no > longer restrict it to just i.MX7 and i.MX8MQ. > > Signed-off-by: Ahmad Fatoum > --- > drivers/soc/imx/Kconfig | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) Applied, thanks Sascha > > diff --git a/drivers/soc/imx/Kconfig b/drivers/soc/imx/Kconfig > index eabe4a06d22c..624aff2ecae3 100644 > --- a/drivers/soc/imx/Kconfig > +++ b/drivers/soc/imx/Kconfig > @@ -3,9 +3,9 @@ menu "i.MX SoC drivers" > > config IMX_GPCV2_PM_DOMAINS > bool "i.MX GPCv2 PM domains" > - depends on ARCH_IMX7 || ARCH_IMX8MQ > + depends on ARCH_IMX7 || ARCH_IMX8M > select PM_GENERIC_DOMAINS > - default y if ARCH_IMX7 || ARCH_IMX8MQ > + default y if ARCH_IMX7 || ARCH_IMX8M > > config IMX8M_FEATCTRL > bool "i.MX8M feature controller" > -- > 2.30.2 > > > -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
Re: [PATCH] blspec: fix memory leak handling NFS URLs
On Mon, Sep 05, 2022 at 09:02:47AM +0200, Ahmad Fatoum wrote:
> parse_nfs_url() returns either an allocated string on success or an
> error pointer otherwise. blspec_bootentry_provider() will early
> exit if the path couldn't be resolved and thus not free() the string.
>
> Fix this memory leak. While at it, change parse_nfs_url() to return NULL
> on error. The error code is unused and just returning NULL, simplifies
> the code.
>
> Signed-off-by: Ahmad Fatoum
> ---
> common/blspec.c | 14 +++---
> 1 file changed, 7 insertions(+), 7 deletions(-)
Applied, thanks
Sascha
>
> diff --git a/common/blspec.c b/common/blspec.c
> index 9bb25ee72123..d391f690ad0c 100644
> --- a/common/blspec.c
> +++ b/common/blspec.c
> @@ -341,10 +341,10 @@ static char *parse_nfs_url(const char *url)
> int ret;
>
> if (!IS_ENABLED(CONFIG_FS_NFS))
> - return ERR_PTR(-ENOSYS);
> + return NULL;
>
> if (strncmp(url, "nfs://", 6))
> - return ERR_PTR(-EINVAL);
> + return NULL;
>
> url += 6;
>
> @@ -413,7 +413,7 @@ out:
> if (ret)
> free(mountpath);
>
> - return ret ? ERR_PTR(ret) : mountpath;
> + return ret ? NULL : mountpath;
> }
>
> /*
> @@ -824,12 +824,12 @@ static int blspec_bootentry_provider(struct bootentries
> *bootentries,
> if (*name == '/' || !strncmp(name, "nfs://", 6)) {
> char *nfspath = parse_nfs_url(name);
>
> - if (!IS_ERR(nfspath))
> + if (nfspath)
> name = nfspath;
>
> ret = stat(name, );
> if (ret)
> - return found;
> + goto out;
>
> if (S_ISDIR(s.st_mode))
> ret = blspec_scan_directory(bootentries, name);
> @@ -838,8 +838,8 @@ static int blspec_bootentry_provider(struct bootentries
> *bootentries,
> if (ret > 0)
> found += ret;
>
> - if (!IS_ERR(nfspath))
> - free(nfspath);
> +out:
> + free(nfspath);
> }
>
> return found;
> --
> 2.30.2
>
>
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0|
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
Re: [PATCH] test: self: provide selftest_is_running()
On Mon, Sep 05, 2022 at 09:01:25AM +0200, Ahmad Fatoum wrote:
> For debugging during self-test run, it can be useful to enable select
> logging only when the selftest is running. Provide a selftest_is_running()
> function that can be used to determine whether a test is running.
>
> Signed-off-by: Ahmad Fatoum
> ---
> commands/selftest.c | 2 +-
> include/bselftest.h | 5 +
> test/self/core.c| 26 +-
> 3 files changed, 31 insertions(+), 2 deletions(-)
Applied, thanks
Sascha
>
> diff --git a/commands/selftest.c b/commands/selftest.c
> index a10f1467fece..bb62575aa7bb 100644
> --- a/commands/selftest.c
> +++ b/commands/selftest.c
> @@ -24,7 +24,7 @@ static int run_selftest(const char *match, bool list)
> if (match && strcmp(test->name, match))
> continue;
>
> - err |= test->func();
> + err |= selftest_run(test);
> matches++;
> }
>
> diff --git a/include/bselftest.h b/include/bselftest.h
> index 21eeba0526ef..f03c803b6553 100644
> --- a/include/bselftest.h
> +++ b/include/bselftest.h
> @@ -15,6 +15,7 @@ struct selftest {
> const char *name;
> int (*func)(void);
> struct list_head list;
> + bool running;
> };
>
> static inline int selftest_report(unsigned int total_tests, unsigned int
> failed_tests,
> @@ -71,4 +72,8 @@ static inline void selftests_run(void)
> } \
> __bselftest_initcall(_func##_bselftest_register);
>
> +
> +int selftest_run(struct selftest *test);
> +bool selftest_is_running(struct selftest *test);
> +
> #endif
> diff --git a/test/self/core.c b/test/self/core.c
> index caa4c27f6def..40f5ee842d16 100644
> --- a/test/self/core.c
> +++ b/test/self/core.c
> @@ -7,6 +7,30 @@
>
> LIST_HEAD(selftests);
>
> +int selftest_run(struct selftest *test)
> +{
> + int err;
> +
> + test->running = true;
> + err = test->func();
> + test->running = false;
> +
> + return err;
> +}
> +
> +bool selftest_is_running(struct selftest *test)
> +{
> + if (test)
> + return test->running;
> +
> + list_for_each_entry(test, , list) {
> + if (selftest_is_running(test))
> + return true;
> + }
> +
> + return false;
> +}
> +
> void selftests_run(void)
> {
> struct selftest *test;
> @@ -15,7 +39,7 @@ void selftests_run(void)
> pr_notice("Configured tests will run now\n");
>
> list_for_each_entry(test, , list)
> - err |= test->func();
> + err |= selftest_run(test);
>
> if (err)
> pr_err("Some selftests failed\n");
> --
> 2.30.2
>
>
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0|
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
Re: [PATCH 0/7] Documentation misc fixes
On Mon, Sep 12, 2022 at 11:44:23AM +0300, Antony Pavlov wrote: > Antony Pavlov (7): > Documentation: OKUD Max9331: fix sphinx warning > Documentation: Altera SOCFPGA FPGA Manager: fix sphinx error > Documentation: Altera FPGAs in passive-serial mode: fix sphinx issues > Documentation: barebox DT aliases: fix sphinx issues > Documentation: barebox environment: fix list rendering > Documentation: Common leds properties: fix 'panic-indicator' list > entry rendering > Documentation: Voltage/Current Regulators: fix sphinx error > > Documentation/boards/mips/max9331.rst | 2 +- > Documentation/devicetree/bindings/barebox/aliases.rst | 3 ++- > .../devicetree/bindings/barebox/barebox,environment.rst | 1 + > .../devicetree/bindings/firmware/altr,passive-serial.rst| 1 + > .../devicetree/bindings/firmware/altr,socfpga-fpga-mgr.rst | 6 -- > Documentation/devicetree/bindings/leds/common.rst | 2 +- > Documentation/devicetree/bindings/regulator/regulator.rst | 1 + > 7 files changed, 11 insertions(+), 5 deletions(-) Applied, thanks Sascha -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
Re: [PATCH next] Documentation: filesystems: tftp: fix code blocks
On Mon, Sep 12, 2022 at 11:50:47AM +0300, Antony Pavlov wrote: > The patch fixes these sphinx errors: > > Documentation/filesystems/tftp.rst:44: ERROR: Error in "code-block" > directive: > maximum 1 argument(s) allowed, 3 supplied. > Documentation/filesystems/tftp.rst:53: ERROR: Error in "code-block" > directive: > maximum 1 argument(s) allowed, 4 supplied. > > Signed-off-by: Antony Pavlov > --- > Documentation/filesystems/tftp.rst | 2 ++ > 1 file changed, 2 insertions(+) Applied, thanks Sascha > > diff --git a/Documentation/filesystems/tftp.rst > b/Documentation/filesystems/tftp.rst > index 8929213d3c4..e88ad3dd4c8 100644 > --- a/Documentation/filesystems/tftp.rst > +++ b/Documentation/filesystems/tftp.rst > @@ -42,6 +42,7 @@ the opposite effect. Performance depends on: > 100 Mb/s) it had to be reduced to > > .. code-block:: console > + > global tftp.windowsize=26 > > for example. > @@ -51,6 +52,7 @@ the opposite effect. Performance depends on: > example, the `fec-imx` driver reserves place for > > .. code-block:: c > + > #define FEC_RBD_NUM 64 > > packets before they are dropped > -- > 2.37.2 > > -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
Re: [PATCH v2] of: implement of_prepend_property
On Mon, Sep 12, 2022 at 05:54:36PM +0200, Ahmad Fatoum wrote:
> Like of_append_property for adding at the end of properties, implement
> of_prepend_property for placing data into the front.
>
> This is especially useful to fixup most-specific compatibles into
> existing nodes.
>
> Signed-off-by: Ahmad Fatoum
> ---
> v1 -> v2:
> - simplify with malloc/memcpy instead of realloc/memmove (Sascha)
> ---
> drivers/of/base.c | 30 ++
> include/of.h| 8
> test/self/of_manipulation.c | 2 +-
> 3 files changed, 39 insertions(+), 1 deletion(-)
Applied, thanks
Sascha
>
> diff --git a/drivers/of/base.c b/drivers/of/base.c
> index 212b226eb55c..ea2a88764bb2 100644
> --- a/drivers/of/base.c
> +++ b/drivers/of/base.c
> @@ -2378,6 +2378,36 @@ int of_append_property(struct device_node *np, const
> char *name, const void *val
> return 0;
> }
>
> +int of_prepend_property(struct device_node *np, const char *name, const void
> *val, int len)
> +{
> + struct property *pp;
> + const void *oldval;
> + void *buf;
> + int oldlen;
> +
> + pp = of_find_property(np, name, );
> + if (!pp) {
> + of_new_property(np, name, val, len);
> + return 0;
> + }
> +
> + oldval = of_property_get_value(pp);
> +
> + buf = malloc(len + oldlen);
> + if (!buf)
> + return -ENOMEM;
> +
> + memcpy(buf, val, len);
> + memcpy(buf + len, oldval, oldlen);
> +
> + free(pp->value);
> + pp->value = buf;
> + pp->length = len + oldlen;
> + pp->value_const = NULL;
> +
> + return 0;
> +}
> +
> int of_property_sprintf(struct device_node *np,
> const char *propname, const char *fmt, ...)
> {
> diff --git a/include/of.h b/include/of.h
> index 153e75d3e51d..052d5fcad84c 100644
> --- a/include/of.h
> +++ b/include/of.h
> @@ -135,6 +135,8 @@ extern int of_set_property(struct device_node *node,
> const char *p,
> const void *val, int len, int create);
> extern int of_append_property(struct device_node *np, const char *p,
> const void *val, int len);
> +extern int of_prepend_property(struct device_node *np, const char *name,
> +const void *val, int len);
> extern struct property *of_new_property(struct device_node *node,
> const char *name, const void *data, int len);
> extern struct property *of_new_property_const(struct device_node *node,
> @@ -536,6 +538,12 @@ static inline int of_append_property(struct device_node
> *np, const char *p,
> return -ENOSYS;
> }
>
> +static inline int of_prepend_property(struct device_node *np, const char
> *name,
> + const void *val, int len)
> +{
> + return -ENOSYS;
> +}
> +
> static inline struct property *of_new_property(struct device_node *node,
> const char *name, const void *data, int len)
> {
> diff --git a/test/self/of_manipulation.c b/test/self/of_manipulation.c
> index 7e30a60ca687..f7f95fa269af 100644
> --- a/test/self/of_manipulation.c
> +++ b/test/self/of_manipulation.c
> @@ -103,9 +103,9 @@ static void test_of_property_strings(struct device_node
> *root)
>
> of_append_property(np4, "property-single", "ayy", 4);
>
> - of_append_property(np4, "property-multi", "ayy", 4);
> of_append_property(np4, "property-multi", "bee", 4);
> of_append_property(np4, "property-multi", "sea", 4);
> + of_prepend_property(np4, "property-multi", "ayy", 4);
>
> assert_equal(np3, np4);
> }
> --
> 2.30.2
>
>
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0|
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
