[PATCH v2 4/5] ARM: i.MX8MP: don't reparent GIC from BootROM default
On i.MX8MP, GIC can run at up to 400 MHz in nominal drive mode and up
to 500 MHz in overdrive mode. We currently configure unconditionally
to 100 MHz on i.MX8MP.
The BootROM default is running it on 400 MHz, which works well for us on
the i.MX8MP, so skip the GIC configuration on the i.MX8MP.
Signed-off-by: Ahmad Fatoum
---
v1 -> v2:
User if (!8mp) condition for clarity and move comment into it (Lucas)
---
arch/arm/mach-imx/imx8m.c | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-imx/imx8m.c b/arch/arm/mach-imx/imx8m.c
index 56330cef500c..6286ab7344bc 100644
--- a/arch/arm/mach-imx/imx8m.c
+++ b/arch/arm/mach-imx/imx8m.c
@@ -100,12 +100,15 @@ static void __imx8m_early_clock_init(int cpu_type)
INTPLL_DIV20_CLKE_MASK;
writel(val, ana + IMX8MM_CCM_ANALOG_SYS_PLL2_GEN_CTRL);
- /* config GIC to sys_pll2_100m */
- imx8m_ccgr_clock_disable(IMX8M_CCM_CCGR_GIC);
- imx8m_clock_set_target_val(IMX8M_GIC_CLK_ROOT,
- IMX8M_CCM_TARGET_ROOTn_ENABLE |
- IMX8M_CCM_TARGET_ROOTn_MUX(3));
- imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_GIC);
+ if (cpu_type != IMX_CPU_IMX8MP) {
+ /* 8MP ROM already set GIC to 400Mhz, system_pll1_800m with div
= 2 */
+ /* For everything else, config GIC to sys_pll2_100m */
+ imx8m_ccgr_clock_disable(IMX8M_CCM_CCGR_GIC);
+ imx8m_clock_set_target_val(IMX8M_GIC_CLK_ROOT,
+ IMX8M_CCM_TARGET_ROOTn_ENABLE |
+ IMX8M_CCM_TARGET_ROOTn_MUX(3));
+ imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_GIC);
+ }
if (cpu_type == IMX_CPU_IMX8MN || cpu_type == IMX_CPU_IMX8MP)
pll3_freq = 6UL;
--
2.39.2
[PATCH v2 3/5] ARM: i.MX8MP: configure PLL3 as noc_io parent
noc_io is clocked at 24MHz when exiting bootrom, which is a far cry
below the 600MHz it can run at in nominal drive mode.
This doesn't bother us much, because we reconfigure it to 800MHz later
on via assigned-clock-properties, but that frequency is only suitable
when running in overdrive mode (VDD_SOC = 950 mV).
Make switching to nominal mode easier by initializing NOC_IO to
the highest nominal frequency.
Signed-off-by: Ahmad Fatoum
---
v1 -> v2:
- no change
---
arch/arm/mach-imx/imx8m.c | 7 +++
include/mach/imx/imx8m-ccm-regs.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/arch/arm/mach-imx/imx8m.c b/arch/arm/mach-imx/imx8m.c
index 211b4f782199..56330cef500c 100644
--- a/arch/arm/mach-imx/imx8m.c
+++ b/arch/arm/mach-imx/imx8m.c
@@ -116,6 +116,13 @@ static void __imx8m_early_clock_init(int cpu_type)
clk_pll1416x_early_set_rate(ana + IMX8MM_CCM_ANALOG_SYS_PLL3_GEN_CTRL,
pll3_freq, 2500UL);
+ if (cpu_type == IMX_CPU_IMX8MP) {
+ /* 8MP ROM already set NOC to 800Mhz, only need to configure
NOC_IO clk to 600Mhz */
+ imx8m_clock_set_target_val(IMX8M_NOC_IO_CLK_ROOT,
+ IMX8M_CCM_TARGET_ROOTn_ENABLE |
+ IMX8M_CCM_TARGET_ROOTn_MUX(2));
+ }
+
clrsetbits_le32(ccm + IMX8M_CCM_TARGET_ROOTn(IMX8M_ARM_A53_CLK_ROOT),
IMX8M_CCM_TARGET_ROOTn_MUX(7),
IMX8M_CCM_TARGET_ROOTn_MUX(2));
diff --git a/include/mach/imx/imx8m-ccm-regs.h
b/include/mach/imx/imx8m-ccm-regs.h
index 29186eb8a7bc..035cd13ed694 100644
--- a/include/mach/imx/imx8m-ccm-regs.h
+++ b/include/mach/imx/imx8m-ccm-regs.h
@@ -22,6 +22,7 @@
* Applications Processor Reference Manual
*/
#define IMX8M_ARM_A53_CLK_ROOT 0
+#define IMX8M_NOC_IO_CLK_ROOT 27
#define IMX8M_DRAM_SEL_CFG 48
#define IMX8M_DRAM_ALT_CLK_ROOT64
#define IMX8M_DRAM_APB_CLK_ROOT65
--
2.39.2
[PATCH v2 2/5] ARM: i.MX8MP: configure PLL3 as 600MHz
When running the i.MX8MP in nominal drive mode, a number of clocks are validated only up to 600MHz: m7_core, audio_axi, vpu_bus, gpu_axi, noc_io, vpu_g1. Let's configure PLL3 as 600MHz to make it a suitable parent for these clocks. The upstream Linux DTs don't yet use PLL3, but this aligns us with U-Boot's boot-time configuration. While at it, we also add a comment about how pll1 and pll2 are configured. Signed-off-by: Ahmad Fatoum --- v1 -> v2: - no change --- arch/arm/mach-imx/imx8m.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/imx8m.c b/arch/arm/mach-imx/imx8m.c index d798c52c6a6e..211b4f782199 100644 --- a/arch/arm/mach-imx/imx8m.c +++ b/arch/arm/mach-imx/imx8m.c @@ -77,6 +77,13 @@ static void __imx8m_early_clock_init(int cpu_type) imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_DDR1); + /* +* The gate is not exported to clk tree, so configure them here. +* According to ANAMIX SPEC +* sys pll1 fixed at 800MHz +* sys pll2 fixed at 1GHz +* Here we only enable the outputs. +*/ val = readl(ana + IMX8MM_CCM_ANALOG_SYS_PLL1_GEN_CTRL); val |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK | INTPLL_DIV3_CLKE_MASK | INTPLL_DIV4_CLKE_MASK | @@ -100,7 +107,7 @@ static void __imx8m_early_clock_init(int cpu_type) IMX8M_CCM_TARGET_ROOTn_MUX(3)); imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_GIC); - if (cpu_type == IMX_CPU_IMX8MN) + if (cpu_type == IMX_CPU_IMX8MN || cpu_type == IMX_CPU_IMX8MP) pll3_freq = 6UL; else pll3_freq = 75000UL; -- 2.39.2
[PATCH v2 1/5] ARM: i.MX8M: pass cpu_type parameter to __imx8m_early_clock_init
We do some limited clock tree configuration in PBL and do the proper
configuration later in the barebox proper drivers.
The clock tree of the i.MX8MP is a bit different though than that of the
i.MX8MM and i.MX8MN and we'll want to add some more SoC-specific
configuration in the follow-up commit. Prepare for that by giving the
function a cpu_type parameter that can be checked.
Note that we can't use imx_cpu_type here, because it has not been set
yet.
No functional change intended.
Signed-off-by: Ahmad Fatoum
---
v1 -> v2:
- no change
---
arch/arm/mach-imx/imx8m.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-imx/imx8m.c b/arch/arm/mach-imx/imx8m.c
index 52e42ee9ef63..d798c52c6a6e 100644
--- a/arch/arm/mach-imx/imx8m.c
+++ b/arch/arm/mach-imx/imx8m.c
@@ -56,8 +56,9 @@ void imx8m_ccgr_clock_disable(int index)
#define IMX8MM_CCM_ANALOG_SYS_PLL2_GEN_CTRL0x104
#define IMX8MM_CCM_ANALOG_SYS_PLL3_GEN_CTRL0x114
-static void __imx8m_early_clock_init(unsigned long pll3_freq) /* and later */
+static void __imx8m_early_clock_init(int cpu_type)
{
+ unsigned long pll3_freq;
void __iomem *ana = IOMEM(MX8M_ANATOP_BASE_ADDR);
void __iomem *ccm = IOMEM(MX8M_CCM_BASE_ADDR);
u32 val;
@@ -99,6 +100,11 @@ static void __imx8m_early_clock_init(unsigned long
pll3_freq) /* and later */
IMX8M_CCM_TARGET_ROOTn_MUX(3));
imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_GIC);
+ if (cpu_type == IMX_CPU_IMX8MN)
+ pll3_freq = 6UL;
+ else
+ pll3_freq = 75000UL;
+
/* Configure SYS_PLL3 */
clk_pll1416x_early_set_rate(ana + IMX8MM_CCM_ANALOG_SYS_PLL3_GEN_CTRL,
pll3_freq, 2500UL);
@@ -126,17 +132,17 @@ static void __imx8m_early_clock_init(unsigned long
pll3_freq) /* and later */
void imx8mm_early_clock_init(void)
{
- __imx8m_early_clock_init(75000UL);
+ __imx8m_early_clock_init(IMX_CPU_IMX8MM);
}
void imx8mn_early_clock_init(void)
{
- __imx8m_early_clock_init(6UL);
+ __imx8m_early_clock_init(IMX_CPU_IMX8MN);
}
void imx8mp_early_clock_init(void)
{
- __imx8m_early_clock_init(75000UL);
+ __imx8m_early_clock_init(IMX_CPU_IMX8MP);
}
--
2.39.2
[PATCH v2 0/5] ARM: i.MX8MP: add nominal drive mode support
Unlike the i.MX8MM and i.MX8MN SoCs added earlier, the early setup code and device tree for the i.MX8MP configures some clocks at frequencies that are only validated for overdrive mode, i.e. when VDD_SOC is 950 mV. Boards may want to run their SoC at the lower voltage of 850 mV though to reduce heat generation and power usage. For this to work, clock rates need to adhere to the limits of the nominal drive mode. This needs to be done across both barebox and Linux. This series handles the barebox side and a separate series will follow for the kernel. Ahmad Fatoum (5): ARM: i.MX8M: pass cpu_type parameter to __imx8m_early_clock_init ARM: i.MX8MP: configure PLL3 as 600MHz ARM: i.MX8MP: configure PLL3 as noc_io parent ARM: i.MX8MP: don't reparent GIC from BootROM default ARM: dts: i.MX8MP: Add optional nominal drive mode DTSI arch/arm/dts/imx8mp-nominal.dtsi | 49 +++ arch/arm/mach-imx/imx8m.c | 43 --- include/mach/imx/imx8m-ccm-regs.h | 1 + 3 files changed, 83 insertions(+), 10 deletions(-) create mode 100644 arch/arm/dts/imx8mp-nominal.dtsi -- 2.39.2
[PATCH v2 5/5] ARM: dts: i.MX8MP: Add optional nominal drive mode DTSI
Unlike the i.MX8MM and i.MX8MN SoCs added earlier, the device tree for
the i.MX8MP configures some clocks at frequencies that are only
validated for overdrive mode, i.e. when VDD_SOC is 950 mV.
Boards may want to run their SoC at the lower voltage of 850 mV though
to reduce heat generation and power usage. For this to work, clock rates
need to adhere to the limits of the nominal drive mode.
Add an optional DTSI file which can be included by various boards to run
in this mode.
Signed-off-by: Ahmad Fatoum
---
v1 -> v2:
- use PLL3 as GPU parent instead of GPU PLL (Lucas)
---
arch/arm/dts/imx8mp-nominal.dtsi | 49
1 file changed, 49 insertions(+)
create mode 100644 arch/arm/dts/imx8mp-nominal.dtsi
diff --git a/arch/arm/dts/imx8mp-nominal.dtsi b/arch/arm/dts/imx8mp-nominal.dtsi
new file mode 100644
index ..d675d1e5486e
--- /dev/null
+++ b/arch/arm/dts/imx8mp-nominal.dtsi
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+&clk {
+ assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
+ <&clk IMX8MP_CLK_A53_CORE>,
+ <&clk IMX8MP_SYS_PLL3>,
+ <&clk IMX8MP_CLK_NOC>,
+ <&clk IMX8MP_CLK_NOC_IO>,
+ <&clk IMX8MP_CLK_GIC>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
+<&clk IMX8MP_ARM_PLL_OUT>,
+<0>,
+<&clk IMX8MP_SYS_PLL1_800M>,
+<&clk IMX8MP_SYS_PLL3_OUT>,
+<&clk IMX8MP_SYS_PLL1_800M>;
+ assigned-clock-rates = <0>, <0>,
+ <6>,
+ <8>,
+ <6>,
+ <4>;
+};
+
+&pgc_hsiomix {
+ assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
+ assigned-clock-rates = <4>;
+};
+
+&pgc_gpumix {
+ assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>,
+ <&clk IMX8MP_CLK_GPU_AHB>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL3_OUT>,
+<&clk IMX8MP_SYS_PLL3_OUT>;
+ assigned-clock-rates = <6>, <3>;
+};
+
+&media_blk_ctrl {
+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
+ <&clk IMX8MP_CLK_MEDIA_APB>,
+ <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>,
+ <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>,
+ <&clk IMX8MP_VIDEO_PLL1>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
+<&clk IMX8MP_SYS_PLL1_800M>,
+<&clk IMX8MP_VIDEO_PLL1_OUT>,
+<&clk IMX8MP_VIDEO_PLL1_OUT>;
+ assigned-clock-rates = <4>, <2>,
+ <0>, <0>, <103950>;
+};
--
2.39.2
[PATCH 1/3] firmware: support optional firmware in barebox proper
For firmware used in the prebootloader, missing firmware is handled
according to the CONFIG_MISSING_FIRMWARE_ERROR symbol:
- If set, barebox will throw an error when assmebling the final image
with a list of missing firmware
- If unset, a warning will be printed for each barebox image that
can't be built due to missing firmware and all
This replaced the previous behavior of make throwing an error due to a
missing dependency, which broke the ability to use a single config for
multiple platforms, where only some have missing firmware.
Nothing of the sort was done for firmware in barebox proper. We only
have that on Layerscape for PPA (EL3 Secure Monitor) and FMan (NIC).
With the addition of Layerscape to multi_v8_defconfig, building that
config now also throws aforementioned make errors.
This is now also resolved depending on CONFIG_MISSING_FIRMWARE_ERROR:
- If set, an immediate make error occurs as before as we can't
pinpoint which of the enabled barebox images will at runtime
instantiate the driver that requires the firmware.
- If unset, we continue build as normal and the size of the firmware
as determined at runtime will be zero bytes. Code in barebox
proper is expected to check for that and report an error.
Fixes: 9922f78ec58c3a7b8d28427f470edc469627c9cd.
Signed-off-by: Ahmad Fatoum
---
firmware/Makefile | 24 ++--
1 file changed, 18 insertions(+), 6 deletions(-)
diff --git a/firmware/Makefile b/firmware/Makefile
index 83ce77f510ba..d5e4cee8594b 100644
--- a/firmware/Makefile
+++ b/firmware/Makefile
@@ -61,7 +61,7 @@ filechk_fwbin = { \
echo "_fw_$(FWSTR)_start:" ;\
echo "\#if $(FWNAME_EXISTS)";\
echo ".incbin \"$(fwdir)/$(FWNAME)\"" ;\
- echo "\#else" ;\
+ echo "\#elif defined(__PBL__)" ;\
echo "ASM_PTR _fwname_$(FWSTR)" ;\
echo "\#endif" ;\
echo ".global _fw_$(FWSTR)_end" ;\
@@ -102,13 +102,25 @@ $(obj)/%.sum: FORCE
clean-files += *.sha.bin *.sum
-# The .o files depend on the binaries directly; the .S files don't.
-$(patsubst %.gen.o,$(obj)/%.gen.o, $(obj-pbl-y)): $(obj)/%.gen.o: $(fwdir)/%
+# This dependency is used if missing firmware should fail the build immediately
+fwdep-required-y = $(fwdir)/%
+# This dependency expands to nothing if the file doesn't exist. This allows
+# delaying the firmware check:
+#
+# - to final assembly of the PBL image for pbl-firmware
+# - to runtime for firmware in barebox proper
+#
+# This way, we allow users to build defconfigs with multiple images without
requiring
+# them to install all firmware for all platforms if only few are of interest.
+fwdep-required-n = $$(wildcard $(fwdir)/%)
-# The same for pbl:
.SECONDEXPANSION:
-$(patsubst %.gen.o,$(obj)/%.gen.pbl.o, $(obj-pbl-y) $(pbl-y)):
$(obj)/%.gen.pbl.o: $$(wildcard $(fwdir)/%)
-$(patsubst %.extgen.o,$(obj)/%.extgen.pbl.o, $(pbl-fwext-y)):
$(obj)/%.extgen.pbl.o: $$(wildcard $(fwdir)/%)
+# The .o files depend on the binaries directly if available; the .S files
don't.
+$(patsubst %.gen.o,$(obj)/%.gen.pbl.o, $(obj-pbl-y) $(pbl-y)):
$(obj)/%.gen.pbl.o: $(fwdep-required-n)
+$(patsubst %.extgen.o,$(obj)/%.extgen.pbl.o, $(pbl-fwext-y)):
$(obj)/%.extgen.pbl.o: $(fwdep-required-n)
+# For barebox proper, firmware existance is either checked here
+# or in driver code by checking whether size != 0
+$(patsubst %.gen.o,$(obj)/%.gen.o, $(obj-pbl-y)): $(obj)/%.gen.o:
$(fwdep-required-$(CONFIG_MISSING_FIRMWARE_ERROR))
pbl-y += $(pbl-fwext-y)
--
2.39.2
[PATCH 3/3] ci: test: remove generation of dummy firmware
Generating dummy firmware for images that are not only built, but also
runtime tested doesn't make sense. Either the firmware is required for
proper operation (which isn't the case for any platform we currently
test) or it isn't, in which case enabling it could hide errors during
build.
The added benefit here is that we now test e.g. multi_v8_defconfig the
same way that a user with a new checkout would: Using the defconfig and
without any generated firmware.
Signed-off-by: Ahmad Fatoum
---
.github/workflows/test-labgrid-pytest.yml | 2 --
1 file changed, 2 deletions(-)
diff --git a/.github/workflows/test-labgrid-pytest.yml
b/.github/workflows/test-labgrid-pytest.yml
index 514122ebf886..6eb38cc03e6b 100644
--- a/.github/workflows/test-labgrid-pytest.yml
+++ b/.github/workflows/test-labgrid-pytest.yml
@@ -55,8 +55,6 @@ jobs:
run: |
export ARCH=${{matrix.arch}}
-./test/generate-dummy-fw.sh
-
./MAKEALL -O build-${{matrix.arch}} -k
test/kconfig/enable_self_test.kconf \
-k test/kconfig/disable_target_tools.kconf
${{matrix.defconfig}}
--
2.39.2
[PATCH 2/3] ARM: layerscape: add helpful runtime warning when firmware is missing
Firmware compiled into barebox PBL is rarely optional, so even if
CONFIG_MISSING_FIRMWARE_ERROR is disabled, barebox will not generate
images with missing PBL firmware.
We can relax this for firmware compiled into barebox proper though: If
the user disables CONFIG_MISSING_FIRMWARE_ERROR, just have the driver
fail at runtime as not to break other boards in the same build that
don't require the firmware.
Missing barebox proper firmware will be detectable as a 0-byte firmware
blob in the follow-up commit, so prepare for that by printing an
informative error message.
Signed-off-by: Ahmad Fatoum
---
arch/arm/mach-layerscape/ppa.c | 4
drivers/net/fsl-fman.c | 4
2 files changed, 8 insertions(+)
diff --git a/arch/arm/mach-layerscape/ppa.c b/arch/arm/mach-layerscape/ppa.c
index 21efaae3ab32..99b76b4c30d7 100644
--- a/arch/arm/mach-layerscape/ppa.c
+++ b/arch/arm/mach-layerscape/ppa.c
@@ -121,6 +121,10 @@ int ls1046a_ppa_init(resource_size_t ppa_start,
resource_size_t ppa_size)
}
get_builtin_firmware(ppa_ls1046a_bin, &ppa_fw, &ppa_fw_size);
+ if (!ppa_fw_size) {
+ pr_err("PPA Firmware was not included in build\n");
+ return -ENOSYS;
+ }
if (el == 3) {
unsigned long cr;
diff --git a/drivers/net/fsl-fman.c b/drivers/net/fsl-fman.c
index 5528e950..98af3dafb44a 100644
--- a/drivers/net/fsl-fman.c
+++ b/drivers/net/fsl-fman.c
@@ -213,6 +213,10 @@ static int fman_upload_firmware(struct device *dev, struct
fm_imem *fm_imem)
const struct qe_firmware *firmware;
get_builtin_firmware(fsl_fman_ucode_ls1046_r1_0_106_4_18_bin,
&firmware, &size);
+ if (!size) {
+ dev_err(dev, "FMan Firmware was not included in build\n");
+ return -ENOSYS;
+ }
ret = qe_validate_firmware(firmware, size);
if (ret)
--
2.39.2
[PATCH] dma: of_fixups: add fallbacks if /soc doesn't exist
The fixup was written for Layerscape LS1046A. Enabling it on i.MX8MP
throws an initcall error, because the SoC node is called /soc@0.
Improve the situation by falling back to either /soc@0 or just plain /.
Signed-off-by: Ahmad Fatoum
---
drivers/dma/of_fixups.c | 33 ++---
1 file changed, 18 insertions(+), 15 deletions(-)
diff --git a/drivers/dma/of_fixups.c b/drivers/dma/of_fixups.c
index 668313bbfb57..084ab94cc71c 100644
--- a/drivers/dma/of_fixups.c
+++ b/drivers/dma/of_fixups.c
@@ -6,15 +6,22 @@
static int of_dma_coherent_fixup(struct device_node *root, void *data)
{
- struct device_node *soc;
- enum dev_dma_coherence coherency = (enum
dev_dma_coherence)(uintptr_t)data;
+ struct device_node *soc_bb = data, *soc_kernel;
+ enum dev_dma_coherence coherency;
- soc = of_find_node_by_path_from(root, "/soc");
- if (!soc)
+ if (of_property_read_bool(soc_bb, "dma-coherent"))
+ coherency = DEV_DMA_COHERENT;
+ else if (of_property_read_bool(soc_bb, "dma-noncoherent"))
+ coherency = DEV_DMA_NON_COHERENT;
+ else
+ coherency = DEV_DMA_COHERENCE_DEFAULT;
+
+ soc_kernel = of_find_node_by_path_from(root, soc_bb->full_name);
+ if (!soc_kernel)
return -ENOENT;
- of_property_write_bool(soc, "dma-noncoherent", coherency ==
DEV_DMA_NON_COHERENT);
- of_property_write_bool(soc, "dma-coherent", coherency ==
DEV_DMA_COHERENT);
+ of_property_write_bool(soc_kernel, "dma-noncoherent", coherency ==
DEV_DMA_NON_COHERENT);
+ of_property_write_bool(soc_kernel, "dma-coherent", coherency ==
DEV_DMA_COHERENT);
return 0;
}
@@ -22,19 +29,15 @@ static int of_dma_coherent_fixup(struct device_node *root,
void *data)
static int of_dma_coherent_fixup_register(void)
{
struct device_node *soc;
- enum dev_dma_coherence soc_dma_coherency;
soc = of_find_node_by_path("/soc");
+ if (!soc)
+ soc = of_find_node_by_path("/soc@0");
+ if (!soc)
+ soc = of_find_node_by_path("/");
if (!soc)
return -ENOENT;
- if (of_property_read_bool(soc, "dma-coherent"))
- soc_dma_coherency = DEV_DMA_COHERENT;
- else if (of_property_read_bool(soc, "dma-noncoherent"))
- soc_dma_coherency = DEV_DMA_NON_COHERENT;
- else
- soc_dma_coherency = DEV_DMA_COHERENCE_DEFAULT;
-
- return of_register_fixup(of_dma_coherent_fixup, (void
*)(uintptr_t)soc_dma_coherency);
+ return of_register_fixup(of_dma_coherent_fixup, soc);
}
coredevice_initcall(of_dma_coherent_fixup_register);
--
2.39.2
[PATCH] mtd: nand: mxc_nand: clear NAND_BBT_CREATE flag
On i.MX NAND the factory bad block markers are not at the place the NAND
core expects them to be, so the core also can't properly generate a bad
block table. Clear the NAND_BBT_CREATE flag to prevent the core from
doing so. This preserves the behaviour we had previously with the
barebox driver which was lost when we replaced it with the Kernel
driver.
Signed-off-by: Sascha Hauer
---
drivers/mtd/nand/raw/mxc_nand.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/raw/mxc_nand.c b/drivers/mtd/nand/raw/mxc_nand.c
index 2774b6bb4f..c6533b20fc 100644
--- a/drivers/mtd/nand/raw/mxc_nand.c
+++ b/drivers/mtd/nand/raw/mxc_nand.c
@@ -1167,7 +1167,7 @@ static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
static struct nand_bbt_descr bbt_main_descr = {
- .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
+ .options = NAND_BBT_LASTBLOCK | NAND_BBT_WRITE
| NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
.offs = 0,
.len = 4,
@@ -1177,7 +1177,7 @@ static struct nand_bbt_descr bbt_main_descr = {
};
static struct nand_bbt_descr bbt_mirror_descr = {
- .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
+ .options = NAND_BBT_LASTBLOCK | NAND_BBT_WRITE
| NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
.offs = 0,
.len = 4,
--
2.39.2
[PATCH] mfd: pca9450: don't warn if PCA9450_PWRON_STAT is 0
The register is zeroed on read, so network booting always prints the warning that the reset reason is unknown. Skip the warning in this case. Signed-off-by: Ahmad Fatoum --- drivers/mfd/pca9450.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mfd/pca9450.c b/drivers/mfd/pca9450.c index be357c10239f..89eca9f890e3 100644 --- a/drivers/mfd/pca9450.c +++ b/drivers/mfd/pca9450.c @@ -53,6 +53,8 @@ static int pca9450_get_reset_source(struct device *dev, struct regmap *map) break; default: dev_warn(dev, "Unknown reset reason: 0x%02x\n", reg); + fallthrough; + case 0: type = RESET_UKWN; } -- 2.39.2
[PATCH] arm: rockchip: mecsbc: drop duplicate reserved-memory node
The exact same node is duplicated. Drop one instance.
Signed-off-by: Ahmad Fatoum
---
arch/arm/dts/rk3568-mecsbc.dts | 11 ---
1 file changed, 11 deletions(-)
diff --git a/arch/arm/dts/rk3568-mecsbc.dts b/arch/arm/dts/rk3568-mecsbc.dts
index 05893b8f724a..c9bab7f36e2f 100644
--- a/arch/arm/dts/rk3568-mecsbc.dts
+++ b/arch/arm/dts/rk3568-mecsbc.dts
@@ -91,31 +91,20 @@ data_partitions {
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/* Address will be determined by the bootloader */
ramoops {
compatible = "ramoops";
};
};
-
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- /* Address will be determined by the bootloader */
- ramoops {
- compatible = "ramoops";
- };
- };
};
&sdhci {
no-sd;
partitions {
compatible = "fixed-partitions";
#address-cells = <2>;
#size-cells = <2>;
--
2.39.2
[PATCH master] ARM: i.MX9: tqma93xx: handle unknown form factors
GCC warns that fdt may be uninitialized. Fix that by treating unknown
variants as the CA variant. CA was chosen for no particular reason.
Signed-off-by: Ahmad Fatoum
---
arch/arm/boards/tqma93xx/lowlevel.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boards/tqma93xx/lowlevel.c
b/arch/arm/boards/tqma93xx/lowlevel.c
index 8d89ee530ff8..66991fc6b03b 100644
--- a/arch/arm/boards/tqma93xx/lowlevel.c
+++ b/arch/arm/boards/tqma93xx/lowlevel.c
@@ -89,6 +89,9 @@ static noinline void tqma93xx_continue(void)
case VARD_FORMFACTOR_TYPE_LGA:
fdt = __dtb_z_imx93_tqma9352_mba93xxla_start;
break;
+ default:
+ pr_warn("Unknown formfactor: 0%x. Assuming connector\n",
formfactor);
+ fallthrough;
case VARD_FORMFACTOR_TYPE_CONNECTOR:
fdt = __dtb_z_imx93_tqma9352_mba93xxca_start;
break;
--
2.39.2
[PATCH master] pblimage: suppress stdout output
Any output, stdout or stderr, during normal operation looks jarring when
interleaved with Kbuild, so utilities should just be always silent on
stdout and print errors to stderr if they occur.
The pblimage tool violated this and had a stdout debug print left-over and
printed part of an error message to stdout instead of stderr. Fix both
instances.
Signed-off-by: Ahmad Fatoum
---
scripts/pblimage.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/scripts/pblimage.c b/scripts/pblimage.c
index ef09b0f96084..610d93b36800 100644
--- a/scripts/pblimage.c
+++ b/scripts/pblimage.c
@@ -258,7 +258,6 @@ static void pbl_load_image(void)
read(in_fd, mem_buf + 0x1000, image_size);
pbl_size = 0x1000 + image_size;
- printf("%s imagesize: %d\n", rcwfile, image_size);
} else {
exit(EXIT_FAILURE);
}
@@ -419,7 +418,7 @@ int main(int argc, char *argv[])
if (soc_type == SOC_TYPE_INVALID) {
fprintf(stderr, "Invalid CPU type %s. Valid types are:\n",
cputypestr);
for (i = 0; i < ARRAY_SIZE(socs); i++)
- printf(" %s\n", socs[i].name);
+ fprintf(stderr, " %s\n", socs[i].name);
exit(EXIT_FAILURE);
}
--
2.39.2
Re: [PATCH] ddr: imx8m: fix broken sharing of DRAM timing with TF-A for DFS
On Mon, 29 Apr 2024 16:16:10 +0200, Ahmad Fatoum wrote: > To facilitate dynamic frequency scaling, barebox will place the DRAM > parameters it has configured into a well-known location in DRAM > for consumption by TF-A. > > This means that we need to be very picky about the struct layout for the > data we write there to maintain ABI-compatibility. Unfortunately, NXP > chose for the i.MX9 to add two fields into the middle, when it would > have been possible to cleanly embed the i.MX8 DRAM timings in the > i.MX9 DRAM timing struct. This is done now, so we need to arrange > ourselves with it and ensure that the i.MX8M DRAM timings we share with > TF-A don't have glimpses of the i.MX9 future. > > [...] Applied, thanks! [1/1] ddr: imx8m: fix broken sharing of DRAM timing with TF-A for DFS https://git.pengutronix.de/cgit/barebox/commit/?id=ea580697c269 (link may not be stable) Best regards, -- Sascha Hauer
Re: [PATCH] treewide: use runtime_address() where possible
On Tue, 30 Apr 2024 07:56:34 +0200, Sascha Hauer wrote: > We now have runtime_address() to access a linker variable when the > binary is not yet relocated to the correct address. It provides a > safer API, so use this one where possible instead of using previous > way of adding get_runtime_offset() manually. > > Applied, thanks! [1/1] treewide: use runtime_address() where possible https://git.pengutronix.de/cgit/barebox/commit/?id=b2ce148e7016 (link may not be stable) Best regards, -- Sascha Hauer
Re: [PATCH] ARM: remove MLO target
On Tue, 30 Apr 2024 07:53:48 +0200, Sascha Hauer wrote: > All am335x boards use multi image support, so the MLO target is unused. > Remove it. > > Applied, thanks! [1/1] ARM: remove MLO target https://git.pengutronix.de/cgit/barebox/commit/?id=3bdf86c81919 (link may not be stable) Best regards, -- Sascha Hauer
Re: [PATCH 3/3] mtd: mxc-nand: Only automatically create BBT if NAND seems to be pristine
On Tue, Apr 30, 2024 at 11:44:54AM +0200, Uwe Kleine-König wrote:
> Automatically creating a BBT is the right thing to do if the NAND is
> factory new. However when migrating from a barebox older than commit
> v2020.03.0~28^2~1 ("mtd: nand-imx: Create BBT automatically when
> necessary") on a used machine, this automatism is really bad because it
> most likely marks the blocks containing the barebox image (and possibly
> more) as bad. On such a system the vendor BBMs are gone, but it was
> operated without that information before, so continuing to do so is a
> sane option.
>
> Add a light check for the NAND to be really pristine: If the first block
> looks like containing a barebox image or a UBI refuse to create a BBT.
>
> Signed-off-by: Uwe Kleine-König
> ---
> drivers/mtd/nand/raw/mxc_nand.c | 58 ++---
> 1 file changed, 31 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/mtd/nand/raw/mxc_nand.c b/drivers/mtd/nand/raw/mxc_nand.c
> index a72275480144..fd5ae447a198 100644
> --- a/drivers/mtd/nand/raw/mxc_nand.c
> +++ b/drivers/mtd/nand/raw/mxc_nand.c
> @@ -1555,30 +1555,6 @@ static const struct nand_controller_ops
> mxcnd_controller_ops = {
> * From this point on we can forget about the BBMs and rely completely
> * on the flash BBT.
> */
> -static int checkbad(struct nand_chip *chip, loff_t ofs)
> -{
> - struct mtd_info *mtd = nand_to_mtd(chip);
> - int ret;
> - uint8_t buf[mtd->writesize + mtd->oobsize];
> - struct mtd_oob_ops ops;
> -
> - ops.mode = MTD_OPS_RAW;
> - ops.ooboffs = 0;
> - ops.datbuf = buf;
> - ops.len = mtd->writesize;
> - ops.oobbuf = buf + mtd->writesize;
> - ops.ooblen = mtd->oobsize;
> -
> - ret = mtd_read_oob(mtd, ofs, &ops);
> - if (ret < 0)
> - return ret;
> -
> - if (buf[2000] != 0xff)
> - return 1;
> -
> - return 0;
> -}
> -
> static int imxnd_create_bbt(struct nand_chip *chip)
> {
> struct mtd_info *mtd = nand_to_mtd(chip);
> @@ -1598,12 +1574,40 @@ static int imxnd_create_bbt(struct nand_chip *chip)
>
> for (i = 0; i < numblocks; ++i) {
> loff_t ofs = i << chip->bbt_erase_shift;
> + uint8_t buf[mtd->writesize + mtd->oobsize];
> + struct mtd_oob_ops ops = {
> + .mode = MTD_OPS_RAW,
> + .ooboffs = 0,
> + .datbuf = buf,
> + .len = mtd->writesize,
> + .oobbuf = buf + mtd->writesize,
> + .ooblen = mtd->oobsize,
> + };
>
> - ret = checkbad(chip, ofs);
> - if (ret < 0)
> + ret = mtd_read_oob(mtd, ofs, &ops);
> + if (ret < 0) {
> + dev_err(mtd->dev.parent, "Failed to read page at
> 0x%08x\n", (unsigned int)ofs);
> goto out;
> + }
>
> - if (ret) {
> + /*
> + * Automatically adding a BBT based on factory BBTs is only
> + * sensible if the NAND is pristine. Abort if the first page
> + * looks like a bootloader or UBI block.
> + */
> + if (ofs == 0 && is_barebox_arm_head(buf)) {
> + dev_err(mtd->dev.parent, "Flash seems to contain a
> barebox image, refusing\n");
> + ret = -EINVAL;
> + goto out;
> + }
> +
> + if (ofs == 0 && !memcmp(buf, "UBI#", 4)) {
> + dev_err(mtd->dev.parent, "Flash seems to contain a UBI,
> refusing\n");
> + ret = -EINVAL;
> + goto out;
> + }
> +
> + if (buf[2000] != 0xff) {
> bbt[i >> 2] |= 0x03 << (2 * (i & 0x3));
> dev_info(mtd->dev.parent, "Bad eraseblock %d at
> 0x%08x\n",
>i, (unsigned int)ofs);
Could you add the new code to checkbad() instead of inlining it? That
way it seems easier to adjust the code in case we have to change the way
how we detect useful data on a page. Rename checkbad() in case the name
doesn't feel appropriate anymore.
Sascha
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0|
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
Re: [PATCH] ARM: i.MX8MP: fix compatible string for koenigbauer,alphajet board
On Tue, 30 Apr 2024 12:23:57 +0200, Roland Hieber wrote: > During the review of the initial board support patch, the SoM compatible > was changed (and unified) to "congatec,qmx8p" from several different > incompatible variants. However, the compatible in the alphajet device > tree contained a different typo and was overlooked, which had the effect > that the barebox_update handler and the Ethernet fixups were not > registered on the alphajet board. > > [...] Applied, thanks! [1/1] ARM: i.MX8MP: fix compatible string for koenigbauer,alphajet board https://git.pengutronix.de/cgit/barebox/commit/?id=f18bb339857d (link may not be stable) Best regards, -- Sascha Hauer
Re: [PATCH 2/2] ARM: i.MX8M: add support to handle ROM SError ERR050350
On Tue, Apr 30, 2024 at 01:29:41PM +0200, Marco Felsch wrote:
> This ports U-Boot commit:
>
> | commit 2f3c92060dcd6bc9cfd3e2e344a3e1745ca39f09
> | Author: Peng Fan
> | Date: Thu Jul 9 13:39:26 2020 +0800
> |
> | imx8m: workaround ROM serror
> |
> | ROM SError happens on two cases:
> |
> | 1. ERR050342, on iMX8MQ HDCP enabled parts ROM writes to GPV1 register,
> but
> | when ROM patch lock is fused, this write will cause SError.
> |
> | 2. ERR050350, on iMX8MQ/MM/MN, when the field return fuse is burned, HAB
> | is field return mode, but the last 4K of ROM is still protected and
> cause
> | SError.
> |
> | Since ROM mask SError until ATF unmask it, so then ATF always meets the
> | exception. This patch works around the issue in SPL by enabling SPL
> | Exception vectors table and the SError exception, take the exception
> | to eret immediately to clear the SError.
> |
> | Signed-off-by: Ye Li
> | Signed-off-by: Peng Fan
>
> Other than U-Boot we don't support exceptions in PBL and therefore we
> can handle it simpler by installing an dummy exception table which does
> nothing. The table gets overriden by TF-A later on anyway.
>
> Signed-off-by: Marco Felsch
> ---
> Hi all,
>
> I'm not sure if the relocation should be done within the erratum
> handler or if we should move it into the lowlevel code per default for
> all i.MX8M platforms since the board files call it anyway after the
> lowlevel init. In the later case this would be an separate patch to drop
> the pattern:
>
> lowlevel_setup();
> relocate_to_current_adr();
>
> from the board files.
>
> Regards,
> Marco
>
> arch/arm/mach-imx/Makefile| 1 +
> arch/arm/mach-imx/cpu_init.c | 12 +-
> arch/arm/mach-imx/errata.c| 22 ++
> arch/arm/mach-imx/imx8m_early_exceptions_64.S | 42 +++
> include/mach/imx/errata.h | 12 ++
> 5 files changed, 88 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/mach-imx/errata.c
> create mode 100644 arch/arm/mach-imx/imx8m_early_exceptions_64.S
> create mode 100644 include/mach/imx/errata.h
>
> diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
> index ce8af486aed4..d182f95673f5 100644
> --- a/arch/arm/mach-imx/Makefile
> +++ b/arch/arm/mach-imx/Makefile
> @@ -34,6 +34,7 @@ obj-$(CONFIG_BAREBOX_UPDATE_IMX_EXTERNAL_NAND) +=
> imx-bbu-external-nand.o
> pbl-$(CONFIG_USB_GADGET_DRIVER_ARC_PBL) += imx-udc.o
> obj-$(CONFIG_RESET_IMX_SRC) += src.o
> lwl-y += cpu_init.o
> +lwl-y += errata.o imx8m_early_exceptions_64.o
Should likely be:
lwl-$(CONFIG_ARCH_IMX8M) += imx8m_early_exceptions_64.o
Also you can drop the _64 suffix from the filename as the imx8m_ preifx
already implies this.
> pbl-y += xload-spi.o xload-common.o xload-imx-nand.o xload-gpmi-nand.o
> pbl-y += xload-qspi.o
> obj-pbl-$(CONFIG_ARCH_IMX9) += ele.o
> diff --git a/arch/arm/mach-imx/cpu_init.c b/arch/arm/mach-imx/cpu_init.c
> index c5a47d9b9154..aebbd3defaec 100644
> --- a/arch/arm/mach-imx/cpu_init.c
> +++ b/arch/arm/mach-imx/cpu_init.c
> @@ -6,6 +6,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -75,17 +76,26 @@ void imx8mm_cpu_lowlevel_init(void)
> imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_SCTR);
>
> imx8m_cpu_lowlevel_init();
> +
> + erratum_050350_imx8m();
> }
>
> void imx8mn_cpu_lowlevel_init(void)
> __alias(imx8mm_cpu_lowlevel_init);
>
> void imx8mp_cpu_lowlevel_init(void)
> - __alias(imx8mm_cpu_lowlevel_init);
> +{
> + /* ungate system counter */
> + imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_SCTR);
> +
> + imx8m_cpu_lowlevel_init();
> +}
>
> void imx8mq_cpu_lowlevel_init(void)
> {
> imx8m_cpu_lowlevel_init();
> +
> + erratum_050350_imx8m();
> }
>
> #define CCM_AUTHEN_TZ_NS BIT(9)
> diff --git a/arch/arm/mach-imx/errata.c b/arch/arm/mach-imx/errata.c
> new file mode 100644
> index ..ef8de91a9278
> --- /dev/null
> +++ b/arch/arm/mach-imx/errata.c
> @@ -0,0 +1,22 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +
> +#include
> +#include
> +#include
> +
> +#ifdef CONFIG_CPU_V8
> +
> +extern unsigned long early_imx8m_vectors;
> +
> +void erratum_050350_imx8m(void)
> +{
> + if (current_el() != 3)
> + return;
> +
> + relocate_to_current_adr();
> +
> + asm volatile("msr vbar_el3, %0" : : "r" (&early_imx8m_vectors) : "cc");
> + asm volatile("msr daifclr, #4;isb");
> +}
> +
> +#endif /* CONFIG_CPU_V8 */
> diff --git a/arch/arm/mach-imx/imx8m_early_exceptions_64.S
> b/arch/arm/mach-imx/imx8m_early_exceptions_64.S
> new file mode 100644
> index ..cd91e1a07b9c
> --- /dev/null
> +++ b/arch/arm/mach-imx/imx8m_early_exceptions_64.S
> @@ -0,0 +1,42 @@
> +/*
> + * (C) Copyright 2013
> + * David Feng
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include
> +
> +#ifdef CONFIG_CPU_
Re: [PATCH] kbuild: make implicit int to pointer conversion warning an error
On Tue, 30 Apr 2024 15:15:40 +0200, Ahmad Fatoum wrote: > We are guilty of using ints as pointers in readl/writel, but the old > definition of these uses a cast to silence the warning. > > Everywhere else there's no reason to allow this, so make this a hard > error always to weed out any instances we may still have. > > Disallowing this has the added benefit of making it easier to change API > in barebox: We do not guarantee out-of-tree board code API stability, > but we want changes in API to result in build errors, not in warnings > that may be eaten up by a build system sitting in-between Kbuild and the > user. > > [...] Applied, thanks! [1/1] kbuild: make implicit int to pointer conversion warning an error https://git.pengutronix.de/cgit/barebox/commit/?id=bcb16b721fb8 (link may not be stable) Best regards, -- Sascha Hauer
Re: [PATCH 0/3] bootm: make uImage support optional
On Tue, 30 Apr 2024 20:06:30 +0200, Ahmad Fatoum wrote: > While looking into CONFIG_TIMESTAMP, I noticed we still build UIMAGE > support unconditionally, when BOOTM is enabled. This series makes it > optional as most users no longer need it. > > Saves me 4KiB in an LZO-compressed ARM64 image. > > Ahmad Fatoum (3): > uimage: move file_to_sdram implementation to libfile > bootm: allow disabling uImage support > uimage: have TIMESTMAP depend on UIMAGE > > [...] Applied, thanks! [1/3] uimage: move file_to_sdram implementation to libfile https://git.pengutronix.de/cgit/barebox/commit/?id=7b29c539e461 (link may not be stable) [2/3] bootm: allow disabling uImage support https://git.pengutronix.de/cgit/barebox/commit/?id=59edd0c3be21 (link may not be stable) [3/3] uimage: have TIMESTMAP depend on UIMAGE https://git.pengutronix.de/cgit/barebox/commit/?id=76131012282d (link may not be stable) Best regards, -- Sascha Hauer
