[PATCH] commands: add msleep command

[Steffen Trumtrar]

Add a command to sleep for n milliseconds.

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 commands/Kconfig  |4 
 commands/Makefile |1 +
 commands/msleep.c |   40 
 3 files changed, 45 insertions(+)
 create mode 100644 commands/msleep.c

diff --git a/commands/Kconfig b/commands/Kconfig
index 52e1f17..adc0914 100644
--- a/commands/Kconfig
+++ b/commands/Kconfig
@@ -25,6 +25,10 @@ config CMD_SLEEP
tristate
prompt sleep
 
+config CMD_MSLEEP
+   tristate
+   prompt msleep
+
 config CMD_SAVEENV
tristate
select ENV_HANDLING
diff --git a/commands/Makefile b/commands/Makefile
index 4c8a0a9..0970ba3 100644
--- a/commands/Makefile
+++ b/commands/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_CMD_MTEST)   += memtest.o
 obj-$(CONFIG_CMD_EDIT) += edit.o
 obj-$(CONFIG_CMD_EXEC) += exec.o
 obj-$(CONFIG_CMD_SLEEP)+= sleep.o
+obj-$(CONFIG_CMD_MSLEEP)   += msleep.o
 obj-$(CONFIG_CMD_RESET)+= reset.o
 obj-$(CONFIG_CMD_GO)   += go.o
 obj-$(CONFIG_NET)  += net.o
diff --git a/commands/msleep.c b/commands/msleep.c
new file mode 100644
index 000..c9fa23c
--- /dev/null
+++ b/commands/msleep.c
@@ -0,0 +1,40 @@
+/*
+ * msleep.c - delay execution for n milliseconds
+ *
+ * Copyright (c) 2012 Steffen Trumtrar s.trumt...@pengutronix.de, Pengutronix
+ *
+ * derived from commands/sleep.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include common.h
+#include command.h
+#include clock.h
+
+static int do_msleep(int argc, char *argv[])
+{
+   ulong delay;
+
+   if (argc != 2)
+   return COMMAND_ERROR_USAGE;
+
+   delay = simple_strtoul(argv[1], NULL, 10);
+
+   mdelay(delay);
+
+   return 0;
+}
+
+BAREBOX_CMD_START(msleep)
+   .cmd= do_msleep,
+   .usage  = delay execution for n milliseconds,
+BAREBOX_CMD_END
-- 
1.7.10


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[PATCH] common: fix typo cammand_var_complete

[Steffen Trumtrar]

Change function name to command_var_complete in all calls and its declaration.

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 commands/go.c  |2 +-
 commands/sleep.c   |2 +-
 common/complete.c  |2 +-
 include/complete.h |2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/commands/go.c b/commands/go.c
index e9e9d40..14569a5 100644
--- a/commands/go.c
+++ b/commands/go.c
@@ -92,5 +92,5 @@ BAREBOX_CMD_START(go)
.cmd= do_go,
.usage  = start application at address or file,
BAREBOX_CMD_HELP(cmd_go_help)
-   BAREBOX_CMD_COMPLETE(cammand_var_complete)
+   BAREBOX_CMD_COMPLETE(command_var_complete)
 BAREBOX_CMD_END
diff --git a/commands/sleep.c b/commands/sleep.c
index c5f7867..950ec08 100644
--- a/commands/sleep.c
+++ b/commands/sleep.c
@@ -47,5 +47,5 @@ static int do_sleep(int argc, char *argv[])
 BAREBOX_CMD_START(sleep)
.cmd= do_sleep,
.usage  = delay execution for n seconds,
-   BAREBOX_CMD_COMPLETE(cammand_var_complete)
+   BAREBOX_CMD_COMPLETE(command_var_complete)
 BAREBOX_CMD_END
diff --git a/common/complete.c b/common/complete.c
index 0780888..4370b20 100644
--- a/common/complete.c
+++ b/common/complete.c
@@ -198,7 +198,7 @@ int empty_complete(struct string_list *sl, char *instr)
return COMPLETE_END;
 }
 
-int cammand_var_complete(struct string_list *sl, char *instr)
+int command_var_complete(struct string_list *sl, char *instr)
 {
return COMPLETE_CONTINUE;
 }
diff --git a/include/complete.h b/include/complete.h
index 8248c64..33b848c 100644
--- a/include/complete.h
+++ b/include/complete.h
@@ -15,7 +15,7 @@ int command_complete(struct string_list *sl, char *instr);
 int device_complete(struct string_list *sl, char *instr);
 int empty_complete(struct string_list *sl, char *instr);
 int eth_complete(struct string_list *sl, char *instr);
-int cammand_var_complete(struct string_list *sl, char *instr);
+int command_var_complete(struct string_list *sl, char *instr);
 int devfs_partition_complete(struct string_list *sl, char *instr);
 
 #endif /* __COMPLETE_ */
-- 
1.7.10


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[PATCH] ARM i.MX: Add support for i2c on imx6

[Steffen Trumtrar]

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
Hi all,

this patch adds support for i2c on imx6. The patch was tested on a sabrelite
board, where I measured SCL and SDATA, as there are no devices connected (apart
from an sgtl5000).

 arch/arm/mach-imx/include/mach/devices-imx6.h |   15 +++
 arch/arm/mach-imx/speed-imx6.c|6 ++
 2 files changed, 21 insertions(+)

diff --git a/arch/arm/mach-imx/include/mach/devices-imx6.h 
b/arch/arm/mach-imx/include/mach/devices-imx6.h
index ca063c5..c73e488 100644
--- a/arch/arm/mach-imx/include/mach/devices-imx6.h
+++ b/arch/arm/mach-imx/include/mach/devices-imx6.h
@@ -49,3 +49,18 @@ static inline struct device_d *imx6_add_spi0(struct 
spi_imx_master *pdata)
 {
return imx_add_spi((void *)MX6_ECSPI1_BASE_ADDR, 0, pdata);
 }
+
+static inline struct device_d *imx6_add_i2c0(struct i2c_platform_data *pdata)
+{
+   return imx_add_i2c((void *)MX6_I2C1_BASE_ADDR, 0, pdata);
+}
+
+static inline struct device_d *imx6_add_i2c1(struct i2c_platform_data *pdata)
+{
+   return imx_add_i2c((void *)MX6_I2C2_BASE_ADDR, 1, pdata);
+}
+
+static inline struct device_d *imx6_add_i2c2(struct i2c_platform_data *pdata)
+{
+   return imx_add_i2c((void *)MX6_I2C3_BASE_ADDR, 2, pdata);
+}
diff --git a/arch/arm/mach-imx/speed-imx6.c b/arch/arm/mach-imx/speed-imx6.c
index df24545..645b2c9 100644
--- a/arch/arm/mach-imx/speed-imx6.c
+++ b/arch/arm/mach-imx/speed-imx6.c
@@ -332,6 +332,11 @@ u32 imx_get_fecclk(void)
return __get_ipg_clk();
 }
 
+u32 imx_get_i2cclk(void)
+{
+   return __get_ipg_per_clk();
+}
+
 u32 imx_get_cspiclk(void)
 {
return __get_cspi_clk();
@@ -351,6 +356,7 @@ void imx_dump_clocks(void)
printf(mx6q pll8: %d\n, freq);
printf(mcu main:  %d\n, __get_mcu_main_clk());
printf(periph:%d\n, __get_periph_clk());
+   printf(i2c:   %d\n, __get_ipg_per_clk());
printf(ipg:   %d\n, __get_ipg_clk());
printf(ipg per:   %d\n, __get_ipg_per_clk());
printf(cspi:  %d\n, __get_cspi_clk());
-- 
1.7.10.4


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[PATCH 2/2] trivial: bootm: correct grammar in error message

[Steffen Trumtrar]

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 commands/bootm.c |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/commands/bootm.c b/commands/bootm.c
index 5f858e8..2d9f7f2 100644
--- a/commands/bootm.c
+++ b/commands/bootm.c
@@ -180,7 +180,7 @@ static int bootm_open_oftree(struct image_data *data, const 
char *oftree, int nu
 
ft = file_detect_type(fdt);
if (ft != filetype_oftree) {
-   printf(%s is not a oftree but %s\n, oftree,
+   printf(%s is not an oftree but %s\n, oftree,
file_type_to_string(ft));
}
 
-- 
1.7.10.4


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[PATCH 0/2] trivial: correct spellings and grammar

[Steffen Trumtrar]

Hi all,

this patchseries fixes just some spelling, grammar, etc errors I
stumbled upon.

Steffen Trumtrar (2):
  trivial: fix spelling in usb code
  trivial: bootm: correct grammar in error message

 commands/bootm.c   |2 +-
 commands/usb.c |2 +-
 drivers/usb/core/usb.c |4 ++--
 3 files changed, 4 insertions(+), 4 deletions(-)

-- 
1.7.10.4


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[PATCH 1/2] trivial: fix spelling in usb code

[Steffen Trumtrar]

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 commands/usb.c |2 +-
 drivers/usb/core/usb.c |4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/commands/usb.c b/commands/usb.c
index d02ea4b..729a402 100644
--- a/commands/usb.c
+++ b/commands/usb.c
@@ -50,7 +50,7 @@ static int do_usb(int argc, char *argv[])
 BAREBOX_CMD_HELP_START(usb)
 BAREBOX_CMD_HELP_USAGE(usb [-f]\n)
 BAREBOX_CMD_HELP_SHORT(Scan for USB devices.\n)
-BAREBOX_CMD_HELP_OPT(-f, force. Rescan if if if have scanned once\n)
+BAREBOX_CMD_HELP_OPT(-f, force. Rescan although scanned already\n)
 BAREBOX_CMD_HELP_END
 
 BAREBOX_CMD_START(usb)
diff --git a/drivers/usb/core/usb.c b/drivers/usb/core/usb.c
index a5075d5..81ae9f1 100644
--- a/drivers/usb/core/usb.c
+++ b/drivers/usb/core/usb.c
@@ -528,10 +528,10 @@ int usb_submit_int_msg(struct usb_device *dev, unsigned 
long pipe,
 }
 
 /*
- * submits a control message and waits for comletion (at least timeout * 1ms)
+ * submits a control message and waits for completion (at least timeout * 1ms)
  * If timeout is 0, we don't wait for completion (used as example to set and
  * clear keyboards LEDs). For data transfers, (storage transfers) we don't
- * allow control messages with 0 timeout, by previousely resetting the flag
+ * allow control messages with 0 timeout, by previously resetting the flag
  * asynch_allowed (usb_disable_asynch(1)).
  * returns the transfered length if OK or -1 if error. The transfered length
  * and the current status are stored in the dev-act_len and dev-status.
-- 
1.7.10.4


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[PATCH 0/3] ARM i.MX6: basic USB H1 support

[Steffen Trumtrar]

This series adds basic support for usb host1 on imx6q. This was tested on a
sabrelite board.

Steffen Trumtrar (3):
  ARM i.MX6: add the usbphy1 base addr
  ARM i.MX6: enable usbphy1
  usb: use ep-specific pwrgood delay

 arch/arm/mach-imx/Makefile |2 +-
 arch/arm/mach-imx/include/mach/imx6-regs.h |1 +
 arch/arm/mach-imx/usb-imx6.c   |  111 
 drivers/usb/core/usb.c |3 +-
 4 files changed, 115 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/mach-imx/usb-imx6.c

-- 
1.7.10.4


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[PATCH 3/3] usb: use ep-specific pwrgood delay

[Steffen Trumtrar]

In usb_hub_configure the hub is asked for its descriptor and among other things
its bPwrOn2PwrGood time. In the actual hub_power_on function this information
was not used and a hardcoded value was used instead. For some hubs this delay
is to short. So, use the delay the hub wants.

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
Signed-off-by: Michael Grzeschik m.grzesc...@pengutronix.de
---
 drivers/usb/core/usb.c |3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/core/usb.c b/drivers/usb/core/usb.c
index 81ae9f1..48bc121 100644
--- a/drivers/usb/core/usb.c
+++ b/drivers/usb/core/usb.c
@@ -948,7 +948,8 @@ static void usb_hub_power_on(struct usb_hub_device *hub)
usb_set_port_feature(dev, i + 1, USB_PORT_FEAT_POWER);
USB_HUB_PRINTF(port %d returns %lX\n, i + 1, dev-status);
}
-   mdelay(20);
+   /* power on is encoded in 2ms increments - times 2 for the actual 
delay */
+   mdelay(hub-desc.bPwrOn2PwrGood*2);
 }
 
 #define MAX_TRIES 5
-- 
1.7.10.4


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[PATCH 1/2] ARM i.MX6: Add usb-ehci to sabrelite

[Steffen Trumtrar]

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 arch/arm/boards/freescale-mx6-sabrelite/board.c |   20 
 1 file changed, 20 insertions(+)

diff --git a/arch/arm/boards/freescale-mx6-sabrelite/board.c 
b/arch/arm/boards/freescale-mx6-sabrelite/board.c
index 13279bc..6490988 100644
--- a/arch/arm/boards/freescale-mx6-sabrelite/board.c
+++ b/arch/arm/boards/freescale-mx6-sabrelite/board.c
@@ -77,6 +77,11 @@ static iomux_v3_cfg_t sabrelite_pads[] = {
MX6Q_PAD_EIM_D17__ECSPI1_MISO,
MX6Q_PAD_EIM_D18__ECSPI1_MOSI,
MX6Q_PAD_EIM_D19__GPIO_3_19,/* CS1 */
+
+   /* USB */
+   MX6Q_PAD_GPIO_17__GPIO_7_12,
+   MX6Q_PAD_EIM_D22__GPIO_3_22,
+   MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC,
 };
 
 static iomux_v3_cfg_t sabrelite_enet_pads[] = {
@@ -227,6 +232,19 @@ static struct esdhc_platform_data sabrelite_sd4_data = {
.wp_type = ESDHC_WP_NONE,
 };
 
+static void sabrelite_ehci_init(void)
+{
+   imx6_usb_phy1_disable_oc();
+   imx6_usb_phy1_enable();
+
+   /* hub reset */
+   gpio_direction_output(204, 0);
+   udelay(2000);
+   gpio_set_value(204, 1);
+
+   add_generic_usb_ehci_device(1, MX6_USBOH3_USB_BASE_ADDR + 0x200, NULL);
+}
+
 static int sabrelite_devices_init(void)
 {
imx6_add_mmc2(sabrelite_sd3_data);
@@ -237,6 +255,8 @@ static int sabrelite_devices_init(void)
imx6_add_fec(fec_info);
mx6_rgmii_rework();
 
+   sabrelite_ehci_init();
+
spi_register_board_info(sabrelite_spi_board_info,
ARRAY_SIZE(sabrelite_spi_board_info));
imx6_add_spi0(sabrelite_spi_0_data);
-- 
1.7.10.4


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[PATCH 0/2] ARM i.MX6: Add sabrelite features

[Steffen Trumtrar]

This adds usb h1 and the i2c iomux to the sabrelite board.

Steffen Trumtrar (2):
  ARM i.MX6: Add usb-ehci to sabrelite
  ARM i.MX6: Add i2c iomux to sabrelite

 arch/arm/boards/freescale-mx6-sabrelite/board.c |   32 +++
 1 file changed, 32 insertions(+)

-- 
1.7.10.4


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Re: [PATCH 3/3] usb: use ep-specific pwrgood delay

[Steffen Trumtrar]

Hi Eric,

 Hi Steffen,
 
 Le Thu, 30 Aug 2012 14:30:50 +0200,
 Steffen Trumtrar s.trumt...@pengutronix.de a écrit :
 
  In usb_hub_configure the hub is asked for its descriptor and among other 
  things
  its bPwrOn2PwrGood time. In the actual hub_power_on function this 
  information
  was not used and a hardcoded value was used instead. For some hubs this 
  delay
  is to short. So, use the delay the hub wants.
  
  Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
  Signed-off-by: Michael Grzeschik m.grzesc...@pengutronix.de
  ---
   drivers/usb/core/usb.c |3 ++-
   1 file changed, 2 insertions(+), 1 deletion(-)
  
  diff --git a/drivers/usb/core/usb.c b/drivers/usb/core/usb.c
  index 81ae9f1..48bc121 100644
  --- a/drivers/usb/core/usb.c
  +++ b/drivers/usb/core/usb.c
  @@ -948,7 +948,8 @@ static void usb_hub_power_on(struct usb_hub_device *hub)
  usb_set_port_feature(dev, i + 1, USB_PORT_FEAT_POWER);
  USB_HUB_PRINTF(port %d returns %lX\n, i + 1, dev-status);
  }
  -   mdelay(20);
  +   /* power on is encoded in 2ms increments - times 2 for the actual 
  delay */
  +   mdelay(hub-desc.bPwrOn2PwrGood*2);
   }
   
   #define MAX_TRIES 5
 
 I tested you patch on my MX35 board and it doesn't work (the hub
 requires 50 ms, the mdelay is thus 100 ms and in the end that's not
 enough to see the USB mass storage connected to the hub) but
 mdelay(hub-desc.bPwrOn2PwrGood*3) works fine.
 Is it possible to increase this delay (*3 instead of *2) ?
 
 Thanks
 Eric
 

Where does your 50ms come from? From the debug messages of the usb-tool?
It has the same factor of times 2.
Have you tried hardcoding mdelay(100)?
I first thought about doing it the same way linux does it and use
max(pwrgood, 100). But 100ms minimum wouldn't help you either.
I don't really like the idea of just guessing a value. But if necessary,
I'm surely willing to change this patch.

Greetings
Steffen

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Re: [PATCH 3/3] usb: use ep-specific pwrgood delay

[Steffen Trumtrar]

Hi Eric,

On Thu, Aug 30, 2012 at 03:59:32PM +0200, Eric Bénard wrote:
 Hi Steffen,
 
 Le Thu, 30 Aug 2012 15:26:31 +0200,
 Steffen Trumtrar s.trumt...@pengutronix.de a écrit :
  Where does your 50ms come from? From the debug messages of the usb-tool?
 from a printf of bPwrOn2PwrGood
 
  It has the same factor of times 2.
 yes, so in the end the hub is supposed to need 100ms to enable power.

Okay. So you have an equal setting like me.

 
  Have you tried hardcoding mdelay(100)?
 yes - doesn't work (see previous patch I sent 2 days ago on the same
 subject).

Ah, okay.

  I first thought about doing it the same way linux does it and use
  max(pwrgood, 100). But 100ms minimum wouldn't help you either.
  I don't really like the idea of just guessing a value. But if necessary,
  I'm surely willing to change this patch.
 
 with Linux's 100ms that works fine on the same board (under Linux). So
 I'll check the if the mdelay(100) in barebox is really a 100ms timing
 because the problem's root may be here !

As both, barebox and linux, reset the hub and wait, it seems like the root
of the problem, yes.

Greetings
Steffen


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[PATCH 06/10] ARM i.MX35: add imx-gpio devices

[Steffen Trumtrar]

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 arch/arm/mach-imx/imx35.c |4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/mach-imx/imx35.c b/arch/arm/mach-imx/imx35.c
index fe0c99e..066436c 100644
--- a/arch/arm/mach-imx/imx35.c
+++ b/arch/arm/mach-imx/imx35.c
@@ -66,6 +66,10 @@ static int imx35_init(void)
add_generic_device(imx_iim, 0, NULL, IMX_IIM_BASE, SZ_4K,
IORESOURCE_MEM, NULL);
 
+   add_generic_device(imx-gpio, 0, NULL, 0x53fcc000, 0x1000, 
IORESOURCE_MEM, NULL);
+   add_generic_device(imx-gpio, 1, NULL, 0x53fd, 0x1000, 
IORESOURCE_MEM, NULL);
+   add_generic_device(imx-gpio, 2, NULL, 0x53fa4000, 0x1000, 
IORESOURCE_MEM, NULL);
+
return 0;
 }
 coredevice_initcall(imx35_init);
-- 
1.7.10.4


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[PATCH 07/10] ARM i.MX27: add imx-gpio devices

[Steffen Trumtrar]

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 arch/arm/mach-imx/imx27.c |6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/mach-imx/imx27.c b/arch/arm/mach-imx/imx27.c
index 1af291d..cf5ec21 100644
--- a/arch/arm/mach-imx/imx27.c
+++ b/arch/arm/mach-imx/imx27.c
@@ -86,6 +86,12 @@ static int imx27_init(void)
 
imx27_init_max();
 
+   add_generic_device(imx-gpio, 0, NULL, 0x10015000, 0x100, 
IORESOURCE_MEM, NULL);
+   add_generic_device(imx-gpio, 1, NULL, 0x10015100, 0x100, 
IORESOURCE_MEM, NULL);
+   add_generic_device(imx-gpio, 2, NULL, 0x10015200, 0x100, 
IORESOURCE_MEM, NULL);
+   add_generic_device(imx-gpio, 3, NULL, 0x10015300, 0x100, 
IORESOURCE_MEM, NULL);
+   add_generic_device(imx-gpio, 4, NULL, 0x10015400, 0x100, 
IORESOURCE_MEM, NULL);
+   add_generic_device(imx-gpio, 5, NULL, 0x10015500, 0x100, 
IORESOURCE_MEM, NULL);
return 0;
 }
 coredevice_initcall(imx27_init);
-- 
1.7.10.4


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[PATCH 04/10] ARM i.MX6: add imx-gpio devices

[Steffen Trumtrar]

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 arch/arm/mach-imx/imx6.c |   14 ++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
index a443343..b6067d7 100644
--- a/arch/arm/mach-imx/imx6.c
+++ b/arch/arm/mach-imx/imx6.c
@@ -69,3 +69,17 @@ void imx6_init_lowlevel(void)
writel(0x, 0x020c407c);
writel(0x, 0x020c4080);
 }
+
+static int imx6_init(void)
+{
+   add_generic_device(imx-gpio, 0, NULL, MX6_GPIO1_BASE_ADDR, 0x4000, 
IORESOURCE_MEM, NULL);
+   add_generic_device(imx-gpio, 1, NULL, MX6_GPIO2_BASE_ADDR, 0x4000, 
IORESOURCE_MEM, NULL);
+   add_generic_device(imx-gpio, 2, NULL, MX6_GPIO3_BASE_ADDR, 0x4000, 
IORESOURCE_MEM, NULL);
+   add_generic_device(imx-gpio, 3, NULL, MX6_GPIO4_BASE_ADDR, 0x4000, 
IORESOURCE_MEM, NULL);
+   add_generic_device(imx-gpio, 4, NULL, MX6_GPIO5_BASE_ADDR, 0x4000, 
IORESOURCE_MEM, NULL);
+   add_generic_device(imx-gpio, 5, NULL, MX6_GPIO6_BASE_ADDR, 0x4000, 
IORESOURCE_MEM, NULL);
+   add_generic_device(imx-gpio, 6, NULL, MX6_GPIO7_BASE_ADDR, 0x4000, 
IORESOURCE_MEM, NULL);
+
+   return 0;
+}
+coredevice_initcall(imx6_init);
-- 
1.7.10.4


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[PATCH 10/10] ARM i.MX21: add imx-gpio devices

[Steffen Trumtrar]

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 arch/arm/mach-imx/imx21.c |   15 +++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm/mach-imx/imx21.c b/arch/arm/mach-imx/imx21.c
index bbef33d..19e9bd0 100644
--- a/arch/arm/mach-imx/imx21.c
+++ b/arch/arm/mach-imx/imx21.c
@@ -39,3 +39,18 @@ void *imx_gpio_base[] = {
 
 int imx_gpio_count = ARRAY_SIZE(imx_gpio_base) * 32;
 
+static int imx21_init(void)
+{
+   add_generic_device(imx_iim, 0, NULL, MX51_IIM_BASE_ADDR, SZ_4K,
+   IORESOURCE_MEM, NULL);
+
+   add_generic_device(imx-gpio, 0, NULL, 0x10015000, 0x100, 
IORESOURCE_MEM, NULL);
+   add_generic_device(imx-gpio, 1, NULL, 0x10015100, 0x100, 
IORESOURCE_MEM, NULL);
+   add_generic_device(imx-gpio, 2, NULL, 0x10015200, 0x100, 
IORESOURCE_MEM, NULL);
+   add_generic_device(imx-gpio, 3, NULL, 0x10015300, 0x100, 
IORESOURCE_MEM, NULL);
+   add_generic_device(imx-gpio, 4, NULL, 0x10015400, 0x100, 
IORESOURCE_MEM, NULL);
+   add_generic_device(imx-gpio, 5, NULL, 0x10015500, 0x100, 
IORESOURCE_MEM, NULL);
+
+   return 0;
+}
+coredevice_initcall(imx21_init);
-- 
1.7.10.4


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[PATCH 09/10] ARM i.MX1: add imx-gpio devices

[Steffen Trumtrar]

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 arch/arm/mach-imx/imx1.c |9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/mach-imx/imx1.c b/arch/arm/mach-imx/imx1.c
index 742a260..1ce0e39 100644
--- a/arch/arm/mach-imx/imx1.c
+++ b/arch/arm/mach-imx/imx1.c
@@ -28,4 +28,13 @@ void *imx_gpio_base[] = {
 
 int imx_gpio_count = ARRAY_SIZE(imx_gpio_base) * 32;
 
+static int imx1_init(void)
+{
+   add_generic_device(imx-gpio, 0, NULL, 0x0021c000, 0x100, 
IORESOURCE_MEM, NULL);
+   add_generic_device(imx-gpio, 1, NULL, 0x0021c100, 0x100, 
IORESOURCE_MEM, NULL);
+   add_generic_device(imx-gpio, 2, NULL, 0x0021c200, 0x100, 
IORESOURCE_MEM, NULL);
+   add_generic_device(imx-gpio, 3, NULL, 0x0021c300, 0x100, 
IORESOURCE_MEM, NULL);
 
+   return 0;
+}
+coredevice_initcall(imx1_init);
-- 
1.7.10.4


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[PATCH 00/10] ARM i.MX: add gpiolib support

[Steffen Trumtrar]

Hi all,

this patch series moves mach-imx to gpiolib support.
This was tested on imx6 and at least compiles on other SoC-defconfigs.

Greetings,
Steffen

Sascha Hauer (2):
  add gpiolib support
  ARM i.MX: switch to gpiolib support

Steffen Trumtrar (8):
  ARM i.MX5: add imx-gpio devices
  ARM i.MX6: add imx-gpio devices
  ARM i.MX53: add imx-gpio devices
  ARM i.MX35: add imx-gpio devices
  ARM i.MX27: add imx-gpio devices
  ARM i.MX25: add imx-gpio devices
  ARM i.MX1: add imx-gpio devices
  ARM i.MX21: add imx-gpio devices

 arch/arm/mach-imx/gpio.c  |   91 +++---
 arch/arm/mach-imx/imx1.c  |9 +++
 arch/arm/mach-imx/imx21.c |   15 +
 arch/arm/mach-imx/imx25.c |4 ++
 arch/arm/mach-imx/imx27.c |6 ++
 arch/arm/mach-imx/imx35.c |4 ++
 arch/arm/mach-imx/imx51.c |5 ++
 arch/arm/mach-imx/imx53.c |7 +++
 arch/arm/mach-imx/imx6.c  |   14 +
 drivers/Makefile  |1 +
 drivers/gpio/Makefile |1 +
 drivers/gpio/gpio.c   |  134 +
 include/gpio.h|   32 ---
 13 files changed, 283 insertions(+), 40 deletions(-)
 create mode 100644 drivers/gpio/Makefile
 create mode 100644 drivers/gpio/gpio.c

-- 
1.7.10.4


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[PATCH 02/10] ARM i.MX: switch to gpiolib support

[Steffen Trumtrar]

From: Sascha Hauer s.ha...@pengutronix.de

Signed-off-by: Sascha Hauer s.ha...@pengutronix.de
Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 arch/arm/mach-imx/gpio.c |   91 ++
 1 file changed, 59 insertions(+), 32 deletions(-)

diff --git a/arch/arm/mach-imx/gpio.c b/arch/arm/mach-imx/gpio.c
index fdee20b..370b555 100644
--- a/arch/arm/mach-imx/gpio.c
+++ b/arch/arm/mach-imx/gpio.c
@@ -27,7 +27,8 @@
 #include errno.h
 #include io.h
 #include mach/imx-regs.h
-#include mach/gpio.h
+#include gpio.h
+#include init.h
 
 #if defined CONFIG_ARCH_IMX1 || defined CONFIG_ARCH_IMX21 || defined 
CONFIG_ARCH_IMX27
 #define GPIO_DR0x1c
@@ -51,18 +52,15 @@
 extern void __iomem *imx_gpio_base[];
 extern int imx_gpio_count;
 
-static void __iomem *gpio_get_base(unsigned gpio)
-{
-   if (gpio = imx_gpio_count)
-   return NULL;
-
-   return imx_gpio_base[gpio / 32];
-}
+struct imx_gpio_chip {
+   void __iomem *base;
+   struct gpio_chip chip;
+};
 
-void gpio_set_value(unsigned gpio, int value)
+static void imx_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int 
value)
 {
-   void __iomem *base = gpio_get_base(gpio);
-   int shift = gpio % 32;
+   struct imx_gpio_chip *imxgpio = container_of(chip, struct 
imx_gpio_chip, chip);
+   void __iomem *base = imxgpio-base;
u32 val;
 
if (!base)
@@ -71,59 +69,88 @@ void gpio_set_value(unsigned gpio, int value)
val = readl(base + GPIO_DR);
 
if (value)
-   val |= 1  shift;
+   val |= 1  gpio;
else
-   val = ~(1  shift);
+   val = ~(1  gpio);
 
writel(val, base + GPIO_DR);
 }
 
-int gpio_direction_input(unsigned gpio)
+static int imx_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
 {
-   void __iomem *base = gpio_get_base(gpio);
-   int shift = gpio % 32;
+   struct imx_gpio_chip *imxgpio = container_of(chip, struct 
imx_gpio_chip, chip);
+   void __iomem *base = imxgpio-base;
u32 val;
 
if (!base)
return -EINVAL;
 
val = readl(base + GPIO_GDIR);
-   val = ~(1  shift);
+   val = ~(1  gpio);
writel(val, base + GPIO_GDIR);
 
return 0;
 }
 
 
-int gpio_direction_output(unsigned gpio, int value)
+static int imx_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, 
int value)
 {
-   void __iomem *base = gpio_get_base(gpio);
-   int shift = gpio % 32;
+   struct imx_gpio_chip *imxgpio = container_of(chip, struct 
imx_gpio_chip, chip);
+   void __iomem *base = imxgpio-base;
u32 val;
 
-   if (!base)
-   return -EINVAL;
-
-   gpio_set_value(gpio, value);
+   gpio_set_value(gpio + chip-base, value);
 
val = readl(base + GPIO_GDIR);
-   val |= 1  shift;
+   val |= 1  gpio;
writel(val, base + GPIO_GDIR);
 
return 0;
 }
 
-int gpio_get_value(unsigned gpio)
+static int imx_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
 {
-   void __iomem *base = gpio_get_base(gpio);
-   int shift = gpio % 32;
+   struct imx_gpio_chip *imxgpio = container_of(chip, struct 
imx_gpio_chip, chip);
+   void __iomem *base = imxgpio-base;
u32 val;
 
-   if (!base)
-   return -EINVAL;
-
val = readl(base + GPIO_PSR);
 
-   return val  (1  shift) ? 1 : 0;
+   return val  (1  gpio) ? 1 : 0;
 }
 
+static struct gpio_ops imx_gpio_ops = {
+   .direction_input = imx_gpio_direction_input,
+   .direction_output = imx_gpio_direction_output,
+   .get = imx_gpio_get_value,
+   .set = imx_gpio_set_value,
+};
+
+static int imx_gpio_probe(struct device_d *dev)
+{
+   struct imx_gpio_chip *imxgpio;
+
+   imxgpio = xzalloc(sizeof(*imxgpio));
+   imxgpio-base = dev_request_mem_region(dev, 0);
+   imxgpio-chip.ops = imx_gpio_ops;
+   imxgpio-chip.base = -1;
+   imxgpio-chip.ngpio = 32;
+   imxgpio-chip.dev = dev;
+   gpiochip_add(imxgpio-chip);
+
+   dev_info(dev, probed gpiochip%d with base %d\n, dev-id, 
imxgpio-chip.base);
+
+   return 0;
+}
+
+static struct driver_d imx_gpio_driver = {
+   .name = imx-gpio,
+   .probe = imx_gpio_probe,
+};
+
+static int imx_gpio_add(void)
+{
+   register_driver(imx_gpio_driver);
+   return 0;
+}
+coredevice_initcall(imx_gpio_add);
-- 
1.7.10.4


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[PATCH 03/10] ARM i.MX5: add imx-gpio devices

[Steffen Trumtrar]

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 arch/arm/mach-imx/imx51.c |5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/mach-imx/imx51.c b/arch/arm/mach-imx/imx51.c
index 53205a9..506a7d9 100644
--- a/arch/arm/mach-imx/imx51.c
+++ b/arch/arm/mach-imx/imx51.c
@@ -89,6 +89,11 @@ static int imx51_init(void)
add_generic_device(imx_iim, 0, NULL, MX51_IIM_BASE_ADDR, SZ_4K,
IORESOURCE_MEM, NULL);
 
+   add_generic_device(imx-gpio, 0, NULL, 0x73f84000, 0x1000, 
IORESOURCE_MEM, NULL);
+   add_generic_device(imx-gpio, 1, NULL, 0x73f88000, 0x1000, 
IORESOURCE_MEM, NULL);
+   add_generic_device(imx-gpio, 2, NULL, 0x73f8c000, 0x1000, 
IORESOURCE_MEM, NULL);
+   add_generic_device(imx-gpio, 3, NULL, 0x73f9, 0x1000, 
IORESOURCE_MEM, NULL);
+
return 0;
 }
 coredevice_initcall(imx51_init);
-- 
1.7.10.4


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[PATCH 0/2] Add stmpe mfd

[Steffen Trumtrar]

Hi all,

this adds support for a stmpe1601 mfd connected via i2c.
This was only tested with the gpiolib support from the previous patch-series
ARM i.MX: add gpiolib support.

Greetings,
Steffen

Steffen Trumtrar (2):
  mfd: add stmpe-i2c driver
  gpio: add driver for stmpe io-expander

 drivers/Kconfig   |1 +
 drivers/gpio/Kconfig  |8 +++
 drivers/gpio/Makefile |1 +
 drivers/gpio/gpio-stmpe.c |  155 ++
 drivers/mfd/Kconfig   |4 ++
 drivers/mfd/Makefile  |1 +
 drivers/mfd/stmpe-i2c.c   |  166 +
 include/mfd/stmpe-i2c.h   |   55 +++
 8 files changed, 391 insertions(+)
 create mode 100644 drivers/gpio/Kconfig
 create mode 100644 drivers/gpio/gpio-stmpe.c
 create mode 100644 drivers/mfd/stmpe-i2c.c
 create mode 100644 include/mfd/stmpe-i2c.h

-- 
1.7.10.4


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[PATCH 1/2] mfd: add stmpe-i2c driver

[Steffen Trumtrar]

The stmpe mfds can be connected via i2c and spi. This driver provides the basic
infrastructure for the i2c kind. It can be added as a normal i2c-device in the
board code. To enable functions a platform_data struct has to be provided, that
describes what parts of the chip are to be used.

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 drivers/mfd/Kconfig |4 ++
 drivers/mfd/Makefile|1 +
 drivers/mfd/stmpe-i2c.c |  166 +++
 include/mfd/stmpe-i2c.h |   55 
 4 files changed, 226 insertions(+)
 create mode 100644 drivers/mfd/stmpe-i2c.c
 create mode 100644 include/mfd/stmpe-i2c.h

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index af67935..20eef86 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -33,4 +33,8 @@ config I2C_TWL6030
select I2C_TWLCORE
bool TWL6030 driver
 
+config I2C_STMPE
+   depends on I2C
+   bool STMPE-i2c driver
+
 endmenu
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index e11223b..792ae2d 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_I2C_LP3972) += lp3972.o
 obj-$(CONFIG_I2C_TWLCORE) += twl-core.o
 obj-$(CONFIG_I2C_TWL4030) += twl4030.o
 obj-$(CONFIG_I2C_TWL6030) += twl6030.o
+obj-$(CONFIG_I2C_STMPE) += stmpe-i2c.o
diff --git a/drivers/mfd/stmpe-i2c.c b/drivers/mfd/stmpe-i2c.c
new file mode 100644
index 000..a0cfa75
--- /dev/null
+++ b/drivers/mfd/stmpe-i2c.c
@@ -0,0 +1,166 @@
+/*
+ * Copyright (C) 2012 Pengutronix
+ * Steffen Trumtrar s.trumt...@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include common.h
+#include init.h
+#include driver.h
+#include xfuncs.h
+#include errno.h
+
+#include i2c/i2c.h
+#include mfd/stmpe-i2c.h
+
+#define DRIVERNAME stmpe-i2c
+
+#define to_stmpe(a)container_of(a, struct stmpe, cdev)
+
+static struct stmpe *stmpe_dev;
+
+struct stmpe *stmpe_get(void)
+{
+   if (!stmpe_dev)
+   return NULL;
+
+   return stmpe_dev;
+}
+EXPORT_SYMBOL(stmpe_get);
+
+int stmpe_reg_read(struct stmpe *stmpe, u32 reg, u8 *val)
+{
+   int ret;
+
+   ret = i2c_read_reg(stmpe-client, reg, val, 1);
+
+   return ret == 1 ? 0 : ret;
+}
+EXPORT_SYMBOL(stmpe_reg_read)
+
+int stmpe_reg_write(struct stmpe *stmpe, u32 reg, u8 val)
+{
+   int ret;
+
+   ret = i2c_write_reg(stmpe-client, reg, val, 1);
+
+   return ret == 1 ? 0 : ret;
+}
+EXPORT_SYMBOL(stmpe_reg_write)
+
+int stmpe_set_bits(struct stmpe *stmpe, u32 reg, u8 mask, u8 val)
+{
+   u8 tmp;
+   int err;
+
+   err = stmpe_reg_read(stmpe, reg, tmp);
+   tmp = (tmp  ~mask) | val;
+
+   if (!err)
+   err = stmpe_reg_write(stmpe, reg, tmp);
+
+   return err;
+}
+EXPORT_SYMBOL(stmpe_set_bits);
+
+static ssize_t stmpe_read(struct cdev *cdev, void *_buf, size_t count, loff_t 
offset, ulong flags)
+{
+   struct stmpe *stmpe = to_stmpe(cdev);
+   u8 *buf = _buf;
+   size_t i = count;
+   int err;
+
+   while (i) {
+   err = stmpe_reg_read(stmpe, offset, buf);
+   if (err)
+   return (ssize_t)err;
+   buf++;
+   i--;
+   offset++;
+   }
+
+   return count;
+}
+
+static ssize_t stmpe_write(struct cdev *cdev, const void *_buf, size_t count, 
loff_t offset, ulong flags)
+{
+   struct stmpe *stmpe = to_stmpe(cdev);
+   const u8 *buf = _buf;
+   size_t i = count;
+   int err;
+
+   while (i) {
+   err = stmpe_reg_write(stmpe, offset, *buf);
+   if (err)
+   return (ssize_t)err;
+   buf++;
+   i--;
+   offset++;
+   }
+
+   return count;
+}
+
+static struct file_operations stmpe_fops = {
+   .lseek  = dev_lseek_default,
+   .read   = stmpe_read,
+   .write  = stmpe_write,
+};
+
+static struct stmpe_client_info i2c_ci = {
+   .read_reg = stmpe_reg_read,
+   .write_reg = stmpe_reg_write,
+};
+
+static int stmpe_probe(struct device_d *dev)
+{
+   struct stmpe_platform_data *pdata = dev-platform_data;
+
+   if (!pdata) {
+   dev_dbg(dev, no platform data\n);
+   return -ENODEV;
+   }
+
+   if (stmpe_dev)
+   return -EBUSY;
+
+   stmpe_dev = xzalloc(sizeof(struct stmpe));
+   stmpe_dev-cdev.name = DRIVERNAME;
+   stmpe_dev-client = to_i2c_client(dev);
+   stmpe_dev-cdev.size

[PATCH 2/2] gpio: add driver for stmpe io-expander

[Steffen Trumtrar]

Add a driver for the stmpe1601 gpio block. The stmpe io-expanders have multiple
blocks (keypad, gpio...) that can be enabled and used. Only gpio is supported 
atm.

This was only tested on a stmpe connected via i2c. It is also possible to 
connect
via spi.

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 drivers/Kconfig   |1 +
 drivers/gpio/Kconfig  |8 +++
 drivers/gpio/Makefile |1 +
 drivers/gpio/gpio-stmpe.c |  155 +
 4 files changed, 165 insertions(+)
 create mode 100644 drivers/gpio/Kconfig
 create mode 100644 drivers/gpio/gpio-stmpe.c

diff --git a/drivers/Kconfig b/drivers/Kconfig
index 883b0e7..adf8fcd 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -18,5 +18,6 @@ source drivers/input/Kconfig
 source drivers/watchdog/Kconfig
 source drivers/pwm/Kconfig
 source drivers/dma/Kconfig
+source drivers/gpio/Kconfig
 
 endmenu
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
new file mode 100644
index 000..939cda8
--- /dev/null
+++ b/drivers/gpio/Kconfig
@@ -0,0 +1,8 @@
+menu GPIO  
+
+config STMPE_GPIO
+   depends on I2C
+   select I2C_STMPE
+   bool STMPE GPIO Expander
+
+endmenu
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 7837966..da1bc21 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -1 +1,2 @@
 obj-y += gpio.o
+obj-$(CONFIG_STMPE_GPIO) += gpio-stmpe.o
diff --git a/drivers/gpio/gpio-stmpe.c b/drivers/gpio/gpio-stmpe.c
new file mode 100644
index 000..44e7ae6
--- /dev/null
+++ b/drivers/gpio/gpio-stmpe.c
@@ -0,0 +1,155 @@
+/*
+ * Copyright (C) 2012 Pengutronix
+ * Steffen Trumtrar s.trumt...@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include common.h
+#include errno.h
+#include io.h
+#include gpio.h
+#include init.h
+#include mfd/stmpe-i2c.h
+
+#define GPIO_BASE  0x80
+#define GPIO_SET   (GPIO_BASE + 0x02)
+#define GPIO_CLR   (GPIO_BASE + 0x04)
+#define GPIO_MP(GPIO_BASE + 0x06)
+#define GPIO_SET_DIR   (GPIO_BASE + 0x08)
+#define GPIO_ED(GPIO_BASE + 0x0a)
+#define GPIO_RE(GPIO_BASE + 0x0c)
+#define GPIO_FE(GPIO_BASE + 0x0e)
+#define GPIO_PULL_UP   (GPIO_BASE + 0x10)
+#define GPIO_AF(GPIO_BASE + 0x12)
+#define GPIO_LT(GPIO_BASE + 0x16)
+
+#define OFFSET(gpio)   (0xff  (1  (gpio)) ? 1 : 0)
+
+extern void __iomem *stmpe_gpio_base[];
+extern int stmpe_gpio_count;
+
+struct stmpe_gpio_chip {
+   void __iomem *base;
+   struct gpio_chip chip;
+   void *ci;
+};
+
+static void stmpe_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int 
value)
+{
+   struct stmpe_gpio_chip *stmpegpio = container_of(chip, struct 
stmpe_gpio_chip, chip);
+   struct stmpe_client_info *ci = (struct stmpe_client_info 
*)stmpegpio-ci;
+   int ret;
+   u8 val;
+
+   ci-read_reg(ci-stmpe, GPIO_MP + OFFSET(gpio), val);
+
+   val |= 1  (gpio % 8);
+
+   if (value)
+   ret = ci-write_reg(ci-stmpe, GPIO_SET + OFFSET(gpio), val);
+   else
+   ret = ci-write_reg(ci-stmpe, GPIO_CLR + OFFSET(gpio), val);
+
+   if (ret)
+   dev_err(chip-dev, write failed!\n);
+}
+
+static int stmpe_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
+{
+   struct stmpe_gpio_chip *stmpegpio = container_of(chip, struct 
stmpe_gpio_chip, chip);
+   struct stmpe_client_info *ci = (struct stmpe_client_info 
*)stmpegpio-ci;
+   int ret;
+   u8 val;
+
+   ci-read_reg(ci-stmpe, GPIO_SET_DIR + OFFSET(gpio), val);
+   val = ~(1  (gpio % 8));
+   ret = ci-write_reg(ci-stmpe, GPIO_SET_DIR + OFFSET(gpio), val);
+
+   if (ret)
+   dev_err(chip-dev, couldn't change direction. Write 
failed!\n);
+
+   return 0;
+}
+
+static int stmpe_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, 
int value)
+{
+   struct stmpe_gpio_chip *stmpegpio = container_of(chip, struct 
stmpe_gpio_chip, chip);
+   struct stmpe_client_info *ci = (struct stmpe_client_info 
*)stmpegpio-ci;
+   int ret;
+   u8 val;
+
+   ci-read_reg(ci-stmpe, GPIO_SET_DIR + OFFSET(gpio), val);
+   val |= 1  (gpio % 8);
+   ret = ci-write_reg(ci-stmpe, GPIO_SET_DIR + OFFSET(gpio), val);
+
+   stmpe_gpio_set_value(chip, gpio, value);
+
+   if (ret)
+   dev_err(chip-dev, couldn't change direction. Write 
failed!\n);
+
+   return 0;
+}
+
+static

[PATCH] ARM i.MX6: query silicon revision

[Steffen Trumtrar]

Read silicon revision from ???-register.
This is based on a7683867463481bfea84af4d60af832ddfb3da7f from u-boot.
The address 0x020c8260 is used and decoded. I haven't found that in my
datasheet, so I must trust the code to be correct.
At least on a SabreLite v1.0 I get the correct version though.

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 arch/arm/mach-imx/imx6.c |   36 +++-
 1 file changed, 35 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
index b6067d7..9c90444 100644
--- a/arch/arm/mach-imx/imx6.c
+++ b/arch/arm/mach-imx/imx6.c
@@ -19,7 +19,7 @@
 #include common.h
 #include io.h
 #include sizes.h
-#include mach/imx6-regs.h
+#include mach/imx-regs.h
 
 #include gpio.h
 
@@ -35,6 +35,40 @@ void *imx_gpio_base[] = {
 
 int imx_gpio_count = ARRAY_SIZE(imx_gpio_base) * 32;
 
+static u32 mx6_silicon_revision;
+static char *mx6_rev_string = unknown;
+
+int imx_silicon_revision(void)
+{
+   return mx6_silicon_revision;
+}
+
+static int query_silicon_revision(void)
+{
+   void __iomem *anatop = (void *) MX6_ANATOP_BASE_ADDR;
+   u32 rev, reg;
+
+   reg = readl(anatop + 0x260);
+   /* read mx6 variant: quad, dual, solo */
+   //rev = (reg  4)  0xff000;
+   rev = (reg  0xff) + 0x10;
+   switch (rev) {
+   case 0x10:
+   mx6_silicon_revision = IMX_CHIP_REV_1_0;
+   mx6_rev_string = 1.0;
+   break;
+   case 0x11:
+   mx6_silicon_revision = IMX_CHIP_REV_1_1;
+   mx6_rev_string = 1.1;
+   break;
+   default:
+   mx6_silicon_revision = 0;
+   }
+
+   return 0;
+}
+core_initcall(query_silicon_revision);
+
 void imx6_init_lowlevel(void)
 {
void __iomem *aips1 = (void *)MX6_AIPS1_ON_BASE_ADDR;
-- 
1.7.10.4


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Re: [PATCH] ARM i.MX6: query silicon revision

[Steffen Trumtrar]

On Sat, Sep 01, 2012 at 10:53:41AM +0200, Jean-Christophe PLAGNIOL-VILLARD 
wrote:
 On 15:55 Fri 31 Aug , Steffen Trumtrar wrote:
  Read silicon revision from ???-register.
  This is based on a7683867463481bfea84af4d60af832ddfb3da7f from u-boot.
  The address 0x020c8260 is used and decoded. I haven't found that in my
  datasheet, so I must trust the code to be correct.
  At least on a SabreLite v1.0 I get the correct version though.
  
  Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
  ---
   arch/arm/mach-imx/imx6.c |   36 +++-
   1 file changed, 35 insertions(+), 1 deletion(-)
  
  diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
  index b6067d7..9c90444 100644
  --- a/arch/arm/mach-imx/imx6.c
  +++ b/arch/arm/mach-imx/imx6.c
  @@ -19,7 +19,7 @@
   #include common.h
   #include io.h
   #include sizes.h
  -#include mach/imx6-regs.h
  +#include mach/imx-regs.h
   
   #include gpio.h
   
  @@ -35,6 +35,40 @@ void *imx_gpio_base[] = {
   
   int imx_gpio_count = ARRAY_SIZE(imx_gpio_base) * 32;
   
  +static u32 mx6_silicon_revision;
  +static char *mx6_rev_string = unknown;
  +
  +int imx_silicon_revision(void)
  +{
  +   return mx6_silicon_revision;
  +}
  +
  +static int query_silicon_revision(void)
  +{
  +   void __iomem *anatop = (void *) MX6_ANATOP_BASE_ADDR;
  +   u32 rev, reg;
  +
  +   reg = readl(anatop + 0x260);
  +   /* read mx6 variant: quad, dual, solo */
  +   //rev = (reg  4)  0xff000;
 ??

Tnx. I will fix that.

Regards,

Steffen

-- 
Pengutronix e.K.   | |
Industrial Linux Solutions | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0|
Amtsgericht Hildesheim, HRA 2686   | Fax:   +49-5121-206917- |

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[PATCH v2] ARM i.MX6: query silicon revision

[Steffen Trumtrar]

Read silicon revision from ???-register.
This is based on a7683867463481bfea84af4d60af832ddfb3da7f from u-boot.
The address 0x020c8260 is used and decoded. I haven't found that in my
datasheet, so I must trust the code to be correct.
At least on a SabreLite v1.0 I get the correct version though.

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 arch/arm/mach-imx/imx6.c |   34 +-
 1 file changed, 33 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
index b6067d7..fef0a00 100644
--- a/arch/arm/mach-imx/imx6.c
+++ b/arch/arm/mach-imx/imx6.c
@@ -19,7 +19,7 @@
 #include common.h
 #include io.h
 #include sizes.h
-#include mach/imx6-regs.h
+#include mach/imx-regs.h
 
 #include gpio.h
 
@@ -35,6 +35,38 @@ void *imx_gpio_base[] = {
 
 int imx_gpio_count = ARRAY_SIZE(imx_gpio_base) * 32;
 
+static u32 mx6_silicon_revision;
+static char *mx6_rev_string = unknown;
+
+int imx_silicon_revision(void)
+{
+   return mx6_silicon_revision;
+}
+
+static int query_silicon_revision(void)
+{
+   void __iomem *anatop = (void *) MX6_ANATOP_BASE_ADDR;
+   u32 rev, reg;
+
+   reg = readl(anatop + 0x260);
+   rev = (reg  0xff) + 0x10;
+   switch (rev) {
+   case 0x10:
+   mx6_silicon_revision = IMX_CHIP_REV_1_0;
+   mx6_rev_string = 1.0;
+   break;
+   case 0x11:
+   mx6_silicon_revision = IMX_CHIP_REV_1_1;
+   mx6_rev_string = 1.1;
+   break;
+   default:
+   mx6_silicon_revision = 0;
+   }
+
+   return 0;
+}
+core_initcall(query_silicon_revision);
+
 void imx6_init_lowlevel(void)
 {
void __iomem *aips1 = (void *)MX6_AIPS1_ON_BASE_ADDR;
-- 
1.7.10.4


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[PATCH v2 03/11] ARM i.MX1: add imx-gpio devices

[Steffen Trumtrar]

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 arch/arm/mach-imx/Kconfig |1 +
 arch/arm/mach-imx/imx1.c  |   18 +-
 2 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index ce5edaa..112dcb1 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -148,6 +148,7 @@ choice
 
 config ARCH_IMX1
bool i.MX1
+   select GPIOLIB
select CPU_ARM920T
 
 config ARCH_IMX21
diff --git a/arch/arm/mach-imx/imx1.c b/arch/arm/mach-imx/imx1.c
index 742a260..bdd4f74 100644
--- a/arch/arm/mach-imx/imx1.c
+++ b/arch/arm/mach-imx/imx1.c
@@ -19,13 +19,13 @@
 
 #include gpio.h
 
-void *imx_gpio_base[] = {
-   (void *)0x0021c000,
-   (void *)0x0021c100,
-   (void *)0x0021c200,
-   (void *)0x0021c300,
-};
-
-int imx_gpio_count = ARRAY_SIZE(imx_gpio_base) * 32;
-
+static int imx1_init(void)
+{
+   add_generic_device(imx-gpio, 0, NULL, 0x0021c000, 0x100, 
IORESOURCE_MEM, NULL);
+   add_generic_device(imx-gpio, 1, NULL, 0x0021c100, 0x100, 
IORESOURCE_MEM, NULL);
+   add_generic_device(imx-gpio, 2, NULL, 0x0021c200, 0x100, 
IORESOURCE_MEM, NULL);
+   add_generic_device(imx-gpio, 3, NULL, 0x0021c300, 0x100, 
IORESOURCE_MEM, NULL);
 
+   return 0;
+}
+coredevice_initcall(imx1_init);
-- 
1.7.10.4


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[PATCH v2 04/11] ARM i.MX21: add imx-gpio devices

[Steffen Trumtrar]

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 arch/arm/mach-imx/Kconfig |1 +
 arch/arm/mach-imx/imx21.c |   22 +-
 2 files changed, 14 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 112dcb1..c069ae8 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -153,6 +153,7 @@ config ARCH_IMX1
 
 config ARCH_IMX21
bool i.MX21
+   select GPIOLIB
select CPU_ARM926T
 
 config ARCH_IMX25
diff --git a/arch/arm/mach-imx/imx21.c b/arch/arm/mach-imx/imx21.c
index bbef33d..264477a 100644
--- a/arch/arm/mach-imx/imx21.c
+++ b/arch/arm/mach-imx/imx21.c
@@ -28,14 +28,18 @@ int imx_silicon_revision(void)
return CID;
 }
 
-void *imx_gpio_base[] = {
-   (void *)0x10015000,
-   (void *)0x10015100,
-   (void *)0x10015200,
-   (void *)0x10015300,
-   (void *)0x10015400,
-   (void *)0x10015500,
-};
+static int imx21_init(void)
+{
+   add_generic_device(imx_iim, 0, NULL, MX51_IIM_BASE_ADDR, SZ_4K,
+   IORESOURCE_MEM, NULL);
 
-int imx_gpio_count = ARRAY_SIZE(imx_gpio_base) * 32;
+   add_generic_device(imx-gpio, 0, NULL, 0x10015000, 0x100, 
IORESOURCE_MEM, NULL);
+   add_generic_device(imx-gpio, 1, NULL, 0x10015100, 0x100, 
IORESOURCE_MEM, NULL);
+   add_generic_device(imx-gpio, 2, NULL, 0x10015200, 0x100, 
IORESOURCE_MEM, NULL);
+   add_generic_device(imx-gpio, 3, NULL, 0x10015300, 0x100, 
IORESOURCE_MEM, NULL);
+   add_generic_device(imx-gpio, 4, NULL, 0x10015400, 0x100, 
IORESOURCE_MEM, NULL);
+   add_generic_device(imx-gpio, 5, NULL, 0x10015500, 0x100, 
IORESOURCE_MEM, NULL);
 
+   return 0;
+}
+coredevice_initcall(imx21_init);
-- 
1.7.10.4


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[PATCH v2 10/11] ARM i.MX53: add imx-gpio devices

[Steffen Trumtrar]

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 arch/arm/mach-imx/Kconfig |1 +
 arch/arm/mach-imx/imx53.c |   19 +++
 2 files changed, 8 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 9d7b931..0c09b57 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -188,6 +188,7 @@ config ARCH_IMX51
 config ARCH_IMX53
bool i.MX53
select CPU_V7
+   select GPIOLIB
select ARCH_HAS_FEC_IMX
 
 config ARCH_IMX6
diff --git a/arch/arm/mach-imx/imx53.c b/arch/arm/mach-imx/imx53.c
index 7c679bb..24530ad 100644
--- a/arch/arm/mach-imx/imx53.c
+++ b/arch/arm/mach-imx/imx53.c
@@ -26,18 +26,6 @@
 
 #include gpio.h
 
-void *imx_gpio_base[] = {
-   (void *)MX53_GPIO1_BASE_ADDR,
-   (void *)MX53_GPIO2_BASE_ADDR,
-   (void *)MX53_GPIO3_BASE_ADDR,
-   (void *)MX53_GPIO4_BASE_ADDR,
-   (void *)MX53_GPIO5_BASE_ADDR,
-   (void *)MX53_GPIO6_BASE_ADDR,
-   (void *)MX53_GPIO7_BASE_ADDR,
-};
-
-int imx_gpio_count = ARRAY_SIZE(imx_gpio_base) * 32;
-
 #define SI_REV 0x48
 
 static u32 mx53_silicon_revision;
@@ -88,6 +76,13 @@ static int imx53_init(void)
add_generic_device(imx_iim, 0, NULL, MX53_IIM_BASE_ADDR, SZ_4K,
IORESOURCE_MEM, NULL);
 
+   add_generic_device(imx-gpio, 0, NULL, MX53_GPIO1_BASE_ADDR, 0x1000, 
IORESOURCE_MEM, NULL);
+   add_generic_device(imx-gpio, 1, NULL, MX53_GPIO2_BASE_ADDR, 0x1000, 
IORESOURCE_MEM, NULL);
+   add_generic_device(imx-gpio, 2, NULL, MX53_GPIO3_BASE_ADDR, 0x1000, 
IORESOURCE_MEM, NULL);
+   add_generic_device(imx-gpio, 3, NULL, MX53_GPIO4_BASE_ADDR, 0x1000, 
IORESOURCE_MEM, NULL);
+   add_generic_device(imx-gpio, 4, NULL, MX53_GPIO5_BASE_ADDR, 0x1000, 
IORESOURCE_MEM, NULL);
+   add_generic_device(imx-gpio, 5, NULL, MX53_GPIO6_BASE_ADDR, 0x1000, 
IORESOURCE_MEM, NULL);
+   add_generic_device(imx-gpio, 6, NULL, MX53_GPIO7_BASE_ADDR, 0x1000, 
IORESOURCE_MEM, NULL);
return 0;
 }
 coredevice_initcall(imx53_init);
-- 
1.7.10.4


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[PATCH v2 0/2] Add stmpe mfd

[Steffen Trumtrar]

Hi,

this adds support for a stmpe1601 mfd connected via i2c.
This was only tested with the gpiolib support from the previous patch-series
ARM i.MX: add gpiolib support.

With v2 I added the dependency on gpiolib in the Kconfig file and removed the
hardcoded gpiobase by a platformdata-provided or dynamic gpiobase.

Regards,

Steffen


Steffen Trumtrar (2):
  mfd: add stmpe-i2c driver
  gpio: add driver for stmpe io-expander

 drivers/Kconfig   |1 +
 drivers/gpio/Kconfig  |9 +++
 drivers/gpio/Makefile |2 +
 drivers/gpio/gpio-stmpe.c |  162 +++
 drivers/mfd/Kconfig   |4 ++
 drivers/mfd/Makefile  |1 +
 drivers/mfd/stmpe-i2c.c   |  166 +
 include/mfd/stmpe-i2c.h   |   56 +++
 8 files changed, 401 insertions(+)
 create mode 100644 drivers/gpio/Kconfig
 create mode 100644 drivers/gpio/Makefile
 create mode 100644 drivers/gpio/gpio-stmpe.c
 create mode 100644 drivers/mfd/stmpe-i2c.c
 create mode 100644 include/mfd/stmpe-i2c.h

-- 
1.7.10.4


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[PATCH v3 1/2] mfd: add stmpe-i2c driver

[Steffen Trumtrar]

The stmpe mfds can be connected via i2c and spi. This driver provides the basic
infrastructure for the i2c kind. It can be added as a normal i2c-device in the
board code. To enable functions a platform_data struct has to be provided, that
describes what parts of the chip are to be used.

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 drivers/mfd/Kconfig |4 ++
 drivers/mfd/Makefile|1 +
 drivers/mfd/stmpe-i2c.c |  153 +++
 include/mfd/stmpe-i2c.h |   56 +
 4 files changed, 214 insertions(+)
 create mode 100644 drivers/mfd/stmpe-i2c.c
 create mode 100644 include/mfd/stmpe-i2c.h

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index af67935..20eef86 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -33,4 +33,8 @@ config I2C_TWL6030
select I2C_TWLCORE
bool TWL6030 driver
 
+config I2C_STMPE
+   depends on I2C
+   bool STMPE-i2c driver
+
 endmenu
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index e11223b..792ae2d 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_I2C_LP3972) += lp3972.o
 obj-$(CONFIG_I2C_TWLCORE) += twl-core.o
 obj-$(CONFIG_I2C_TWL4030) += twl4030.o
 obj-$(CONFIG_I2C_TWL6030) += twl6030.o
+obj-$(CONFIG_I2C_STMPE) += stmpe-i2c.o
diff --git a/drivers/mfd/stmpe-i2c.c b/drivers/mfd/stmpe-i2c.c
new file mode 100644
index 000..53b3d06
--- /dev/null
+++ b/drivers/mfd/stmpe-i2c.c
@@ -0,0 +1,153 @@
+/*
+ * Copyright (C) 2012 Pengutronix
+ * Steffen Trumtrar s.trumt...@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include common.h
+#include init.h
+#include driver.h
+#include xfuncs.h
+#include errno.h
+
+#include i2c/i2c.h
+#include mfd/stmpe-i2c.h
+
+#define DRIVERNAME stmpe-i2c
+
+#define to_stmpe(a)container_of(a, struct stmpe, cdev)
+
+int stmpe_reg_read(struct stmpe *stmpe, u32 reg, u8 *val)
+{
+   int ret;
+
+   ret = i2c_read_reg(stmpe-client, reg, val, 1);
+
+   return ret == 1 ? 0 : ret;
+}
+EXPORT_SYMBOL(stmpe_reg_read)
+
+int stmpe_reg_write(struct stmpe *stmpe, u32 reg, u8 val)
+{
+   int ret;
+
+   ret = i2c_write_reg(stmpe-client, reg, val, 1);
+
+   return ret == 1 ? 0 : ret;
+}
+EXPORT_SYMBOL(stmpe_reg_write)
+
+int stmpe_set_bits(struct stmpe *stmpe, u32 reg, u8 mask, u8 val)
+{
+   u8 tmp;
+   int err;
+
+   err = stmpe_reg_read(stmpe, reg, tmp);
+   tmp = (tmp  ~mask) | val;
+
+   if (!err)
+   err = stmpe_reg_write(stmpe, reg, tmp);
+
+   return err;
+}
+EXPORT_SYMBOL(stmpe_set_bits);
+
+static ssize_t stmpe_read(struct cdev *cdev, void *_buf, size_t count, loff_t 
offset, ulong flags)
+{
+   struct stmpe *stmpe = to_stmpe(cdev);
+   u8 *buf = _buf;
+   size_t i = count;
+   int err;
+
+   while (i) {
+   err = stmpe_reg_read(stmpe, offset, buf);
+   if (err)
+   return (ssize_t)err;
+   buf++;
+   i--;
+   offset++;
+   }
+
+   return count;
+}
+
+static ssize_t stmpe_write(struct cdev *cdev, const void *_buf, size_t count, 
loff_t offset, ulong flags)
+{
+   struct stmpe *stmpe = to_stmpe(cdev);
+   const u8 *buf = _buf;
+   size_t i = count;
+   int err;
+
+   while (i) {
+   err = stmpe_reg_write(stmpe, offset, *buf);
+   if (err)
+   return (ssize_t)err;
+   buf++;
+   i--;
+   offset++;
+   }
+
+   return count;
+}
+
+static struct file_operations stmpe_fops = {
+   .lseek  = dev_lseek_default,
+   .read   = stmpe_read,
+   .write  = stmpe_write,
+};
+
+static struct stmpe_client_info i2c_ci = {
+   .read_reg = stmpe_reg_read,
+   .write_reg = stmpe_reg_write,
+};
+
+static int stmpe_probe(struct device_d *dev)
+{
+   struct stmpe_platform_data *pdata = dev-platform_data;
+   struct stmpe *stmpe_dev;
+
+   if (!pdata) {
+   dev_dbg(dev, no platform data\n);
+   return -ENODEV;
+   }
+
+   stmpe_dev = xzalloc(sizeof(struct stmpe));
+   stmpe_dev-cdev.name = DRIVERNAME;
+   stmpe_dev-client = to_i2c_client(dev);
+   stmpe_dev-cdev.size = 191; /* 191 known registers */
+   stmpe_dev-cdev.dev = dev;
+   stmpe_dev-cdev.ops = stmpe_fops;
+   stmpe_dev-pdata = pdata;
+   dev-priv = stmpe_dev;
+   i2c_ci.stmpe

[PATCH v3 2/2] gpio: add driver for stmpe io-expander

[Steffen Trumtrar]

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 drivers/Kconfig   |1 +
 drivers/gpio/Kconfig  |9 +++
 drivers/gpio/Makefile |2 +
 drivers/gpio/gpio-stmpe.c |  162 +
 4 files changed, 174 insertions(+)
 create mode 100644 drivers/gpio/Kconfig
 create mode 100644 drivers/gpio/Makefile
 create mode 100644 drivers/gpio/gpio-stmpe.c

diff --git a/drivers/Kconfig b/drivers/Kconfig
index 883b0e7..adf8fcd 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -18,5 +18,6 @@ source drivers/input/Kconfig
 source drivers/watchdog/Kconfig
 source drivers/pwm/Kconfig
 source drivers/dma/Kconfig
+source drivers/gpio/Kconfig
 
 endmenu
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
new file mode 100644
index 000..acfd4ef
--- /dev/null
+++ b/drivers/gpio/Kconfig
@@ -0,0 +1,9 @@
+menu GPIO  
+
+config STMPE_GPIO
+   depends on I2C
+   depends on GPIOLIB
+   select I2C_STMPE
+   bool STMPE GPIO Expander
+
+endmenu
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
new file mode 100644
index 000..da1bc21
--- /dev/null
+++ b/drivers/gpio/Makefile
@@ -0,0 +1,2 @@
+obj-y += gpio.o
+obj-$(CONFIG_STMPE_GPIO) += gpio-stmpe.o
diff --git a/drivers/gpio/gpio-stmpe.c b/drivers/gpio/gpio-stmpe.c
new file mode 100644
index 000..0746458
--- /dev/null
+++ b/drivers/gpio/gpio-stmpe.c
@@ -0,0 +1,162 @@
+/*
+ * Copyright (C) 2012 Pengutronix
+ * Steffen Trumtrar s.trumt...@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include common.h
+#include errno.h
+#include io.h
+#include gpio.h
+#include init.h
+#include mfd/stmpe-i2c.h
+
+#define GPIO_BASE  0x80
+#define GPIO_SET   (GPIO_BASE + 0x02)
+#define GPIO_CLR   (GPIO_BASE + 0x04)
+#define GPIO_MP(GPIO_BASE + 0x06)
+#define GPIO_SET_DIR   (GPIO_BASE + 0x08)
+#define GPIO_ED(GPIO_BASE + 0x0a)
+#define GPIO_RE(GPIO_BASE + 0x0c)
+#define GPIO_FE(GPIO_BASE + 0x0e)
+#define GPIO_PULL_UP   (GPIO_BASE + 0x10)
+#define GPIO_AF(GPIO_BASE + 0x12)
+#define GPIO_LT(GPIO_BASE + 0x16)
+
+#define OFFSET(gpio)   (0xff  (1  (gpio)) ? 1 : 0)
+
+struct stmpe_gpio_chip {
+   struct gpio_chip chip;
+   struct stmpe_client_info *ci;
+};
+
+static void stmpe_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int 
value)
+{
+   struct stmpe_gpio_chip *stmpegpio = container_of(chip, struct 
stmpe_gpio_chip, chip);
+   struct stmpe_client_info *ci = (struct stmpe_client_info 
*)stmpegpio-ci;
+   int ret;
+   u8 val;
+
+   ci-read_reg(ci-stmpe, GPIO_MP + OFFSET(gpio), val);
+
+   val |= 1  (gpio % 8);
+
+   if (value)
+   ret = ci-write_reg(ci-stmpe, GPIO_SET + OFFSET(gpio), val);
+   else
+   ret = ci-write_reg(ci-stmpe, GPIO_CLR + OFFSET(gpio), val);
+
+   if (ret)
+   dev_err(chip-dev, write failed!\n);
+}
+
+static int stmpe_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
+{
+   struct stmpe_gpio_chip *stmpegpio = container_of(chip, struct 
stmpe_gpio_chip, chip);
+   struct stmpe_client_info *ci = (struct stmpe_client_info 
*)stmpegpio-ci;
+   int ret;
+   u8 val;
+
+   ci-read_reg(ci-stmpe, GPIO_SET_DIR + OFFSET(gpio), val);
+   val = ~(1  (gpio % 8));
+   ret = ci-write_reg(ci-stmpe, GPIO_SET_DIR + OFFSET(gpio), val);
+
+   if (ret)
+   dev_err(chip-dev, couldn't change direction. Write 
failed!\n);
+
+   return ret;
+}
+
+static int stmpe_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, 
int value)
+{
+   struct stmpe_gpio_chip *stmpegpio = container_of(chip, struct 
stmpe_gpio_chip, chip);
+   struct stmpe_client_info *ci = (struct stmpe_client_info 
*)stmpegpio-ci;
+   int ret;
+   u8 val;
+
+   ci-read_reg(ci-stmpe, GPIO_SET_DIR + OFFSET(gpio), val);
+   val |= 1  (gpio % 8);
+   ret = ci-write_reg(ci-stmpe, GPIO_SET_DIR + OFFSET(gpio), val);
+
+   stmpe_gpio_set_value(chip, gpio, value);
+
+   if (ret)
+   dev_err(chip-dev, couldn't change direction. Write 
failed!\n);
+
+   return ret;
+}
+
+static int stmpe_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
+{
+   struct stmpe_gpio_chip *stmpegpio = container_of(chip, struct 
stmpe_gpio_chip, chip);
+   struct stmpe_client_info *ci = (struct stmpe_client_info 
*)stmpegpio-ci;
+   u8 val

[PATCH v3 0/2] Add stmpe mfd

[Steffen Trumtrar]

Hi,

this fixes some issues with the v2 patches:
- remove unused variables
- allow multiple instances of stmpe-i2c
- remove unnecessary castings

Thanks to Sascha and Mark for reviewing.

Steffen Trumtrar (2):
  mfd: add stmpe-i2c driver
  gpio: add driver for stmpe io-expander

 drivers/Kconfig   |1 +
 drivers/gpio/Kconfig  |9 +++
 drivers/gpio/Makefile |2 +
 drivers/gpio/gpio-stmpe.c |  162 +
 drivers/mfd/Kconfig   |4 ++
 drivers/mfd/Makefile  |1 +
 drivers/mfd/stmpe-i2c.c   |  153 ++
 include/mfd/stmpe-i2c.h   |   56 
 8 files changed, 388 insertions(+)
 create mode 100644 drivers/gpio/Kconfig
 create mode 100644 drivers/gpio/Makefile
 create mode 100644 drivers/gpio/gpio-stmpe.c
 create mode 100644 drivers/mfd/stmpe-i2c.c
 create mode 100644 include/mfd/stmpe-i2c.h

-- 
1.7.10.4


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[PATCH v4 0/2] Add stmpe mfd

[Steffen Trumtrar]

Hi,

another day, another patch version. This version includes the following 
requests by
Sascha and Marc (Thanks again):
- remove all the iomem stuff in add_generic_device in stmpe-i2c.c
- allocate stmpe_client_info for every device, not just one
- remove unused struct fields
- remove extern for prototypes

Regards,
Steffen


Steffen Trumtrar (2):
  mfd: add stmpe-i2c driver
  gpio: add driver for stmpe io-expander

 drivers/Kconfig   |1 +
 drivers/gpio/Kconfig  |9 +++
 drivers/gpio/Makefile |2 +
 drivers/gpio/gpio-stmpe.c |  161 +
 drivers/mfd/Kconfig   |4 ++
 drivers/mfd/Makefile  |1 +
 drivers/mfd/stmpe-i2c.c   |  153 ++
 include/mfd/stmpe-i2c.h   |   53 +++
 8 files changed, 384 insertions(+)
 create mode 100644 drivers/gpio/Kconfig
 create mode 100644 drivers/gpio/Makefile
 create mode 100644 drivers/gpio/gpio-stmpe.c
 create mode 100644 drivers/mfd/stmpe-i2c.c
 create mode 100644 include/mfd/stmpe-i2c.h

-- 
1.7.10.4


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[PATCH v4 1/2] mfd: add stmpe-i2c driver

[Steffen Trumtrar]

The stmpe mfds can be connected via i2c and spi. This driver provides the basic
infrastructure for the i2c kind. It can be added as a normal i2c-device in the
board code. To enable functions a platform_data struct has to be provided, that
describes what parts of the chip are to be used.

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 drivers/mfd/Kconfig |4 ++
 drivers/mfd/Makefile|1 +
 drivers/mfd/stmpe-i2c.c |  153 +++
 include/mfd/stmpe-i2c.h |   53 
 4 files changed, 211 insertions(+)
 create mode 100644 drivers/mfd/stmpe-i2c.c
 create mode 100644 include/mfd/stmpe-i2c.h

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index af67935..20eef86 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -33,4 +33,8 @@ config I2C_TWL6030
select I2C_TWLCORE
bool TWL6030 driver
 
+config I2C_STMPE
+   depends on I2C
+   bool STMPE-i2c driver
+
 endmenu
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index e11223b..792ae2d 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_I2C_LP3972) += lp3972.o
 obj-$(CONFIG_I2C_TWLCORE) += twl-core.o
 obj-$(CONFIG_I2C_TWL4030) += twl4030.o
 obj-$(CONFIG_I2C_TWL6030) += twl6030.o
+obj-$(CONFIG_I2C_STMPE) += stmpe-i2c.o
diff --git a/drivers/mfd/stmpe-i2c.c b/drivers/mfd/stmpe-i2c.c
new file mode 100644
index 000..4af8b7b
--- /dev/null
+++ b/drivers/mfd/stmpe-i2c.c
@@ -0,0 +1,153 @@
+/*
+ * Copyright (C) 2012 Pengutronix
+ * Steffen Trumtrar s.trumt...@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include common.h
+#include init.h
+#include driver.h
+#include xfuncs.h
+#include errno.h
+
+#include i2c/i2c.h
+#include mfd/stmpe-i2c.h
+
+#define DRIVERNAME stmpe-i2c
+
+#define to_stmpe(a)container_of(a, struct stmpe, cdev)
+
+int stmpe_reg_read(struct stmpe *stmpe, u32 reg, u8 *val)
+{
+   int ret;
+
+   ret = i2c_read_reg(stmpe-client, reg, val, 1);
+
+   return ret == 1 ? 0 : ret;
+}
+EXPORT_SYMBOL(stmpe_reg_read)
+
+int stmpe_reg_write(struct stmpe *stmpe, u32 reg, u8 val)
+{
+   int ret;
+
+   ret = i2c_write_reg(stmpe-client, reg, val, 1);
+
+   return ret == 1 ? 0 : ret;
+}
+EXPORT_SYMBOL(stmpe_reg_write)
+
+int stmpe_set_bits(struct stmpe *stmpe, u32 reg, u8 mask, u8 val)
+{
+   u8 tmp;
+   int err;
+
+   err = stmpe_reg_read(stmpe, reg, tmp);
+   tmp = (tmp  ~mask) | val;
+
+   if (!err)
+   err = stmpe_reg_write(stmpe, reg, tmp);
+
+   return err;
+}
+EXPORT_SYMBOL(stmpe_set_bits);
+
+static ssize_t stmpe_read(struct cdev *cdev, void *_buf, size_t count, loff_t 
offset, ulong flags)
+{
+   struct stmpe *stmpe = to_stmpe(cdev);
+   u8 *buf = _buf;
+   size_t i = count;
+   int err;
+
+   while (i) {
+   err = stmpe_reg_read(stmpe, offset, buf);
+   if (err)
+   return (ssize_t)err;
+   buf++;
+   i--;
+   offset++;
+   }
+
+   return count;
+}
+
+static ssize_t stmpe_write(struct cdev *cdev, const void *_buf, size_t count, 
loff_t offset, ulong flags)
+{
+   struct stmpe *stmpe = to_stmpe(cdev);
+   const u8 *buf = _buf;
+   size_t i = count;
+   int err;
+
+   while (i) {
+   err = stmpe_reg_write(stmpe, offset, *buf);
+   if (err)
+   return (ssize_t)err;
+   buf++;
+   i--;
+   offset++;
+   }
+
+   return count;
+}
+
+static struct file_operations stmpe_fops = {
+   .lseek  = dev_lseek_default,
+   .read   = stmpe_read,
+   .write  = stmpe_write,
+};
+
+static int stmpe_probe(struct device_d *dev)
+{
+   struct stmpe_platform_data *pdata = dev-platform_data;
+   struct stmpe *stmpe_dev;
+   struct stmpe_client_info *i2c_ci;
+
+   if (!pdata) {
+   dev_dbg(dev, no platform data\n);
+   return -ENODEV;
+   }
+
+   stmpe_dev = xzalloc(sizeof(struct stmpe));
+   stmpe_dev-cdev.name = DRIVERNAME;
+   stmpe_dev-client = to_i2c_client(dev);
+   stmpe_dev-cdev.size = 191; /* 191 known registers */
+   stmpe_dev-cdev.dev = dev;
+   stmpe_dev-cdev.ops = stmpe_fops;
+   stmpe_dev-pdata = pdata;
+   dev-priv = stmpe_dev;
+
+   i2c_ci = xzalloc(sizeof(struct stmpe_client_info));
+   i2c_ci-stmpe = stmpe_dev

[PATCH 1/2] ARM i.MX6: add usb function prototypes

[Steffen Trumtrar]

Add missing prototypes to mach/usb.h

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 arch/arm/mach-imx/include/mach/usb.h |3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-imx/include/mach/usb.h 
b/arch/arm/mach-imx/include/mach/usb.h
index 5d6670d..d953bf0 100644
--- a/arch/arm/mach-imx/include/mach/usb.h
+++ b/arch/arm/mach-imx/include/mach/usb.h
@@ -11,4 +11,7 @@
 #define MX35_H1_USBTE_BIT  (1  4)
 #define MXC_EHCI_INTERFACE_SINGLE_UNI  (2  0)
 
+
+int imx6_usb_phy1_disable_oc(void);
+int imx6_usb_phy1_enable(void);
 #endif /* __MACH_USB_H_*/
-- 
1.7.10.4


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[PATCH 2/2] ARM i.MX6: fix usb_ehci warnings for sabrelite

[Steffen Trumtrar]

This fixes the following warnings:

arch/arm/boards/freescale-mx6-sabrelite/board.c: In function 
'sabrelite_ehci_init':
arch/arm/boards/freescale-mx6-sabrelite/board.c:265:2: warning: implicit 
declaration of function 'imx6_usb_phy1_disable_oc' 
[-Wimplicit-function-declaration]
arch/arm/boards/freescale-mx6-sabrelite/board.c:266:2: warning: implicit 
declaration of function 'imx6_usb_phy1_enable' [-Wimplicit-function-declaration]

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de

---
 arch/arm/boards/freescale-mx6-sabrelite/board.c |1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boards/freescale-mx6-sabrelite/board.c 
b/arch/arm/boards/freescale-mx6-sabrelite/board.c
index 1ac401e..c5bcf8b 100644
--- a/arch/arm/boards/freescale-mx6-sabrelite/board.c
+++ b/arch/arm/boards/freescale-mx6-sabrelite/board.c
@@ -40,6 +40,7 @@
 #include mach/gpio.h
 #include spi/spi.h
 #include mach/spi.h
+#include mach/usb.h
 
 #define SABRELITE_SD3_WP   IMX_GPIO_NR(7, 1)
 #define SABRELITE_SD3_CD   IMX_GPIO_NR(7, 0)
-- 
1.7.10.4


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[PATCH] stringlist: fix cpp macro in header

[Steffen Trumtrar]

Both include/string.h and include/stringlist.h define the c preprocessor macro
__STRING_H. This leads to a compile time error, in case both files are
(indirectly) included.

Rename the macro to __STRINGLIST_H in stringlist.h.

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 include/stringlist.h |6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/include/stringlist.h b/include/stringlist.h
index dd3f623..8738137 100644
--- a/include/stringlist.h
+++ b/include/stringlist.h
@@ -1,5 +1,5 @@
-#ifndef __STRING_H
-#define __STRING_H
+#ifndef __STRINGLIST_H
+#define __STRINGLIST_H
 
 #include linux/list.h
 
@@ -29,4 +29,4 @@ static inline void string_list_free(struct string_list *sl)
}
 }
 
-#endif /* __STRING_H */
+#endif /* __STRINGLIST_H */
-- 
1.7.10.4


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Re: [RFC PATCH] ARM i.MX6: Add support for SabreSD board

[Steffen Trumtrar]

Hi Hubert!

On Tue, Feb 05, 2013 at 05:53:54PM +0100, Hubert Feurstein wrote:
 Signed-off-by: Hubert Feurstein h.feurst...@gmail.com
 ---
  Ethernet is not working yet. I took over the initialisation from u-boot.
  Phy access seems to work, but I don't get any data out. 
  So some help is very appreciated ...
 
  Best regards
  Hubert
 
  arch/arm/Makefile  |   1 +
  arch/arm/boards/freescale-mx6-sabresd/Makefile |   4 +
  arch/arm/boards/freescale-mx6-sabresd/board.c  | 271 
 +
  arch/arm/boards/freescale-mx6-sabresd/config.h |   4 +
  .../freescale-mx6-sabresd/env/init/config-board|   7 +
  .../boards/freescale-mx6-sabresd/flash_header.c| 181 ++
  arch/arm/boards/freescale-mx6-sabresd/lowlevel.c   |  10 +
  arch/arm/configs/freescale-mx6-sabresd_defconfig   |  71 ++
  arch/arm/mach-imx/Kconfig  |   5 +
  9 files changed, 554 insertions(+)
  create mode 100644 arch/arm/boards/freescale-mx6-sabresd/Makefile
  create mode 100644 arch/arm/boards/freescale-mx6-sabresd/board.c
  create mode 100644 arch/arm/boards/freescale-mx6-sabresd/config.h
  create mode 100644 
 arch/arm/boards/freescale-mx6-sabresd/env/init/config-board
  create mode 100644 arch/arm/boards/freescale-mx6-sabresd/flash_header.c
  create mode 100644 arch/arm/boards/freescale-mx6-sabresd/lowlevel.c
  create mode 100644 arch/arm/configs/freescale-mx6-sabresd_defconfig
 
 diff --git a/arch/arm/Makefile b/arch/arm/Makefile
 index fcb2969..55290a9 100644
 --- a/arch/arm/Makefile
 +++ b/arch/arm/Makefile
 @@ -157,6 +157,7 @@ board-$(CONFIG_MACH_SABRELITE):= 
 freescale-mx6-sabrelite
  board-$(CONFIG_MACH_TX53):= karo-tx53
  board-$(CONFIG_MACH_GUF_VINCELL) := guf-vincell
  board-$(CONFIG_MACH_EFIKA_MX_SMARTBOOK)  := efika-mx-smartbook
 +board-$(CONFIG_MACH_SABRESD) := freescale-mx6-sabresd
  
  machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
  
 diff --git a/arch/arm/boards/freescale-mx6-sabresd/Makefile 
 b/arch/arm/boards/freescale-mx6-sabresd/Makefile
 new file mode 100644
 index 000..21fb7d9
 --- /dev/null
 +++ b/arch/arm/boards/freescale-mx6-sabresd/Makefile
 @@ -0,0 +1,4 @@
 +obj-y += board.o flash_header.o
 +pbl-y += flash_header.o
 +obj-y += lowlevel.o
 +pbl-y += lowlevel.o
 diff --git a/arch/arm/boards/freescale-mx6-sabresd/board.c 
 b/arch/arm/boards/freescale-mx6-sabresd/board.c
 new file mode 100644
 index 000..d341cf9
 --- /dev/null
 +++ b/arch/arm/boards/freescale-mx6-sabresd/board.c
 @@ -0,0 +1,271 @@
 +/*
 + * Copyright (C) 2013 Hubert Feurstein h.feurst...@gmail.com
 + *
 + * based on arch/arm/boards/freescale-mx6-sabrelite/board.c
 + * Copyright (C) 2012 Steffen Trumtrar, Pengutronix
 + *
 + * This program is free software; you can redistribute it and/or
 + * modify it under the terms of the GNU General Public License as
 + * published by the Free Software Foundation; either version 2 of
 + * the License, or (at your option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful,
 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 + * GNU General Public License for more details.
 + */
 +
 +#include common.h
 +#include init.h
 +#include environment.h
 +#include mach/imx6-regs.h
 +#include fec.h
 +#include mach/gpio.h
 +#include asm/armlinux.h
 +#include generated/mach-types.h
 +#include partition.h
 +#include linux/phy.h
 +#include asm/io.h
 +#include asm/mmu.h
 +#include mach/generic.h
 +#include sizes.h
 +#include net.h
 +#include mach/imx6.h
 +#include mach/devices-imx6.h
 +#include mach/iomux-mx6.h
 +#include mach/gpio.h
 +#include spi/spi.h
 +#include mach/spi.h
 +#include mach/usb.h
 +
 +#define SABRESD_SD2_CD   IMX_GPIO_NR(2, 2)
 +#define SABRESD_SD2_WP   IMX_GPIO_NR(2, 3)
 +
 +#define SABRESD_SD3_CD   IMX_GPIO_NR(2, 0)
 +#define SABRESD_SD3_WP   IMX_GPIO_NR(2, 1)
 +
 +static iomux_v3_cfg_t sabresd_pads[] = {
 + /* UART1 */
 + MX6Q_PAD_CSI0_DAT11__UART1_RXD,
 + MX6Q_PAD_CSI0_DAT10__UART1_TXD,
 +
 + /* SD2 */
 + MX6Q_PAD_SD2_CLK__USDHC2_CLK,
 + MX6Q_PAD_SD2_CMD__USDHC2_CMD,
 + MX6Q_PAD_SD2_DAT0__USDHC2_DAT0,
 + MX6Q_PAD_SD2_DAT1__USDHC2_DAT1,
 + MX6Q_PAD_SD2_DAT2__USDHC2_DAT2,
 + MX6Q_PAD_SD2_DAT3__USDHC2_DAT3,
 + MX6Q_PAD_NANDF_D4__USDHC2_DAT4,
 + MX6Q_PAD_NANDF_D5__USDHC2_DAT5,
 + MX6Q_PAD_NANDF_D6__USDHC2_DAT6,
 + MX6Q_PAD_NANDF_D7__USDHC2_DAT7,
 + MX6Q_PAD_NANDF_D2__GPIO_2_2,/* CD */
 + MX6Q_PAD_NANDF_D3__GPIO_2_3,/* WP */
 +
 + /* SD3 */
 + MX6Q_PAD_SD3_CMD__USDHC3_CMD,
 + MX6Q_PAD_SD3_CLK__USDHC3_CLK,
 + MX6Q_PAD_SD3_DAT0__USDHC3_DAT0,
 + MX6Q_PAD_SD3_DAT1__USDHC3_DAT1,
 + MX6Q_PAD_SD3_DAT2__USDHC3_DAT2,
 + MX6Q_PAD_SD3_DAT3__USDHC3_DAT3,
 + MX6Q_PAD_SD3_DAT4__USDHC3_DAT4

[PATCH] ARM i.MX28: change default watchdog reset method

[Steffen Trumtrar]

The default setting for the imx28 watchdog is to do a power-off reset. If the
SoC is only powered via battery, then the watchdog powers the chip down, though.
According to the datasheet it should still be possible to execute a proper POR
with battery power, but testing showed otherwise.
When the watchdog power-off reset is disabled, a software reset is executed
instead. This works with and without battery power.

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 arch/arm/mach-mxs/soc-imx28.c |   12 
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/mach-mxs/soc-imx28.c b/arch/arm/mach-mxs/soc-imx28.c
index a181b75..a5f3d68 100644
--- a/arch/arm/mach-mxs/soc-imx28.c
+++ b/arch/arm/mach-mxs/soc-imx28.c
@@ -21,6 +21,7 @@
 
 #define HW_CLKCTRL_RESET 0x1e0
 # define HW_CLKCTRL_RESET_CHIP (1  1)
+#define HW_CLKCTRL_WDOG_POR_DISABLE (1  5)
 
 /* Reset the full i.MX28 SoC via a chipset feature */
 void __noreturn reset_cpu(unsigned long addr)
@@ -35,3 +36,14 @@ void __noreturn reset_cpu(unsigned long addr)
/*NOTREACHED*/
 }
 EXPORT_SYMBOL(reset_cpu);
+
+static int imx28_init(void)
+{
+   /*
+* The default setting for the WDT is to do a POR. If the SoC is only
+* powered via battery, then a WDT reset powers the chip down instead
+* of resetting it. Use a software reset only.
+*/
+   writel(HW_CLKCTRL_WDOG_POR_DISABLE, IMX_CCM_BASE + HW_CLKCTRL_RESET);
+}
+postcore_initcall(imx28_init);
-- 
1.7.10.4


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Re: [PATCH 0/5] Zynq support for barebox

[Steffen Trumtrar]

Hi!

On Sat, Mar 02, 2013 at 07:20:12PM -0600, Josh Cartwright wrote:
 In San Francisco a couple weeks ago (ELC2013), Thomas Petazzoni
 informally mentioned barebox in passing, so I decided to toy with it a
 bit...
 
 This patchset adds basic support for the Zynq SoC to barebox.  So far,
 it's only been tested as a 'secondary' bootloader (after u-boot).  Also
 added is support for the zc702 development board.
 

I have some patches laying around, that have support for booting first stage
from a SD-Card on a ZedBoard. I didn't send them as of yet, because I'm not
completely satisfied with them in one or two places. (The clocksource seems to
be inverse to what barebox expects, which would be a quick fix, and barebox 
boots
uuultra slow, if I do everything according to the TRM)
At the moment, I do not have access to the board though. But I hope I can get a
hand on it in the next days.
What I do not have atm is the clkdev stuff, that you already have.

Regards,
Steffen

 The first two patches are simple typos I found getting acclimated to the
 barebox source.
 
 Josh Cartwright (5):
   trivial: doc: fix typos in mach-arm.dox
   defaultenv: fixed mismatched braces in bin/boot
   ARM: zynq: add driver for Zynq uarts
   ARM: zynq: add support for Zynq 7000 SoC
   ARM: zynq: add support for zc702 development board
 
  arch/arm/Kconfig   |   9 +
  arch/arm/Makefile  |   2 +
  arch/arm/boards/zynq-zc702/Makefile|   1 +
  arch/arm/boards/zynq-zc702/config.h|   0
  arch/arm/boards/zynq-zc702/devices.c   |  70 ++
  arch/arm/boards/zynq-zc702/lowlevel.c  |  28 +++
  arch/arm/mach-arm.dox  |   4 +-
  arch/arm/mach-zynq/Kconfig |  22 ++
  arch/arm/mach-zynq/Makefile|   1 +
  arch/arm/mach-zynq/clocks.c| 341 
 +
  arch/arm/mach-zynq/include/mach/clkdev.h   |   7 +
  arch/arm/mach-zynq/include/mach/debug_ll.h |  21 ++
  arch/arm/mach-zynq/include/mach/slcr.h |  26 +++
  arch/arm/mach-zynq/reset.c |  28 +++
  defaultenv/bin/boot|   2 +-
  drivers/serial/Kconfig |   6 +
  drivers/serial/Makefile|   1 +
  drivers/serial/serial_zynq.c   | 144 
  18 files changed, 710 insertions(+), 3 deletions(-)
  create mode 100644 arch/arm/boards/zynq-zc702/Makefile
  create mode 100644 arch/arm/boards/zynq-zc702/config.h
  create mode 100644 arch/arm/boards/zynq-zc702/devices.c
  create mode 100644 arch/arm/boards/zynq-zc702/lowlevel.c
  create mode 100644 arch/arm/mach-zynq/Kconfig
  create mode 100644 arch/arm/mach-zynq/Makefile
  create mode 100644 arch/arm/mach-zynq/clocks.c
  create mode 100644 arch/arm/mach-zynq/include/mach/clkdev.h
  create mode 100644 arch/arm/mach-zynq/include/mach/debug_ll.h
  create mode 100644 arch/arm/mach-zynq/include/mach/slcr.h
  create mode 100644 arch/arm/mach-zynq/reset.c
  create mode 100644 drivers/serial/serial_zynq.c
 
 -- 
 1.8.1.2
 
 
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Re: [PATCH 0/5] Zynq support for barebox

[Steffen Trumtrar]

On Tue, Mar 05, 2013 at 11:09:29AM -0600, Josh Cartwright wrote:
 On Sun, Mar 03, 2013 at 03:58:10PM +0100, Steffen Trumtrar wrote:
  Hi!
  
  On Sat, Mar 02, 2013 at 07:20:12PM -0600, Josh Cartwright wrote:
   In San Francisco a couple weeks ago (ELC2013), Thomas Petazzoni
   informally mentioned barebox in passing, so I decided to toy with it a
   bit...
   
   This patchset adds basic support for the Zynq SoC to barebox.  So far,
   it's only been tested as a 'secondary' bootloader (after u-boot).  Also
   added is support for the zc702 development board.
   
  
  I have some patches laying around, that have support for booting first stage
  from a SD-Card on a ZedBoard. I didn't send them as of yet, because I'm not
  completely satisfied with them in one or two places. (The clocksource seems 
  to
  be inverse to what barebox expects, which would be a quick fix, and barebox 
  boots
  uuultra slow, if I do everything according to the TRM)
  At the moment, I do not have access to the board though. But I hope I can 
  get a
  hand on it in the next days.
 
 If you have a chance to send out what you have, I'd be curious to see
 it.  Fortunately I have several Zynq boards to play with.
 

Hi!

Have a look at
http://git.pengutronix.de/?p=str/barebox.git;a=summary

I stole your clk driver and added it to my patch stack :-)
Current state for ZedBoard:
- boot first stage from SD-Card
- barebox.bin needs to be processed with
./scripts/zynq_checksum barebox.bin BOOT.bin
to have the checksum in the BootROM header
- clocksource is arm_smp_tmd at seems accurate
- the BootROM needs about 4-5 seconds to copy barebox from
  SD to the OCM. I guess, I need to mess with the SD setup
  in the BootROM somehow
- just enough clkdev to use the timer
- all pinctrl, clk setup etc happens in the lowlevel init

Regards,
Steffen

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Re: [PATCH 0/5] Zynq support for barebox

[Steffen Trumtrar]

On Thu, Mar 07, 2013 at 04:46:25PM -0600, Josh Cartwright wrote:
 On Wed, Mar 06, 2013 at 06:28:50PM +0100, Steffen Trumtrar wrote:
  On Tue, Mar 05, 2013 at 11:09:29AM -0600, Josh Cartwright wrote:
 [..]
I have some patches laying around, that have support for booting first 
stage
from a SD-Card on a ZedBoard. I didn't send them as of yet, because I'm 
not
completely satisfied with them in one or two places. (The clocksource 
seems to
be inverse to what barebox expects, which would be a quick fix, and 
barebox boots
uuultra slow, if I do everything according to the TRM)
At the moment, I do not have access to the board though. But I hope I 
can get a
hand on it in the next days.
   
   If you have a chance to send out what you have, I'd be curious to see
   it.  Fortunately I have several Zynq boards to play with.
   
  
  Hi!
  
  Have a look at
  http://git.pengutronix.de/?p=str/barebox.git;a=summary
  
  I stole your clk driver and added it to my patch stack :-)
  Current state for ZedBoard:
  - boot first stage from SD-Card
  - barebox.bin needs to be processed with
  ./scripts/zynq_checksum barebox.bin BOOT.bin
  to have the checksum in the BootROM header
  - clocksource is arm_smp_tmd at seems accurate
  - the BootROM needs about 4-5 seconds to copy barebox from
SD to the OCM. I guess, I need to mess with the SD setup
in the BootROM somehow
  - just enough clkdev to use the timer
  - all pinctrl, clk setup etc happens in the lowlevel init

Hi Josh!

 
 Hey Steffen-
 
 Thanks for sharing this! I'll be looking to get board support for the
 zc702 on top of your work this weekend (I have several Zynq boards, but
 none of them are ZedBoards).  I'm also in the process of porting the
 uboot zynq_gem driver.

First, \o/. I don't know how the two differ. But I would guess, that
you can pretty much copy the lowlevel stuff et al.
Only the DDR timing stuff may make problems.

Second: No! Don't! I'm trying to get drivers/net/macb.c running on Zynq.
As far as I can tell at the moment, this is a driver for a
Cadence IP gem. And the zynq uses exactly that IP core.
Alas, I have problems with the dma_alloc_coherent call in its
probe function.

The same goes for the UART driver and other cores. We should not start
developing Xilinx drivers for everything, if in reality we have IP cores
from other providers.

The same goes for Linux. I haven't managed to boot mainline linux yet,
but I saw that there are multiple bindings and drivers for Xilinx.
And the TRM clearly states, that WDT, GEM, SPI, UART and TTC are all
Cadence IP cores.

 Do you have plans for submitting this to the list?

Yes, definitely! I need to cleanup the patches a little and want to
be sure that I didn't do anything stupidly wrong. The problem with
dma_alloc is at least a hint, that I maybe did.

Regards,
Steffen

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Re: [PATCH 0/5] Zynq support for barebox

[Steffen Trumtrar]

On Fri, Mar 08, 2013 at 10:10:11AM -0600, Josh Cartwright wrote:
 On Fri, Mar 08, 2013 at 07:39:18AM +0100, Steffen Trumtrar wrote:
  On Thu, Mar 07, 2013 at 04:46:25PM -0600, Josh Cartwright wrote:
   On Wed, Mar 06, 2013 at 06:28:50PM +0100, Steffen Trumtrar wrote:
On Tue, Mar 05, 2013 at 11:09:29AM -0600, Josh Cartwright wrote:
   [..]
  I have some patches laying around, that have support for booting 
  first stage
  from a SD-Card on a ZedBoard. I didn't send them as of yet, because 
  I'm not
  completely satisfied with them in one or two places. (The 
  clocksource seems to
  be inverse to what barebox expects, which would be a quick fix, and 
  barebox boots
  uuultra slow, if I do everything according to the TRM)
  At the moment, I do not have access to the board though. But I hope 
  I can get a
  hand on it in the next days.
 
 If you have a chance to send out what you have, I'd be curious to see
 it.  Fortunately I have several Zynq boards to play with.
 

Hi!

Have a look at
http://git.pengutronix.de/?p=str/barebox.git;a=summary

I stole your clk driver and added it to my patch stack :-)
Current state for ZedBoard:
- boot first stage from SD-Card
- barebox.bin needs to be processed with
./scripts/zynq_checksum barebox.bin BOOT.bin
to have the checksum in the BootROM header
- clocksource is arm_smp_tmd at seems accurate
- the BootROM needs about 4-5 seconds to copy barebox from
  SD to the OCM. I guess, I need to mess with the SD setup
  in the BootROM somehow
- just enough clkdev to use the timer
- all pinctrl, clk setup etc happens in the lowlevel init
  
  Hi Josh!
  
   Hey Steffen-
   
   Thanks for sharing this! I'll be looking to get board support for the
   zc702 on top of your work this weekend (I have several Zynq boards, but
   none of them are ZedBoards).  I'm also in the process of porting the
   uboot zynq_gem driver.
  
  First, \o/. I don't know how the two differ. But I would guess, that
  you can pretty much copy the lowlevel stuff et al.
  Only the DDR timing stuff may make problems.
  
  Second: No! Don't! I'm trying to get drivers/net/macb.c running on Zynq.
  As far as I can tell at the moment, this is a driver for a
  Cadence IP gem. And the zynq uses exactly that IP core.
  Alas, I have problems with the dma_alloc_coherent call in its
  probe function.
 
 Doh!  I certainly did not want to duplicate a driver unnecessarily.
 I'll keep this in mind going forward.


Just a quick note: it seems that the macb can be used. I didn't manage to
get a connection yet. But I can talk to the phy, get a link etc.

So, the linux macb driver should work two.

Regards,
Steffen


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Re: [PATCH 0/5] Zynq support for barebox

[Steffen Trumtrar]

Hi,

On Fri, Mar 08, 2013 at 01:20:47PM +0100, Michal Simek wrote:
 Hi,
 
 2013/3/8 Steffen Trumtrar s.trumt...@pengutronix.de:
  On Thu, Mar 07, 2013 at 04:46:25PM -0600, Josh Cartwright wrote:
  On Wed, Mar 06, 2013 at 06:28:50PM +0100, Steffen Trumtrar wrote:
   On Tue, Mar 05, 2013 at 11:09:29AM -0600, Josh Cartwright wrote:
  [..]
 I have some patches laying around, that have support for booting 
 first stage
 from a SD-Card on a ZedBoard. I didn't send them as of yet, because 
 I'm not
 completely satisfied with them in one or two places. (The 
 clocksource seems to
 be inverse to what barebox expects, which would be a quick fix, and 
 barebox boots
 uuultra slow, if I do everything according to the TRM)
 At the moment, I do not have access to the board though. But I hope 
 I can get a
 hand on it in the next days.
   
If you have a chance to send out what you have, I'd be curious to see
it.  Fortunately I have several Zynq boards to play with.
   
  
   Hi!
  
   Have a look at
   http://git.pengutronix.de/?p=str/barebox.git;a=summary
  
   I stole your clk driver and added it to my patch stack :-)
   Current state for ZedBoard:
   - boot first stage from SD-Card
   - barebox.bin needs to be processed with
   ./scripts/zynq_checksum barebox.bin BOOT.bin
   to have the checksum in the BootROM header
   - clocksource is arm_smp_tmd at seems accurate
   - the BootROM needs about 4-5 seconds to copy barebox from
 SD to the OCM. I guess, I need to mess with the SD setup
 in the BootROM somehow
   - just enough clkdev to use the timer
   - all pinctrl, clk setup etc happens in the lowlevel init
 
 Nice. What's the difference between this barebox and u-boot?
 I remember that discussion on u-boot mailing list.
 Is it just that Kconfig stuff and driver initialization?
 
 What about DT support? Initialized u-boot from device tree?
 Is it there?
 

Well, I don't actually know, what u-boot can do, as I do not follow it.
barebox uses Kconfig, the linux driver model, a lot less #ifdefs, has
support for a compressed bootloader, that extracts itself, the environment
system is IHMO way better than in u-boot, a menu, where you can select the
bootsource etc, you can boot images via tftp with bootm /mnt/tftp/zImage,
you can boot zImage, uImage, ... with appended DT, with separate DT,
there is support for DT probing of devices.
What I like the most: if you know linux kernel and its structure, you know
barebox and its structure (well, mostly).

 
  Thanks for sharing this! I'll be looking to get board support for the
  zc702 on top of your work this weekend (I have several Zynq boards, but
  none of them are ZedBoards).  I'm also in the process of porting the
  uboot zynq_gem driver.
 
  First, \o/. I don't know how the two differ. But I would guess, that
  you can pretty much copy the lowlevel stuff et al.
  Only the DDR timing stuff may make problems.
 
 Difference is only in connection out of chip. How barebox handle this?

barebox has /arch/arm/boards/avnet-zedboard/board.c, here you can define
the boardspecific pincontrol etc. Well, like the platformcode in the kernel.
For the zynq there is no pinctrl driver though, as I have to write it first :-)

Clocks are handled like in linux. With clockdev and clocktree.

ATM this is all hardcoded in the lowlevel init.

 Serial IP selections, ddr size, mmc, etc.
 
 
  Second: No! Don't! I'm trying to get drivers/net/macb.c running on Zynq.
  As far as I can tell at the moment, this is a driver for a
  Cadence IP gem. And the zynq uses exactly that IP core.
  Alas, I have problems with the dma_alloc_coherent call in its
  probe function.
 
 Nice. I will look forward on input from this. We need to use this IP
 in linux kernel too.
 
 
  The same goes for the UART driver and other cores. We should not start
  developing Xilinx drivers for everything, if in reality we have IP cores
  from other providers.
 
 definitely.
 
  The same goes for Linux. I haven't managed to boot mainline linux yet,
  but I saw that there are multiple bindings and drivers for Xilinx.
  And the TRM clearly states, that WDT, GEM, SPI, UART and TTC are all
  Cadence IP cores.
 
 yep, pl330, cadence gem, spi not sure, wdt also not sure, xilinx uart
 is in the mainline
 and none reports that there is cadence serial driver too.
 TTC is also news for me.
 If you can point me to them, that will be great.
 
Well, I don't know if there are drivers for all those IPs, but if there
aren't any, they should be called cadence-something with the according
bindings. Oh, and Arasan-something for the SD-Controller.

Well, maybe those IPs are even not really developed by Cadence and compatible
to other drivers, who knows.
For the Synopsys USB controller you might want to take a look at the ChipIdea
driver (ci13xxx-something). It is the same core ;-)

 
  Do you have plans for submitting

[PATCH 6/9] ARM: zynq: clk: replace define with header

[Steffen Trumtrar]

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 arch/arm/mach-zynq/clk-zynq7000.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/arch/arm/mach-zynq/clk-zynq7000.c 
b/arch/arm/mach-zynq/clk-zynq7000.c
index 8dbde2b..5a8a12a 100644
--- a/arch/arm/mach-zynq/clk-zynq7000.c
+++ b/arch/arm/mach-zynq/clk-zynq7000.c
@@ -25,10 +25,9 @@
 #include linux/clk.h
 #include linux/clkdev.h
 #include linux/err.h
+#include mach/zynq7000-regs.h
 #include malloc.h
 
-#define ZYNQ_SLCR_BASE 0xF800
-
 enum zynq_clks {
dummy, ps_clk, arm_pll, ddr_pll, io_pll, uart_clk, uart0, uart1,
cpu_clk, cpu_6x4x, cpu_3x2x, cpu_2x, cpu_1x, clks_max
-- 
1.8.2.rc2


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[PATCH 0/9] ARM: add support for Zynq

[Steffen Trumtrar]

Hi!

This series adds basic support for Xilinx Zynq based SoCs.
Atm one can boot first stage from SD card and ... that is it.
Ethernet support is on its way, but not functional as of yet.

Regards,
str


Josh Cartwright (1):
  ARM: zynq: add clk support for zynq7000

Steffen Trumtrar (8):
  serial: Add driver for Cadence UART
  ARM: Zynq: Add new architecture zynq
  ARM: zynq: add zynq fsbl checksum script
  ARM: zynq: Add support for the Avnet Zedboard
  ARM: zynq: clk: replace define with header
  ARM: zynq: clk: add pll type
  ARM: zynq: clk: convert to platform driver
  ARM: zynq: remove clocksource

 arch/arm/Kconfig   |   5 +
 arch/arm/Makefile  |   2 +
 arch/arm/boards/avnet-zedboard/Makefile|   1 +
 arch/arm/boards/avnet-zedboard/board.c |  38 ++
 arch/arm/boards/avnet-zedboard/config.h|   4 +
 .../boards/avnet-zedboard/env/init/config-board|   7 +
 arch/arm/boards/avnet-zedboard/flash_header.c  |  56 +++
 arch/arm/boards/avnet-zedboard/lowlevel.c  | 249 +
 arch/arm/configs/zedboard_defconfig| 360 +++
 arch/arm/mach-zynq/Kconfig |  35 ++
 arch/arm/mach-zynq/Makefile|   1 +
 arch/arm/mach-zynq/clk-zynq7000.c  | 393 +
 arch/arm/mach-zynq/devices.c   |  14 +
 arch/arm/mach-zynq/include/mach/barebox.lds.h  |   9 +
 arch/arm/mach-zynq/include/mach/clkdev.h   |   6 +
 arch/arm/mach-zynq/include/mach/debug_ll.h |  34 ++
 arch/arm/mach-zynq/include/mach/devices.h  |  13 +
 .../arm/mach-zynq/include/mach/zynq-flash-header.h |  40 +++
 arch/arm/mach-zynq/include/mach/zynq7000-regs.h| 132 +++
 arch/arm/mach-zynq/zynq.c  |  39 ++
 drivers/serial/Kconfig |   4 +
 drivers/serial/Makefile|   1 +
 drivers/serial/serial_cadence.c| 299 
 include/asm-generic/barebox.lds.h  |   3 +-
 scripts/Makefile   |   1 +
 scripts/zynq_checksum.c|  55 +++
 26 files changed, 1800 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boards/avnet-zedboard/Makefile
 create mode 100644 arch/arm/boards/avnet-zedboard/board.c
 create mode 100644 arch/arm/boards/avnet-zedboard/config.h
 create mode 100644 arch/arm/boards/avnet-zedboard/env/init/config-board
 create mode 100644 arch/arm/boards/avnet-zedboard/flash_header.c
 create mode 100644 arch/arm/boards/avnet-zedboard/lowlevel.c
 create mode 100644 arch/arm/configs/zedboard_defconfig
 create mode 100644 arch/arm/mach-zynq/Kconfig
 create mode 100644 arch/arm/mach-zynq/Makefile
 create mode 100644 arch/arm/mach-zynq/clk-zynq7000.c
 create mode 100644 arch/arm/mach-zynq/devices.c
 create mode 100644 arch/arm/mach-zynq/include/mach/barebox.lds.h
 create mode 100644 arch/arm/mach-zynq/include/mach/clkdev.h
 create mode 100644 arch/arm/mach-zynq/include/mach/debug_ll.h
 create mode 100644 arch/arm/mach-zynq/include/mach/devices.h
 create mode 100644 arch/arm/mach-zynq/include/mach/zynq-flash-header.h
 create mode 100644 arch/arm/mach-zynq/include/mach/zynq7000-regs.h
 create mode 100644 arch/arm/mach-zynq/zynq.c
 create mode 100644 drivers/serial/serial_cadence.c
 create mode 100644 scripts/zynq_checksum.c

-- 
1.8.2.rc2


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[PATCH 7/9] ARM: zynq: clk: add pll type

[Steffen Trumtrar]

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 arch/arm/mach-zynq/clk-zynq7000.c | 33 -
 1 file changed, 32 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-zynq/clk-zynq7000.c 
b/arch/arm/mach-zynq/clk-zynq7000.c
index 5a8a12a..0d3c3a8 100644
--- a/arch/arm/mach-zynq/clk-zynq7000.c
+++ b/arch/arm/mach-zynq/clk-zynq7000.c
@@ -33,10 +33,21 @@ enum zynq_clks {
cpu_clk, cpu_6x4x, cpu_3x2x, cpu_2x, cpu_1x, clks_max
 };
 
+enum zynq_pll_type {
+   ZYNQ_PLL_ARM,
+   ZYNQ_PLL_DDR,
+   ZYNQ_PLL_IO,
+};
+
+#define PLL_ARM_LOCK   (1  0)
+#define PLL_DDR_LOCK   (1  1)
+#define PLL_IO_LOCK(1  2)
+
 static struct clk *clks[clks_max];
 
 struct zynq_pll_clk {
struct clk  clk;
+   u32 pll_lock;
void __iomem*pll_ctrl;
 };
 
@@ -51,11 +62,19 @@ static unsigned long zynq_pll_recalc_rate(struct clk *clk,
return parent_rate * PLL_CTRL_FDIV(readl(pll-pll_ctrl));
 }
 
+static int zynq_pll_enable(struct clk *clk)
+{
+   return 0;
+}
+
 static struct clk_ops zynq_pll_clk_ops = {
.recalc_rate = zynq_pll_recalc_rate,
+   .enable = zynq_pll_enable,
 };
 
-static inline struct clk *zynq_pll_clk(const char *name, void __iomem 
*pll_ctrl)
+static inline struct clk *zynq_pll_clk(enum zynq_pll_type type,
+  const char *name,
+  void __iomem *pll_ctrl)
 {
static const char *pll_parent = ps_clk;
struct zynq_pll_clk *pll;
@@ -68,6 +87,18 @@ static inline struct clk *zynq_pll_clk(const char *name, 
void __iomem *pll_ctrl)
pll-clk.parent_names   = pll_parent;
pll-clk.num_parents= 1;
 
+   switch(type) {
+   case ZYNQ_PLL_ARM:
+   pll-pll_lock = PLL_ARM_LOCK;
+   break;
+   case ZYNQ_PLL_DDR:
+   pll-pll_lock = PLL_DDR_LOCK;
+   break;
+   case ZYNQ_PLL_IO:
+   pll-pll_lock = PLL_IO_LOCK;
+   break;
+   }
+
ret = clk_register(pll-clk);
if (ret) {
free(pll);
-- 
1.8.2.rc2


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[PATCH 8/9] ARM: zynq: clk: convert to platform driver

[Steffen Trumtrar]

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 arch/arm/mach-zynq/Kconfig|  2 ++
 arch/arm/mach-zynq/clk-zynq7000.c | 25 ++---
 arch/arm/mach-zynq/zynq.c |  1 +
 3 files changed, 25 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
index cec749a..a4ce949 100644
--- a/arch/arm/mach-zynq/Kconfig
+++ b/arch/arm/mach-zynq/Kconfig
@@ -14,6 +14,8 @@ config ARCH_ZYNQ7000
bool Zynq-7000
select CPU_V7
select DRIVER_SERIAL_CADENCE
+   select CLKDEV_LOOKUP
+   select COMMON_CLK
 
 endchoice
 
diff --git a/arch/arm/mach-zynq/clk-zynq7000.c 
b/arch/arm/mach-zynq/clk-zynq7000.c
index 0d3c3a8..74f08ad 100644
--- a/arch/arm/mach-zynq/clk-zynq7000.c
+++ b/arch/arm/mach-zynq/clk-zynq7000.c
@@ -335,7 +335,7 @@ static struct clk *zynq_cpu_subclk(const char *name,
return subclk-clk;
 }
 
-static int zynq_init_clks(void)
+static int zynq_clock_probe(struct device_d *dev)
 {
void __iomem *slcr_base = (void __iomem *) ZYNQ_SLCR_BASE;
unsigned long ps_clk_rate = 3330;
@@ -365,9 +365,28 @@ static int zynq_init_clks(void)
clks[cpu_1x] = zynq_cpu_subclk(cpu_1x, CPU_SUBCLK_1X,
slcr_base + 0x120, slcr_base + 0x1C4);
 
-   clk_register_clkdev(clks[cpu_3x2x], NULL, smp_twd0);
+   clk_register_clkdev(clks[cpu_3x2x], NULL, arm_smp_twd);
clk_register_clkdev(clks[uart0], NULL, zynq_serial0);
clk_register_clkdev(clks[uart1], NULL, zynq_serial1);
return 0;
 }
-postcore_initcall(zynq_init_clks);
+
+static __maybe_unused struct of_device_id zynq_clock_dt_ids[] = {
+   {
+   .compatible = xlnx,zynq-clock,
+   }, {
+   /* sentinel */
+   }
+};
+
+static struct driver_d zynq_clock_driver = {
+   .probe  = zynq_clock_probe,
+   .name   = zynq-clock,
+   .of_compatible = DRV_OF_COMPAT(zynq_clock_dt_ids),
+};
+
+static int zynq_clock_init(void)
+{
+   return platform_driver_register(zynq_clock_driver);
+}
+postcore_initcall(zynq_clock_init);
diff --git a/arch/arm/mach-zynq/zynq.c b/arch/arm/mach-zynq/zynq.c
index 2043655..33fc1ab 100644
--- a/arch/arm/mach-zynq/zynq.c
+++ b/arch/arm/mach-zynq/zynq.c
@@ -20,6 +20,7 @@
 
 static int zynq_init(void)
 {
+   add_generic_device(zynq-clock, 0, NULL, ZYNQ_SLCR_BASE, 0x4000, 
IORESOURCE_MEM, NULL);
return 0;
 }
 postcore_initcall(zynq_init);
-- 
1.8.2.rc2


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[PATCH 9/9] ARM: zynq: remove clocksource

[Steffen Trumtrar]

With clkdev in place the generic arm_smp_twd can be used.

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 arch/arm/configs/zedboard_defconfig |  4 +++
 arch/arm/mach-zynq/Kconfig  |  1 +
 arch/arm/mach-zynq/Makefile |  2 +-
 arch/arm/mach-zynq/clk-zynq7000.c   |  3 +-
 arch/arm/mach-zynq/clocksource.c| 58 -
 arch/arm/mach-zynq/zynq.c   |  2 ++
 6 files changed, 10 insertions(+), 60 deletions(-)
 delete mode 100644 arch/arm/mach-zynq/clocksource.c

diff --git a/arch/arm/configs/zedboard_defconfig 
b/arch/arm/configs/zedboard_defconfig
index a9d52dd..0d546ff 100644
--- a/arch/arm/configs/zedboard_defconfig
+++ b/arch/arm/configs/zedboard_defconfig
@@ -250,6 +250,7 @@ CONFIG_CMD_VERSION=y
 # CONFIG_CMD_MAGICVAR is not set
 CONFIG_CMD_DEVINFO=y
 # CONFIG_CMD_UNCOMPRESS is not set
+CONFIG_CMD_CLK=y
 CONFIG_NET=y
 CONFIG_NET_DHCP=y
 # CONFIG_NET_NFS is not set
@@ -295,6 +296,9 @@ CONFIG_DRIVER_SERIAL_CADENCE=y
 # CONFIG_USB is not set
 # CONFIG_VIDEO is not set
 # CONFIG_MCI is not set
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_COMMON_CLK=y
+CONFIG_ARM_SMP_TWD=y
 
 #
 # MFD
diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
index a4ce949..72c96b5 100644
--- a/arch/arm/mach-zynq/Kconfig
+++ b/arch/arm/mach-zynq/Kconfig
@@ -16,6 +16,7 @@ config ARCH_ZYNQ7000
select DRIVER_SERIAL_CADENCE
select CLKDEV_LOOKUP
select COMMON_CLK
+   select ARM_SMP_TWD
 
 endchoice
 
diff --git a/arch/arm/mach-zynq/Makefile b/arch/arm/mach-zynq/Makefile
index 5d632b8..459c957 100644
--- a/arch/arm/mach-zynq/Makefile
+++ b/arch/arm/mach-zynq/Makefile
@@ -1 +1 @@
-obj-y += zynq.o devices.o clocksource.o
+obj-y += zynq.o devices.o clk-zynq7000.o
diff --git a/arch/arm/mach-zynq/clk-zynq7000.c 
b/arch/arm/mach-zynq/clk-zynq7000.c
index 74f08ad..83ae230 100644
--- a/arch/arm/mach-zynq/clk-zynq7000.c
+++ b/arch/arm/mach-zynq/clk-zynq7000.c
@@ -30,7 +30,7 @@
 
 enum zynq_clks {
dummy, ps_clk, arm_pll, ddr_pll, io_pll, uart_clk, uart0, uart1,
-   cpu_clk, cpu_6x4x, cpu_3x2x, cpu_2x, cpu_1x, clks_max
+   cpu_clk, cpu_6x4x, cpu_3x2x, cpu_2x, cpu_1x, clks_max, arm_smp_twd
 };
 
 enum zynq_pll_type {
@@ -366,6 +366,7 @@ static int zynq_clock_probe(struct device_d *dev)
slcr_base + 0x120, slcr_base + 0x1C4);
 
clk_register_clkdev(clks[cpu_3x2x], NULL, arm_smp_twd);
+   clkdev_add_physbase(clks[cpu_3x2x], CORTEXA9_SCU_TIMER_BASE_ADDR, NULL);
clk_register_clkdev(clks[uart0], NULL, zynq_serial0);
clk_register_clkdev(clks[uart1], NULL, zynq_serial1);
return 0;
diff --git a/arch/arm/mach-zynq/clocksource.c b/arch/arm/mach-zynq/clocksource.c
deleted file mode 100644
index 300a73e..000
--- a/arch/arm/mach-zynq/clocksource.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * (C) Copyright 2012 Steffen Trumtrar s.trumt...@pengutronix.de
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include clock.h
-#include common.h
-#include init.h
-#include io.h
-#include mach/zynq7000-regs.h
-
-#define PRIVATE_TIMER_COUNTER  0x04
-#define PRIVATE_TIMER_CONTROL  0x08
-
-#define TIMER_CTRL_TIMER_EN0x1
-#define TIMER_CTRL_AUTO_RELOAD 0x2
-#define TIMER_PRESCALER_SHIFT  0x8
-#define TIMER_PRESCALER0xFF
-
-static void __iomem *timer_base = (void *) CORTEXA9_SCU_TIMER_BASE_ADDR;
-
-static uint64_t zynq_clocksource_read(void)
-{
-   return readl(timer_base + PRIVATE_TIMER_COUNTER);
-}
-
-static struct clocksource cs = {
-   .read   = zynq_clocksource_read,
-   .mask   = CLOCKSOURCE_MASK(16),
-   .shift  = TIMER_PRESCALER_SHIFT,
-};
-
-static int zynq_timer_init(void)
-{
-   cs.mult = clocksource_hz2mult(3330, cs.shift);
-
-   /* set timer load register */
-   writel(0x, timer_base);
-
-   writel(TIMER_CTRL_TIMER_EN | TIMER_CTRL_AUTO_RELOAD |
-   (TIMER_PRESCALER  cs.shift),
-   timer_base + PRIVATE_TIMER_CONTROL);
-
-   init_clock(cs);
-
-   return 0;
-}
-coredevice_initcall(zynq_timer_init);
diff --git a/arch/arm/mach-zynq/zynq.c b/arch/arm/mach-zynq/zynq.c
index 33fc1ab..d430d5f 100644
--- a/arch/arm/mach-zynq/zynq.c
+++ b/arch/arm/mach-zynq/zynq.c
@@ -21,6 +21,8 @@
 static int zynq_init(void)
 {
add_generic_device(zynq-clock, 0, NULL, ZYNQ_SLCR_BASE, 0x4000, 
IORESOURCE_MEM, NULL);
+   add_generic_device(smp_twd, 0, NULL, CORTEXA9_SCU_TIMER_BASE_ADDR,
+   0x4000

[PATCH 1/9] serial: Add driver for Cadence UART

[Steffen Trumtrar]

Support for Cadence UART core.

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 drivers/serial/Kconfig  |   4 +
 drivers/serial/Makefile |   1 +
 drivers/serial/serial_cadence.c | 299 
 3 files changed, 304 insertions(+)
 create mode 100644 drivers/serial/serial_cadence.c

diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index f61d670..a51510e 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -113,4 +113,8 @@ config DRIVER_SERIAL_OMAP4_USBBOOT
help
  Enable this to get console support over the usb bus used to boot an 
OMAP4
 
+config DRIVER_SERIAL_CADENCE
+   default n
+   bool Cadence UART driver
+
 endmenu
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 893e282..963a7df 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -21,3 +21,4 @@ obj-$(CONFIG_DRIVER_SERIAL_ALTERA)+= 
serial_altera.o
 obj-$(CONFIG_DRIVER_SERIAL_ALTERA_JTAG)+= serial_altera_jtag.o
 obj-$(CONFIG_DRIVER_SERIAL_PXA)+= serial_pxa.o
 obj-$(CONFIG_DRIVER_SERIAL_OMAP4_USBBOOT)  += serial_omap4_usbboot.o
+obj-$(CONFIG_DRIVER_SERIAL_CADENCE)+= serial_cadence.o
diff --git a/drivers/serial/serial_cadence.c b/drivers/serial/serial_cadence.c
new file mode 100644
index 000..0ccb1b3
--- /dev/null
+++ b/drivers/serial/serial_cadence.c
@@ -0,0 +1,299 @@
+/*
+ * (c) 2012 Steffen Trumtrar s.trumt...@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#include common.h
+#include driver.h
+#include init.h
+#include malloc.h
+#include notifier.h
+#include io.h
+#include linux/err.h
+#include linux/clk.h
+
+#define CADENCE_UART_CONTROL   0x00
+#define CADENCE_UART_MODE  0x04
+#define CADENCE_UART_BAUD_GEN  0x18
+#define CADENCE_UART_CHANNEL_STS   0x2C
+#define CADENCE_UART_RXTXFIFO  0x30
+#define CADENCE_UART_BAUD_DIV  0x34
+
+#define CADENCE_CTRL_RXRES (1  0)
+#define CADENCE_CTRL_TXRES (1  1)
+#define CADENCE_CTRL_RXEN  (1  2)
+#define CADENCE_CTRL_RXDIS (1  3)
+#define CADENCE_CTRL_TXEN  (1  4)
+#define CADENCE_CTRL_TXDIS (1  5)
+#define CADENCE_CTRL_RSTTO (1  6)
+#define CADENCE_CTRL_STTBRK(1  7)
+#define CADENCE_CTRL_STPBRK(1  8)
+
+#define CADENCE_MODE_CLK_REF   (0  0)
+#define CADENCE_MODE_CLK_REF_DIV   (1  0)
+#define CADENCE_MODE_CHRL_6(3  1)
+#define CADENCE_MODE_CHRL_7(2  1)
+#define CADENCE_MODE_CHRL_8(0  1)
+#define CADENCE_MODE_PAR_EVEN  (0  3)
+#define CADENCE_MODE_PAR_ODD   (1  3)
+#define CADENCE_MODE_PAR_SPACE (2  3)
+#define CADENCE_MODE_PAR_MARK  (3  3)
+#define CADENCE_MODE_PAR_NONE  (4  3)
+
+#define CADENCE_STS_REMPTY (1  1)
+#define CADENCE_STS_RFUL   (1  2)
+#define CADENCE_STS_TEMPTY (1  3)
+#define CADENCE_STS_TFUL   (1  4)
+
+/*
+ * create default values for different platforms
+ */
+struct cadence_serial_devtype_data {
+   u32 ctrl;
+   u32 mode;
+};
+
+static struct cadence_serial_devtype_data cadence7000_data = {
+   .ctrl = CADENCE_CTRL_RXEN | CADENCE_CTRL_TXEN,
+   .mode = CADENCE_MODE_CLK_REF | CADENCE_MODE_CHRL_8 | 
CADENCE_MODE_PAR_NONE,
+};
+
+struct cadence_serial_priv {
+   struct console_device cdev;
+   int baudrate;
+   struct notifier_block notify;
+   void __iomem *regs;
+   /*struct clk *clk;*/
+   unsigned long clk;
+   struct cadence_serial_devtype_data *devtype;
+};
+
+static int cadence_serial_reset(struct console_device *cdev)
+{
+   struct cadence_serial_priv *priv = container_of(cdev,
+   struct cadence_serial_priv, cdev);
+
+   /* Soft-Reset Tx/Rx paths */
+   writel(CADENCE_CTRL_RXRES | CADENCE_CTRL_TXRES, priv-regs +
+   CADENCE_UART_CONTROL);
+
+   while (readl(priv-regs + CADENCE_UART_CONTROL) 
+   (CADENCE_CTRL_RXRES | CADENCE_CTRL_TXRES))
+   ;
+
+   return 0;
+}
+
+static int cadence_serial_setbaudrate(struct console_device *cdev, int 
baudrate)
+{
+   struct cadence_serial_priv *priv = container_of(cdev,
+   struct cadence_serial_priv, cdev);
+   unsigned int gen, div;
+   int calc_rate;
+   unsigned long clk;
+   int error;
+   int val;
+
+   clk = priv-clk;
+   priv-baudrate = baudrate;
+
+   /* disable

[PATCH 2/9] ARM: Zynq: Add new architecture zynq

[Steffen Trumtrar]

Add basic support for the Xilinx Zynq-7000 EPP architecture.
The Zynq-7000 is an embedded processing platform that combines a Cortex A9
dualcore MPSoC with an Artix-7 FPGA.

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 arch/arm/Kconfig   |   5 +
 arch/arm/Makefile  |   2 +
 arch/arm/mach-zynq/Kconfig |  31 +
 arch/arm/mach-zynq/Makefile|   1 +
 arch/arm/mach-zynq/clocksource.c   |  58 +
 arch/arm/mach-zynq/devices.c   |  14 +++
 arch/arm/mach-zynq/include/mach/barebox.lds.h  |   9 ++
 arch/arm/mach-zynq/include/mach/debug_ll.h |  34 ++
 arch/arm/mach-zynq/include/mach/devices.h  |  13 ++
 .../arm/mach-zynq/include/mach/zynq-flash-header.h |  40 +++
 arch/arm/mach-zynq/include/mach/zynq7000-regs.h| 132 +
 arch/arm/mach-zynq/zynq.c  |  41 +++
 include/asm-generic/barebox.lds.h  |   3 +-
 13 files changed, 382 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-zynq/Kconfig
 create mode 100644 arch/arm/mach-zynq/Makefile
 create mode 100644 arch/arm/mach-zynq/clocksource.c
 create mode 100644 arch/arm/mach-zynq/devices.c
 create mode 100644 arch/arm/mach-zynq/include/mach/barebox.lds.h
 create mode 100644 arch/arm/mach-zynq/include/mach/debug_ll.h
 create mode 100644 arch/arm/mach-zynq/include/mach/devices.h
 create mode 100644 arch/arm/mach-zynq/include/mach/zynq-flash-header.h
 create mode 100644 arch/arm/mach-zynq/include/mach/zynq7000-regs.h
 create mode 100644 arch/arm/mach-zynq/zynq.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 28332ec..8431fa8 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -110,6 +110,10 @@ config ARCH_TEGRA
select CPU_ARM926T
select HAS_DEBUG_LL
 
+config ARCH_ZYNQ
+   bool Xilinx Zynq-based boards
+   select HAS_DEBUG_LL
+
 endchoice
 
 source arch/arm/cpu/Kconfig
@@ -126,6 +130,7 @@ source arch/arm/mach-pxa/Kconfig
 source arch/arm/mach-samsung/Kconfig
 source arch/arm/mach-versatile/Kconfig
 source arch/arm/mach-tegra/Kconfig
+source arch/arm/mach-zynq/Kconfig
 
 config ARM_ASM_UNIFIED
bool
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index fcb2969..ceb45dc 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -64,6 +64,7 @@ machine-$(CONFIG_ARCH_PXA):= pxa
 machine-$(CONFIG_ARCH_SAMSUNG) := samsung
 machine-$(CONFIG_ARCH_VERSATILE)   := versatile
 machine-$(CONFIG_ARCH_TEGRA)   := tegra
+machine-$(CONFIG_ARCH_ZYNQ):= zynq
 
 # Board directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
@@ -157,6 +158,7 @@ board-$(CONFIG_MACH_SABRELITE)  := 
freescale-mx6-sabrelite
 board-$(CONFIG_MACH_TX53)  := karo-tx53
 board-$(CONFIG_MACH_GUF_VINCELL)   := guf-vincell
 board-$(CONFIG_MACH_EFIKA_MX_SMARTBOOK):= efika-mx-smartbook
+board-$(CONFIG_MACH_ZEDBOARD)  := avnet-zedboard
 
 machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
 
diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
new file mode 100644
index 000..8eb67d2
--- /dev/null
+++ b/arch/arm/mach-zynq/Kconfig
@@ -0,0 +1,31 @@
+if ARCH_ZYNQ
+
+config ARCH_TEXT_BASE
+   hex
+   default 0x1ff0 if MACH_ZEDBOARD
+
+config BOARDINFO
+   default ZedBoard if MACH_ZEDBOARD
+
+choice
+   prompt Xilinx Zynq type board
+
+config ARCH_ZYNQ7000
+   bool Zynq-7000
+   select CPU_V7
+   select DRIVER_SERIAL_CADENCE
+
+endchoice
+
+if ARCH_ZYNQ7000
+
+choice
+   prompt Zynq-7000 Board Type
+
+config MACH_ZEDBOARD
+   bool Avnet Zynq-7000 ZedBoard
+
+endchoice
+endif
+
+endif
diff --git a/arch/arm/mach-zynq/Makefile b/arch/arm/mach-zynq/Makefile
new file mode 100644
index 000..5d632b8
--- /dev/null
+++ b/arch/arm/mach-zynq/Makefile
@@ -0,0 +1 @@
+obj-y += zynq.o devices.o clocksource.o
diff --git a/arch/arm/mach-zynq/clocksource.c b/arch/arm/mach-zynq/clocksource.c
new file mode 100644
index 000..300a73e
--- /dev/null
+++ b/arch/arm/mach-zynq/clocksource.c
@@ -0,0 +1,58 @@
+/*
+ * (C) Copyright 2012 Steffen Trumtrar s.trumt...@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include clock.h
+#include common.h
+#include init.h
+#include io.h
+#include mach/zynq7000-regs.h
+
+#define

Re: [PATCH 6/9] ARM: zynq: clk: replace define with header

[Steffen Trumtrar]

On Mon, Mar 11, 2013 at 01:29:25PM -0500, Josh Cartwright wrote:
 On Mon, Mar 11, 2013 at 10:15:03AM +0100, Steffen Trumtrar wrote:
  Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
  ---
   arch/arm/mach-zynq/clk-zynq7000.c | 3 +--
   1 file changed, 1 insertion(+), 2 deletions(-)
  
  diff --git a/arch/arm/mach-zynq/clk-zynq7000.c 
  b/arch/arm/mach-zynq/clk-zynq7000.c
  index 8dbde2b..5a8a12a 100644
  --- a/arch/arm/mach-zynq/clk-zynq7000.c
  +++ b/arch/arm/mach-zynq/clk-zynq7000.c
  @@ -25,10 +25,9 @@
   #include linux/clk.h
   #include linux/clkdev.h
   #include linux/err.h
  +#include mach/zynq7000-regs.h
   #include malloc.h
   
  -#define ZYNQ_SLCR_BASE 0xF800
  -
   enum zynq_clks {
  dummy, ps_clk, arm_pll, ddr_pll, io_pll, uart_clk, uart0, uart1,
  cpu_clk, cpu_6x4x, cpu_3x2x, cpu_2x, cpu_1x, clks_max
 
 Again, this is one of those intermediate state things that could be
 cleaned up with a rebase.
 

I wanted to keep the series bisectable, but Sascha already told me that it
is unnecessary. So, I will squash it all down a little.

str

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Re: [PATCH 7/9] ARM: zynq: clk: add pll type

[Steffen Trumtrar]

On Mon, Mar 11, 2013 at 01:28:09PM -0500, Josh Cartwright wrote:
 On Mon, Mar 11, 2013 at 10:15:04AM +0100, Steffen Trumtrar wrote:
  Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
  ---
   arch/arm/mach-zynq/clk-zynq7000.c | 33 -
   1 file changed, 32 insertions(+), 1 deletion(-)
  
  diff --git a/arch/arm/mach-zynq/clk-zynq7000.c 
  b/arch/arm/mach-zynq/clk-zynq7000.c
  index 5a8a12a..0d3c3a8 100644
  --- a/arch/arm/mach-zynq/clk-zynq7000.c
  +++ b/arch/arm/mach-zynq/clk-zynq7000.c
  @@ -33,10 +33,21 @@ enum zynq_clks {
  cpu_clk, cpu_6x4x, cpu_3x2x, cpu_2x, cpu_1x, clks_max
   };
   
  +enum zynq_pll_type {
  +   ZYNQ_PLL_ARM,
  +   ZYNQ_PLL_DDR,
  +   ZYNQ_PLL_IO,
  +};
  +
  +#define PLL_ARM_LOCK   (1  0)
  +#define PLL_DDR_LOCK   (1  1)
  +#define PLL_IO_LOCK(1  2)
 
 Having both an enum and the #define's seem like an unnecessary
 indirection.  I'd suggest just:
 
 enum zynq_pll_lockbit {
   PLL_ARM_LOCK= (1  0),
   PLL_DDR_LOCK= (1  1),
   PLL_IO_LOCK = (1  2),
 };
 
 struct zynq_pll_clk {
   /* ... */
   enum zynq_pll_lockbit lockbit;
 };
 
 static inline struct clk *zynq_pll_clk(enum zynq_pll_lockbit lockbit,
  const char *name,
  void __iomem *pll_ctrl)
 {
   /* ... */
   pll-lockbit = lockbit; 
   /* ... */
 }
 
  +
   static struct clk *clks[clks_max];
   
   struct zynq_pll_clk {
  struct clk  clk;
  +   u32 pll_lock;
  void __iomem*pll_ctrl;
   };
   
  @@ -51,11 +62,19 @@ static unsigned long zynq_pll_recalc_rate(struct clk 
  *clk,
  return parent_rate * PLL_CTRL_FDIV(readl(pll-pll_ctrl));
   }
   
  +static int zynq_pll_enable(struct clk *clk)
  +{
  +   return 0;
  +}
  +
   static struct clk_ops zynq_pll_clk_ops = {
  .recalc_rate = zynq_pll_recalc_rate,
  +   .enable = zynq_pll_enable,
   };
   
  -static inline struct clk *zynq_pll_clk(const char *name, void __iomem 
  *pll_ctrl)
  +static inline struct clk *zynq_pll_clk(enum zynq_pll_type type,
  +  const char *name,
  +  void __iomem *pll_ctrl)
   {
  static const char *pll_parent = ps_clk;
  struct zynq_pll_clk *pll;
  @@ -68,6 +87,18 @@ static inline struct clk *zynq_pll_clk(const char *name, 
  void __iomem *pll_ctrl)
  pll-clk.parent_names   = pll_parent;
  pll-clk.num_parents= 1;
   
  +   switch(type) {
  +   case ZYNQ_PLL_ARM:
  +   pll-pll_lock = PLL_ARM_LOCK;
  +   break;
  +   case ZYNQ_PLL_DDR:
  +   pll-pll_lock = PLL_DDR_LOCK;
  +   break;
  +   case ZYNQ_PLL_IO:
  +   pll-pll_lock = PLL_IO_LOCK;
 
 Actually, maybe I've gotten a little ahead of myself...you add bits for
 the lock, but you never use it!  So, what's the point!  (If it's to be
 used in the future, it'd be nice to see that in the commit description).

I will remove this from this series. This only makes sense, when
the enable function is filled.

str

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[PATCH 1/2] net: macb: remove gem_recv and reorder probe

[Steffen Trumtrar]

The function gem_recv implements a buffer ring that stops at filling level 10.
That means, when the driver is used as gem, it stops receiving after exactly
10 packets. Instead of implementing macb_recv twice, use it also for the gem
part. If there needs to be an extra recv function for the gigabit case, it can
be added than.
Also, first set the type of device (macb or gem) and then use functions that
use this info.

Tested on a Zynq7000.

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
Cc: Nicolas Ferre nicolas.fe...@atmel.com
Cc: Jean-Christophe PLAGNIOL-VILLARD plagn...@jcrosoft.com
---
 drivers/net/macb.c | 47 +++
 1 file changed, 7 insertions(+), 40 deletions(-)

diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index 8602437..a12eea7 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -169,37 +169,6 @@ static void reclaim_rx_buffers(struct macb_device *macb,
macb-rx_tail = new_tail;
 }
 
-static int gem_recv(struct eth_device *edev)
-{
-   struct macb_device *macb = edev-priv;
-   unsigned int rx_tail = macb-rx_tail;
-   void *buffer;
-   int length;
-   u32 status;
-
-   dev_dbg(macb-dev, %s\n, __func__);
-
-   for (;;) {
-   barrier();
-   if (!(macb-rx_ring[rx_tail].addr  MACB_BIT(RX_USED)))
-   return -1;
-
-   barrier();
-   status = macb-rx_ring[rx_tail].ctrl;
-   length = MACB_BFEXT(RX_FRMLEN, status);
-   if (status  MACB_BIT(RX_SOF)) {
-   buffer = macb-rx_buffer + macb-rx_buffer_size * 
macb-rx_tail;
-   net_receive(buffer, length);
-   macb-rx_ring[rx_tail].ctrl = ~MACB_BIT(RX_USED);
-   barrier();
-   }
-   rx_tail++;
-   macb-rx_tail++;
-   }
-
-   return 0;
-}
-
 static int macb_recv(struct eth_device *edev)
 {
struct macb_device *macb = edev-priv;
@@ -619,11 +588,6 @@ static int macb_probe(struct device_d *dev)
 
macb-phy_flags = pdata-phy_flags;
 
-   macb_init_rx_buffer_size(macb, PKTSIZE);
-   macb-rx_buffer = dma_alloc_coherent(macb-rx_buffer_size * 
macb-rx_ring_size);
-   macb-rx_ring = dma_alloc_coherent(RX_RING_BYTES(macb));
-   macb-tx_ring = dma_alloc_coherent(TX_RING_BYTES);
-
macb-regs = dev_request_mem_region(dev, 0);
 
/*
@@ -638,12 +602,15 @@ static int macb_probe(struct device_d *dev)
 
clk_enable(macb-pclk);
 
-   if (macb_is_gem(macb))
-   edev-recv = gem_recv;
-   else
-   edev-recv = macb_recv;
macb-is_gem = read_is_gem(macb);
 
+   macb_init_rx_buffer_size(macb, PKTSIZE);
+   macb-rx_buffer = dma_alloc_coherent(macb-rx_buffer_size * 
macb-rx_ring_size);
+   macb-rx_ring = dma_alloc_coherent(RX_RING_BYTES(macb));
+   macb-tx_ring = dma_alloc_coherent(TX_RING_BYTES);
+
+   edev-recv = macb_recv;
+
macb_reset_hw(macb);
ncfgr = macb_mdc_clk_div(macb);
ncfgr |= MACB_BIT(PAE); /* PAuse Enable */
-- 
1.8.2.rc2


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[PATCH 2/2] net: macb: turn off endian_swp_pkt_en

[Steffen Trumtrar]

The core has a bit for swapping packet data endianism.
Reset default from Cadence is off. Xilinx however, that uses this core on the
Zynq SoCs, opted for on. Turn it off for all devices.

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
Cc: Nicolas Ferre nicolas.fe...@atmel.com
Cc: Jean-Christophe PLAGNIOL-VILLARD plagn...@jcrosoft.com
---
 drivers/net/macb.c | 1 +
 drivers/net/macb.h | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index a12eea7..005234e 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -277,6 +277,7 @@ static void macb_configure_dma(struct macb_device *bp)
dmacfg |= GEM_BF(FBLDO, 16);
dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
dmacfg |= GEM_BIT(DDRP);
+   dmacfg = ~GEM_BIT(ENDIA);
gem_writel(bp, DMACFG, dmacfg);
}
 }
diff --git a/drivers/net/macb.h b/drivers/net/macb.h
index cadd561..1be9ff9 100644
--- a/drivers/net/macb.h
+++ b/drivers/net/macb.h
@@ -168,6 +168,8 @@
 /* Bitfields in DMACFG. */
 #define GEM_FBLDO_OFFSET   0
 #define GEM_FBLDO_SIZE 5
+#define GEM_ENDIA_OFFSET   7
+#define GEM_ENDIA_SIZE 1
 #define GEM_RXBMS_OFFSET   8
 #define GEM_RXBMS_SIZE 2
 #define GEM_TXPBMS_OFFSET  10
-- 
1.8.2.rc2


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Re: [PATCH 2/2] net: macb: turn off endian_swp_pkt_en

[Steffen Trumtrar]

Hi!

On Wed, Mar 13, 2013 at 10:04:45AM +0100, Jean-Christophe PLAGNIOL-VILLARD 
wrote:
 On 09:48 Wed 13 Mar , Steffen Trumtrar wrote:
  The core has a bit for swapping packet data endianism.
  Reset default from Cadence is off. Xilinx however, that uses this core on 
  the
  Zynq SoCs, opted for on. Turn it off for all devices.
 
 is this xilinx specifc?
 
 on at91 and other we do not need it
 

Well, as stated in the commit log, Cadence default is off. I guess, at91 does
not change this. So, where is the problem then forcing it to the sane default
from Cadence?

Regards,
str

 Best Regards,
 J.
  
  Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
  Cc: Nicolas Ferre nicolas.fe...@atmel.com
  Cc: Jean-Christophe PLAGNIOL-VILLARD plagn...@jcrosoft.com
  ---
   drivers/net/macb.c | 1 +
   drivers/net/macb.h | 2 ++
   2 files changed, 3 insertions(+)
  
  diff --git a/drivers/net/macb.c b/drivers/net/macb.c
  index a12eea7..005234e 100644
  --- a/drivers/net/macb.c
  +++ b/drivers/net/macb.c
  @@ -277,6 +277,7 @@ static void macb_configure_dma(struct macb_device *bp)
  dmacfg |= GEM_BF(FBLDO, 16);
  dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
  dmacfg |= GEM_BIT(DDRP);
  +   dmacfg = ~GEM_BIT(ENDIA);
  gem_writel(bp, DMACFG, dmacfg);
  }
   }
  diff --git a/drivers/net/macb.h b/drivers/net/macb.h
  index cadd561..1be9ff9 100644
  --- a/drivers/net/macb.h
  +++ b/drivers/net/macb.h
  @@ -168,6 +168,8 @@
   /* Bitfields in DMACFG. */
   #define GEM_FBLDO_OFFSET   0
   #define GEM_FBLDO_SIZE 5
  +#define GEM_ENDIA_OFFSET   7
  +#define GEM_ENDIA_SIZE 1
   #define GEM_RXBMS_OFFSET   8
   #define GEM_RXBMS_SIZE 2
   #define GEM_TXPBMS_OFFSET  10
  -- 
  1.8.2.rc2
  
 
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Re: [PATCH 1/2] net: macb: remove gem_recv and reorder probe

[Steffen Trumtrar]

On Wed, Mar 13, 2013 at 10:03:36AM +0100, Jean-Christophe PLAGNIOL-VILLARD 
wrote:
 On 09:48 Wed 13 Mar , Steffen Trumtrar wrote:
  The function gem_recv implements a buffer ring that stops at filling 
  level 10.
  That means, when the driver is used as gem, it stops receiving after exactly
  10 packets. Instead of implementing macb_recv twice, use it also for the gem
  part. If there needs to be an extra recv function for the gigabit case, it 
  can
  be added than.
  Also, first set the type of device (macb or gem) and then use functions that
  use this info.
  
  Tested on a Zynq7000.
 NACK
 
 on gem we can receive the packet in one buffer the gem_recv implement this
 the macb can only receive splited buffer and then you have to reconstruct the
 packet
 

Okay. That is nice and all. But try receiving more than just 10 packets with
the current implementation.

Regards,
str

 Best Regards,
 J.
  
  Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
  Cc: Nicolas Ferre nicolas.fe...@atmel.com
  Cc: Jean-Christophe PLAGNIOL-VILLARD plagn...@jcrosoft.com
  ---
   drivers/net/macb.c | 47 +++
   1 file changed, 7 insertions(+), 40 deletions(-)
  
  diff --git a/drivers/net/macb.c b/drivers/net/macb.c
  index 8602437..a12eea7 100644
  --- a/drivers/net/macb.c
  +++ b/drivers/net/macb.c
  @@ -169,37 +169,6 @@ static void reclaim_rx_buffers(struct macb_device 
  *macb,
  macb-rx_tail = new_tail;
   }
   
  -static int gem_recv(struct eth_device *edev)
  -{
  -   struct macb_device *macb = edev-priv;
  -   unsigned int rx_tail = macb-rx_tail;
  -   void *buffer;
  -   int length;
  -   u32 status;
  -
  -   dev_dbg(macb-dev, %s\n, __func__);
  -
  -   for (;;) {
  -   barrier();
  -   if (!(macb-rx_ring[rx_tail].addr  MACB_BIT(RX_USED)))
  -   return -1;
  -
  -   barrier();
  -   status = macb-rx_ring[rx_tail].ctrl;
  -   length = MACB_BFEXT(RX_FRMLEN, status);
  -   if (status  MACB_BIT(RX_SOF)) {
  -   buffer = macb-rx_buffer + macb-rx_buffer_size * 
  macb-rx_tail;
  -   net_receive(buffer, length);
  -   macb-rx_ring[rx_tail].ctrl = ~MACB_BIT(RX_USED);
  -   barrier();
  -   }
  -   rx_tail++;
  -   macb-rx_tail++;
  -   }
  -
  -   return 0;
  -}
  -
   static int macb_recv(struct eth_device *edev)
   {
  struct macb_device *macb = edev-priv;
  @@ -619,11 +588,6 @@ static int macb_probe(struct device_d *dev)
   
  macb-phy_flags = pdata-phy_flags;
   
  -   macb_init_rx_buffer_size(macb, PKTSIZE);
  -   macb-rx_buffer = dma_alloc_coherent(macb-rx_buffer_size * 
  macb-rx_ring_size);
  -   macb-rx_ring = dma_alloc_coherent(RX_RING_BYTES(macb));
  -   macb-tx_ring = dma_alloc_coherent(TX_RING_BYTES);
  -
  macb-regs = dev_request_mem_region(dev, 0);
   
  /*
  @@ -638,12 +602,15 @@ static int macb_probe(struct device_d *dev)
   
  clk_enable(macb-pclk);
   
  -   if (macb_is_gem(macb))
  -   edev-recv = gem_recv;
  -   else
  -   edev-recv = macb_recv;
  macb-is_gem = read_is_gem(macb);
   
  +   macb_init_rx_buffer_size(macb, PKTSIZE);
  +   macb-rx_buffer = dma_alloc_coherent(macb-rx_buffer_size * 
  macb-rx_ring_size);
  +   macb-rx_ring = dma_alloc_coherent(RX_RING_BYTES(macb));
  +   macb-tx_ring = dma_alloc_coherent(TX_RING_BYTES);
  +
  +   edev-recv = macb_recv;
  +
  macb_reset_hw(macb);
  ncfgr = macb_mdc_clk_div(macb);
  ncfgr |= MACB_BIT(PAE); /* PAuse Enable */
  -- 
  1.8.2.rc2
  
 

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[PATCH] net: macb: initialize is_gem before usage

[Steffen Trumtrar]

The variable macb-is_gem is evaluated before it is initialized.
That leads to a wrong rx_buffer setup in the gem case. Also, the
function gem_recv will never be used.

Set the variable first and then use it.

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 drivers/net/macb.c | 13 +++--
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index 0cfad05..30e8476 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -619,11 +619,6 @@ static int macb_probe(struct device_d *dev)
 
macb-phy_flags = pdata-phy_flags;
 
-   macb_init_rx_buffer_size(macb, PKTSIZE);
-   macb-rx_buffer = dma_alloc_coherent(macb-rx_buffer_size * 
macb-rx_ring_size);
-   macb-rx_ring = dma_alloc_coherent(RX_RING_BYTES(macb));
-   macb-tx_ring = dma_alloc_coherent(TX_RING_BYTES);
-
macb-regs = dev_request_mem_region(dev, 0);
 
/*
@@ -638,11 +633,17 @@ static int macb_probe(struct device_d *dev)
 
clk_enable(macb-pclk);
 
+   macb-is_gem = read_is_gem(macb);
+
+   macb_init_rx_buffer_size(macb, PKTSIZE);
+   macb-rx_buffer = dma_alloc_coherent(macb-rx_buffer_size * 
macb-rx_ring_size);
+   macb-rx_ring = dma_alloc_coherent(RX_RING_BYTES(macb));
+   macb-tx_ring = dma_alloc_coherent(TX_RING_BYTES);
+
if (macb_is_gem(macb))
edev-recv = gem_recv;
else
edev-recv = macb_recv;
-   macb-is_gem = read_is_gem(macb);
 
macb_reset_hw(macb);
ncfgr = macb_mdc_clk_div(macb);
-- 
1.8.2.rc2


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Re: [PATCH 1/2] net: macb: remove gem_recv and reorder probe

[Steffen Trumtrar]

On Wed, Mar 13, 2013 at 01:17:03PM +0100, Jean-Christophe PLAGNIOL-VILLARD 
wrote:
 On 11:15 Wed 13 Mar , Sascha Hauer wrote:
  On Wed, Mar 13, 2013 at 10:03:36AM +0100, Jean-Christophe PLAGNIOL-VILLARD 
  wrote:
   On 09:48 Wed 13 Mar , Steffen Trumtrar wrote:
The function gem_recv implements a buffer ring that stops at filling 
level 10.
That means, when the driver is used as gem, it stops receiving after 
exactly
10 packets. Instead of implementing macb_recv twice, use it also for 
the gem
part. If there needs to be an extra recv function for the gigabit case, 
it can
be added than.
Also, first set the type of device (macb or gem) and then use functions 
that
use this info.

Tested on a Zynq7000.
   NACK
   
   on gem we can receive the packet in one buffer the gem_recv implement this
   the macb can only receive splited buffer and then you have to reconstruct 
   the
   packet
  
  The gem received function was never used...
  
 static int macb_recv(struct eth_device *edev)
 {
struct macb_device *macb = edev-priv;
@@ -619,11 +588,6 @@ static int macb_probe(struct device_d *dev)
 
macb-phy_flags = pdata-phy_flags;
 
-   macb_init_rx_buffer_size(macb, PKTSIZE);
-   macb-rx_buffer = dma_alloc_coherent(macb-rx_buffer_size * 
macb-rx_ring_size);
-   macb-rx_ring = dma_alloc_coherent(RX_RING_BYTES(macb));
-   macb-tx_ring = dma_alloc_coherent(TX_RING_BYTES);
-
macb-regs = dev_request_mem_region(dev, 0);
 
/*
@@ -638,12 +602,15 @@ static int macb_probe(struct device_d *dev)
 
clk_enable(macb-pclk);
 
-   if (macb_is_gem(macb))
  
  ... because macb_is_gem() is used here ...
  
-   edev-recv = gem_recv;
-   else
-   edev-recv = macb_recv;
macb-is_gem = read_is_gem(macb);
  
  ... but the variable is initialized here. Up to this point macb_is_gem()
  will return 0.
 so this is a bug when the driver was merge to the mailine but here I does use
 the gem_recv.
 

What about the gem_recv function itself? It only increases rx_tail, but never
resets it. Therefore the buffer is full after 10 packets. Do you already have a
patch for that?

Regards,
Steffen

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Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0|
Amtsgericht Hildesheim, HRA 2686   | Fax:   +49-5121-206917- |

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Re: [PATCH 1/1] macb: fix gem_recv circular buffer handling

[Steffen Trumtrar]

On Wed, Mar 13, 2013 at 04:39:40PM +0100, Jean-Christophe PLAGNIOL-VILLARD 
wrote:
 as we use a full buffer no need to check the SOF
 and reset the rx_tail
 
 fix at the same time the gem detection so we can have the rx_buffer
 allocated correctly according to the IP
 
 Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD plagn...@jcrosoft.com
 ---
  drivers/net/macb.c |   32 
  1 file changed, 16 insertions(+), 16 deletions(-)
 
 diff --git a/drivers/net/macb.c b/drivers/net/macb.c
 index 0cfad05..2d4e373 100644
 --- a/drivers/net/macb.c
 +++ b/drivers/net/macb.c
 @@ -172,7 +172,6 @@ static void reclaim_rx_buffers(struct macb_device *macb,
  static int gem_recv(struct eth_device *edev)
  {
   struct macb_device *macb = edev-priv;
 - unsigned int rx_tail = macb-rx_tail;
   void *buffer;
   int length;
   u32 status;
 @@ -181,20 +180,20 @@ static int gem_recv(struct eth_device *edev)
  
   for (;;) {
   barrier();
 - if (!(macb-rx_ring[rx_tail].addr  MACB_BIT(RX_USED)))
 + if (!(macb-rx_ring[macb-rx_tail].addr  MACB_BIT(RX_USED)))
   return -1;
  
   barrier();
 - status = macb-rx_ring[rx_tail].ctrl;
 + status = macb-rx_ring[macb-rx_tail].ctrl;
   length = MACB_BFEXT(RX_FRMLEN, status);
 - if (status  MACB_BIT(RX_SOF)) {
 - buffer = macb-rx_buffer + macb-rx_buffer_size * 
 macb-rx_tail;
 - net_receive(buffer, length);
 - macb-rx_ring[rx_tail].ctrl = ~MACB_BIT(RX_USED);
 - barrier();
 - }
 - rx_tail++;
 + buffer = macb-rx_buffer + macb-rx_buffer_size * macb-rx_tail;
 + net_receive(buffer, length);
 + macb-rx_ring[macb-rx_tail].addr = ~MACB_BIT(RX_USED);
 + barrier();
 +
   macb-rx_tail++;
 + if (macb-rx_tail = macb-rx_ring_size)
 + macb-rx_tail = 0;
   }
  
   return 0;
 @@ -619,11 +618,6 @@ static int macb_probe(struct device_d *dev)
  
   macb-phy_flags = pdata-phy_flags;
  
 - macb_init_rx_buffer_size(macb, PKTSIZE);
 - macb-rx_buffer = dma_alloc_coherent(macb-rx_buffer_size * 
 macb-rx_ring_size);
 - macb-rx_ring = dma_alloc_coherent(RX_RING_BYTES(macb));
 - macb-tx_ring = dma_alloc_coherent(TX_RING_BYTES);
 -
   macb-regs = dev_request_mem_region(dev, 0);
  
   /*
 @@ -638,11 +632,17 @@ static int macb_probe(struct device_d *dev)
  
   clk_enable(macb-pclk);
  
 + macb-is_gem = read_is_gem(macb);
 +
   if (macb_is_gem(macb))
   edev-recv = gem_recv;
   else
   edev-recv = macb_recv;
 - macb-is_gem = read_is_gem(macb);
 +
 + macb_init_rx_buffer_size(macb, PKTSIZE);
 + macb-rx_buffer = dma_alloc_coherent(macb-rx_buffer_size * 
 macb-rx_ring_size);
 + macb-rx_ring = dma_alloc_coherent(RX_RING_BYTES(macb));
 + macb-tx_ring = dma_alloc_coherent(TX_RING_BYTES);
  
   macb_reset_hw(macb);
   ncfgr = macb_mdc_clk_div(macb);

I know that the last part is not a very sophisticated patch, but you could at 
least
mention that I found the error and/or made part of this patch. Don't just
pretend that you came up with this all alone.

Regards,
Steffen

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Industrial Linux Solutions | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0|
Amtsgericht Hildesheim, HRA 2686   | Fax:   +49-5121-206917- |

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[PATCH v2 4/5] ARM: zynq: add zynq fsbl checksum script

[Steffen Trumtrar]

The bootrom only reads an image if the correct checksum is present in the
header. The calculation is pretty simple:
sum over all words from 0x20 to 0x44
Two of this words are the image length. That is why the checksum can not be
calculated until barebox_image_size is known.
The easiest solution is a program that has to be run after make.
Maybe this can be replaced with some linker-fu.

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 scripts/Makefile|  1 +
 scripts/zynq_checksum.c | 72 +
 2 files changed, 73 insertions(+)
 create mode 100644 scripts/zynq_checksum.c

diff --git a/scripts/Makefile b/scripts/Makefile
index 08b325c..41c892e 100644
--- a/scripts/Makefile
+++ b/scripts/Makefile
@@ -12,6 +12,7 @@ hostprogs-$(CONFIG_ARCH_NETX)+= gen_netx_image
 hostprogs-$(CONFIG_ARCH_OMAP)+= omap_signGP mk-am35xx-spi-image
 hostprogs-$(CONFIG_ARCH_S5PCxx)  += s5p_cksum
 hostprogs-$(CONFIG_ARCH_DAVINCI) += mkublheader
+hostprogs-$(CONFIG_ARCH_ZYNQ)   += zynq_checksum
 
 HOSTLOADLIBES_omap4_usbboot = -lpthread
 omap4_usbboot-objs   := usb_linux.o omap4_usbboot.o
diff --git a/scripts/zynq_checksum.c b/scripts/zynq_checksum.c
new file mode 100644
index 000..f32db61
--- /dev/null
+++ b/scripts/zynq_checksum.c
@@ -0,0 +1,72 @@
+#include endian.h
+#include errno.h
+#include malloc.h
+#include stdio.h
+#include stdlib.h
+#include sys/stat.h
+
+static void usage(char *name)
+{
+   printf(Usage: %s barebox.bin outfile\n, name);
+}
+
+int main(int argc, char *argv[])
+{
+   FILE *ifile, *ofile;
+   unsigned int *buf;
+   const char *infile;
+   const char *outfile;
+   struct stat st;
+   unsigned int i;
+   unsigned long sum = 0;
+
+   if (argc != 3) {
+   usage(argv[0]);
+   exit(1);
+   }
+
+   infile = argv[1];
+   outfile = argv[2];
+
+   if (stat(infile, st) == -1) {
+   perror(stat);
+   exit(EXIT_FAILURE);
+   }
+
+   buf = malloc(sizeof(*buf) * st.st_size);
+   if (!buf) {
+   fprintf(stderr, Unable to allocate buffer\n);
+   return -1;
+   }
+   ifile = fopen(infile, rb);
+   if (!ifile) {
+   fprintf(stderr, Cannot open %s for reading\n,
+   infile);
+   free(buf);
+   exit(EXIT_FAILURE);
+   }
+   ofile = fopen(outfile, wb);
+   if (!ofile) {
+   fprintf(stderr, Cannot open %s for writing\n,
+   outfile);
+   fclose(ifile);
+   free(buf);
+   exit(EXIT_FAILURE);
+   }
+
+   fread(buf, 4, st.st_size, ifile);
+
+   for (i = 0x8; i  0x12; i++)
+   sum += htole32(buf[i]);
+
+   sum = ~sum;
+   buf[i] = sum;
+
+   fwrite(buf, st.st_size / 4, 4, ofile);
+
+   fclose(ofile);
+   fclose(ifile);
+   free(buf);
+
+   return 0;
+}
-- 
1.8.2.rc2


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[PATCH v2 5/5] ARM: zynq: Add support for the Avnet Zedboard

[Steffen Trumtrar]

The Avnet ZedBoard is an evalboard with a Zynq-7020 based MPSoC.
There is also a Digilent ZedBoard, that is the same but only for
academic customers.

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 arch/arm/boards/avnet-zedboard/Makefile|   1 +
 arch/arm/boards/avnet-zedboard/board.c |  38 
 arch/arm/boards/avnet-zedboard/config.h|   4 +
 .../boards/avnet-zedboard/env/init/config-board|   7 +
 arch/arm/boards/avnet-zedboard/flash_header.c  |  76 +++
 arch/arm/boards/avnet-zedboard/lowlevel.c  | 252 +
 arch/arm/configs/zedboard_defconfig|  45 
 7 files changed, 423 insertions(+)
 create mode 100644 arch/arm/boards/avnet-zedboard/Makefile
 create mode 100644 arch/arm/boards/avnet-zedboard/board.c
 create mode 100644 arch/arm/boards/avnet-zedboard/config.h
 create mode 100644 arch/arm/boards/avnet-zedboard/env/init/config-board
 create mode 100644 arch/arm/boards/avnet-zedboard/flash_header.c
 create mode 100644 arch/arm/boards/avnet-zedboard/lowlevel.c
 create mode 100644 arch/arm/configs/zedboard_defconfig

diff --git a/arch/arm/boards/avnet-zedboard/Makefile 
b/arch/arm/boards/avnet-zedboard/Makefile
new file mode 100644
index 000..5c05544
--- /dev/null
+++ b/arch/arm/boards/avnet-zedboard/Makefile
@@ -0,0 +1 @@
+obj-y += board.o lowlevel.o flash_header.o
diff --git a/arch/arm/boards/avnet-zedboard/board.c 
b/arch/arm/boards/avnet-zedboard/board.c
new file mode 100644
index 000..4e3d5a5
--- /dev/null
+++ b/arch/arm/boards/avnet-zedboard/board.c
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2013 Steffen Trumtrar s.trumt...@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include asm/armlinux.h
+#include common.h
+#include environment.h
+#include generated/mach-types.h
+#include init.h
+#include mach/devices.h
+#include mach/zynq7000-regs.h
+#include sizes.h
+
+static int zedboard_mem_init(void)
+{
+   arm_add_mem_device(ram0, 0, SZ_512M);
+
+   return 0;
+}
+mem_initcall(zedboard_mem_init);
+
+static int zedboard_console_init(void)
+{
+   zynq_add_uart1();
+
+   return 0;
+}
+console_initcall(zedboard_console_init);
diff --git a/arch/arm/boards/avnet-zedboard/config.h 
b/arch/arm/boards/avnet-zedboard/config.h
new file mode 100644
index 000..ca15136
--- /dev/null
+++ b/arch/arm/boards/avnet-zedboard/config.h
@@ -0,0 +1,4 @@
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#endif /* __CONFIG_H */
diff --git a/arch/arm/boards/avnet-zedboard/env/init/config-board 
b/arch/arm/boards/avnet-zedboard/env/init/config-board
new file mode 100644
index 000..9957653
--- /dev/null
+++ b/arch/arm/boards/avnet-zedboard/env/init/config-board
@@ -0,0 +1,7 @@
+#!/bin/sh
+
+# board defaults, do not change in running system. Change /env/config
+# instead
+
+global.hostname=ZedBoard
+global.linux.bootargs.base=console=ttyPS1,115200
diff --git a/arch/arm/boards/avnet-zedboard/flash_header.c 
b/arch/arm/boards/avnet-zedboard/flash_header.c
new file mode 100644
index 000..e7e2f8d
--- /dev/null
+++ b/arch/arm/boards/avnet-zedboard/flash_header.c
@@ -0,0 +1,76 @@
+/*
+ * Copyright (C) 2012 Steffen Trumtrar s.trumt...@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include common.h
+#include asm/byteorder.h
+#include mach/zynq-flash-header.h
+#include mach/zynq7000-regs.h
+#include asm/barebox-arm-head.h
+
+void __naked __flash_header_start go(void)
+{
+   __asm__ __volatile__ (
+   b barebox_arm_reset_vector\n
+   1: b 1b\n
+   1: b 1b\n
+   1: b 1b\n
+   1: b 1b\n
+   1: b 1b\n
+   1: b 1b\n
+   1: b 1b\n
+   );
+}
+
+#define REG(a, v) { .addr = cpu_to_le32(a), .val = cpu_to_le32(v), }
+
+struct zynq_reg_entry __ps7reg_entry_section reg_entry[] = {
+   REG(ZYNQ_SLCR_UNLOCK, 0xDF0D),
+   REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_CLK_621_TRUE, 0x0001),
+   REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_APER_CLK_CTRL, 0x01FC044D

[PATCH v2 1/5] serial: Add driver for Cadence UART

[Steffen Trumtrar]

Support for Cadence UART core.

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 drivers/serial/Kconfig  |   4 +
 drivers/serial/Makefile |   1 +
 drivers/serial/serial_cadence.c | 307 
 3 files changed, 312 insertions(+)
 create mode 100644 drivers/serial/serial_cadence.c

diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index f61d670..a51510e 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -113,4 +113,8 @@ config DRIVER_SERIAL_OMAP4_USBBOOT
help
  Enable this to get console support over the usb bus used to boot an 
OMAP4
 
+config DRIVER_SERIAL_CADENCE
+   default n
+   bool Cadence UART driver
+
 endmenu
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 893e282..963a7df 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -21,3 +21,4 @@ obj-$(CONFIG_DRIVER_SERIAL_ALTERA)+= 
serial_altera.o
 obj-$(CONFIG_DRIVER_SERIAL_ALTERA_JTAG)+= serial_altera_jtag.o
 obj-$(CONFIG_DRIVER_SERIAL_PXA)+= serial_pxa.o
 obj-$(CONFIG_DRIVER_SERIAL_OMAP4_USBBOOT)  += serial_omap4_usbboot.o
+obj-$(CONFIG_DRIVER_SERIAL_CADENCE)+= serial_cadence.o
diff --git a/drivers/serial/serial_cadence.c b/drivers/serial/serial_cadence.c
new file mode 100644
index 000..c29c391
--- /dev/null
+++ b/drivers/serial/serial_cadence.c
@@ -0,0 +1,307 @@
+/*
+ * (c) 2012 Steffen Trumtrar s.trumt...@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#include common.h
+#include driver.h
+#include init.h
+#include malloc.h
+#include notifier.h
+#include io.h
+#include linux/err.h
+#include linux/clk.h
+
+#define CADENCE_UART_CONTROL   0x00
+#define CADENCE_UART_MODE  0x04
+#define CADENCE_UART_BAUD_GEN  0x18
+#define CADENCE_UART_CHANNEL_STS   0x2C
+#define CADENCE_UART_RXTXFIFO  0x30
+#define CADENCE_UART_BAUD_DIV  0x34
+
+#define CADENCE_CTRL_RXRES (1  0)
+#define CADENCE_CTRL_TXRES (1  1)
+#define CADENCE_CTRL_RXEN  (1  2)
+#define CADENCE_CTRL_RXDIS (1  3)
+#define CADENCE_CTRL_TXEN  (1  4)
+#define CADENCE_CTRL_TXDIS (1  5)
+#define CADENCE_CTRL_RSTTO (1  6)
+#define CADENCE_CTRL_STTBRK(1  7)
+#define CADENCE_CTRL_STPBRK(1  8)
+
+#define CADENCE_MODE_CLK_REF   (0  0)
+#define CADENCE_MODE_CLK_REF_DIV   (1  0)
+#define CADENCE_MODE_CHRL_6(3  1)
+#define CADENCE_MODE_CHRL_7(2  1)
+#define CADENCE_MODE_CHRL_8(0  1)
+#define CADENCE_MODE_PAR_EVEN  (0  3)
+#define CADENCE_MODE_PAR_ODD   (1  3)
+#define CADENCE_MODE_PAR_SPACE (2  3)
+#define CADENCE_MODE_PAR_MARK  (3  3)
+#define CADENCE_MODE_PAR_NONE  (4  3)
+
+#define CADENCE_STS_REMPTY (1  1)
+#define CADENCE_STS_RFUL   (1  2)
+#define CADENCE_STS_TEMPTY (1  3)
+#define CADENCE_STS_TFUL   (1  4)
+
+/*
+ * create default values for different platforms
+ */
+struct cadence_serial_devtype_data {
+   u32 ctrl;
+   u32 mode;
+};
+
+static struct cadence_serial_devtype_data cadence_r1p08_data = {
+   .ctrl = CADENCE_CTRL_RXEN | CADENCE_CTRL_TXEN,
+   .mode = CADENCE_MODE_CLK_REF | CADENCE_MODE_CHRL_8 | 
CADENCE_MODE_PAR_NONE,
+};
+
+struct cadence_serial_priv {
+   struct console_device cdev;
+   int baudrate;
+   struct notifier_block notify;
+   void __iomem *regs;
+   struct clk *clk;
+   struct cadence_serial_devtype_data *devtype;
+};
+
+static int cadence_serial_reset(struct console_device *cdev)
+{
+   struct cadence_serial_priv *priv = container_of(cdev,
+   struct cadence_serial_priv, cdev);
+
+   /* Soft-Reset Tx/Rx paths */
+   writel(CADENCE_CTRL_RXRES | CADENCE_CTRL_TXRES, priv-regs +
+   CADENCE_UART_CONTROL);
+
+   while (readl(priv-regs + CADENCE_UART_CONTROL) 
+   (CADENCE_CTRL_RXRES | CADENCE_CTRL_TXRES))
+   ;
+
+   return 0;
+}
+
+static int cadence_serial_setbaudrate(struct console_device *cdev, int 
baudrate)
+{
+   struct cadence_serial_priv *priv = container_of(cdev,
+   struct cadence_serial_priv, cdev);
+   unsigned int gen, div;
+   int calc_rate;
+   unsigned long clk;
+   int error;
+   int val

Re: [PATCH v2 5/5] ARM: zynq: Add support for the Avnet Zedboard

[Steffen Trumtrar]

On Tue, Mar 19, 2013 at 08:40:42AM -0500, Josh Cartwright wrote:
 On Tue, Mar 19, 2013 at 10:22:00AM +0100, Steffen Trumtrar wrote:
  The Avnet ZedBoard is an evalboard with a Zynq-7020 based MPSoC.
  There is also a Digilent ZedBoard, that is the same but only for
  academic customers.
  
  Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
  ---
   arch/arm/boards/avnet-zedboard/Makefile|   1 +
   arch/arm/boards/avnet-zedboard/board.c |  38 
   arch/arm/boards/avnet-zedboard/config.h|   4 +
   .../boards/avnet-zedboard/env/init/config-board|   7 +
   arch/arm/boards/avnet-zedboard/flash_header.c  |  76 +++
   arch/arm/boards/avnet-zedboard/lowlevel.c  | 252 
  +
   arch/arm/configs/zedboard_defconfig|  45 
   7 files changed, 423 insertions(+)
   create mode 100644 arch/arm/boards/avnet-zedboard/Makefile
   create mode 100644 arch/arm/boards/avnet-zedboard/board.c
   create mode 100644 arch/arm/boards/avnet-zedboard/config.h
   create mode 100644 arch/arm/boards/avnet-zedboard/env/init/config-board
   create mode 100644 arch/arm/boards/avnet-zedboard/flash_header.c
   create mode 100644 arch/arm/boards/avnet-zedboard/lowlevel.c
   create mode 100644 arch/arm/configs/zedboard_defconfig
  
  diff --git a/arch/arm/boards/avnet-zedboard/Makefile 
  b/arch/arm/boards/avnet-zedboard/Makefile
  new file mode 100644
  index 000..5c05544
  --- /dev/null
  +++ b/arch/arm/boards/avnet-zedboard/Makefile
  @@ -0,0 +1 @@
  +obj-y += board.o lowlevel.o flash_header.o
 
 Should lowlevel.o and flash_header.o only be built into the PBL image?
 

I didn't get around to using PBL. But, yes.

 [..]
  diff --git a/arch/arm/boards/avnet-zedboard/flash_header.c 
  b/arch/arm/boards/avnet-zedboard/flash_header.c
  new file mode 100644
  index 000..e7e2f8d
  --- /dev/null
  +++ b/arch/arm/boards/avnet-zedboard/flash_header.c
  @@ -0,0 +1,76 @@
 [..]
  +#define REG(a, v) { .addr = cpu_to_le32(a), .val = cpu_to_le32(v), }
  +
  +struct zynq_reg_entry __ps7reg_entry_section reg_entry[] = {
  +   REG(ZYNQ_SLCR_UNLOCK, 0xDF0D),
  +   REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_CLK_621_TRUE, 0x0001),
  +   REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_APER_CLK_CTRL, 0x01FC044D),
  +
  +   REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CTRL, 0x00028008),
  +   REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CFG, 0x000FA220),
  +   REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CTRL, 0x00028010),
  +   REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CTRL, 0x00028011),
  +   REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CTRL, 0x00028010),
  +   REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CTRL, 0x00028000),
  +
  +   REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_IO_PLL_CTRL, 0x0001E008),
  +   REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_IO_PLL_CFG, 0x001452C0),
  +   REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_IO_PLL_CTRL, 0x0001E010),
  +   REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_IO_PLL_CTRL, 0x0001E011),
  +   REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_IO_PLL_CTRL, 0x0001E010),
  +   REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_IO_PLL_CTRL, 0x0001E000),
  +
  +   REG(0xf8000150, 0x0a03),
  +
  +   /* stop */
  +   REG(0x, 0x),
  +};
  +
 [..]
  diff --git a/arch/arm/boards/avnet-zedboard/lowlevel.c 
  b/arch/arm/boards/avnet-zedboard/lowlevel.c
  new file mode 100644
  index 000..b50886e
  --- /dev/null
  +++ b/arch/arm/boards/avnet-zedboard/lowlevel.c
 [..]
  +void __naked barebox_arm_reset_vector(void)
  +{
  +   /* open sesame */
  +   writel(0xDF0D, ZYNQ_SLCR_UNLOCK);
  +
  +   /* turn on LD9 */
  +   writel(0x0200, 0xF800071C);
  +   writel(0x0080, 0xE000A204);
  +   writel(0x0080, 0xE000A000);
  +
  +   /* ps7_clock_init_data */
  +   writel(0x1F000200, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_CLK_CTRL);
  +   writel(0x00F00701, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_DCI_CLK_CTRL);
  +   writel(0x2803, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_UART_CLK_CTRL);
  +   writel(0x0A03, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_DBG_CLK_CTRL);
  +   writel(0x0501, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_PCAP_CLK_CTRL);
  +   writel(0x, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_TOPSW_CLK_CTRL);
  +   writel(0x00100A00, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_FPGA0_CLK_CTRL);
  +   writel(0x00100700, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_FPGA1_CLK_CTRL);
  +   writel(0x00101400, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_FPGA2_CLK_CTRL);
  +   writel(0x00101400, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_FPGA3_CLK_CTRL);
  +   /* 6:2:1 mode */
  +   writel(0x0001, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_CLK_621_TRUE);
  +   writel(0x01FC044D, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_APER_CLK_CTRL);
  +
  +   /* configure the PLLs */
  +   /* ARM PLL */
  +   writel(0x00028008, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CTRL);
  +   writel(0x000FA220, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CFG);
  +   writel(0x00028010, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CTRL);
  +   writel(0x00028011, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CTRL);
  +   writel(0x00028010, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CTRL);
 
 Any particular reason why you are configuring

[PATCH v3 0/5] ARM: add support for Zynq

[Steffen Trumtrar]

Hi!

Next shot at Zynq support.
I addressed all/most comments from Jean-Christophe and Josh
(changelogs are in the respective patches).
The lowlevel stuff is still suboptimal with a bunch of writels.
Reason: no complete clk- and no pinctrl-support yet. This will be added
next.

Regards,
Steffen

Steffen Trumtrar (5):
  serial: Add driver for Cadence UART
  ARM: zynq: Add new architecture zynq
  ARM: zynq: add clk support for zynq7000
  ARM: zynq: add zynq fsbl checksum script
  ARM: zynq: Add support for the Avnet Zedboard

 arch/arm/Kconfig   |   5 +
 arch/arm/Makefile  |   2 +
 arch/arm/boards/avnet-zedboard/Makefile|   3 +
 arch/arm/boards/avnet-zedboard/board.c |  38 ++
 arch/arm/boards/avnet-zedboard/config.h|   4 +
 .../boards/avnet-zedboard/env/init/config-board|   7 +
 arch/arm/boards/avnet-zedboard/flash_header.c  |  62 +++
 arch/arm/boards/avnet-zedboard/lowlevel.c  | 252 +
 arch/arm/configs/zedboard_defconfig|  49 +++
 arch/arm/mach-zynq/Kconfig |  38 ++
 arch/arm/mach-zynq/Makefile|   1 +
 arch/arm/mach-zynq/clk-zynq7000.c  | 417 +
 arch/arm/mach-zynq/devices.c   |   8 +
 arch/arm/mach-zynq/include/mach/barebox.lds.h  |   8 +
 arch/arm/mach-zynq/include/mach/clkdev.h   |   6 +
 arch/arm/mach-zynq/include/mach/debug_ll.h |  37 ++
 arch/arm/mach-zynq/include/mach/devices.h  |  13 +
 .../arm/mach-zynq/include/mach/zynq-flash-header.h |  38 ++
 arch/arm/mach-zynq/include/mach/zynq7000-regs.h| 132 +++
 arch/arm/mach-zynq/zynq.c  |  56 +++
 drivers/serial/Kconfig |   5 +
 drivers/serial/Makefile|   1 +
 drivers/serial/serial_cadence.c| 307 +++
 include/asm-generic/barebox.lds.h  |   3 +-
 scripts/Makefile   |   1 +
 scripts/zynq_checksum.c|  72 
 26 files changed, 1564 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boards/avnet-zedboard/Makefile
 create mode 100644 arch/arm/boards/avnet-zedboard/board.c
 create mode 100644 arch/arm/boards/avnet-zedboard/config.h
 create mode 100644 arch/arm/boards/avnet-zedboard/env/init/config-board
 create mode 100644 arch/arm/boards/avnet-zedboard/flash_header.c
 create mode 100644 arch/arm/boards/avnet-zedboard/lowlevel.c
 create mode 100644 arch/arm/configs/zedboard_defconfig
 create mode 100644 arch/arm/mach-zynq/Kconfig
 create mode 100644 arch/arm/mach-zynq/Makefile
 create mode 100644 arch/arm/mach-zynq/clk-zynq7000.c
 create mode 100644 arch/arm/mach-zynq/devices.c
 create mode 100644 arch/arm/mach-zynq/include/mach/barebox.lds.h
 create mode 100644 arch/arm/mach-zynq/include/mach/clkdev.h
 create mode 100644 arch/arm/mach-zynq/include/mach/debug_ll.h
 create mode 100644 arch/arm/mach-zynq/include/mach/devices.h
 create mode 100644 arch/arm/mach-zynq/include/mach/zynq-flash-header.h
 create mode 100644 arch/arm/mach-zynq/include/mach/zynq7000-regs.h
 create mode 100644 arch/arm/mach-zynq/zynq.c
 create mode 100644 drivers/serial/serial_cadence.c
 create mode 100644 scripts/zynq_checksum.c

-- 
1.8.2.rc2


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[PATCH v2 4/5] ARM: zynq: add zynq fsbl checksum script

[Steffen Trumtrar]

The bootrom only reads an image if the correct checksum is present in the
header. The calculation is pretty simple:
sum over all words from 0x20 to 0x44
Two of this words are the image length. That is why the checksum can not be
calculated until barebox_image_size is known.
The easiest solution is a program that has to be run after make.

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 scripts/Makefile|  1 +
 scripts/zynq_checksum.c | 72 +
 2 files changed, 73 insertions(+)
 create mode 100644 scripts/zynq_checksum.c

diff --git a/scripts/Makefile b/scripts/Makefile
index 08b325c..41c892e 100644
--- a/scripts/Makefile
+++ b/scripts/Makefile
@@ -12,6 +12,7 @@ hostprogs-$(CONFIG_ARCH_NETX)+= gen_netx_image
 hostprogs-$(CONFIG_ARCH_OMAP)+= omap_signGP mk-am35xx-spi-image
 hostprogs-$(CONFIG_ARCH_S5PCxx)  += s5p_cksum
 hostprogs-$(CONFIG_ARCH_DAVINCI) += mkublheader
+hostprogs-$(CONFIG_ARCH_ZYNQ)   += zynq_checksum
 
 HOSTLOADLIBES_omap4_usbboot = -lpthread
 omap4_usbboot-objs   := usb_linux.o omap4_usbboot.o
diff --git a/scripts/zynq_checksum.c b/scripts/zynq_checksum.c
new file mode 100644
index 000..f32db61
--- /dev/null
+++ b/scripts/zynq_checksum.c
@@ -0,0 +1,72 @@
+#include endian.h
+#include errno.h
+#include malloc.h
+#include stdio.h
+#include stdlib.h
+#include sys/stat.h
+
+static void usage(char *name)
+{
+   printf(Usage: %s barebox.bin outfile\n, name);
+}
+
+int main(int argc, char *argv[])
+{
+   FILE *ifile, *ofile;
+   unsigned int *buf;
+   const char *infile;
+   const char *outfile;
+   struct stat st;
+   unsigned int i;
+   unsigned long sum = 0;
+
+   if (argc != 3) {
+   usage(argv[0]);
+   exit(1);
+   }
+
+   infile = argv[1];
+   outfile = argv[2];
+
+   if (stat(infile, st) == -1) {
+   perror(stat);
+   exit(EXIT_FAILURE);
+   }
+
+   buf = malloc(sizeof(*buf) * st.st_size);
+   if (!buf) {
+   fprintf(stderr, Unable to allocate buffer\n);
+   return -1;
+   }
+   ifile = fopen(infile, rb);
+   if (!ifile) {
+   fprintf(stderr, Cannot open %s for reading\n,
+   infile);
+   free(buf);
+   exit(EXIT_FAILURE);
+   }
+   ofile = fopen(outfile, wb);
+   if (!ofile) {
+   fprintf(stderr, Cannot open %s for writing\n,
+   outfile);
+   fclose(ifile);
+   free(buf);
+   exit(EXIT_FAILURE);
+   }
+
+   fread(buf, 4, st.st_size, ifile);
+
+   for (i = 0x8; i  0x12; i++)
+   sum += htole32(buf[i]);
+
+   sum = ~sum;
+   buf[i] = sum;
+
+   fwrite(buf, st.st_size / 4, 4, ofile);
+
+   fclose(ofile);
+   fclose(ifile);
+   free(buf);
+
+   return 0;
+}
-- 
1.8.2.rc2


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[PATCH v3 1/5] serial: Add driver for Cadence UART

[Steffen Trumtrar]

Support for Cadence UART core.

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---

Changes since v2:
- remove superfluous Kconfig option
- add help text to Kconfig option

 drivers/serial/Kconfig  |   5 +
 drivers/serial/Makefile |   1 +
 drivers/serial/serial_cadence.c | 307 
 3 files changed, 313 insertions(+)
 create mode 100644 drivers/serial/serial_cadence.c

diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index f61d670..73cb9f8 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -113,4 +113,9 @@ config DRIVER_SERIAL_OMAP4_USBBOOT
help
  Enable this to get console support over the usb bus used to boot an 
OMAP4
 
+config DRIVER_SERIAL_CADENCE
+   bool Cadence UART driver
+   help
+ Say Y here if you have a Cadence serial IP core.
+
 endmenu
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 893e282..963a7df 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -21,3 +21,4 @@ obj-$(CONFIG_DRIVER_SERIAL_ALTERA)+= 
serial_altera.o
 obj-$(CONFIG_DRIVER_SERIAL_ALTERA_JTAG)+= serial_altera_jtag.o
 obj-$(CONFIG_DRIVER_SERIAL_PXA)+= serial_pxa.o
 obj-$(CONFIG_DRIVER_SERIAL_OMAP4_USBBOOT)  += serial_omap4_usbboot.o
+obj-$(CONFIG_DRIVER_SERIAL_CADENCE)+= serial_cadence.o
diff --git a/drivers/serial/serial_cadence.c b/drivers/serial/serial_cadence.c
new file mode 100644
index 000..c29c391
--- /dev/null
+++ b/drivers/serial/serial_cadence.c
@@ -0,0 +1,307 @@
+/*
+ * (c) 2012 Steffen Trumtrar s.trumt...@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#include common.h
+#include driver.h
+#include init.h
+#include malloc.h
+#include notifier.h
+#include io.h
+#include linux/err.h
+#include linux/clk.h
+
+#define CADENCE_UART_CONTROL   0x00
+#define CADENCE_UART_MODE  0x04
+#define CADENCE_UART_BAUD_GEN  0x18
+#define CADENCE_UART_CHANNEL_STS   0x2C
+#define CADENCE_UART_RXTXFIFO  0x30
+#define CADENCE_UART_BAUD_DIV  0x34
+
+#define CADENCE_CTRL_RXRES (1  0)
+#define CADENCE_CTRL_TXRES (1  1)
+#define CADENCE_CTRL_RXEN  (1  2)
+#define CADENCE_CTRL_RXDIS (1  3)
+#define CADENCE_CTRL_TXEN  (1  4)
+#define CADENCE_CTRL_TXDIS (1  5)
+#define CADENCE_CTRL_RSTTO (1  6)
+#define CADENCE_CTRL_STTBRK(1  7)
+#define CADENCE_CTRL_STPBRK(1  8)
+
+#define CADENCE_MODE_CLK_REF   (0  0)
+#define CADENCE_MODE_CLK_REF_DIV   (1  0)
+#define CADENCE_MODE_CHRL_6(3  1)
+#define CADENCE_MODE_CHRL_7(2  1)
+#define CADENCE_MODE_CHRL_8(0  1)
+#define CADENCE_MODE_PAR_EVEN  (0  3)
+#define CADENCE_MODE_PAR_ODD   (1  3)
+#define CADENCE_MODE_PAR_SPACE (2  3)
+#define CADENCE_MODE_PAR_MARK  (3  3)
+#define CADENCE_MODE_PAR_NONE  (4  3)
+
+#define CADENCE_STS_REMPTY (1  1)
+#define CADENCE_STS_RFUL   (1  2)
+#define CADENCE_STS_TEMPTY (1  3)
+#define CADENCE_STS_TFUL   (1  4)
+
+/*
+ * create default values for different platforms
+ */
+struct cadence_serial_devtype_data {
+   u32 ctrl;
+   u32 mode;
+};
+
+static struct cadence_serial_devtype_data cadence_r1p08_data = {
+   .ctrl = CADENCE_CTRL_RXEN | CADENCE_CTRL_TXEN,
+   .mode = CADENCE_MODE_CLK_REF | CADENCE_MODE_CHRL_8 | 
CADENCE_MODE_PAR_NONE,
+};
+
+struct cadence_serial_priv {
+   struct console_device cdev;
+   int baudrate;
+   struct notifier_block notify;
+   void __iomem *regs;
+   struct clk *clk;
+   struct cadence_serial_devtype_data *devtype;
+};
+
+static int cadence_serial_reset(struct console_device *cdev)
+{
+   struct cadence_serial_priv *priv = container_of(cdev,
+   struct cadence_serial_priv, cdev);
+
+   /* Soft-Reset Tx/Rx paths */
+   writel(CADENCE_CTRL_RXRES | CADENCE_CTRL_TXRES, priv-regs +
+   CADENCE_UART_CONTROL);
+
+   while (readl(priv-regs + CADENCE_UART_CONTROL) 
+   (CADENCE_CTRL_RXRES | CADENCE_CTRL_TXRES))
+   ;
+
+   return 0;
+}
+
+static int cadence_serial_setbaudrate(struct console_device *cdev, int 
baudrate)
+{
+   struct cadence_serial_priv *priv = container_of(cdev

[PATCH v3 2/5] ARM: zynq: Add new architecture zynq

[Steffen Trumtrar]

Add basic support for the Xilinx Zynq-7000 EPP architecture.
The Zynq-7000 is an embedded processing platform that combines a Cortex A9
dualcore MPSoC with an Artix-7 FPGA.

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---

Changes since v2:
- don't force serial driver in Kconfig
- remove MACH_HAS_LOWLEVEL_INIT
- use (void __iomem *) in debug_ll.h
- remove zynq_add_device inline function
- use resource_size_t instead of void *
- use __le32 consistently in zynq-flash-header.h
- remove useless flash_header_start section

 arch/arm/Kconfig   |   5 +
 arch/arm/Makefile  |   2 +
 arch/arm/mach-zynq/Kconfig |  38 ++
 arch/arm/mach-zynq/Makefile|   1 +
 arch/arm/mach-zynq/devices.c   |   8 ++
 arch/arm/mach-zynq/include/mach/barebox.lds.h  |   8 ++
 arch/arm/mach-zynq/include/mach/debug_ll.h |  37 ++
 arch/arm/mach-zynq/include/mach/devices.h  |  13 ++
 .../arm/mach-zynq/include/mach/zynq-flash-header.h |  38 ++
 arch/arm/mach-zynq/include/mach/zynq7000-regs.h| 132 +
 arch/arm/mach-zynq/zynq.c  |  56 +
 include/asm-generic/barebox.lds.h  |   3 +-
 12 files changed, 340 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-zynq/Kconfig
 create mode 100644 arch/arm/mach-zynq/Makefile
 create mode 100644 arch/arm/mach-zynq/devices.c
 create mode 100644 arch/arm/mach-zynq/include/mach/barebox.lds.h
 create mode 100644 arch/arm/mach-zynq/include/mach/debug_ll.h
 create mode 100644 arch/arm/mach-zynq/include/mach/devices.h
 create mode 100644 arch/arm/mach-zynq/include/mach/zynq-flash-header.h
 create mode 100644 arch/arm/mach-zynq/include/mach/zynq7000-regs.h
 create mode 100644 arch/arm/mach-zynq/zynq.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 28332ec..8431fa8 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -110,6 +110,10 @@ config ARCH_TEGRA
select CPU_ARM926T
select HAS_DEBUG_LL
 
+config ARCH_ZYNQ
+   bool Xilinx Zynq-based boards
+   select HAS_DEBUG_LL
+
 endchoice
 
 source arch/arm/cpu/Kconfig
@@ -126,6 +130,7 @@ source arch/arm/mach-pxa/Kconfig
 source arch/arm/mach-samsung/Kconfig
 source arch/arm/mach-versatile/Kconfig
 source arch/arm/mach-tegra/Kconfig
+source arch/arm/mach-zynq/Kconfig
 
 config ARM_ASM_UNIFIED
bool
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index fcb2969..ceb45dc 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -64,6 +64,7 @@ machine-$(CONFIG_ARCH_PXA):= pxa
 machine-$(CONFIG_ARCH_SAMSUNG) := samsung
 machine-$(CONFIG_ARCH_VERSATILE)   := versatile
 machine-$(CONFIG_ARCH_TEGRA)   := tegra
+machine-$(CONFIG_ARCH_ZYNQ):= zynq
 
 # Board directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
@@ -157,6 +158,7 @@ board-$(CONFIG_MACH_SABRELITE)  := 
freescale-mx6-sabrelite
 board-$(CONFIG_MACH_TX53)  := karo-tx53
 board-$(CONFIG_MACH_GUF_VINCELL)   := guf-vincell
 board-$(CONFIG_MACH_EFIKA_MX_SMARTBOOK):= efika-mx-smartbook
+board-$(CONFIG_MACH_ZEDBOARD)  := avnet-zedboard
 
 machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
 
diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
new file mode 100644
index 000..5bbd648
--- /dev/null
+++ b/arch/arm/mach-zynq/Kconfig
@@ -0,0 +1,38 @@
+if ARCH_ZYNQ
+
+config ARCH_TEXT_BASE
+   hex
+   default 0x1ff0 if MACH_ZEDBOARD
+
+config ZYNQ_DEBUG_LL_UART_BASE
+   hex
+   default 0xe0001000 if MACH_ZEDBOARD
+
+config BOARDINFO
+   default ZedBoard if MACH_ZEDBOARD
+
+choice
+   prompt Xilinx Zynq type board
+
+config ARCH_ZYNQ7000
+   bool Zynq-7000
+   select CPU_V7
+   select CLKDEV_LOOKUP
+   select COMMON_CLK
+   select ARM_SMP_TWD
+
+endchoice
+
+if ARCH_ZYNQ7000
+
+choice
+   prompt Zynq-7000 Board Type
+
+config MACH_ZEDBOARD
+   bool Avnet Zynq-7000 ZedBoard
+   select DRIVER_SERIAL_CADENCE
+
+endchoice
+endif
+
+endif
diff --git a/arch/arm/mach-zynq/Makefile b/arch/arm/mach-zynq/Makefile
new file mode 100644
index 000..459c957
--- /dev/null
+++ b/arch/arm/mach-zynq/Makefile
@@ -0,0 +1 @@
+obj-y += zynq.o devices.o clk-zynq7000.o
diff --git a/arch/arm/mach-zynq/devices.c b/arch/arm/mach-zynq/devices.c
new file mode 100644
index 000..777bb87
--- /dev/null
+++ b/arch/arm/mach-zynq/devices.c
@@ -0,0 +1,8 @@
+#include common.h
+#include driver.h
+#include mach/devices.h
+
+struct device_d *zynq_add_uart(resource_size_t base, int id)
+{
+   return add_generic_device(cadence-uart, id, NULL, base, 0x1000, 
IORESOURCE_MEM, NULL);
+}
diff --git a/arch/arm/mach-zynq/include/mach/barebox.lds.h 
b/arch/arm/mach-zynq/include/mach

[PATCH v3 5/5] ARM: zynq: Add support for the Avnet Zedboard

[Steffen Trumtrar]

The Avnet ZedBoard is an evalboard with a Zynq-7020 based MPSoC.
There is also a Digilent ZedBoard, that is the same but only for
academic customers.

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---

Changes since v2:
- use pbl image
- remove useless flash_header_start

 arch/arm/boards/avnet-zedboard/Makefile|   3 +
 arch/arm/boards/avnet-zedboard/board.c |  38 
 arch/arm/boards/avnet-zedboard/config.h|   4 +
 .../boards/avnet-zedboard/env/init/config-board|   7 +
 arch/arm/boards/avnet-zedboard/flash_header.c  |  62 +
 arch/arm/boards/avnet-zedboard/lowlevel.c  | 252 +
 arch/arm/configs/zedboard_defconfig|  49 
 7 files changed, 415 insertions(+)
 create mode 100644 arch/arm/boards/avnet-zedboard/Makefile
 create mode 100644 arch/arm/boards/avnet-zedboard/board.c
 create mode 100644 arch/arm/boards/avnet-zedboard/config.h
 create mode 100644 arch/arm/boards/avnet-zedboard/env/init/config-board
 create mode 100644 arch/arm/boards/avnet-zedboard/flash_header.c
 create mode 100644 arch/arm/boards/avnet-zedboard/lowlevel.c
 create mode 100644 arch/arm/configs/zedboard_defconfig

diff --git a/arch/arm/boards/avnet-zedboard/Makefile 
b/arch/arm/boards/avnet-zedboard/Makefile
new file mode 100644
index 000..a2c3104
--- /dev/null
+++ b/arch/arm/boards/avnet-zedboard/Makefile
@@ -0,0 +1,3 @@
+obj-y += board.o
+lwl-y += lowlevel.o
+lwl-y += flash_header.o
diff --git a/arch/arm/boards/avnet-zedboard/board.c 
b/arch/arm/boards/avnet-zedboard/board.c
new file mode 100644
index 000..4e3d5a5
--- /dev/null
+++ b/arch/arm/boards/avnet-zedboard/board.c
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2013 Steffen Trumtrar s.trumt...@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include asm/armlinux.h
+#include common.h
+#include environment.h
+#include generated/mach-types.h
+#include init.h
+#include mach/devices.h
+#include mach/zynq7000-regs.h
+#include sizes.h
+
+static int zedboard_mem_init(void)
+{
+   arm_add_mem_device(ram0, 0, SZ_512M);
+
+   return 0;
+}
+mem_initcall(zedboard_mem_init);
+
+static int zedboard_console_init(void)
+{
+   zynq_add_uart1();
+
+   return 0;
+}
+console_initcall(zedboard_console_init);
diff --git a/arch/arm/boards/avnet-zedboard/config.h 
b/arch/arm/boards/avnet-zedboard/config.h
new file mode 100644
index 000..ca15136
--- /dev/null
+++ b/arch/arm/boards/avnet-zedboard/config.h
@@ -0,0 +1,4 @@
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#endif /* __CONFIG_H */
diff --git a/arch/arm/boards/avnet-zedboard/env/init/config-board 
b/arch/arm/boards/avnet-zedboard/env/init/config-board
new file mode 100644
index 000..9957653
--- /dev/null
+++ b/arch/arm/boards/avnet-zedboard/env/init/config-board
@@ -0,0 +1,7 @@
+#!/bin/sh
+
+# board defaults, do not change in running system. Change /env/config
+# instead
+
+global.hostname=ZedBoard
+global.linux.bootargs.base=console=ttyPS1,115200
diff --git a/arch/arm/boards/avnet-zedboard/flash_header.c 
b/arch/arm/boards/avnet-zedboard/flash_header.c
new file mode 100644
index 000..ea20524
--- /dev/null
+++ b/arch/arm/boards/avnet-zedboard/flash_header.c
@@ -0,0 +1,62 @@
+/*
+ * Copyright (C) 2012 Steffen Trumtrar s.trumt...@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include common.h
+#include asm/byteorder.h
+#include mach/zynq-flash-header.h
+#include mach/zynq7000-regs.h
+#include asm/barebox-arm-head.h
+
+#define REG(a, v) { .addr = cpu_to_le32(a), .val = cpu_to_le32(v), }
+
+struct zynq_reg_entry __ps7reg_entry_section reg_entry[] = {
+   REG(ZYNQ_SLCR_UNLOCK, 0xDF0D),
+   REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_CLK_621_TRUE, 0x0001),
+   REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_APER_CLK_CTRL, 0x01FC044D),
+
+   REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CTRL, 0x00028008),
+   REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CFG, 0x000FA220),
+   REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CTRL, 0x00028010),
+   REG

[PATCH v2 3/5] ARM: zynq: add clk support for zynq7000

[Steffen Trumtrar]

This adds support for the clocktree on zynq7000 SoCs.
The patch is based on clocks.c from the larger patch
ARM: zynq: add suppport for Zynq 7000 SoC
by Josh Cartwright.

The driver in that patch is converted to a platform_driver and code to
enable plls was added.

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 arch/arm/mach-zynq/clk-zynq7000.c| 417 +++
 arch/arm/mach-zynq/include/mach/clkdev.h |   6 +
 2 files changed, 423 insertions(+)
 create mode 100644 arch/arm/mach-zynq/clk-zynq7000.c
 create mode 100644 arch/arm/mach-zynq/include/mach/clkdev.h

diff --git a/arch/arm/mach-zynq/clk-zynq7000.c 
b/arch/arm/mach-zynq/clk-zynq7000.c
new file mode 100644
index 000..1e03514
--- /dev/null
+++ b/arch/arm/mach-zynq/clk-zynq7000.c
@@ -0,0 +1,417 @@
+/*
+ * Copyright (c) 2013 Josh Cartwright jo...@eso.teric.us
+ * Copyright (c) 2013 Steffen Trumtrar s.trumt...@pengutronix.de
+ *
+ * Based on drivers/clk-zynq.c from Linux.
+ *
+ * Copyright (c) 2012 National Instruments
+ *
+ * Josh Cartwright josh.cartwri...@ni.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see http://www.gnu.org/licenses/.
+ */
+#include common.h
+#include init.h
+#include io.h
+#include linux/clk.h
+#include linux/clkdev.h
+#include linux/err.h
+#include mach/zynq7000-regs.h
+#include malloc.h
+
+enum zynq_clks {
+   dummy, ps_clk, arm_pll, ddr_pll, io_pll, uart_clk, uart0, uart1,
+   cpu_clk, cpu_6x4x, cpu_3x2x, cpu_2x, cpu_1x, clks_max
+};
+
+enum zynq_pll_type {
+   ZYNQ_PLL_ARM,
+   ZYNQ_PLL_DDR,
+   ZYNQ_PLL_IO,
+};
+
+#define PLL_STATUS_ARM_PLL_LOCK(1  0)
+#define PLL_STATUS_DDR_PLL_LOCK(1  1)
+#define PLL_STATUS_IO_PLL_LOCK (1  2)
+#define PLL_STATUS_ARM_PLL_STABLE  (1  0)
+#define PLL_STATUS_DDR_PLL_STABLE  (1  1)
+#define PLL_STATUS_IO_PLL_STABLE   (1  2)
+#define PLL_CTRL_BYPASS_FORCE  (1  4)
+
+static struct clk *clks[clks_max];
+
+struct zynq_pll_clk {
+   struct clk  clk;
+   u32 pll_lock;
+   void __iomem*pll_ctrl;
+};
+
+#define to_zynq_pll_clk(c) container_of(c, struct zynq_pll_clk, clk)
+
+#define PLL_CTRL_FDIV(x)   (((x)  12)  0x7F)
+
+static unsigned long zynq_pll_recalc_rate(struct clk *clk,
+ unsigned long parent_rate)
+{
+   struct zynq_pll_clk *pll = to_zynq_pll_clk(clk);
+   return parent_rate * PLL_CTRL_FDIV(readl(pll-pll_ctrl));
+}
+
+static int zynq_pll_enable(struct clk *clk)
+{
+   struct zynq_pll_clk *pll = to_zynq_pll_clk(clk);
+   u32 val;
+   int timeout = 1;
+
+   val = readl(pll-pll_ctrl);
+   val = ~PLL_CTRL_BYPASS_FORCE;
+   writel(val, pll-pll_ctrl);
+
+   while (timeout--) {
+   if (readl(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_PLL_STATUS)  
pll-pll_lock)
+   break;
+   }
+
+   if (!timeout)
+   return -ETIMEDOUT;
+
+   return 0;
+}
+
+static struct clk_ops zynq_pll_clk_ops = {
+   .recalc_rate = zynq_pll_recalc_rate,
+   .enable = zynq_pll_enable,
+};
+
+static inline struct clk *zynq_pll_clk(enum zynq_pll_type type,
+  const char *name,
+  void __iomem *pll_ctrl)
+{
+   static const char *pll_parent = ps_clk;
+   struct zynq_pll_clk *pll;
+   int ret;
+
+   pll = xzalloc(sizeof(*pll));
+   pll-pll_ctrl   = pll_ctrl;
+   pll-clk.ops= zynq_pll_clk_ops;
+   pll-clk.name   = name;
+   pll-clk.parent_names   = pll_parent;
+   pll-clk.num_parents= 1;
+
+   switch(type) {
+   case ZYNQ_PLL_ARM:
+   pll-pll_lock = PLL_STATUS_ARM_PLL_LOCK;
+   break;
+   case ZYNQ_PLL_DDR:
+   pll-pll_lock = PLL_STATUS_DDR_PLL_LOCK;
+   break;
+   case ZYNQ_PLL_IO:
+   pll-pll_lock = PLL_STATUS_IO_PLL_LOCK;
+   break;
+   }
+
+   ret = clk_register(pll-clk);
+   if (ret) {
+   free(pll);
+   return ERR_PTR(ret);
+   }
+
+   return pll-clk;
+}
+
+struct zynq_periph_clk {
+   struct clk  clk;
+   void __iomem*clk_ctrl;
+};
+
+#define to_zynq_periph_clk(c)  container_of(c, struct zynq_periph_clk, c)
+
+static const u8 periph_clk_parent_map[] = {
+   0, 0, 1, 2
+};
+#define PERIPH_CLK_CTRL_SRC(x

[PATCH v3 4/5] ARM: zynq: add zynq fsbl checksum script

[Steffen Trumtrar]

The bootrom only reads an image if the correct checksum is present in the
header. The calculation is pretty simple:
sum over all words from 0x20 to 0x44
Two of this words are the image length. That is why the checksum can not be
calculated until barebox_image_size is known.
The easiest solution is a program that has to be run after make.

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---

Changes since v2:
- rename to zynq_mkimage
- add to gitignores
- always pipe barebox through zynq_mkimage
- don't waste memory with malloc
- add license header

 .gitignore |  1 +
 arch/arm/Makefile  |  8 +
 scripts/.gitignore |  1 +
 scripts/Makefile   |  1 +
 scripts/zynq_mkimage.c | 86 ++
 5 files changed, 97 insertions(+)
 create mode 100644 scripts/zynq_mkimage.c

diff --git a/.gitignore b/.gitignore
index 064753d..d197196 100644
--- a/.gitignore
+++ b/.gitignore
@@ -36,6 +36,7 @@ barebox.netx
 barebox.s5p
 barebox.spi
 barebox.ubl
+barebox.zynq
 barebox.uimage
 barebox.map
 barebox-flash-image
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index ceb45dc..5682e36 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -244,6 +244,14 @@ KBUILD_TARGET := barebox.spi
 KBUILD_IMAGE := barebox.spi
 endif
 
+barebox.zynq: $(KBUILD_BINARY)
+   $(Q)scripts/zynq_mkimage $ $@
+
+ifeq ($(machine-y),zynq)
+KBUILD_TARGET := barebox.zynq
+KBUILD_IMAGE := barebox.zynq
+endif
+
 pbl := arch/arm/pbl
 zbarebox.S zbarebox.bin zbarebox: barebox.bin
$(Q)$(MAKE) $(build)=$(pbl) $(pbl)/$@
diff --git a/scripts/.gitignore b/scripts/.gitignore
index 1ca6603..bff805d 100644
--- a/scripts/.gitignore
+++ b/scripts/.gitignore
@@ -7,3 +7,4 @@ mkimage
 mkublheader
 omap_signGP
 omap4_usbboot
+zynq_mkimage
diff --git a/scripts/Makefile b/scripts/Makefile
index 08b325c..fd526e5 100644
--- a/scripts/Makefile
+++ b/scripts/Makefile
@@ -12,6 +12,7 @@ hostprogs-$(CONFIG_ARCH_NETX)+= gen_netx_image
 hostprogs-$(CONFIG_ARCH_OMAP)+= omap_signGP mk-am35xx-spi-image
 hostprogs-$(CONFIG_ARCH_S5PCxx)  += s5p_cksum
 hostprogs-$(CONFIG_ARCH_DAVINCI) += mkublheader
+hostprogs-$(CONFIG_ARCH_ZYNQ)   += zynq_mkimage
 
 HOSTLOADLIBES_omap4_usbboot = -lpthread
 omap4_usbboot-objs   := usb_linux.o omap4_usbboot.o
diff --git a/scripts/zynq_mkimage.c b/scripts/zynq_mkimage.c
new file mode 100644
index 000..a096b83
--- /dev/null
+++ b/scripts/zynq_mkimage.c
@@ -0,0 +1,86 @@
+/*
+ * Copyright (C) 2013 Steffen Trumtrar s.trumt...@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include endian.h
+#include errno.h
+#include malloc.h
+#include stdio.h
+#include stdlib.h
+#include sys/stat.h
+
+static void usage(char *name)
+{
+   printf(Usage: %s barebox-flash-image outfile\n, name);
+}
+
+int main(int argc, char *argv[])
+{
+   FILE *ifile, *ofile;
+   unsigned int *buf;
+   const char *infile;
+   const char *outfile;
+   struct stat st;
+   unsigned int i;
+   unsigned long sum = 0;
+
+   if (argc != 3) {
+   usage(argv[0]);
+   exit(1);
+   }
+
+   infile = argv[1];
+   outfile = argv[2];
+
+   if (stat(infile, st) == -1) {
+   perror(stat);
+   exit(EXIT_FAILURE);
+   }
+
+   buf = malloc(st.st_size);
+   if (!buf) {
+   fprintf(stderr, Unable to allocate buffer\n);
+   return -1;
+   }
+   ifile = fopen(infile, rb);
+   if (!ifile) {
+   fprintf(stderr, Cannot open %s for reading\n,
+   infile);
+   free(buf);
+   exit(EXIT_FAILURE);
+   }
+   ofile = fopen(outfile, wb);
+   if (!ofile) {
+   fprintf(stderr, Cannot open %s for writing\n,
+   outfile);
+   fclose(ifile);
+   free(buf);
+   exit(EXIT_FAILURE);
+   }
+
+   fread(buf, 4, st.st_size, ifile);
+
+   for (i = 0x8; i  0x12; i++)
+   sum += htole32(buf[i]);
+
+   sum = ~sum;
+   buf[i] = sum;
+
+   fwrite(buf, st.st_size / 4, 4, ofile);
+
+   fclose(ofile);
+   fclose(ifile);
+   free(buf);
+
+   return 0;
+}
-- 
1.8.2.rc2


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[PATCH v3 1/5] serial: Add driver for Cadence UART

[Steffen Trumtrar]

Support for Cadence UART core.

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---

Changes since v2:
- remove superfluous Kconfig option
- add help text to Kconfig option

 drivers/serial/Kconfig  |   5 +
 drivers/serial/Makefile |   1 +
 drivers/serial/serial_cadence.c | 307 
 3 files changed, 313 insertions(+)
 create mode 100644 drivers/serial/serial_cadence.c

diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index f61d670..73cb9f8 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -113,4 +113,9 @@ config DRIVER_SERIAL_OMAP4_USBBOOT
help
  Enable this to get console support over the usb bus used to boot an 
OMAP4
 
+config DRIVER_SERIAL_CADENCE
+   bool Cadence UART driver
+   help
+ Say Y here if you have a Cadence serial IP core.
+
 endmenu
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 893e282..963a7df 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -21,3 +21,4 @@ obj-$(CONFIG_DRIVER_SERIAL_ALTERA)+= 
serial_altera.o
 obj-$(CONFIG_DRIVER_SERIAL_ALTERA_JTAG)+= serial_altera_jtag.o
 obj-$(CONFIG_DRIVER_SERIAL_PXA)+= serial_pxa.o
 obj-$(CONFIG_DRIVER_SERIAL_OMAP4_USBBOOT)  += serial_omap4_usbboot.o
+obj-$(CONFIG_DRIVER_SERIAL_CADENCE)+= serial_cadence.o
diff --git a/drivers/serial/serial_cadence.c b/drivers/serial/serial_cadence.c
new file mode 100644
index 000..c29c391
--- /dev/null
+++ b/drivers/serial/serial_cadence.c
@@ -0,0 +1,307 @@
+/*
+ * (c) 2012 Steffen Trumtrar s.trumt...@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#include common.h
+#include driver.h
+#include init.h
+#include malloc.h
+#include notifier.h
+#include io.h
+#include linux/err.h
+#include linux/clk.h
+
+#define CADENCE_UART_CONTROL   0x00
+#define CADENCE_UART_MODE  0x04
+#define CADENCE_UART_BAUD_GEN  0x18
+#define CADENCE_UART_CHANNEL_STS   0x2C
+#define CADENCE_UART_RXTXFIFO  0x30
+#define CADENCE_UART_BAUD_DIV  0x34
+
+#define CADENCE_CTRL_RXRES (1  0)
+#define CADENCE_CTRL_TXRES (1  1)
+#define CADENCE_CTRL_RXEN  (1  2)
+#define CADENCE_CTRL_RXDIS (1  3)
+#define CADENCE_CTRL_TXEN  (1  4)
+#define CADENCE_CTRL_TXDIS (1  5)
+#define CADENCE_CTRL_RSTTO (1  6)
+#define CADENCE_CTRL_STTBRK(1  7)
+#define CADENCE_CTRL_STPBRK(1  8)
+
+#define CADENCE_MODE_CLK_REF   (0  0)
+#define CADENCE_MODE_CLK_REF_DIV   (1  0)
+#define CADENCE_MODE_CHRL_6(3  1)
+#define CADENCE_MODE_CHRL_7(2  1)
+#define CADENCE_MODE_CHRL_8(0  1)
+#define CADENCE_MODE_PAR_EVEN  (0  3)
+#define CADENCE_MODE_PAR_ODD   (1  3)
+#define CADENCE_MODE_PAR_SPACE (2  3)
+#define CADENCE_MODE_PAR_MARK  (3  3)
+#define CADENCE_MODE_PAR_NONE  (4  3)
+
+#define CADENCE_STS_REMPTY (1  1)
+#define CADENCE_STS_RFUL   (1  2)
+#define CADENCE_STS_TEMPTY (1  3)
+#define CADENCE_STS_TFUL   (1  4)
+
+/*
+ * create default values for different platforms
+ */
+struct cadence_serial_devtype_data {
+   u32 ctrl;
+   u32 mode;
+};
+
+static struct cadence_serial_devtype_data cadence_r1p08_data = {
+   .ctrl = CADENCE_CTRL_RXEN | CADENCE_CTRL_TXEN,
+   .mode = CADENCE_MODE_CLK_REF | CADENCE_MODE_CHRL_8 | 
CADENCE_MODE_PAR_NONE,
+};
+
+struct cadence_serial_priv {
+   struct console_device cdev;
+   int baudrate;
+   struct notifier_block notify;
+   void __iomem *regs;
+   struct clk *clk;
+   struct cadence_serial_devtype_data *devtype;
+};
+
+static int cadence_serial_reset(struct console_device *cdev)
+{
+   struct cadence_serial_priv *priv = container_of(cdev,
+   struct cadence_serial_priv, cdev);
+
+   /* Soft-Reset Tx/Rx paths */
+   writel(CADENCE_CTRL_RXRES | CADENCE_CTRL_TXRES, priv-regs +
+   CADENCE_UART_CONTROL);
+
+   while (readl(priv-regs + CADENCE_UART_CONTROL) 
+   (CADENCE_CTRL_RXRES | CADENCE_CTRL_TXRES))
+   ;
+
+   return 0;
+}
+
+static int cadence_serial_setbaudrate(struct console_device *cdev, int 
baudrate)
+{
+   struct cadence_serial_priv *priv = container_of(cdev

[PATCH v3 2/5] ARM: zynq: Add new architecture zynq

[Steffen Trumtrar]

Add basic support for the Xilinx Zynq-7000 EPP architecture.
The Zynq-7000 is an embedded processing platform that combines a Cortex A9
dualcore MPSoC with an Artix-7 FPGA.

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---

Changes since v2:
- don't force serial driver in Kconfig
- remove MACH_HAS_LOWLEVEL_INIT
- use (void __iomem *) in debug_ll.h
- remove zynq_add_device inline function
- use resource_size_t instead of void *
- use __le32 consistently in zynq-flash-header.h
- remove useless flash_header_start section

 arch/arm/Kconfig   |   5 +
 arch/arm/Makefile  |   2 +
 arch/arm/mach-zynq/Kconfig |  38 ++
 arch/arm/mach-zynq/Makefile|   1 +
 arch/arm/mach-zynq/devices.c   |   8 ++
 arch/arm/mach-zynq/include/mach/barebox.lds.h  |   8 ++
 arch/arm/mach-zynq/include/mach/debug_ll.h |  37 ++
 arch/arm/mach-zynq/include/mach/devices.h  |  13 ++
 .../arm/mach-zynq/include/mach/zynq-flash-header.h |  38 ++
 arch/arm/mach-zynq/include/mach/zynq7000-regs.h| 132 +
 arch/arm/mach-zynq/zynq.c  |  56 +
 include/asm-generic/barebox.lds.h  |   3 +-
 12 files changed, 340 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-zynq/Kconfig
 create mode 100644 arch/arm/mach-zynq/Makefile
 create mode 100644 arch/arm/mach-zynq/devices.c
 create mode 100644 arch/arm/mach-zynq/include/mach/barebox.lds.h
 create mode 100644 arch/arm/mach-zynq/include/mach/debug_ll.h
 create mode 100644 arch/arm/mach-zynq/include/mach/devices.h
 create mode 100644 arch/arm/mach-zynq/include/mach/zynq-flash-header.h
 create mode 100644 arch/arm/mach-zynq/include/mach/zynq7000-regs.h
 create mode 100644 arch/arm/mach-zynq/zynq.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 28332ec..8431fa8 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -110,6 +110,10 @@ config ARCH_TEGRA
select CPU_ARM926T
select HAS_DEBUG_LL
 
+config ARCH_ZYNQ
+   bool Xilinx Zynq-based boards
+   select HAS_DEBUG_LL
+
 endchoice
 
 source arch/arm/cpu/Kconfig
@@ -126,6 +130,7 @@ source arch/arm/mach-pxa/Kconfig
 source arch/arm/mach-samsung/Kconfig
 source arch/arm/mach-versatile/Kconfig
 source arch/arm/mach-tegra/Kconfig
+source arch/arm/mach-zynq/Kconfig
 
 config ARM_ASM_UNIFIED
bool
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index fcb2969..ceb45dc 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -64,6 +64,7 @@ machine-$(CONFIG_ARCH_PXA):= pxa
 machine-$(CONFIG_ARCH_SAMSUNG) := samsung
 machine-$(CONFIG_ARCH_VERSATILE)   := versatile
 machine-$(CONFIG_ARCH_TEGRA)   := tegra
+machine-$(CONFIG_ARCH_ZYNQ):= zynq
 
 # Board directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
@@ -157,6 +158,7 @@ board-$(CONFIG_MACH_SABRELITE)  := 
freescale-mx6-sabrelite
 board-$(CONFIG_MACH_TX53)  := karo-tx53
 board-$(CONFIG_MACH_GUF_VINCELL)   := guf-vincell
 board-$(CONFIG_MACH_EFIKA_MX_SMARTBOOK):= efika-mx-smartbook
+board-$(CONFIG_MACH_ZEDBOARD)  := avnet-zedboard
 
 machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
 
diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
new file mode 100644
index 000..5bbd648
--- /dev/null
+++ b/arch/arm/mach-zynq/Kconfig
@@ -0,0 +1,38 @@
+if ARCH_ZYNQ
+
+config ARCH_TEXT_BASE
+   hex
+   default 0x1ff0 if MACH_ZEDBOARD
+
+config ZYNQ_DEBUG_LL_UART_BASE
+   hex
+   default 0xe0001000 if MACH_ZEDBOARD
+
+config BOARDINFO
+   default ZedBoard if MACH_ZEDBOARD
+
+choice
+   prompt Xilinx Zynq type board
+
+config ARCH_ZYNQ7000
+   bool Zynq-7000
+   select CPU_V7
+   select CLKDEV_LOOKUP
+   select COMMON_CLK
+   select ARM_SMP_TWD
+
+endchoice
+
+if ARCH_ZYNQ7000
+
+choice
+   prompt Zynq-7000 Board Type
+
+config MACH_ZEDBOARD
+   bool Avnet Zynq-7000 ZedBoard
+   select DRIVER_SERIAL_CADENCE
+
+endchoice
+endif
+
+endif
diff --git a/arch/arm/mach-zynq/Makefile b/arch/arm/mach-zynq/Makefile
new file mode 100644
index 000..459c957
--- /dev/null
+++ b/arch/arm/mach-zynq/Makefile
@@ -0,0 +1 @@
+obj-y += zynq.o devices.o clk-zynq7000.o
diff --git a/arch/arm/mach-zynq/devices.c b/arch/arm/mach-zynq/devices.c
new file mode 100644
index 000..777bb87
--- /dev/null
+++ b/arch/arm/mach-zynq/devices.c
@@ -0,0 +1,8 @@
+#include common.h
+#include driver.h
+#include mach/devices.h
+
+struct device_d *zynq_add_uart(resource_size_t base, int id)
+{
+   return add_generic_device(cadence-uart, id, NULL, base, 0x1000, 
IORESOURCE_MEM, NULL);
+}
diff --git a/arch/arm/mach-zynq/include/mach/barebox.lds.h 
b/arch/arm/mach-zynq/include/mach

[PATCH] ARM: zynq: fix zynq_clks enum

[Steffen Trumtrar]

clk-zynq7000 registers arm_smp_twd as clk. This clock was however not added to
the zynq_clks enum.

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 arch/arm/mach-zynq/clk-zynq7000.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-zynq/clk-zynq7000.c 
b/arch/arm/mach-zynq/clk-zynq7000.c
index 1e03514..3dedefa 100644
--- a/arch/arm/mach-zynq/clk-zynq7000.c
+++ b/arch/arm/mach-zynq/clk-zynq7000.c
@@ -31,7 +31,8 @@
 
 enum zynq_clks {
dummy, ps_clk, arm_pll, ddr_pll, io_pll, uart_clk, uart0, uart1,
-   cpu_clk, cpu_6x4x, cpu_3x2x, cpu_2x, cpu_1x, clks_max
+   cpu_clk, cpu_6x4x, cpu_3x2x, cpu_2x, cpu_1x, arm_smp_twd,
+   clks_max
 };
 
 enum zynq_pll_type {
-- 
1.8.2.rc2


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[PATCH 3/3] ARM: zedboard: add ethernet device

[Steffen Trumtrar]

The ZedBoard has a connection for the GEM0. Use it.

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 arch/arm/boards/avnet-zedboard/board.c| 13 +
 arch/arm/boards/avnet-zedboard/lowlevel.c | 11 ++-
 2 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boards/avnet-zedboard/board.c 
b/arch/arm/boards/avnet-zedboard/board.c
index 4e3d5a5..7b95754 100644
--- a/arch/arm/boards/avnet-zedboard/board.c
+++ b/arch/arm/boards/avnet-zedboard/board.c
@@ -29,6 +29,19 @@ static int zedboard_mem_init(void)
 }
 mem_initcall(zedboard_mem_init);
 
+static struct macb_platform_data macb_pdata = {
+   .phy_interface = PHY_INTERFACE_MODE_RGMII,
+   .phy_addr = 0x0,
+};
+
+static int zedboard_device_init(void)
+{
+   zynq_add_eth0(macb_pdata);
+
+   return 0;
+}
+device_initcall(zedboard_device_init);
+
 static int zedboard_console_init(void)
 {
zynq_add_uart1();
diff --git a/arch/arm/boards/avnet-zedboard/lowlevel.c 
b/arch/arm/boards/avnet-zedboard/lowlevel.c
index b50886e..fb05ef8 100644
--- a/arch/arm/boards/avnet-zedboard/lowlevel.c
+++ b/arch/arm/boards/avnet-zedboard/lowlevel.c
@@ -233,14 +233,23 @@ void __naked barebox_arm_reset_vector(void)
/* poor mans clkctrl */
writel(0x1403, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_UART_CLK_CTRL);
 
+   /* GEM0 */
writel(0x0001, 0xf8000138);
-   writel(0x00100801, 0xf8000140);
+   writel(0x00500801, 0xf8000140);
writel(0x0302, 0xf8000740);
writel(0x0302, 0xf8000744);
writel(0x0302, 0xf8000748);
writel(0x0302, 0xf800074C);
writel(0x0302, 0xf8000750);
writel(0x0302, 0xf8000754);
+   writel(0x1303, 0xf8000758);
+   writel(0x1303, 0xf800075C);
+   writel(0x1303, 0xf8000760);
+   writel(0x1303, 0xf8000764);
+   writel(0x1303, 0xf8000768);
+   writel(0x1303, 0xf800076C);
+   writel(0x1280, 0xf80007D0);
+   writel(0x1280, 0xf80007D4);
 
writel(0x0001, 0xf8000B00);
 
-- 
1.8.2.rc2


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[PATCH 1/3] net: macb: turn off endian_swp_pkt_en

[Steffen Trumtrar]

The core has a bit for swapping packet data endianism.
Reset default from Cadence is off. Xilinx however, that uses this core on the
Zynq SoCs, opted for on. Turn it off for all devices.

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
Cc: Jean-Christophe PLAGNIOL-VILLARD plagn...@jcrosoft.com
---

Notes:
This fix was already applied to next for the linux driver counterpart.

 drivers/net/macb.c | 1 +
 drivers/net/macb.h | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index 14a0689..4c0f206 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -307,6 +307,7 @@ static void macb_configure_dma(struct macb_device *bp)
dmacfg |= GEM_BF(FBLDO, 16);
dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
dmacfg |= GEM_BIT(DDRP);
+   dmacfg = ~GEM_BIT(ENDIA);
gem_writel(bp, DMACFG, dmacfg);
}
 }
diff --git a/drivers/net/macb.h b/drivers/net/macb.h
index cadd561..1be9ff9 100644
--- a/drivers/net/macb.h
+++ b/drivers/net/macb.h
@@ -168,6 +168,8 @@
 /* Bitfields in DMACFG. */
 #define GEM_FBLDO_OFFSET   0
 #define GEM_FBLDO_SIZE 5
+#define GEM_ENDIA_OFFSET   7
+#define GEM_ENDIA_SIZE 1
 #define GEM_RXBMS_OFFSET   8
 #define GEM_RXBMS_SIZE 2
 #define GEM_TXPBMS_OFFSET  10
-- 
1.8.2.rc2


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[PATCH] of: property: fix error message

[Steffen Trumtrar]

At least in standard oxford english one not is enough.

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 commands/of_property.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/commands/of_property.c b/commands/of_property.c
index 6311b70..44bb388 100644
--- a/commands/of_property.c
+++ b/commands/of_property.c
@@ -62,7 +62,7 @@ static int of_parse_prop_cells(char * const *newval, int 
count, char *data, int
 
/* If the ptr didn't advance, something went wrong */
if ((newp - cp) = 0) {
-   printf(cannot not convert \%s\\n, cp);
+   printf(cannot convert \%s\\n, cp);
return -EINVAL;
}
 
@@ -105,7 +105,7 @@ static int of_parse_prop_stream(char * const *newval, int 
count, char *data, int
 
/* If the ptr didn't advance, something went wrong */
if ((newp - cp) = 0) {
-   printf(cannot not convert \%s\\n, cp);
+   printf(cannot convert \%s\\n, cp);
return -EINVAL;
}
}
-- 
1.8.2.rc2


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[PATCH] mci i.MX esdhc: Fix clock divider calculation

[Steffen Trumtrar]

From: Sascha Hauer s.ha...@pengutronix.de

This updates the i.MX esdhc divider settings to FSLs U-Boot.
Current timings work fine for SD cards, but not for eMMC.
Although the calculation is fine according to the datasheet and reading from
eMMC works, writing is broken. Atleast on i.MX53/tqma53.
With this patch the result is the same, but uses different divider values to
achieve it.

While at it, replace the udelay with a busy-loop.

Signed-off-by: Sascha Hauer s.ha...@pengutronix.de
Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 drivers/mci/imx-esdhc.c | 46 +++---
 drivers/mci/imx-esdhc.h |  1 +
 2 files changed, 28 insertions(+), 19 deletions(-)

diff --git a/drivers/mci/imx-esdhc.c b/drivers/mci/imx-esdhc.c
index 8c2695c..6a9faf9 100644
--- a/drivers/mci/imx-esdhc.c
+++ b/drivers/mci/imx-esdhc.c
@@ -69,7 +69,6 @@ struct fsl_esdhc_host {
struct mci_host mci;
struct fsl_esdhc __iomem*regs;
u32 no_snoop;
-   unsigned long   cur_clock;
struct device_d *dev;
struct clk  *clk;
 };
@@ -358,37 +357,46 @@ static void set_sysctl(struct mci_host *mci, u32 clock)
struct fsl_esdhc __iomem *regs = host-regs;
int sdhc_clk = clk_get_rate(host-clk);
u32 clk;
-
-   if (clock  mci-f_min)
-   clock = mci-f_min;
-
-   pre_div = 0;
-
-   for (pre_div = 1; pre_div  256; pre_div = 1) {
-   if (sdhc_clk / pre_div  clock * 16)
+   unsigned long  cur_clock;
+
+   /*
+* With eMMC and imx53 (sdhc_clk=200MHz) a pre_div of 1 results in
+*  pre_div=1,div=4 (=50MHz)
+* which is valid and should work, but somehow doesn't.
+* Starting with pre_div=2 gives
+*  pre_div=2, div=2 (=50MHz)
+* and works fine.
+*/
+   pre_div = 2;
+
+   if (sdhc_clk == clock)
+   pre_div = 1;
+   else if (sdhc_clk / 16  clock)
+   for (; pre_div  256; pre_div *= 2)
+   if ((sdhc_clk / pre_div) = (clock * 16))
+   break;
+
+   for (div = 1; div = 16; div++)
+   if ((sdhc_clk / (div * pre_div)) = clock)
break;
-   };
-
-   div = sdhc_clk / pre_div / clock;
 
-   if (sdhc_clk / pre_div / div  clock)
-   div++;
+   cur_clock = sdhc_clk / pre_div / div;
 
-   host-cur_clock = sdhc_clk / pre_div / div;
+   dev_dbg(host-dev, set clock: wanted: %d got: %ld\n, clock, 
cur_clock);
+   dev_dbg(host-dev, pre_div: %d div: %d\n, pre_div, div);
 
+   /* the register values start with 0 */
div -= 1;
pre_div = 1;
 
-   dev_dbg(host-dev, set clock: wanted: %d got: %ld\n, clock, 
host-cur_clock);
-   dev_dbg(host-dev, pre_div: %d div: %d\n, pre_div, div);
-
clk = (pre_div  8) | (div  4);
 
esdhc_clrbits32(regs-sysctl, SYSCTL_CKEN);
 
esdhc_clrsetbits32(regs-sysctl, SYSCTL_CLOCK_MASK, clk);
 
-   udelay(1);
+   wait_on_timeout(10 * MSECOND,
+   !(esdhc_read32(regs-prsstat)  PRSSTAT_SDSTB));
 
clk = SYSCTL_PEREN | SYSCTL_CKEN;
 
diff --git a/drivers/mci/imx-esdhc.h b/drivers/mci/imx-esdhc.h
index 2be63a5..e145bcb 100644
--- a/drivers/mci/imx-esdhc.h
+++ b/drivers/mci/imx-esdhc.h
@@ -86,6 +86,7 @@
 #define PRSSTAT_CINS   (0x0001)
 #define PRSSTAT_BREN   (0x0800)
 #define PRSSTAT_BWEN   (0x0400)
+#define PRSSTAT_SDSTB  (0x0008)
 #define PRSSTAT_DLA(0x0004)
 #define PRSSTAT_CICHB  (0x0002)
 #define PRSSTAT_CIDHB  (0x0001)
-- 
1.8.2.rc2


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Re: [PATCH] mci i.MX esdhc: Fix clock divider calculation

[Steffen Trumtrar]

On Tue, May 21, 2013 at 09:27:08PM +0200, Sascha Hauer wrote:
 On Tue, May 21, 2013 at 12:29:20PM +0200, Steffen Trumtrar wrote:
  From: Sascha Hauer s.ha...@pengutronix.de
  
  This updates the i.MX esdhc divider settings to FSLs U-Boot.
  Current timings work fine for SD cards, but not for eMMC.
  Although the calculation is fine according to the datasheet and reading from
  eMMC works, writing is broken. Atleast on i.MX53/tqma53.
  With this patch the result is the same, but uses different divider values to
  achieve it.
  
  While at it, replace the udelay with a busy-loop.
  
  Signed-off-by: Sascha Hauer s.ha...@pengutronix.de
  Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
  ---
   drivers/mci/imx-esdhc.c | 46 +++---
   drivers/mci/imx-esdhc.h |  1 +
   2 files changed, 28 insertions(+), 19 deletions(-)
 
 Could you rebase this one on -next?
 
 Sascha
 

Sure. Will resend in a second.

Steffen

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[PATCH v2] mci i.MX esdhc: Fix clock divider calculation

[Steffen Trumtrar]

From: Sascha Hauer s.ha...@pengutronix.de

This updates the i.MX esdhc divider settings to FSLs U-Boot.
Current timings work fine for SD cards, but not for eMMC.
Although the calculation is fine according to the datasheet and reading from
eMMC works, writing is broken. Atleast on i.MX53/tqma53.
With this patch the result is the same, but uses different divider values to
achieve it.

While at it, replace the udelay with a busy-loop.

Signed-off-by: Sascha Hauer s.ha...@pengutronix.de
Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
Changes since v1:
- rebased onto -next

 drivers/mci/imx-esdhc.c | 46 +++---
 drivers/mci/sdhci.h |  1 +
 2 files changed, 28 insertions(+), 19 deletions(-)

diff --git a/drivers/mci/imx-esdhc.c b/drivers/mci/imx-esdhc.c
index ae934f4..46bd6d2 100644
--- a/drivers/mci/imx-esdhc.c
+++ b/drivers/mci/imx-esdhc.c
@@ -44,7 +44,6 @@
 struct fsl_esdhc_host {
struct mci_host mci;
void __iomem*regs;
-   unsigned long   cur_clock;
struct device_d *dev;
struct clk  *clk;
 };
@@ -333,30 +332,38 @@ static void set_sysctl(struct mci_host *mci, u32 clock)
void __iomem *regs = host-regs;
int sdhc_clk = clk_get_rate(host-clk);
u32 clk;
-
-   if (clock  mci-f_min)
-   clock = mci-f_min;
-
-   pre_div = 0;
-
-   for (pre_div = 1; pre_div  256; pre_div = 1) {
-   if (sdhc_clk / pre_div  clock * 16)
+   unsigned long  cur_clock;
+
+   /*
+* With eMMC and imx53 (sdhc_clk=200MHz) a pre_div of 1 results in
+*  pre_div=1,div=4 (=50MHz)
+* which is valid and should work, but somehow doesn't.
+* Starting with pre_div=2 gives
+*  pre_div=2, div=2 (=50MHz)
+* and works fine.
+*/
+   pre_div = 2;
+
+   if (sdhc_clk == clock)
+   pre_div = 1;
+   else if (sdhc_clk / 16  clock)
+   for (; pre_div  256; pre_div *= 2)
+   if ((sdhc_clk / pre_div) = (clock * 16))
+   break;
+
+   for (div = 1; div = 16; div++)
+   if ((sdhc_clk / (div * pre_div)) = clock)
break;
-   };
-
-   div = sdhc_clk / pre_div / clock;
 
-   if (sdhc_clk / pre_div / div  clock)
-   div++;
+   cur_clock = sdhc_clk / pre_div / div;
 
-   host-cur_clock = sdhc_clk / pre_div / div;
+   dev_dbg(host-dev, set clock: wanted: %d got: %ld\n, clock, 
cur_clock);
+   dev_dbg(host-dev, pre_div: %d div: %d\n, pre_div, div);
 
+   /* the register values start with 0 */
div -= 1;
pre_div = 1;
 
-   dev_dbg(host-dev, set clock: wanted: %d got: %ld\n, clock, 
host-cur_clock);
-   dev_dbg(host-dev, pre_div: %d div: %d\n, pre_div, div);
-
clk = (pre_div  8) | (div  4);
 
esdhc_clrbits32(regs + 
SDHCI_CLOCK_CONTROL__TIMEOUT_CONTROL__SOFTWARE_RESET,
@@ -365,7 +372,8 @@ static void set_sysctl(struct mci_host *mci, u32 clock)
esdhc_clrsetbits32(regs + 
SDHCI_CLOCK_CONTROL__TIMEOUT_CONTROL__SOFTWARE_RESET,
SYSCTL_CLOCK_MASK, clk);
 
-   udelay(1);
+   wait_on_timeout(10 * MSECOND,
+   !(esdhc_read32(regs + SDHCI_PRESENT_STATE)  
PRSSTAT_SDSTB));
 
clk = SYSCTL_PEREN | SYSCTL_CKEN;
 
diff --git a/drivers/mci/sdhci.h b/drivers/mci/sdhci.h
index ad1bbd9..b2d6779 100644
--- a/drivers/mci/sdhci.h
+++ b/drivers/mci/sdhci.h
@@ -81,6 +81,7 @@
 #define PRSSTAT_CINS   0x0001
 #define PRSSTAT_BREN   0x0800
 #define PRSSTAT_BWEN   0x0400
+#define PRSSTAT_SDSTB  0x0008
 #define PRSSTAT_DLA0x0004
 #define PRSSTAT_CIDHB  0x0002
 #define PRSSTAT_CICHB  0x0001
-- 
1.8.2.rc2


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[PATCH] ARM i.MX53: tqma53: fix console entry

[Steffen Trumtrar]

The default baseboard for the tqma53 (MBa53) uses UART2 for debug console.

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 arch/arm/boards/tqma53/env/config-board | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boards/tqma53/env/config-board 
b/arch/arm/boards/tqma53/env/config-board
index 4776438..28d015e 100644
--- a/arch/arm/boards/tqma53/env/config-board
+++ b/arch/arm/boards/tqma53/env/config-board
@@ -4,4 +4,4 @@
 # instead
 
 global.hostname=tqma53
-global.linux.bootargs.base=console=ttymxc0,115200
+global.linux.bootargs.base=console=ttymxc1,115200
-- 
1.8.2.rc2


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[PATCH] mci: sdhci: fix IRQSTAT_DMAE bit shift

[Steffen Trumtrar]

According to the SD Host Controller Specification Version 3.00, the ADMA error
status bit is on the wrong bit. Fix this.

While at it, add the missing standard error status bits.

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 drivers/mci/sdhci.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/mci/sdhci.h b/drivers/mci/sdhci.h
index b2d6779..2c8b6f5 100644
--- a/drivers/mci/sdhci.h
+++ b/drivers/mci/sdhci.h
@@ -37,8 +37,10 @@
 #define TRANSFER_MODE_BCEN 0x0002
 #define TRANSFER_MODE_DMAEN0x0001
 
-#define IRQSTAT_DMAE   0x1000
+#define IRQSTAT_TE 0x0400
+#define IRQSTAT_DMAE   0x0200
 #define IRQSTAT_AC12E  0x0100
+#define IRQSTAT_CLE0x0080
 #define IRQSTAT_DEBE   0x0040
 #define IRQSTAT_DCE0x0020
 #define IRQSTAT_DTOE   0x0010
-- 
1.8.4.rc3


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Re: [PATCH 08/11] ARM: socfpga: Add FPGA programming command

[Steffen Trumtrar]

On Mon, Sep 16, 2013 at 01:09:14PM +0200, Sascha Hauer wrote:
 Hi Steffen,
 
 On Mon, Sep 16, 2013 at 12:40:41PM +0200, Steffen Trumtrar wrote:
  Hi!
  
  On Mon, Sep 16, 2013 at 10:48:17AM +0200, Sascha Hauer wrote:
   This adds a simple socfpga specific 'fpga' command to load a firmware
   to the FPGA. For the moment this is enough, but should we get more
   FPGA support it might be a good idea to introduce some generic framework
   and command.
   
   Signed-off-by: Sascha Hauer s.ha...@pengutronix.de
   ---
arch/arm/mach-socfpga/Kconfig |   5 +
arch/arm/mach-socfpga/Makefile|   1 +
arch/arm/mach-socfpga/fpga.c  | 422 
   ++
arch/arm/mach-socfpga/include/mach/socfpga-regs.h |   2 +
4 files changed, 430 insertions(+)
create mode 100644 arch/arm/mach-socfpga/fpga.c
   
  
  Why did you chose to have an extra command for fpga loading instead of 
  having
  just a (block)device? Do you see any future advantage in that or is it just
  because of the port from u-boot? I know that they need an extra fpga 
  command, but
  they also have an extra mmcload command and stuff.
 
 Main reason was that I was unsure how good a block device will be when
 we get a different firmware format to load (rbf vs. sof vs. something
 else)
 

Aha, okay. If we want/need to support different formats, than a special
command might be necessary. At least when the format is not easy to
autodetect, I guess.

Steffen

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Re: [PATCH] gpio: Add designware gpio controller support

[Steffen Trumtrar]

On Thu, Oct 17, 2013 at 10:24:11AM +0200, Sebastian Hesselbarth wrote:
 On 10/17/2013 10:04 AM, Steffen Trumtrar wrote:
 On Mon, Sep 09, 2013 at 06:28:48PM +0200, Sebastian Hesselbarth wrote:
 On 09/09/13 16:54, Sascha Hauer wrote:
 Signed-off-by: Sascha Hauer s.ha...@pengutronix.de
 ---
   drivers/gpio/Kconfig   |   6 ++
   drivers/gpio/Makefile  |   1 +
   drivers/gpio/gpio-dw.c | 151 
  +
   3 files changed, 158 insertions(+)
   create mode 100644 drivers/gpio/gpio-dw.c
 
 diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
 index d5ac532..18d3135 100644
 --- a/drivers/gpio/Kconfig
 +++ b/drivers/gpio/Kconfig
 @@ -54,6 +54,12 @@ config GPIO_TEGRA
help
  Say yes here to include the driver for the GPIO controller found on 
  the
  Tegra line of SoCs.
 +
 +config GPIO_DESIGNWARE
 +  tristate Synopsys DesignWare GPIO driver
 
 Sascha,
 
 I know DW's GPIO is also used on Armada 1500 which I currently work on.
 Precisely, the IP is named dw-apb-gpio. Maybe the above should also
 reflect APB.
 
 [...]
 
 Please add snps,dw-apb-gpio, that's what the linux driver
 will look for if make to pick it up for Armada 1500.
 
 
 Are you talking about the 'old' linux driver that was posted sometime around
 January 2012 or are you working on your own?
 
 Cannot recall the actual version or time posted. I didn't find time to
 work on a linux driver for dw-apb-gpio, yet. My idea was to pick up the
 latest driver posted plus make it more general. IIRC the one posted was
 very limited to socfpga.
 

The one I found, is already used in a picoxcell dts. Altough, no driver is 
present.
Altera has a driver in their kernel, but the binding is different.
Actually, that is where Sascha got it from. So, let's try and use at least the
binding from Altera ;-)

 Do you have a working pre-release version somewhere?
 
 Sorry, nothing started, yet.
 

Okay.

 Are you going to work on it? If so, feel free to involve me in patches
 and reviews.

If time permits, yes.

Regards,
Steffen

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[PATCH 2/2] ARM: socfgpa: sockit: update sequencer_defines

[Steffen Trumtrar]

Use the new Quartus II v13.1 generated sequencer_defines.h file.

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 arch/arm/boards/terasic-sockit/sequencer_defines.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boards/terasic-sockit/sequencer_defines.h 
b/arch/arm/boards/terasic-sockit/sequencer_defines.h
index a59eed2..a3cd7a8 100644
--- a/arch/arm/boards/terasic-sockit/sequencer_defines.h
+++ b/arch/arm/boards/terasic-sockit/sequencer_defines.h
@@ -21,8 +21,8 @@
 #define BFM_MODE 0
 #define BURST2 0
 #define CALIBRATE_BIT_SLIPS 0
-#define CALIB_LFIFO_OFFSET 11
-#define CALIB_VFIFO_OFFSET 9
+#define CALIB_LFIFO_OFFSET 12
+#define CALIB_VFIFO_OFFSET 10
 #define CYCLONEV 1
 #define DDR2 0
 #define DDR3 1
@@ -79,7 +79,7 @@
 #define RDIMM 0
 #define READ_AFTER_WRITE_CALIBRATION 1
 #define READ_VALID_FIFO_SIZE 16
-#define REG_FILE_INIT_SEQ_SIGNATURE 0x0482
+#define REG_FILE_INIT_SEQ_SIGNATURE 0x0483
 #define RLDRAM3 0
 #define RLDRAMII 0
 #define RLDRAMX 0
-- 
1.8.4.3


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[PATCH 0/2] SOCFPGA: update to v13.1 preloader files

[Steffen Trumtrar]

Hi!

This updates the SocFPGA sequencer to the one generated by quartus v13.1.
Previously this was generated with the v13.0 quartus.

Tested on the SocKit.
The Socrates is only compile tested.

Regards,
Steffen

Steffen Trumtrar (2):
  ARM: socfgpa: update sequencer
  ARM: socfgpa: sockit: update sequencer_defines

 arch/arm/boards/terasic-sockit/sequencer_defines.h |  6 +--
 arch/arm/mach-socfpga/include/mach/sequencer.c | 59 +++---
 2 files changed, 44 insertions(+), 21 deletions(-)

-- 
1.8.4.3


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[PATCH 1/2] ARM: socfgpa: update sequencer

[Steffen Trumtrar]

Quartus II v13.1 generates updated sequencer.[ch] files.
Integrate the changes into the current driver.

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 arch/arm/mach-socfpga/include/mach/sequencer.c | 59 ++
 1 file changed, 41 insertions(+), 18 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/sequencer.c 
b/arch/arm/mach-socfpga/include/mach/sequencer.c
index 1124dee..fa955ce 100644
--- a/arch/arm/mach-socfpga/include/mach/sequencer.c
+++ b/arch/arm/mach-socfpga/include/mach/sequencer.c
@@ -632,6 +632,22 @@ static void scc_mgr_set_dm_in_delay(uint32_t write_group,
WRITE_SCC_DM_IO_IN_DELAY(dm, delay);
 }
 
+static void scc_mgr_load_dqs_for_write_group (uint32_t write_group)
+{
+   uint32_t read_group;
+
+   /*
+* Although OCT affects only write data, the OCT delay is controlled
+* by the DQS logic block which is instantiated once per read group.
+* For protocols where a write group consists of multiple read groups,
+* the setting must be scanned multiple times.
+*/
+   for (read_group = write_group * RW_MGR_NUM_DQS_PER_WRITE_GROUP;
+   read_group  (write_group + 1) * RW_MGR_NUM_DQS_PER_WRITE_GROUP;
+   ++read_group)
+   IOWR_32DIRECT(SCC_MGR_DQS_ENA, 0, read_group);
+}
+
 /*
  * USER Zero all DQS config
  * TODO: maybe rename to scc_mgr_zero_dqs_config (or something)
@@ -741,14 +757,26 @@ static void scc_mgr_zero_group (uint32_t write_group, 
uint32_t test_begin,
 #if ARRIAV || CYCLONEV
/* av/cv don't have out2 */
scc_mgr_set_dqs_out1_delay(write_group, IO_DQS_OUT_RESERVE);
+   scc_mgr_set_oct_out1_delay(write_group, IO_DQS_OUT_RESERVE);
+   scc_mgr_load_dqs_for_write_group(write_group);
 #else
scc_mgr_set_dqs_out1_delay(write_group, 0);
scc_mgr_set_dqs_out2_delay(write_group, IO_DQS_OUT_RESERVE);
+   scc_mgr_set_oct_out1_delay(write_group, 0);
+   scc_mgr_set_oct_out2_delay(write_group, IO_DQS_OUT_RESERVE);
+   scc_mgr_load_dqs_for_write_group(write_group);
 #endif
 
/* multicast to all DQS IO enables (only 1) */
IOWR_32DIRECT(SCC_MGR_DQS_IO_ENA, 0, 0);
 
+#if USE_SHADOW_REGS
+   /*
+* in shadow-register mode, SCC_UPDATE is done on a per-group 
basis
+* unless we explicitly ask for a multicast via the group 
counter
+*/
+   IOWR_32DIRECT(SCC_MGR_UPD, 0, 0);
+#endif
/* hit update to zero everything */
IOWR_32DIRECT(SCC_MGR_UPD, 0, 0);
}
@@ -761,23 +789,6 @@ static void scc_mgr_load_dqs (uint32_t dqs)
IOWR_32DIRECT(SCC_MGR_DQS_ENA, 0, dqs);
 }
 
-static void scc_mgr_load_dqs_for_write_group (uint32_t write_group)
-{
-   uint32_t read_group;
-
-   /*
-* Although OCT affects only write data, the OCT delay is controlled
-* by the DQS logic block which is instantiated once per read group.
-* For protocols where a write group consists of multiple read groups,
-* the setting must be scanned multiple times.
-*/
-   for (read_group = write_group * RW_MGR_NUM_DQS_PER_WRITE_GROUP;
-   read_group  (write_group + 1) * RW_MGR_NUM_DQS_PER_WRITE_GROUP;
-   ++read_group)
-   IOWR_32DIRECT(SCC_MGR_DQS_ENA, 0, read_group);
-}
-
-
 /* load up dqs io config settings */
 
 static void scc_mgr_load_dqs_io (void)
@@ -3807,6 +3818,14 @@ static void mem_config (void)
wlat += IORD_32DIRECT (DATA_MGR_MEM_T_ADD, 0);
/* WL for hard phy does not include additive latency */
 
+   /*
+* YYONG: add addtional write latency to offset the address/command 
extra clock cycle
+* YYONG: We change the AC mux setting causing AC to be delayed by one 
mem clock cycle
+* YYONG: only do this for DDR3
+*/
+#if DDR3 || DDR2
+   wlat += 1;
+#endif
rlat = IORD_32DIRECT (MEM_T_RL_ADD, 0);
 
if (QUARTER_RATE_MODE) {
@@ -4129,7 +4148,11 @@ static void initialize_hps_phy(void)
count in 16 LSB. */
 
reg = 0;
+#if DDR3 || DDR2
+   reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(2);
+#else
reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(1);
+#endif
reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(1);
reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(1);
reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(1);
@@ -4195,7 +4218,7 @@ static void initialize_tracking(void)
concatenated_delays = concatenated_delays ^ 14;
/* trcd, worst case */
concatenated_delays = concatenated_delays  8;
-   concatenated_delays = concatenated_delays ^ 5;
+   concatenated_delays = concatenated_delays ^ 10;
/* vfifo wait */
concatenated_delays = concatenated_delays  8

Re: [PATCH 0/2] SOCFPGA: update to v13.1 preloader files

[Steffen Trumtrar]

On Wed, Dec 04, 2013 at 05:34:10PM +0100, Sascha Hauer wrote:
 On Wed, Dec 04, 2013 at 01:10:38PM +0100, Steffen Trumtrar wrote:
  Hi!
  
  This updates the SocFPGA sequencer to the one generated by quartus v13.1.
  Previously this was generated with the v13.0 quartus.
  
  Tested on the SocKit.
  The Socrates is only compile tested.
 
 Applied, thanks.
 
 Does this have positive effects on the Linux stability?
 

It does make Linux a little bit more stable.
And as far as I can tell, it changes the memory behavior by writing to
undocumented address spaces. (or I just haven't found the description of
those registers).

Steffen

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[PATCH 0/3] Socfpga: update preloader files - The missing link

[Steffen Trumtrar]

Hi!

This is an addon to the series

SOCFPGA: update to v13.1 preloader files

The last series was actually missing a rather important update to the
iocsr setup.
The current barebox version produces a (memory?)setup, that leads to
an unstable linux kernel. Namely: page alloc errors, kmemleaks and
NULL pointer dereferences on the Terasic SoCkit. The EBV Socrates didn't
show these errors.

Something in those magic numbers in patch 2/3 seems to fix this,
as these problems haven't been seen as of yet with this new setup.

Regards,
Steffen

Steffen Trumtrar (3):
  ARM: socfpga: sockit: update sdram config
  ARM: socfpga: update iocsr config
  ARM: socfpga: sockit: reconfigure src for sdmmc

 arch/arm/boards/terasic-sockit/pll_config.h   |   2 +-
 arch/arm/boards/terasic-sockit/sdram_config.h |  21 +-
 arch/arm/mach-socfpga/iocsr-config-cyclone5.c | 418 +-
 3 files changed, 223 insertions(+), 218 deletions(-)

-- 
1.8.4.3


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[PATCH 3/3] ARM: socfpga: sockit: reconfigure src for sdmmc

[Steffen Trumtrar]

Update to Quartus v13.1 autogenerated version.

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 arch/arm/boards/terasic-sockit/pll_config.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boards/terasic-sockit/pll_config.h 
b/arch/arm/boards/terasic-sockit/pll_config.h
index 732f241..672ce41 100644
--- a/arch/arm/boards/terasic-sockit/pll_config.h
+++ b/arch/arm/boards/terasic-sockit/pll_config.h
@@ -54,7 +54,7 @@
  * 1 = MAIN_CLK
  * 2 = PERIPH_CLK
  */
-#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC (1)
+#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC (2)
 #define CONFIG_HPS_PERPLLGRP_SRC_NAND  (2)
 #define CONFIG_HPS_PERPLLGRP_SRC_QSPI  (1)
 
-- 
1.8.4.3


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[PATCH 1/3] ARM: socfpga: sockit: update sdram config

[Steffen Trumtrar]

This updates/changes the sdram config for the sockit to the quartus v13.1
autogenerated version.

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 arch/arm/boards/terasic-sockit/sdram_config.h | 21 +
 1 file changed, 13 insertions(+), 8 deletions(-)

diff --git a/arch/arm/boards/terasic-sockit/sdram_config.h 
b/arch/arm/boards/terasic-sockit/sdram_config.h
index 3d6f938..2c04b02 100644
--- a/arch/arm/boards/terasic-sockit/sdram_config.h
+++ b/arch/arm/boards/terasic-sockit/sdram_config.h
@@ -1,3 +1,6 @@
+#ifndef __SDRAM_CONFIG_H
+#define __SDRAM_CONFIG_H
+
 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE (2)
 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL   (8)
 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER   (0)
@@ -58,12 +61,14 @@
 #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0   (0)
 #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4  (0x41041041)
 #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 (0x410410)
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 
(0x80808080)
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 
(0x80808080)
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 
(0x8080)
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 
(0x01010101)
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 
(0x01010101)
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 
(0x0101)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ(0)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE   (1)
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED  (0x0)
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED (0x0)
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED   (0x0)
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST (0x0)
 
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ(0)
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE   (1)
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED  (0)
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED (0)
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED   (0)
+#endif /*#ifndef__SDRAM_CONFIG_H*/
-- 
1.8.4.3


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[PATCH 2/3] ARM: socfpga: update iocsr config

[Steffen Trumtrar]

Update the IO configuration to the Quartus v13.1 version. This seems to fix a
stability issue under the linux kernel when started with barebox.
As this is undocumented, autogenerated stuff, one can not be sure what it really
does nor if it really fixes the problem or just relocates it.

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 arch/arm/mach-socfpga/iocsr-config-cyclone5.c | 418 +-
 1 file changed, 209 insertions(+), 209 deletions(-)

diff --git a/arch/arm/mach-socfpga/iocsr-config-cyclone5.c 
b/arch/arm/mach-socfpga/iocsr-config-cyclone5.c
index 4b44c29..44238b3 100644
--- a/arch/arm/mach-socfpga/iocsr-config-cyclone5.c
+++ b/arch/arm/mach-socfpga/iocsr-config-cyclone5.c
@@ -10,119 +10,119 @@ const unsigned long 
iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH
0xC000,
0x003F,
0x8000,
-   0x4824,
-   0x01209000,
-   0x8240,
-   0x00018004,
+   0x00060180,
+   0x1806,
+   0x1800,
+   0x00018060,
0x,
0x4000,
-   0x2412,
-   0x00904800,
-   0x4120,
-   0x8002,
-   0x0904,
+   0x000300C0,
+   0x0C03,
+   0x0C00,
+   0x0030,
+   0xC030,
0x2000,
-   0x1209,
-   0x00482400,
-   0x2090,
-   0x4001,
-   0x0482,
+   0x00018060,
+   0x06018000,
+   0x0600,
+   0x0018,
+   0x6018,
0x1000,
 };
 
 const unsigned long 
iocsr_scan_chain1_table[((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = {
-   0x9048,
-   0x02412000,
-   0x048000C0,
-   0x0009,
-   0x2412,
+   0x0010,
+   0x300C,
+   0x30C0,
+   0x00C0,
+   0x000300C0,
0x8000,
-   0x4824,
-   0x01209000,
-   0x8240,
-   0x0004,
-   0x1209,
+   0x0008,
+   0x2000,
+   0x,
+   0x0080,
+   0x0002,
0x4000,
-   0x2412,
-   0x00904800,
-   0x4120,
-   0x8002,
-   0x0904,
+   0x000300C0,
+   0x1000,
+   0x0C00,
+   0x0030,
+   0xC030,
0x2000,
-   0x06001209,
-   0x00482400,
+   0x06018060,
+   0x06018000,
0x01FE,
0xF800,
0x0007,
-   0x80001000,
-   0x0904,
-   0x00241200,
-   0x9048,
-   0x20003000,
-   0x0241,
+   0x1000,
+   0xC030,
+   0x0300C000,
+   0x0300,
+   0x300C,
+   0x300C,
0x0800,
0x,
0x,
-   0x4824,
-   0x9000,
-   0x0120,
+   0x0180,
+   0x0006,
+   0x2000,
0x0400,
0x,
-   0x00090480,
+   0x00C03000,
0x0003,
0x,
0x,
-   0x9200,
-   0x00600120,
+   0x0200,
+   0x00601806,
0x,
-   0x1209,
-   0x24000600,
-   0x0048,
-   0x48000100,
-   0x00300090,
-   0xC0024120,
-   0x09048000,
-   0x12000300,
-   0x000C0024,
+   0x8060,
+   0x8601,
+   0x0601,
+   0x0100,
+   0x00300C03,
+   0xC0300C00,
+   0xC030,
+   0xC300,
+   0x000C0300,
0x0080,
 };
 
 const unsigned long 
iocsr_scan_chain2_table[((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = {
-   0x30009048,
+   0x300C0300,
0x,
0x0FF0,
0x,
-   0x0C002412,
+   0x0C0300C0,
0x8000,
-   0x18004824,
-   0x,
-   0x8240,
-   0x00018004,
-   0x06001209,
+   0x18060180,
+   0x1806,
+   0x1800,
+   0x00018060,
+   0x00018060,
0x4000,
-   0x20002412,
-   0x00904800,
+   0x000300C0,
+   0x0C03,
0x0030,
-   0x8000,
-   0x03000904,
+   0x,
+   0x0300C030,
0x2000,
-   0x10001209,
-   0x00482400,
-   0x2090,
-   0x40010001,
-   0x0482,
-   0x80001000,
-   0x0904,
+   0x00018060,
+   0x06018000,
+   0x0600,
+   0x0018,
+   0x6018,
+   0x1000,
+   0xC030,
0x,
-   0x9048,
-   0x20008000,
-   0x00C00241,
+   0x0300,
+   0x000C,
+   0x00C0300C,
0x0800,
 };
 
 const unsigned long 
iocsr_scan_chain3_table[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = {
-   0x0CC20D80,
-   0x0C3000FF,
+   0x0C420D80,
+   0x882000FF,
0x0A804001,
0x0790,
0x0802,
@@ -131,9 +131,9 @@ const unsigned long 
iocsr_scan_chain3_table[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH
0x0790,
0x0802

[PATCH 2/2] ARM: i.MX53: dts: add support for MCIMX53-START-R

[Steffen Trumtrar]

The start-r QSB has a different pmic than the older start QSB.
Add a new dts for the QSRB and let barebox generate two images when
LOCO is selected.

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 arch/arm/boards/freescale-mx53-loco/lowlevel.c |  13 +++
 arch/arm/dts/Makefile  |   3 +-
 arch/arm/dts/imx53-qsrb.dts| 141 +
 images/Makefile.imx|   5 +
 4 files changed, 161 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/imx53-qsrb.dts

diff --git a/arch/arm/boards/freescale-mx53-loco/lowlevel.c 
b/arch/arm/boards/freescale-mx53-loco/lowlevel.c
index 7556a2e..c9e057a 100644
--- a/arch/arm/boards/freescale-mx53-loco/lowlevel.c
+++ b/arch/arm/boards/freescale-mx53-loco/lowlevel.c
@@ -15,3 +15,16 @@ ENTRY_FUNCTION(start_imx53_loco, r0, r1, r2)
 
imx53_barebox_entry(fdt);
 }
+
+extern char __dtb_imx53_qsrb_start[];
+
+ENTRY_FUNCTION(start_imx53_loco_r, r0, r1, r2)
+{
+   uint32_t fdt;
+
+   arm_cpu_lowlevel_init();
+
+   fdt = (uint32_t)__dtb_imx53_qsrb_start - get_runtime_offset();
+
+   imx53_barebox_entry(fdt);
+}
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index bc314e9..ec46c4f 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -5,6 +5,7 @@ dtb-$(CONFIG_ARCH_AM33XX) += \
 dtb-$(CONFIG_ARCH_IMX51) += imx51-babbage.dtb \
imx51-genesi-efika-sb.dtb
 dtb-$(CONFIG_ARCH_IMX53) += imx53-qsb.dtb \
+   imx53-qsrb.dtb \
imx53-voipac-bsb.dtb
 dtb-$(CONFIG_ARCH_IMX6) += imx6q-gk802.dtb \
imx6dl-dfi-fs700-m60-6s.dtb \
@@ -29,7 +30,7 @@ obj-$(CONFIG_BUILTIN_DTB) += $(BUILTIN_DTB).dtb.o
 pbl-$(CONFIG_MACH_BEAGLEBONE) += am335x-bone.dtb.o am335x-boneblack.dtb.o
 pbl-$(CONFIG_MACH_EFIKA_MX_SMARTBOOK) += imx51-genesi-efika-sb.dtb.o
 pbl-$(CONFIG_MACH_FREESCALE_MX51_PDK) += imx51-babbage.dtb.o
-pbl-$(CONFIG_MACH_FREESCALE_MX53_LOCO) += imx53-qsb.dtb.o
+pbl-$(CONFIG_MACH_FREESCALE_MX53_LOCO) += imx53-qsb.dtb.o imx53-qsrb.dtb.o
 pbl-$(CONFIG_MACH_FREESCALE_MX53_VMX53) += imx53-voipac-bsb.dtb.o
 pbl-$(CONFIG_MACH_DFI_FS700_M60) += imx6q-dfi-fs700-m60-6q.dtb.o 
imx6dl-dfi-fs700-m60-6s.dtb.o
 pbl-$(CONFIG_MACH_PCM051) += am335x-phytec-phycore.dtb.o
diff --git a/arch/arm/dts/imx53-qsrb.dts b/arch/arm/dts/imx53-qsrb.dts
new file mode 100644
index 000..e9a9bc6
--- /dev/null
+++ b/arch/arm/dts/imx53-qsrb.dts
@@ -0,0 +1,141 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include imx53-qsb-common.dtsi
+
+/ {
+   model = Freescale i.MX53 Quick Start-R Board;
+   compatible = fsl,imx53-qsb, fsl,imx53;
+};
+
+iomuxc {
+   i2c1 {
+   /* open drain */
+   pinctrl_i2c1_qsrb: i2c1grp-1 {
+   fsl,pins = 
+   MX53_PAD_CSI0_DAT8__I2C1_SDA  0x41ec
+   MX53_PAD_CSI0_DAT9__I2C1_SCL  0x41ec
+   ;
+   };
+   };
+};
+
+i2c1 {
+   pinctrl-names = default;
+   pinctrl-0 = pinctrl_i2c1_qsrb;
+
+   pmic: ripley@8 {
+   compatible = fsl,mc34708;
+   reg = 0x08;
+   interrupt-parent = gpio5;
+   interrupts = 23 0x8;
+   regulators {
+   mc34708__sw1a {
+   regulator-name = SW1;
+   regulator-min-microvolt = 65;
+   regulator-max-microvolt = 1437500;
+   regulator-boot-on;
+   regulator-always-on;
+   };
+   mc34708__sw1b {
+   regulator-name = SW1B;
+   regulator-min-microvolt = 65;
+   regulator-max-microvolt = 1437500;
+   regulator-boot-on;
+   regulator-always-on;
+   };
+   mc34708__sw2 {
+   regulator-name = SW2;
+   regulator-min-microvolt = 65;
+   regulator-max-microvolt = 1437500;
+   regulator-boot-on;
+   regulator-always-on;
+   };
+   mc34708__sw3 {
+   regulator-name = SW3;
+   regulator-min-microvolt = 65;
+   regulator-max-microvolt = 1425000;
+   regulator-boot

[PATCH 1/2] ARM: i.MX53: dts: move QSB pmic to own file

[Steffen Trumtrar]

There are two versions of the i.MX53 LOCO:
- the MCIMX53-START board
- the MCIMX53-START-R board

The MCIMX53-START-R has a mc34708 pmic and is otherwise the similar to the
MCIMX53-START. To prepare for the START-R, move all common nodes to a new
imx53-qsb-common.dtsi
and remove everything but the board name and pmic from the imx53-qsb.dts.

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 arch/arm/dts/imx53-qsb-common.dtsi | 225 +
 arch/arm/dts/imx53-qsb.dts | 210 +-
 2 files changed, 226 insertions(+), 209 deletions(-)
 create mode 100644 arch/arm/dts/imx53-qsb-common.dtsi

diff --git a/arch/arm/dts/imx53-qsb-common.dtsi 
b/arch/arm/dts/imx53-qsb-common.dtsi
new file mode 100644
index 000..4ecb3ec
--- /dev/null
+++ b/arch/arm/dts/imx53-qsb-common.dtsi
@@ -0,0 +1,225 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include imx53.dtsi
+
+/ {
+   chosen {
+   linux,stdout-path = /soc/aips@5000/serial@53fbc000;
+
+   environment@0 {
+   compatible = barebox,environment;
+   device-path = esdhc1, partname:barebox-environment;
+   };
+   };
+
+   display@di0 {
+   compatible = fsl,imx-parallel-display;
+   crtcs = ipu 0;
+   interface-pix-fmt = rgb565;
+   pinctrl-names = default;
+   pinctrl-0 = pinctrl_ipu_disp0_1;
+   status = disabled;
+   display-timings {
+   claawvga {
+   native-mode;
+   clock-frequency = 2700;
+   hactive = 800;
+   vactive = 480;
+   hback-porch = 40;
+   hfront-porch = 60;
+   vback-porch = 10;
+   vfront-porch = 10;
+   hsync-len = 20;
+   vsync-len = 10;
+   hsync-active = 0;
+   vsync-active = 0;
+   de-active = 1;
+   pixelclk-active = 0;
+   };
+   };
+   };
+
+   gpio-keys {
+   compatible = gpio-keys;
+
+   power {
+   label = Power Button;
+   gpios = gpio1 8 0;
+   linux,code = 116; /* KEY_POWER */
+   gpio-key,wakeup;
+   };
+
+   volume-up {
+   label = Volume Up;
+   gpios = gpio2 14 0;
+   linux,code = 115; /* KEY_VOLUMEUP */
+   };
+
+   volume-down {
+   label = Volume Down;
+   gpios = gpio2 15 0;
+   linux,code = 114; /* KEY_VOLUMEDOWN */
+   };
+   };
+
+   leds {
+   compatible = gpio-leds;
+   pinctrl-names = default;
+   pinctrl-0 = led_pin_gpio7_7;
+
+   user {
+   label = Heartbeat;
+   gpios = gpio7 7 0;
+   linux,default-trigger = heartbeat;
+   };
+   };
+
+   regulators {
+   compatible = simple-bus;
+
+   reg_3p2v: 3p2v {
+   compatible = regulator-fixed;
+   regulator-name = 3P2V;
+   regulator-min-microvolt = 320;
+   regulator-max-microvolt = 320;
+   regulator-always-on;
+   };
+   };
+
+   sound {
+   compatible = fsl,imx53-qsb-sgtl5000,
+fsl,imx-audio-sgtl5000;
+   model = imx53-qsb-sgtl5000;
+   ssi-controller = ssi2;
+   audio-codec = sgtl5000;
+   audio-routing =
+   MIC_IN, Mic Jack,
+   Mic Jack, Mic Bias,
+   Headphone Jack, HP_OUT;
+   mux-int-port = 2;
+   mux-ext-port = 5;
+   };
+};
+
+esdhc1 {
+   pinctrl-names = default;
+   pinctrl-0 = pinctrl_esdhc1_1;
+   cd-gpios = gpio3 13 0;
+   status = okay;
+   #address-cells = 1;
+   #size-cells = 1;
+
+   partition@0 {
+   label = barebox-environment;
+   reg = 0x8 0x2;
+   };
+};
+
+ssi2 {
+   fsl,mode = i2s

[PATCH v2 2/2] ARM: i.MX53: dts: add support for MCIMX53-START-R

[Steffen Trumtrar]

The start-r QSB has a different pmic than the older start QSB.
Add a new dts for the QSRB and let barebox generate two images when
LOCO is selected.

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
Changes in V2:

- add newlines after every DT-node
- add phandle names to pmic-nodes

 arch/arm/boards/freescale-mx53-loco/lowlevel.c |  13 ++
 arch/arm/dts/Makefile  |   3 +-
 arch/arm/dts/imx53-qsrb.dts| 157 +
 images/Makefile.imx|   5 +
 4 files changed, 177 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/imx53-qsrb.dts

diff --git a/arch/arm/boards/freescale-mx53-loco/lowlevel.c 
b/arch/arm/boards/freescale-mx53-loco/lowlevel.c
index 7556a2e..c9e057a 100644
--- a/arch/arm/boards/freescale-mx53-loco/lowlevel.c
+++ b/arch/arm/boards/freescale-mx53-loco/lowlevel.c
@@ -15,3 +15,16 @@ ENTRY_FUNCTION(start_imx53_loco, r0, r1, r2)
 
imx53_barebox_entry(fdt);
 }
+
+extern char __dtb_imx53_qsrb_start[];
+
+ENTRY_FUNCTION(start_imx53_loco_r, r0, r1, r2)
+{
+   uint32_t fdt;
+
+   arm_cpu_lowlevel_init();
+
+   fdt = (uint32_t)__dtb_imx53_qsrb_start - get_runtime_offset();
+
+   imx53_barebox_entry(fdt);
+}
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index bc314e9..ec46c4f 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -5,6 +5,7 @@ dtb-$(CONFIG_ARCH_AM33XX) += \
 dtb-$(CONFIG_ARCH_IMX51) += imx51-babbage.dtb \
imx51-genesi-efika-sb.dtb
 dtb-$(CONFIG_ARCH_IMX53) += imx53-qsb.dtb \
+   imx53-qsrb.dtb \
imx53-voipac-bsb.dtb
 dtb-$(CONFIG_ARCH_IMX6) += imx6q-gk802.dtb \
imx6dl-dfi-fs700-m60-6s.dtb \
@@ -29,7 +30,7 @@ obj-$(CONFIG_BUILTIN_DTB) += $(BUILTIN_DTB).dtb.o
 pbl-$(CONFIG_MACH_BEAGLEBONE) += am335x-bone.dtb.o am335x-boneblack.dtb.o
 pbl-$(CONFIG_MACH_EFIKA_MX_SMARTBOOK) += imx51-genesi-efika-sb.dtb.o
 pbl-$(CONFIG_MACH_FREESCALE_MX51_PDK) += imx51-babbage.dtb.o
-pbl-$(CONFIG_MACH_FREESCALE_MX53_LOCO) += imx53-qsb.dtb.o
+pbl-$(CONFIG_MACH_FREESCALE_MX53_LOCO) += imx53-qsb.dtb.o imx53-qsrb.dtb.o
 pbl-$(CONFIG_MACH_FREESCALE_MX53_VMX53) += imx53-voipac-bsb.dtb.o
 pbl-$(CONFIG_MACH_DFI_FS700_M60) += imx6q-dfi-fs700-m60-6q.dtb.o 
imx6dl-dfi-fs700-m60-6s.dtb.o
 pbl-$(CONFIG_MACH_PCM051) += am335x-phytec-phycore.dtb.o
diff --git a/arch/arm/dts/imx53-qsrb.dts b/arch/arm/dts/imx53-qsrb.dts
new file mode 100644
index 000..aed9862
--- /dev/null
+++ b/arch/arm/dts/imx53-qsrb.dts
@@ -0,0 +1,157 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+
+#include imx53-qsb-common.dtsi
+
+/ {
+   model = Freescale i.MX53 Quick Start-R Board;
+   compatible = fsl,imx53-qsb, fsl,imx53;
+};
+
+iomuxc {
+   i2c1 {
+   /* open drain */
+   pinctrl_i2c1_qsrb: i2c1grp-1 {
+   fsl,pins = 
+   MX53_PAD_CSI0_DAT8__I2C1_SDA  0x41ec
+   MX53_PAD_CSI0_DAT9__I2C1_SCL  0x41ec
+   ;
+   };
+   };
+};
+
+i2c1 {
+   pinctrl-names = default;
+   pinctrl-0 = pinctrl_i2c1_qsrb;
+
+   pmic: ripley@8 {
+   compatible = fsl,mc34708;
+   reg = 0x08;
+   interrupt-parent = gpio5;
+   interrupts = 23 0x8;
+   regulators {
+   sw1_reg: sw1a {
+   regulator-name = SW1;
+   regulator-min-microvolt = 65;
+   regulator-max-microvolt = 1437500;
+   regulator-boot-on;
+   regulator-always-on;
+   };
+
+   sw1b_reg: sw1b {
+   regulator-name = SW1B;
+   regulator-min-microvolt = 65;
+   regulator-max-microvolt = 1437500;
+   regulator-boot-on;
+   regulator-always-on;
+   };
+
+   sw2_reg: sw2 {
+   regulator-name = SW2;
+   regulator-min-microvolt = 65;
+   regulator-max-microvolt = 1437500;
+   regulator-boot-on;
+   regulator-always-on;
+   };
+
+   sw3_reg: sw3 {
+   regulator-name = SW3;
+   regulator-min-microvolt = 65

[PATCH v2 1/2] ARM: i.MX53: dts: move QSB pmic to own file

[Steffen Trumtrar]

There are two versions of the i.MX53 LOCO:
- the MCIMX53-START board
- the MCIMX53-START-R board

The MCIMX53-START-R has a mc34708 pmic and is otherwise the similar to the
MCIMX53-START. To prepare for the START-R, move all common nodes to a new
imx53-qsb-common.dtsi
and remove everything but the board name and pmic from the imx53-qsb.dts.

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
Changes in V2:

- move dts-v1 from imx53-qsb-common.dtsi to imx53-qsb.dts

 arch/arm/dts/imx53-qsb-common.dtsi | 224 +
 arch/arm/dts/imx53-qsb.dts | 210 +-
 2 files changed, 226 insertions(+), 208 deletions(-)
 create mode 100644 arch/arm/dts/imx53-qsb-common.dtsi

diff --git a/arch/arm/dts/imx53-qsb-common.dtsi 
b/arch/arm/dts/imx53-qsb-common.dtsi
new file mode 100644
index 000..f2f912b
--- /dev/null
+++ b/arch/arm/dts/imx53-qsb-common.dtsi
@@ -0,0 +1,224 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include imx53.dtsi
+
+/ {
+   chosen {
+   linux,stdout-path = /soc/aips@5000/serial@53fbc000;
+
+   environment@0 {
+   compatible = barebox,environment;
+   device-path = esdhc1, partname:barebox-environment;
+   };
+   };
+
+   display@di0 {
+   compatible = fsl,imx-parallel-display;
+   crtcs = ipu 0;
+   interface-pix-fmt = rgb565;
+   pinctrl-names = default;
+   pinctrl-0 = pinctrl_ipu_disp0_1;
+   status = disabled;
+   display-timings {
+   claawvga {
+   native-mode;
+   clock-frequency = 2700;
+   hactive = 800;
+   vactive = 480;
+   hback-porch = 40;
+   hfront-porch = 60;
+   vback-porch = 10;
+   vfront-porch = 10;
+   hsync-len = 20;
+   vsync-len = 10;
+   hsync-active = 0;
+   vsync-active = 0;
+   de-active = 1;
+   pixelclk-active = 0;
+   };
+   };
+   };
+
+   gpio-keys {
+   compatible = gpio-keys;
+
+   power {
+   label = Power Button;
+   gpios = gpio1 8 0;
+   linux,code = 116; /* KEY_POWER */
+   gpio-key,wakeup;
+   };
+
+   volume-up {
+   label = Volume Up;
+   gpios = gpio2 14 0;
+   linux,code = 115; /* KEY_VOLUMEUP */
+   };
+
+   volume-down {
+   label = Volume Down;
+   gpios = gpio2 15 0;
+   linux,code = 114; /* KEY_VOLUMEDOWN */
+   };
+   };
+
+   leds {
+   compatible = gpio-leds;
+   pinctrl-names = default;
+   pinctrl-0 = led_pin_gpio7_7;
+
+   user {
+   label = Heartbeat;
+   gpios = gpio7 7 0;
+   linux,default-trigger = heartbeat;
+   };
+   };
+
+   regulators {
+   compatible = simple-bus;
+
+   reg_3p2v: 3p2v {
+   compatible = regulator-fixed;
+   regulator-name = 3P2V;
+   regulator-min-microvolt = 320;
+   regulator-max-microvolt = 320;
+   regulator-always-on;
+   };
+   };
+
+   sound {
+   compatible = fsl,imx53-qsb-sgtl5000,
+fsl,imx-audio-sgtl5000;
+   model = imx53-qsb-sgtl5000;
+   ssi-controller = ssi2;
+   audio-codec = sgtl5000;
+   audio-routing =
+   MIC_IN, Mic Jack,
+   Mic Jack, Mic Bias,
+   Headphone Jack, HP_OUT;
+   mux-int-port = 2;
+   mux-ext-port = 5;
+   };
+};
+
+esdhc1 {
+   pinctrl-names = default;
+   pinctrl-0 = pinctrl_esdhc1_1;
+   cd-gpios = gpio3 13 0;
+   status = okay;
+   #address-cells = 1;
+   #size-cells = 1;
+
+   partition@0 {
+   label = barebox-environment

[PATCH] Makefile: add target for gtags

[Steffen Trumtrar]

The scripts/tags.sh file already supports the generation of gtags with
GNU GLOBAL. The only thing missing is the makefile target to use it.

Copy the setup from the Linux Kernel to allow usage of gtags with barebox.

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 Makefile |7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/Makefile b/Makefile
index 640e589..502e009 100644
--- a/Makefile
+++ b/Makefile
@@ -353,7 +353,7 @@ endif
 # of make so .config is not included in this case either (for *config).
 
 no-dot-config-targets := clean mrproper distclean \
-cscope TAGS tags help %docs check% \
+cscope gtags TAGS tags help %docs check% \
 include/generated/version.h headers_% \
 kernelrelease kernelversion
 
@@ -986,7 +986,7 @@ MRPROPER_DIRS  += include/config include2 usr/include
 MRPROPER_FILES += .config .config.old include/asm .version .old_version \
   include/generated/autoconf.h include/generated/version.h 
 \
   include/generated/utsrelease.h include/config.h   \
- Module.symvers tags TAGS cscope*
+ Module.symvers tags TAGS cscope* GPATH GTAGS GRTAGS GSYMS
 
 # clean - Delete most, but leave enough to build external modules
 #
@@ -1072,6 +1072,7 @@ help:
@echo  '  dir/file.ko - Build module including final link'
@echo  '  tags/TAGS   - Generate tags file for editors'
@echo  '  cscope  - Generate cscope index'
+   @echo  '  gtags   - Generate GNU GLOBAL index'
@echo  '(default: $(INSTALL_HDR_PATH))'
@echo  ''
@echo  'Static analysers'
@@ -1114,7 +1115,7 @@ htmldocs: Doxyfile.version
 quiet_cmd_tags = GEN $@
   cmd_tags = $(CONFIG_SHELL) $(srctree)/scripts/tags.sh $@
 
-tags TAGS cscope: FORCE
+tags TAGS cscope gtags: FORCE
$(call cmd,tags)
 
 
-- 
1.7.10.4


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[PATCH v2] Makefile: add target for gtags

[Steffen Trumtrar]

The scripts/tags.sh file already supports the generation of gtags with
GNU GLOBAL. The only thing missing is the makefile target to use it.

Copy the setup from the Linux Kernel to allow usage of gtags with barebox.

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 .gitignore |6 ++
 Makefile   |7 ---
 2 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/.gitignore b/.gitignore
index 1dec248..710bce0 100644
--- a/.gitignore
+++ b/.gitignore
@@ -70,6 +70,12 @@ series
 # cscope files
 cscope.*
 
+# gnu global files
+GPATH
+GRTAGS
+GSYMS
+GTAGS
+
 # patches
 *.patch
 scripts/gen_netx_image
diff --git a/Makefile b/Makefile
index 640e589..502e009 100644
--- a/Makefile
+++ b/Makefile
@@ -353,7 +353,7 @@ endif
 # of make so .config is not included in this case either (for *config).
 
 no-dot-config-targets := clean mrproper distclean \
-cscope TAGS tags help %docs check% \
+cscope gtags TAGS tags help %docs check% \
 include/generated/version.h headers_% \
 kernelrelease kernelversion
 
@@ -986,7 +986,7 @@ MRPROPER_DIRS  += include/config include2 usr/include
 MRPROPER_FILES += .config .config.old include/asm .version .old_version \
   include/generated/autoconf.h include/generated/version.h 
 \
   include/generated/utsrelease.h include/config.h   \
- Module.symvers tags TAGS cscope*
+ Module.symvers tags TAGS cscope* GPATH GTAGS GRTAGS GSYMS
 
 # clean - Delete most, but leave enough to build external modules
 #
@@ -1072,6 +1072,7 @@ help:
@echo  '  dir/file.ko - Build module including final link'
@echo  '  tags/TAGS   - Generate tags file for editors'
@echo  '  cscope  - Generate cscope index'
+   @echo  '  gtags   - Generate GNU GLOBAL index'
@echo  '(default: $(INSTALL_HDR_PATH))'
@echo  ''
@echo  'Static analysers'
@@ -1114,7 +1115,7 @@ htmldocs: Doxyfile.version
 quiet_cmd_tags = GEN $@
   cmd_tags = $(CONFIG_SHELL) $(srctree)/scripts/tags.sh $@
 
-tags TAGS cscope: FORCE
+tags TAGS cscope gtags: FORCE
$(call cmd,tags)
 
 
-- 
1.7.10.4


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[PATCH] ARM: socfpga: socrates: fix ENTRY_FUNCTION

[Steffen Trumtrar]

The commit
ARM: Make ENTRY_FUNCTION more robust
changed the behaviour of the ENTRY_FUNCTION. For the Socrates the call to
__barebox_arm_head() was not removed. Do so now otherwise the Socrates will
not be able to boot barebox.

Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 arch/arm/boards/ebv-socrates/lowlevel.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm/boards/ebv-socrates/lowlevel.c 
b/arch/arm/boards/ebv-socrates/lowlevel.c
index e93ae38..035df70 100644
--- a/arch/arm/boards/ebv-socrates/lowlevel.c
+++ b/arch/arm/boards/ebv-socrates/lowlevel.c
@@ -49,8 +49,6 @@ ENTRY_FUNCTION(start_socfpga_socrates, r0, r1, r2)
 {
uint32_t fdt;
 
-   __barebox_arm_head();
-
arm_cpu_lowlevel_init();
 
fdt = (uint32_t)__dtb_socfpga_cyclone5_socrates_start - 
get_runtime_offset();
-- 
1.9.0


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