[Bug gas/26858] [arm] unsupported vmul instruction for vfp5-sp-d16 + armv8-r

2020-11-19 Thread avieira at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=26858

Andre Vieira  changed:

   What|Removed |Added

 Resolution|--- |FIXED
 Status|NEW |RESOLVED

--- Comment #8 from Andre Vieira  ---
I believe it has now been backported to all relevant branches. Closing.

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[Bug gas/26858] [arm] unsupported vmul instruction for vfp5-sp-d16 + armv8-r

2020-11-13 Thread avieira at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=26858

--- Comment #4 from Andre Vieira  ---
I'll wait a week or so before backporting to affected branches.

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[Bug gas/26858] [arm] unsupported vmul instruction for vfp5-sp-d16 + armv8-r

2020-11-12 Thread avieira at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=26858

Andre Vieira  changed:

   What|Removed |Added

 CC||avieira at gcc dot gnu.org
   Last reconfirmed||2020-11-12
 Ever confirmed|0   |1
   Assignee|unassigned at sourceware dot org   |avieira at gcc dot 
gnu.org
 Status|UNCONFIRMED |NEW

--- Comment #2 from Andre Vieira  ---
Confirmed this, typo in the ARM_VARIANT minimum requirement used the double
precision feature bit instead of the single precision one.

Testing a patch.

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[Bug gas/25992] Wrong Tag_CPU_arch_profile for armv8-r

2020-05-19 Thread avieira at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=25992

--- Comment #14 from Andre Vieira  ---
Oh doh... I was looking at the Tag_CPU_arch instead of arch_profile. Sorry
Alexander.

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[Bug gas/25992] Wrong Tag_CPU_arch_profile for armv8-r

2020-05-19 Thread avieira at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=25992

--- Comment #11 from Andre Vieira  ---
Nick were you able to reproduce this locally? I have tried a bunch of different
arm targets and branches but could not reproduce this behaviour, which is
weird... Might be there is some other issue masking this.

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[Bug gas/25992] Wrong Tag_CPU_arch_profile for armv8-r

2020-05-15 Thread avieira at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=25992

Andre Vieira  changed:

   What|Removed |Added

 CC||avieira at gcc dot gnu.org

--- Comment #2 from Andre Vieira  ---
Hi Alexander,

I can't seem to reproduce this with trunk. What version is this based on and
how are you configuring binutils?

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[Bug gas/25863] MVE: Issue with scalar vmul inside an it block

2020-05-07 Thread avieira at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=25863

Andre Vieira  changed:

   What|Removed |Added

 Status|NEW |RESOLVED
 Resolution|--- |FIXED

--- Comment #3 from Andre Vieira  ---
Closing as I believe this has been fixed.

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[Bug gas/25863] MVE: Issue with scalar vmul inside an it block

2020-04-22 Thread avieira at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=25863

Andre Vieira  changed:

   What|Removed |Added

   Assignee|unassigned at sourceware dot org   |avieira at gcc dot 
gnu.org

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[Bug gas/25863] New: MVE: Issue with scalar vmul inside an it block

2020-04-22 Thread avieira at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=25863

Bug ID: 25863
   Summary: MVE: Issue with scalar vmul inside an it block
   Product: binutils
   Version: unspecified
Status: NEW
  Severity: normal
  Priority: P2
 Component: gas
  Assignee: unassigned at sourceware dot org
  Reporter: avieira at gcc dot gnu.org
  Target Milestone: ---

When parsing the following with -march=armv8.1-m.main+mve.fp, GAS currently
wrongfully rejects it.

.syntax unified
.text
it lt
vmullt.f32 s0, s1, s2

In my original code I only tested this still worked for non-mve assembly.

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[Bug gas/25376] Setting FPU reset's MVE feature bits but FPU can't set MVE feature bits

2020-03-13 Thread avieira at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=25376

Andre Vieira  changed:

   What|Removed |Added

 Resolution|--- |FIXED
 Status|NEW |RESOLVED

--- Comment #2 from Andre Vieira  ---
Fixed in master, 2.34 and 2.33

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[Bug gas/25660] Failing to parse vsublt in an it block with MVE enabled

2020-03-13 Thread avieira at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=25660

Andre Vieira  changed:

   What|Removed |Added

 Resolution|--- |FIXED
 Status|NEW |RESOLVED

--- Comment #1 from Andre Vieira  ---
Fixed in master 2.34 and 2.33

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[Bug gas/25660] New: Failing to parse vsublt in an it block with MVE enabled

2020-03-12 Thread avieira at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=25660

Bug ID: 25660
   Summary: Failing to parse vsublt in an it block with MVE
enabled
   Product: binutils
   Version: 2.33
Status: NEW
  Severity: normal
  Priority: P2
 Component: gas
  Assignee: unassigned at sourceware dot org
  Reporter: avieira at gcc dot gnu.org
  Target Milestone: ---

The following assembly will be wrongly rejected if mve is enabled:

.syntax unified
.text
itt lt
vsublt.f32 s0, s1, s2
vaddlt.f32 s0, s1, s2

This is because I forgot to allow for single precision register parsing for
vsubl/vaddl which is what gets matched when MVE is enabled as 't' is stripped
as a potential true lane predication suffix.

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[Bug gas/25660] Failing to parse vsublt in an it block with MVE enabled

2020-03-12 Thread avieira at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=25660

Andre Vieira  changed:

   What|Removed |Added

   Assignee|unassigned at sourceware dot org   |avieira at gcc dot 
gnu.org

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[Bug gas/25472] [Arm] +mve does not enable DSP instructions

2020-01-31 Thread avieira at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=25472

Andre Vieira  changed:

   What|Removed |Added

 Status|NEW |RESOLVED
 Resolution|--- |FIXED

--- Comment #4 from Andre Vieira  ---
Fixed.

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[Bug gas/25472] [Arm] +mve does not enable DSP instructions

2020-01-27 Thread avieira at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=25472

Andre Vieira  changed:

   What|Removed |Added

   Assignee|unassigned at sourceware dot org   |avieira at gcc dot 
gnu.org

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[Bug gas/25472] New: [Arm] +mve does not enable DSP instructions

2020-01-27 Thread avieira at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=25472

Bug ID: 25472
   Summary: [Arm] +mve does not enable DSP instructions
   Product: binutils
   Version: 2.33
Status: NEW
  Severity: normal
  Priority: P2
 Component: gas
  Assignee: unassigned at sourceware dot org
  Reporter: avieira at gcc dot gnu.org
  Target Milestone: ---

MVE architecturally demands the implementation of the DSP extensions, so +mve
should also enable DSP instructions like uadd8 r0, r1, r2.

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[Bug gas/25376] Setting FPU reset's MVE feature bits but FPU can't set MVE feature bits

2020-01-13 Thread avieira at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=25376

Andre Vieira  changed:

   What|Removed |Added

 Target||arm-none-eabi
   Assignee|unassigned at sourceware dot org   |avieira at gcc dot 
gnu.org
  Build||2.33

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[Bug gas/25376] New: Setting FPU reset's MVE feature bits but FPU can't set MVE feature bits

2020-01-13 Thread avieira at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=25376

Bug ID: 25376
   Summary: Setting FPU reset's MVE feature bits but FPU can't set
MVE feature bits
   Product: binutils
   Version: 2.33
Status: NEW
  Severity: normal
  Priority: P2
 Component: gas
  Assignee: unassigned at sourceware dot org
  Reporter: avieira at gcc dot gnu.org
  Target Milestone: ---

GAS -mfpu command-line option and .fpu assembler directive reset the MVE
feature bits but can't set it. I.e. -mfpu or .fpu will disable mve but aren't
able to set it. 

It would be more natural if -mfpu and .fpu would only reset the set of bits
they can set.

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[Bug gas/24559] load pseudo-operation handling bug with Armv8-M Baseline

2019-05-23 Thread avieira at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=24559

--- Comment #3 from Andre Vieira  ---
Backported this to 2.32, not planning any other backports. OK To close ticket?

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[Bug binutils/24460] bfd/elf32-arm.c: get_value_helper, uninitialized value used

2019-05-21 Thread avieira at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=24460

Andre Vieira  changed:

   What|Removed |Added

 Status|ASSIGNED|RESOLVED
 CC||avieira at gcc dot gnu.org
 Resolution|--- |FIXED

--- Comment #2 from Andre Vieira  ---
I messed up the commit message for bfd/ChangeLog in
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=commit;h=e6f65e7573a317ac4efff26fe0e49fe1b9e7a596

But that commit fixes this issue, so closing as RESOLVED - FIXED.

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[Bug gas/24559] load pseudo-operation handling bug with Armv8-M Baseline

2019-05-16 Thread avieira at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=24559

--- Comment #1 from Andre Vieira  ---
Patch up for review on the mailing list
https://sourceware.org/ml/binutils/2019-05/msg00201.html

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[Bug gas/24559] load pseudo-operation handling bug with Armv8-M Baseline

2019-05-15 Thread avieira at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=24559

Andre Vieira  changed:

   What|Removed |Added

  Build||2.27, 2.28, 2.29, 2.30,
   ||2.31, 2.32, 2.33

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[Bug gas/24559] load pseudo-operation handling bug with Armv8-M Baseline

2019-05-15 Thread avieira at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=24559

Andre Vieira  changed:

   What|Removed |Added

   Assignee|unassigned at sourceware dot org   |avieira at gcc dot 
gnu.org

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[Bug gas/24559] load pseudo-operation handling bug with Armv8-M Baseline

2019-05-15 Thread avieira at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=24559

Andre Vieira  changed:

   What|Removed |Added

 Target||arm-*

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[Bug gas/24559] New: load pseudo-operation handling bug with Armv8-M Baseline

2019-05-15 Thread avieira at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=24559

Bug ID: 24559
   Summary: load pseudo-operation handling bug with Armv8-M
Baseline
   Product: binutils
   Version: 2.33 (HEAD)
Status: NEW
  Severity: normal
  Priority: P2
 Component: gas
  Assignee: unassigned at sourceware dot org
  Reporter: avieira at gcc dot gnu.org
  Target Milestone: ---

Hello,

When trying to assemble a load pseudo-operation for Cortex-M23 gas currently
incorrectly errors out:

$ cat t.s
ldr r0, =(0x30)
$ arm-none-eabi-as -mcpu=cortex-m23 t.s
t.s: Assembler messages:
t.s:1: Error: cannot honor width suffix -- `ldr r0,=(0x30)'

The same works for Cortex-M0:
$ arm-none-eabi-as -mcpu=cortex-m0 t.s
$ arm-none-eabi-objdump -dr

a.out: file format elf32-littlearm


Disassembly of section .text:

 <.text>:
   0:   4800ldr r0, [pc, #0]; (4 <.text+0x4>)
   2:   .short  0x
   4:   0030.word   0x0030


I have found the issue to lie with the inst.size_req check that is there to
make sure we do not end up with T32 instructions for Thumb-1 targets.  However,
in the case of Armv8-M Baseline the T32 MOVW instructions are allowed.  I have
a patch for this that I will be sending to the mailing list soon.

This patch will lead to the following behavior:
$ cat t.s
ldr r0, =(0x30)
$ arm-none-eabi-as -mcpu=cortex-m23 t.s
$ arm-none-eabi-objdump -dr

a.out: file format elf32-littlearm


Disassembly of section .text:

 <.text>:
   0:   f240 0030   movwr0, #48 ; 0x30

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