Re: Why *** extraneous `endef'. Stop.?

2009-09-06 Thread Tim Murphy
Hi,

define starts a macro.  Everything from the start of the macro to
endef is just text and is not evaluated.

So your inner define is not recognised - it's just treated as text.
That means that the dirst endef matches the first define and all the
other endefs seem to have no corresponding define statement.

In other words, you cannot nest defines like that.

Also note that ifneq doesn't have any effect inside a define - it only
has an effect when you $(eval) the macro.

Cheers,


Tim


2009/9/6 Sergey Zubkovsky serg...@gmail.com:
 Hi,
 Why the below makefile fails with the error text _Makefile:16: ***
 extraneous `endef'.  Stop._?
 Thanks.

 #---
 *define Var1
 ifneq (1,1)
 define Var2
 define Var3
 endef
 endef
 endif
 endef

 .PHONY : EmptyTarget
 EmptyTarget : ;

 $(eval $(value Var1))*
 #---



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Re: Why *** extraneous `endef'. Stop.?

2009-09-06 Thread Alfred M. Szmidt
   define starts a macro.  Everything from the start of the macro to
   endef is just text and is not evaluated.

   So your inner define is not recognised - it's just treated as
   text.  That means that the dirst endef matches the first define and
   all the other endefs seem to have no corresponding define
   statement.

   In other words, you cannot nest defines like that.

Sure you can, it is a documented feature.  From the GNU make manual,
(make) Defining:

|You may nest `define' directives: `make' will keep track of
| nested directives and report an error if they are not all properly
| closed with `endef'.  Note that lines beginning with tab characters
| are considered part of a command script, so any `define' or `endef'
| strings appearing on such a line will not be considered `make'
| operators.

This is more a bug than anything.


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Why *** extraneous `endef'. Stop.?

2009-09-06 Thread Tim Murphy
-- Forwarded message --
From: Tim Murphy tnmur...@gmail.com
Date: 2009/9/6
Subject: Re: Why *** extraneous `endef'. Stop.?
To: a...@gnu.org


Oh dear - sorry - I'm an idiot.

All I can say is that the ifneq statement is what makes it go wrong
for me.  Using $(if works for me but to get the same effect as not
equal you need to do some complicated stuff.

It is a bug.  I can only suggest a workaround:

define equal
$(if $(1:$2=),,$(if $(2:$1=),1))
endef

define Var1
$(if $(call equal,1,1),,
define Var2
define Var3
endef
endef
)
endef


Cheers,

Tim

2009/9/6 Alfred M. Szmidt a...@gnu.org:
   define starts a macro.  Everything from the start of the macro to
   endef is just text and is not evaluated.

   So your inner define is not recognised - it's just treated as
   text.  That means that the dirst endef matches the first define and
   all the other endefs seem to have no corresponding define
   statement.

   In other words, you cannot nest defines like that.

 Sure you can, it is a documented feature.  From the GNU make manual,
 (make) Defining:

 |    You may nest `define' directives: `make' will keep track of
 | nested directives and report an error if they are not all properly
 | closed with `endef'.  Note that lines beginning with tab characters
 | are considered part of a command script, so any `define' or `endef'
 | strings appearing on such a line will not be considered `make'
 | operators.

 This is more a bug than anything.




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Re: Why *** extraneous `endef'. Stop.?

2009-09-06 Thread Sergey Zubkovsky

It seems to me this is a bug.

All will be fine if we just rewrite 'ifneq (1,1)' as 'ifeq (1,1)'.

That is why I sent the question.
I hope someone will add an item in the bug tracker (who know `make' 
better than me and will confirm this supposition).


Alfred M. Szmidt wrote:

   define starts a macro.  Everything from the start of the macro to
   endef is just text and is not evaluated.

   So your inner define is not recognised - it's just treated as
   text.  That means that the dirst endef matches the first define and
   all the other endefs seem to have no corresponding define
   statement.

   In other words, you cannot nest defines like that.

Sure you can, it is a documented feature.  From the GNU make manual,
(make) Defining:

|You may nest `define' directives: `make' will keep track of
| nested directives and report an error if they are not all properly
| closed with `endef'.  Note that lines beginning with tab characters
| are considered part of a command script, so any `define' or `endef'
| strings appearing on such a line will not be considered `make'
| operators.

This is more a bug than anything.

  




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Re: Why *** extraneous `endef'. Stop.?

2009-09-06 Thread Philip Guenther
On Sun, Sep 6, 2009 at 8:09 AM, Sergey Zubkovskyserg...@gmail.com wrote:
 It seems to me this is a bug.

 All will be fine if we just rewrite 'ifneq (1,1)' as 'ifeq (1,1)'.

 That is why I sent the question.
 I hope someone will add an item in the bug tracker (who know `make' better
 than me and will confirm this supposition).

Sure looks like a bug to me.  Note that this has nothing to do with
$(eval); it's presence in your example just confuses the issue.  You
can see the issue directly with this:

ifneq (1,1)
define var1
define var2
endef
endef
endif


I suggest you visit
http://savannah.gnu.org/projects/make

and submit the bug.


Philip Guenther


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Why *** extraneous `endef'. Stop.?

2009-09-05 Thread Sergey Zubkovsky

Hi,
Why the below makefile fails with the error text _Makefile:16: *** 
extraneous `endef'.  Stop._?

Thanks.

#---
*define Var1
ifneq (1,1)
define Var2
define Var3
endef
endef
endif
endef

.PHONY : EmptyTarget
EmptyTarget : ;

$(eval $(value Var1))*
#---



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