Re: Some Framework Laptops fail to resume from zzz

2021-12-19 Thread Aaron Bieber


Renato Aguiar  writes:

> "Mark Kettenis"  writes:
>
>>> Date: Tue, 14 Dec 2021 22:54:48 +
>>> From: Renato Aguiar 
>>>
>>> "Mark Kettenis"  writes:
>>>
>>> >
>>> > Does the diff below help?
>>> >
>>> >
>>> > Index: dev/ic/dwiic.c
>>> > ===
>>> > RCS file: /cvs/src/sys/dev/ic/dwiic.c,v
>>> > retrieving revision 1.13
>>> > diff -u -p -r1.13 dwiic.c
>>> > --- dev/ic/dwiic.c7 Nov 2021 14:07:43 -   1.13
>>> > +++ dev/ic/dwiic.c14 Dec 2021 10:56:37 -
>>> > @@ -153,6 +153,10 @@ dwiic_init(struct dwiic_softc *sc)
>>> >   /* disable the adapter */
>>> >   dwiic_enable(sc, 0);
>>> >
>>> > + /* disable interrupts */
>>> > + dwiic_write(sc, DW_IC_INTR_MASK, 0);
>>> > + dwiic_read(sc, DW_IC_CLR_INTR);
>>> > +
>>> >   /* write standard-mode SCL timing parameters */
>>> >   dwiic_write(sc, DW_IC_SS_SCL_HCNT, sc->ss_hcnt);
>>> >   dwiic_write(sc, DW_IC_SS_SCL_LCNT, sc->ss_lcnt);
>>>
>>> No, it doesn't. I had also tried disabling interrupts at some other
>>> places during my initial investigation, but I couldn't make them stop
>>> without completely disabling the device.
>>
>> Are any bits in DW_IC_INTR_STAT set when this happens upon resume?
>
> No, both DW_IC_ENABLE and DW_IC_INTR_STAT are 0 when dwiic_intr() is
> called for dwiic0 after resume.

I recently picked up a Framework too - I am hitting a similar issue but
my devices seem to be a bit different. Unfortunately the bsd.re-config
trick doesn't work for me.

OpenBSD 7.0-current (GENERIC.MP) #182: Sun Dec 19 00:51:04 MST 2021
dera...@amd64.openbsd.org:/usr/src/sys/arch/amd64/compile/GENERIC.MP
real mem = 68475875328 (65303MB)
avail mem = 66384596992 (63309MB)
random: good seed from bootblocks
mpath0 at root
scsibus0 at mpath0: 256 targets
mainbus0 at root
bios0 at mainbus0: SMBIOS rev. 3.3 @ 0x439e2000 (51 entries)
bios0: vendor INSYDE Corp. version "03.06" date 10/18/2021
bios0: Framework Laptop
acpi0 at bios0: ACPI 6.1
acpi0: sleep states S0 S3 S4 S5
acpi0: tables DSDT FACP UEFI SSDT SSDT SSDT SSDT SSDT SSDT TPM2 SSDT NHLT SSDT 
LPIT WSMT SSDT SSDT DBGP DBG2 ECDT HPET APIC MCFG SSDT DMAR SSDT FPDT PTDT ASF! 
BGRT
acpi0: wakeup devices PEG0(S4) PEGP(S4) PEGP(S4) PEGP(S4) XHCI(S4) XDCI(S4) 
HDAS(S4) RP01(S4) PXSX(S4) RP02(S4) PXSX(S4) RP03(S4) PXSX(S4) RP04(S4) 
PXSX(S4) RP05(S4) [...]
acpitimer0 at acpi0: 3579545 Hz, 24 bits
acpiec0 at acpi0
acpihpet0 at acpi0: 1920 Hz
acpimadt0 at acpi0 addr 0xfee0: PC-AT compat
cpu0 at mainbus0: apid 0 (boot processor)
cpu0: 11th Gen Intel(R) Core(TM) i7-1185G7 @ 3.00GHz, 4788.96 MHz, 06-8c-01
cpu0: 
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,SMX,EST,TM2,SSSE3,SDBG,FMA3,CX16,xTPR,PDCM,PCID,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,DEADLINE,AES,XSAVE,AVX,F16C,RDRAND,NXE,PAGE1GB,RDTSCP,LONG,LAHF,ABM,3DNOWP,PERF,ITSC,FSGSBASE,TSC_ADJUST,BMI1,AVX2,SMEP,BMI2,ERMS,INVPCID,AVX512F,AVX512DQ,RDSEED,ADX,SMAP,AVX512IFMA,CLFLUSHOPT,CLWB,PT,AVX512CD,SHA,AVX512BW,AVX512VL,AVX512VBMI,UMIP,PKU,MD_CLEAR,IBRS,IBPB,STIBP,L1DF,SSBD,SENSOR,ARAT,XSAVEOPT,XSAVEC,XGETBV1,XSAVES
cpu0: 256KB 64b/line disabled L2 cache
cpu0: smt 0, core 0, package 0
mtrr: Pentium Pro MTRR support, 10 var ranges, 88 fixed ranges
cpu0: apic clock running at 38MHz
cpu0: mwait min=64, max=64, C-substates=0.2.0.1.2.1.1.1, IBE
cpu1 at mainbus0: apid 2 (application processor)
cpu1: 11th Gen Intel(R) Core(TM) i7-1185G7 @ 3.00GHz, 4788.96 MHz, 06-8c-01
cpu1: 
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,SMX,EST,TM2,SSSE3,SDBG,FMA3,CX16,xTPR,PDCM,PCID,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,DEADLINE,AES,XSAVE,AVX,F16C,RDRAND,NXE,PAGE1GB,RDTSCP,LONG,LAHF,ABM,3DNOWP,PERF,ITSC,FSGSBASE,TSC_ADJUST,BMI1,AVX2,SMEP,BMI2,ERMS,INVPCID,AVX512F,AVX512DQ,RDSEED,ADX,SMAP,AVX512IFMA,CLFLUSHOPT,CLWB,PT,AVX512CD,SHA,AVX512BW,AVX512VL,AVX512VBMI,UMIP,PKU,MD_CLEAR,IBRS,IBPB,STIBP,L1DF,SSBD,SENSOR,ARAT,XSAVEOPT,XSAVEC,XGETBV1,XSAVES
cpu1: 256KB 64b/line disabled L2 cache
cpu1: smt 0, core 1, package 0
cpu2 at mainbus0: apid 4 (application processor)
cpu2: 11th Gen Intel(R) Core(TM) i7-1185G7 @ 3.00GHz, 4290.11 MHz, 06-8c-01
cpu2: 
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,SMX,EST,TM2,SSSE3,SDBG,FMA3,CX16,xTPR,PDCM,PCID,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,DEADLINE,AES,XSAVE,AVX,F16C,RDRAND,NXE,PAGE1GB,RDTSCP,LONG,LAHF,ABM,3DNOWP,PERF,ITSC,FSGSBASE,TSC_ADJUST,BMI1,AVX2,SMEP,BMI2,ERMS,INVPCID,AVX512F,AVX512DQ,RDSEED,ADX,SMAP,AVX512IFMA,CLFLUSHOPT,CLWB,PT,AVX512CD,SHA,AVX512BW,AVX512VL,AVX512VBMI,UMIP,PKU,MD_CLEAR,IBRS,IBPB,STIBP,L1DF,SSBD,SENSOR,ARAT,XSAVEOPT,XSAVEC,XGETBV1,XSAVES
cpu2: 256KB 64b/line disabled L2 cache
cpu2: disabling user TSC (skew=194)
cpu2: smt 0, core 2, 

Re: Wifi doesn't work on Samsung NP530XBB-AD2BR notebook

2021-12-19 Thread Stefan Sperling
On Sun, Dec 19, 2021 at 12:20:18PM -0300, João Victor wrote:
> >Synopsis:  
> >Category:  
> >Environment:
> System  : OpenBSD 7.0
> Details : OpenBSD 7.0 (GENERIC.MP) #232: Thu Sep 30 14:25:29
> MDT 2021
>  dera...@amd64.openbsd.org:
> /usr/src/sys/arch/amd64/compile/GENERIC.MP
> 
> Architecture: OpenBSD.amd64
> Machine : amd64
> >Description:
>  "Intel Gemini Lake CNVi" rev 0x03 at pci0 dev 12 function 0 not
> configured>

This device is not yet supported.

Here is patch. It is a complete shot in the dark, but worth trying.
The device name string can be fixed up later. What is important for
now is that the driver attaches and produces a working interface.


diff 6bbb73995c8e71f4ccedb27558b1e4887fc58c34 /usr/src
blob - ae02ad71669e77dae57e2df7d89346f5296b0f26
file + sys/dev/pci/if_iwm.c
--- sys/dev/pci/if_iwm.c
+++ sys/dev/pci/if_iwm.c
@@ -847,7 +847,7 @@ iwm_read_firmware(struct iwm_softc *sc)
err = EINVAL;
goto parse_out;
}
-   sc->sc_fw_phy_config = le32toh(*(uint32_t *)tlv_data);
+   sc->sc_fw_phy_config |= le32toh(*(uint32_t *)tlv_data);
break;
 
case IWM_UCODE_TLV_API_CHANGES_SET: {
@@ -11177,6 +11177,7 @@ static const struct pci_matchid iwm_devices[] = {
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_9260_1 },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_9560_1 },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_9560_2 },
+   { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_GLK_WL },
 };
 
 int
@@ -11405,6 +11406,7 @@ iwm_attach(struct device *parent, struct device *self,
break;
case PCI_PRODUCT_INTEL_WL_9560_1:
case PCI_PRODUCT_INTEL_WL_9560_2:
+   case PCI_PRODUCT_INTEL_GLK_WL:
sc->sc_fwname = "iwm-9000-46";
sc->host_interrupt_operation_mode = 0;
sc->sc_device_family = IWM_DEVICE_FAMILY_9000;
@@ -11412,7 +11414,11 @@ iwm_attach(struct device *parent, struct device *self,
sc->sc_nvm_max_section_size = 32768;
sc->sc_mqrx_supported = 1;
sc->sc_integrated = 1;
-   sc->sc_xtal_latency = 650;
+   if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_GLK_WL) {
+   sc->sc_xtal_latency = 670;
+   sc->sc_fw_phy_config = IWM_FW_PHY_CFG_SHARED_CLK;
+   } else
+   sc->sc_xtal_latency = 650;
break;
default:
printf("%s: unknown adapter type\n", DEVNAME(sc));
blob - 59ae267a763600b0893079abfbf5d13d6c5678d0
file + sys/dev/pci/if_iwmreg.h
--- sys/dev/pci/if_iwmreg.h
+++ sys/dev/pci/if_iwmreg.h
@@ -982,6 +982,7 @@ struct iwm_tlv_calib_ctrl {
 #define IWM_FW_PHY_CFG_TX_CHAIN(0xf << 
IWM_FW_PHY_CFG_TX_CHAIN_POS)
 #define IWM_FW_PHY_CFG_RX_CHAIN_POS20
 #define IWM_FW_PHY_CFG_RX_CHAIN(0xf << 
IWM_FW_PHY_CFG_RX_CHAIN_POS)
+#define IWM_FW_PHY_CFG_SHARED_CLK  (1U << 31)
 
 #define IWM_UCODE_MAX_CS   1