Re: [casper] ZDOK+ Layout?
Hi Dan,
The 6367555-1 is the right one. It's the same as the 1367555, but more
RoHS compliant. It has the utility Contacts on the side in addition to the
40 pairs on the 1367130-1.
Regards,
Francois
On Thu, Feb 17, 2011 at 7:13 PM, Daniel S. Klopp dkl...@nrao.edu wrote:
I am designing a board with a ZDOK+ connector to interface with an IBOB.
According to the wiki http://casper.berkeley.edu/wiki/IBOB , it uses a
Tyco ZDOK+ 40 differential pair connector and provides a link to the
website. Using the datasheet I was under the impression I would use
1367130-1 layout with 40 pairs. But when I measured the dimensions of the
physical board and looked at the pin layout of another connector we have in
the lab, it looks as if the correct layout to use is actually 1367555.
http://www.tycoelectronics.com/commerce/DocumentDelivery/DDEController'6367555
?Action=showdocDocId=Customer+Drawing%7F1367555%7FB%7Fpdf%7FEnglish%7FENG_CD_1367555_B.pdf%7FN-Ahttp://www.tycoelectronics.com/commerce/DocumentDelivery/DDEController?Action=showdocDocId=Customer+Drawing%7F1367555%7FB%7Fpdf%7FEnglish%7FENG_CD_1367555_B.pdf%7FN-A.
However, that drawing has me a bit nervous as it is a customer provided
document and not an official Tyco document.
Could someone please confirm the EXACT connector layout I should use?
Thank you,
-Dan
--
:(){ :|: };:
Re: [casper] Tut3 trouble - Error due to multiple causes
Hi Daniel, The extra ports in your design may be due to not having the Number of Simultaneous inputs set correctly in either the pfb or fft. Can you check this in the fft and pfb and verify they are the same? Mark 2011/2/18 Daniel Esteban Herrera Peña danherr...@udec.cl Hi team, Thank you Mark for your suggestion, I identify two blocks pfb_fir_real and fft_wideband_real (only green blocks) I read all the parameters and I insert the same blocks again (the fft block has two different parameters from the tutorial and the pfb only one) the pfb block now shows two extra ports related to an strange second signal (an input pol2_in1 and an output pol2_out1) so I replace this pfb block without making connections in those ports (except for a terminator on pol2_out1). After run simulation and wait for some minutes an error window pops up: MessageSourceReported by Summary Model Error Unknown Simulink Error due to multiple causes. Block Error pfb_fir_real Simulink Error in 'tut3/pfb_fir_real': Initialization commands cannot be evaluated. The first error still chasing me to hell, and the second I think it is related to this new strange ports (pol2), the parameter coefficient bitwidth is set to 18 bits according to the original design but the tutorial suggest to be less than or equal to the input bit width (8), it this alright? Any insights? thank you. Daniel H. On Tue, 15 Feb 2011 13:33:20 -0800, Mark Wagner mwag...@ssl.berkeley.edu wrote: Hi Daniel, This error occurs when the Simulink design is updated. It's possible the library you've loaded has blocks that are different than those used to create the original design. If you start a simulation (Simulation -- Start), the error dialog box should pop up with more detailed information about the offending block or connection. If the issue is a block, try deleting it and replacing it with one from your library. Mark 2011/2/15 Daniel Esteban Herrera Peña Hi everyone, I could get a 800MHz clock source to test the spectrometer in tut3 (using the pre-compiled file you provided) with successful results including changing the input frequency to 1GHz, now I want to change the adc input clock to 2GHz (I see that I must change to interleave mode), but first I tried to synthesize the r_spec_2048_r105 without making any change and I receive this error: Detected Linux OS # ## System Update ## # Error using == gen_xps_files at 199 Error due to multiple causes. If I knew just one cause I will be happy trying to resolve it, but I have no clue at all. I saw in the forums some issue regarding the adc block, I tried to follow those steps (re-adding adc block, disabling link) but the problem persist. Does anyone knows how to inspect more deeply the error I'm having?. Thanks. Daniel H. Links: -- [1] mailto:danherr...@udec.cl -- Daniel Esteban Herrera Peña Ingeniero Civil Electrónico Universidad de Concepción, Chile. (41)236-0289 842-38325
Re: [casper] Tut3 trouble - Error due to multiple causes
Hi Mark, I change strategy and I just change fft_wideband_real (I repeat replacement steps and only fft_wideband_real presented conflicts), I could run simulation so now I'm into synthesis, the problem arises this time with system generator. after some warnings... # ## Block objects creation ## # ## ## Checking objects ## ## Running system generator ... Error using == gen_xps_files at 328 XSG generation failed: and System generator window pops up, I forgot to put the D7 trick but after this the procedure stills stopping at the same point, what else I should check? Thank you so much!! Daniel H. On Fri, 18 Feb 2011 13:25:52 -0800, Mark Wagner mwag...@ssl.berkeley.edu wrote: Hi Daniel, The extra ports in your design may be due to not having the Number of Simultaneous inputs set correctly in either the pfb or fft. Can you check this in the fft and pfb and verify they are the same? Mark 2011/2/18 Daniel Esteban Herrera Peña Hi team, Thank you Mark for your suggestion, I identify two blocks pfb_fir_real and fft_wideband_real (only green blocks) I read all the parameters and I insert the same blocks again (the fft block has two different parameters from the tutorial and the pfb only one) the pfb block now shows two extra ports related to an strange second signal (an input pol2_in1 and an output pol2_out1) so I replace this pfb block without making connections in those ports (except for a terminator on pol2_out1). After run simulation and wait for some minutes an error window pops up: Message Source Reported by Summary Model Error Unknown Simulink Error due to multiple causes. Block Error pfb_fir_real Simulink Error in 'tut3/pfb_fir_real': Initialization commands cannot be evaluated. The first error still chasing me to hell, and the second I think it is related to this new strange ports (pol2), the parameter coefficient bitwidth is set to 18 bits according to the original design but the tutorial suggest to be less than or equal to the input bit width (8), it this alright? Any insights? thank you. Daniel H. On Tue, 15 Feb 2011 13:33:20 -0800, Mark Wagner wrote: Hi Daniel, This error occurs when the Simulink design is updated. It's possible the library you've loaded has blocks that are different than those used to create the original design. If you start a simulation (Simulation -- Start), the error dialog box should pop up with more detailed information about the offending block or connection. If the issue is a block, try deleting it and replacing it with one from your library. Mark 2011/2/15 Daniel Esteban Herrera Peña Hi everyone, I could get a 800MHz clock source to test the spectrometer in tut3 (using the pre-compiled file you provided) with successful results including changing the input frequency to 1GHz, now I want to change the adc input clock to 2GHz (I see that I must change to interleave mode), but first I tried to synthesize the r_spec_2048_r105 without making any change and I receive this error: Detected Linux OS # ## System Update ## # Error using == gen_xps_files at 199 Error due to multiple causes. If I knew just one cause I will be happy trying to resolve it, but I have no clue at all. I saw in the forums some issue regarding the adc block, I tried to follow those steps (re-adding adc block, disabling link) but the problem persist. Does anyone knows how to inspect more deeply the error I'm having?. Thanks. Daniel H. Links: -- [1] mailto:danherr...@udec.cl [3] -- Daniel Esteban Herrera Peña Ingeniero Civil Electrónico Universidad de Concepción, Chile. (41)236-0289 842-38325 Links: -- [1] mailto:danherr...@udec.cl [2] mailto:mwag...@ssl.berkeley.edu [3] mailto:danherr...@udec.cl -- Daniel Esteban Herrera Peña Ingeniero Civil Electrónico Universidad de Concepción, Chile. (41)236-0289 842-38325
