Re: [casper] program ROACH over JTAG
If you already have a bitstream, simply plug a JTAG programmer into P2 (labelled "Xilinx JTAG"), and use IMPACT. But if I read your email correctly, you haven't configured clocks or anything so I'm not sure what the point of this exercise is. I agree with Suraj, easiest would be to start with a CASPER-toolflow generated base system and add/modify from there. Jason On 04 Nov 2009, at 10:33, C-H Cheng wrote: Hello Suraj Thanks for you explanation. Maybe I don't describe clearly. I mean if I want program the FPAG on ROACH over JTAG. Also, the bit file is generated by Xilinx ISE not CASPER toolflow. In this moment, the ucf file of my design is only included the IO pins of my design. But a lot of pins that ROACH are needed are not included in my design. How could I program the FPGA of ROACH with my bit file? Thanks, C-H Cheng Hello, On Nov 3, 2009, at 6:39 PM, C-H Cheng wrote: Hello All If I want to simulate a design in ISE and generate a bit file to download to ROACH over JTAG. You can do this using the .bit generated by the CASPER toolflow, available in the same location as the .bof. bof files are generated from .bit files using the script 'mkbof' distributed in 'XPS_ROACH_BASE'. A problem I meet is the FPGA pin number assignment. For example, in ISE I select the device is vxs95t and the FPGA pin assignment in ucf file is according to my desing. But ROACH has a lot of FPGA pins which are not in my design but needed for ROACH, sys_clk_n, sys_clk_p, aux0_clk_p, aux_clk_n, ppc_irq_n, ...etc. Part of the magic of the toolflow is that it adds the necessary IO pins to the .ucf depending on which IO blocks you have selected to use (10gbe, adc, etc.). It's part of the reason that IO blocks get special designation as "yellowblocks", as they are processed differently for each block. Hence, I can't add these FPGA pins which ROACH is needed into the ucf file of my design. It would definitely be faster to just put the I/O blocks you want to use into a blank model file, and use the CASPER toolflow to generate the .ucf, by un-checking the boxes for 'update system design', 'system generator', and 'ISE/EDK/bitgen' in the 'bee_xps' dialog. This should take about a minute to complete. -Suraj
Re: [casper] program ROACH over JTAG
Hello Suraj Thanks for you explanation. Maybe I don't describe clearly. I mean if I want program the FPAG on ROACH over JTAG. Also, the bit file is generated by Xilinx ISE not CASPER toolflow. In this moment, the ucf file of my design is only included the IO pins of my design. But a lot of pins that ROACH are needed are not included in my design. How could I program the FPGA of ROACH with my bit file? Thanks, C-H Cheng Hello, On Nov 3, 2009, at 6:39 PM, C-H Cheng wrote: Hello All If I want to simulate a design in ISE and generate a bit file to download to ROACH over JTAG. You can do this using the .bit generated by the CASPER toolflow, available in the same location as the .bof. bof files are generated from .bit files using the script 'mkbof' distributed in 'XPS_ROACH_BASE'. A problem I meet is the FPGA pin number assignment. For example, in ISE I select the device is vxs95t and the FPGA pin assignment in ucf file is according to my desing. But ROACH has a lot of FPGA pins which are not in my design but needed for ROACH, sys_clk_n, sys_clk_p, aux0_clk_p, aux_clk_n, ppc_irq_n, ...etc. Part of the magic of the toolflow is that it adds the necessary IO pins to the .ucf depending on which IO blocks you have selected to use (10gbe, adc, etc.). It's part of the reason that IO blocks get special designation as "yellowblocks", as they are processed differently for each block. Hence, I can't add these FPGA pins which ROACH is needed into the ucf file of my design. It would definitely be faster to just put the I/O blocks you want to use into a blank model file, and use the CASPER toolflow to generate the .ucf, by un-checking the boxes for 'update system design', 'system generator', and 'ISE/EDK/bitgen' in the 'bee_xps' dialog. This should take about a minute to complete. -Suraj
Re: [casper] program ROACH over JTAG
Hello, On Nov 3, 2009, at 6:39 PM, C-H Cheng wrote: Hello All If I want to simulate a design in ISE and generate a bit file to download to ROACH over JTAG. You can do this using the .bit generated by the CASPER toolflow, available in the same location as the .bof. bof files are generated from .bit files using the script 'mkbof' distributed in 'XPS_ROACH_BASE'. A problem I meet is the FPGA pin number assignment. For example, in ISE I select the device is vxs95t and the FPGA pin assignment in ucf file is according to my desing. But ROACH has a lot of FPGA pins which are not in my design but needed for ROACH, sys_clk_n, sys_clk_p, aux0_clk_p, aux_clk_n, ppc_irq_n, ...etc. Part of the magic of the toolflow is that it adds the necessary IO pins to the .ucf depending on which IO blocks you have selected to use (10gbe, adc, etc.). It's part of the reason that IO blocks get special designation as "yellowblocks", as they are processed differently for each block. Hence, I can't add these FPGA pins which ROACH is needed into the ucf file of my design. It would definitely be faster to just put the I/O blocks you want to use into a blank model file, and use the CASPER toolflow to generate the .ucf, by un-checking the boxes for 'update system design', 'system generator', and 'ISE/EDK/bitgen' in the 'bee_xps' dialog. This should take about a minute to complete. -Suraj
[casper] program ROACH over JTAG
Hello All If I want to simulate a design in ISE and generate a bit file to download to ROACH over JTAG. A problem I meet is the FPGA pin number assignment. For example, in ISE I select the device is vxs95t and the FPGA pin assignment in ucf file is according to my desing. But ROACH has a lot of FPGA pins which are not in my design but needed for ROACH, sys_clk_n, sys_clk_p, aux0_clk_p, aux_clk_n, ppc_irq_n, ...etc. Hence, I can't add these FPGA pins which ROACH is needed into the ucf file of my design. Otherwise, I will meet error in mapping process. How could I simulate my design and program ROACH over JTAG? Regards, C-H Cheng
