FPGA I/O and external memory (was Re: CDC 6600 emulation - was Re: How do they make Verilog code for unknown ICs?)

[Eric Smith]

On Mon, Jun 20, 2016 at 10:07 PM, ben  wrote:
> Do you use Static or Dynamic ram with the FPGA's?

I've done both.

You indicated that you wanted 5V I/O. AFAIK, there haven't been any
new FPGAs made in many years that have even 5V-tolerant I/O, let alone
actual 5V I/O.  Some really old FPGAs may still be in production, but
are not very cost-effective. The latest midrange to high-end FPGAs
aren't even 3.3V-tolerant. However, the economy FPGAs such as Spartan
6 and Artix 7 still support 3.3V I/O, and are quite inexpensive for
the amount of resources provided.

For 5V-tolerance, it is usually adequate to use 3.3V I/O with series
resistors to limit the current. Xilinx specifies a maximum rated
current for the clamp diodes.  This works fine when interfacing actual
TTL (or TTL-compatible MOS) parts. It is NOT adequate for driving 5V
CMOS, such as CD4000 series, because the FPGA won't drive above 3.3V,
and the 5V CMOS inputs typically are specified for Vih min of 90% of
Vdd, which is 4.5V.

The series resistor does slow down the signal, which usually isn't a
problem with TTL since TTL is quite slow by FPGA standards. Where it
is a problem, an nFET voltage clamp can be used instead.

Re: CDC 6600 emulation - was Re: How do they make Verilog code for unknown ICs?

[Chuck Guzis]

Are you going for the 6600 CPU with PPU or just the CPU itself?

The 6400 CPU, on the other hand was one of the initial proof of concept
targets  when Neil Lincoln at (then) ADL and later ETA was playing with
his "box of Chiclets" IC concept.  To the best of my knowledge, a 6600
was not attempted.   Even then (in the 1970s) the small footprint was
amazing.

--Chuck

Re: CDC 6600 emulation - was Re: How do they make Verilog code for unknown ICs?

[Eric Smith]

On Mon, Jun 20, 2016 at 9:34 PM, ben  wrote:
> My other pet-peave is that every thing is point and click wizard for any
> useful modules. Need a rom module or adder module, point and click no
> portable code.

I predominantly use Xilinx, and I don't use much point-and-click at
all. I do all my HDL editing in emacs, including instantiating any of
the Xilinx-provided IP blocks. My main interaction with the Xilinx
software (whether ISE or Vivado) is to click the "generate bitstream"
button.  It's even possible to do that from the command line or a
Makefile, but I haven't bothered.

Re: CDC 6600 emulation - was Re: How do they make Verilog code for unknown ICs?

[ben]

On 6/20/2016 9:00 PM, Toby Thain wrote:



Altera Cyclone has 9 bit byte lanes, so getting 36 bit memory is no
problem.


Internal memory only.
My other pet-peave is that every thing is point and click wizard for any
useful modules. Need a rom module or adder module, point and click no 
portable code.

Ben.

Re: How do they make Verilog code for unknown ICs?

[Eric Smith]

On Mon, Jun 20, 2016 at 2:56 PM, Swift Griggs  wrote:
> On Mon, 20 Jun 2016, Paul Koning wrote:
>> a and b will both equal 1 at the end.  But in the VHDL code:
>>   a <= 1;
>>   b <= a;
>
> Whoa. That makes total sense, though. In the real world, I'm guessing the
> "less than" just reflects that a signal might not have the level you
> expect.

It's not a "less than".  In VHDL, "<=" is a token for a left arrow,
for signal assignment, as in the quote above.

Also "=>" is a token for a right arrow, used for mappings, e.g.,

  signal foo: std_logic_vector (7 downto 0) := (7 downto 4 => '0',
others => '1');

is one way to declare a signal that is an 8-bit vector, with the left
four bits initialized to 0, and the right four bits initialized to 1.
In this specific case, it probably would be more clear to write:

  signal foo: std_logic_vector (7 downto 0) := "";

but I didn't do that because I wanted to give an example of "=>".
"=>" can also be used to map formal to actual parameters of
subprograms, and (conceptually similarly) to map ports of components
to signals.

(VHDL allows indices to be descending, using "downto", or ascending,
using "to", but it's usually best not to try to mix them in a design.
I almost exclusively use "downto", as it matches the most commonly
used bit numbering of busses, where the most significant bit is
conceptually on the left, and has the highest bit number, and the
place-value weight of each bit is 2^n.)

VHDL is often criticized for being more verbose than Verilog. IMHO, it
more than makes up for that by offering strong type checking, whereas
Verilog makes it easier to shoot yourself in the foot without any
warning. (Much like Ada vs. C.)  I personally don't find the verbosity
to be an issue, because I can type much faster than I can think about
anything complicated. I rarely, if ever, find that the verbosity slows
me down in the slightest, but certainly YMMV.

Originally VHDL was a more expressive language than Verilog, but more
recent Verilog standards have closed much of the gap.

Both Verilog and VHDL make it easy to write code that cannot be
synthesized to hardware (or to "reasonable" hardware), so one learns
to stick to a subset of the language capabilities that is
synthesizable. AFAIK, there is no formal spec for a synthesizable
subset of either language; different synthesizers have variations in
what they accept.

To some extent, knowing what features of the language can be used in
synthesis is a matter of understanding what hardware (gates and
flip-flops) you're trying to represent. While VHDL and Verilog can
provide a higher abstraction than individual gates and flip-flops,
synthesis has to turn everything into those, and if you're writing HDL
code and aren't sure how the synthesizer can turn the specific
constructs into hardware, it's entirely likely that it can't.

A common misconception about both VHDL and Verilog is that they make
it trivial for programmers to become hardware developers. Despite all
of the hoopla over "high level synthesis", the reality is that if you
don't know how to design hardware using gates and flip-flops, anything
you try to build in an HDL, even with high-level synthesis, is likely
to either not work, or to be extremely inefficient.

The parallelism that Paul described in his example is one of the
hardest concepts for programmers new to hardware design to grasp.

Verilog has an innate distinction between "wires" and "registers".
VHDL just has signals. The idiom for a register in VHDL is:

  process (clock)
  begin
if rising_edge (clock) then
  b <= a;
end if;
  end process;

This shows a signal assignment (b <= a) as a sequential statement,
which occurs only when the condition (rising edge of clock) is met.
Outside a process, a signal assignment is a concurrent statement, and
happens all of the time.

Here's an example of a VHDL process that works perfectly well in
simulation, but probably not at all in synthesis:

  process (clock)
  begin
if clock'event then
  b <= a;
end if;
  end process;

That process models a register that is clocked on both edges of the
clock input, e.g., any time the clock signal changes. That's easy to
simulate, but difficult to synthesize as generally speaking no
flip-flops that clock on both edges are available.

Another example of a non-synthesizable VHDL construct is:

  b <= a after 15 ns;

That isn't synthesizable because there isn't any time delay element
available in logic synthesis. The only way to do it is to have some
clock with a cycle time that is a submultiple of 15 ns, and to use a
shift register or counter clocked by that to implement the delay. The
synthesizer won't do that for you; you have to specify it explicitly.

Historically, it seemed that ASIC designers have preferred Verilog,
while FPGA designers have preferred VHDL. I'm not sure that's nearly
as true as it once was.

It's claimed, and perhaps may even be true, that Verilog is 

Re: How do they make Verilog code for unknown ICs?

[Warren Toomey]

All, I messed around with VHDL last year. I found this a great book
to learn VHDL best practices:
http://www.gstitt.ece.ufl.edu/courses/eel4712/labs/free_range_vhdl.pdf
The book is free but you can also buy a printed copy at
http://freerangefactory.org/

I started with GHDL: https://www.fpgarelated.com/showarticle/20.php
and then progressed to a Nexys4 FPGA board. Lots of fun.

Just a few more resources to add to the mix.
Cheers,
Warren

P.S The CPU I built with it: http://minnie.tuhs.org/Programs/UcodeCPU/index.html

Re: CDC 6600 emulation - was Re: How do they make Verilog code for unknown ICs?

[Toby Thain]

On 2016-06-20 5:12 PM, ben wrote:

On 6/20/2016 2:41 PM, Toby Thain wrote:



This is frankly amazing. Thankyou for the details. Maybe one day I'll be
able to volunteer some help. (Actually if there's anything I can do now,
as an electronics noob but beginning student of digital logic & FPGA,
let me know offlist.)


How about a REAL FPGA board that has 5 volt I/O and 36+ bit wide memory


Altera Cyclone has 9 bit byte lanes, so getting 36 bit memory is no problem.

--Toby



would make some big computers a reality.
Ben.

Re: How do they make Verilog code for unknown ICs?

[Seth Morabito]

* On Mon, Jun 20, 2016 at 04:19:56PM -0400, Paul Koning 
 wrote:
> 
> I haven't looked for open source Verilog simulators.

I've used Icarus Verilog ('iverilog') in the past. It's pretty bare
bones, but you can feed the output into gnuplot and make reasonable
diagrams from it.

>   paul

-Seth
-- 
Seth Morabito
s...@loomcom.com

Re: CDC 6600 emulation - was Re: How do they make Verilog code for unknown ICs?

[Paul Koning]

> On Jun 20, 2016, at 5:12 PM, ben  wrote:
> 
> On 6/20/2016 2:41 PM, Toby Thain wrote:
> 
>> 
>> This is frankly amazing. Thankyou for the details. Maybe one day I'll be
>> able to volunteer some help. (Actually if there's anything I can do now,
>> as an electronics noob but beginning student of digital logic & FPGA,
>> let me know offlist.)
> 
> How about a REAL FPGA board that has 5 volt I/O and 36+ bit wide memory
> would make some big computers a reality.

Given the right level of internal detail, a PDP10 emulation should be 
straightforward.

Just to give you a feeling for the currently available scale, I figured that a 
large but not max size FPGA can hold a complete CDC 6600 -- its 15 chassis 
worth of modules, including PPU and CPU memory.  The only thing that -- 
probably -- doesn't quite fit is the ECS.  But CPU memory, 128k words of 60 
bits, is perfectly straightforward inside a modern large FPGA.  (Good thing, 
too; the CM timing is such that trying to hook up external RAM is quite a pain, 
unless you make it SRAM.  ECS is far more lenient.)

paul

Re: HP Series-80 computers - PRM-85 board case? ... maybe!

[Brian Walenz]

I have a printer - just finished putting a Rostock V2 together a week or so
ago - and an 87xm (and 86b, fwiw) and some modules, but no PRM-85.  If fit
against a standard module board is sufficient, I can do an iteration or
two.  I haven't quite finished calibration, but it is printing sufficiently
well so far.

Is the PRM-85 still available?

b


On Mon, Jun 20, 2016 at 5:54 PM, Dave  wrote:

> I'm interested as well.
> Dave
>
>
> On Monday, June 20, 2016 2:16 PM, "alexmcwhir...@triadic.us" <
> alexmcwhir...@triadic.us> wrote:
>
>
>
>  On 2016-06-20 11:34, Pete Plank wrote:
> >> On Jun 20, 2016, at 6:20 AM, martin.heppe...@dlr.de wrote:
> >>
> >> I read in this list that there are more people interested in such a
> >> case.
> >
> > I don’t have a 3D printer either, but I’m on board for one when
> > they’re ready to go - my PRM-85 is still in its anti-static bag.
> >
> > Pete
>
> I have a 3d printer, but not any of the boards in question. I don't mind
> helping if there's anything i can do.
>
>
>
>
>

Re: How do they make Verilog code for unknown ICs?

[Jon Elson]

On 06/20/2016 03:19 PM, Paul Koning wrote:

On Jun 20, 2016, at 4:17 PM, Paul Koning  wrote:



On Jun 20, 2016, at 3:35 PM, Swift Griggs  wrote:

In my recent studies of electronics (I'm a noob for all practical
purposes) I keep seeing folks refer to Verilog almost as a verb. I read
about it in Wikipedia and it sounds pretty interesting. It's basically
described as a coding scheme for electronics, similar to programming but
with extras like signal strength and propagation included. Hey, cool!

Verilog and VHDL are two "hardware description languages".  You can think of 
them as programming languages to describe hardware behavior.  Another way to look at them 
is as languages designed to let you talk easily about lots of things that happen at the 
same time -- which is what happens in hardware.

I forgot to mention: at least for VHDL, there's an open source simulator.  In other 
words, a program that accepts VHDL input and lets you "run" the simulated 
hardware.  You can feed it inputs in various ways, and observe its behavior -- for 
example as waveform traces on a waveform display, like an oscilloscope.  Look for GHDL.  
It's a GCC front end; it takes your VHDL code and compiles it, then it's linked with a 
support library to make an executable program.  Since it's GCC based you can do neat 
things, like run it on various hardware platforms.  Or link in C functions to do stuff, 
like simulate external peripherals connected to your hardware model.

I haven't looked for open source Verilog simulators.


Pretty much any FPGA design package will have a simulator 
that will take FPGA-synthesizable VHDL or Verilog and build 
a simulation environment that produces the functions 
specified in the HDL.  Note that there are LOTS of things 
you can write in VHDL and Verilog that do not synthesize 
into logic, and thus the simulators won't express what those 
statements ask for.


Jon

Re: Quadra 660AV what's with the "PowerPC" label?

[Liam Proven]

On 15 June 2016 at 20:39, Swift Griggs  wrote:
> Hmm. I think you'd fly right through it, Liam. You are a smart guy, I
> doubt you'd have any significant problems these days. Still, it's a
> console-based install.

FWIW, I've tried again this evening. Not on bare metal -- on the
latest VirtualBox.

First I tried the pre-installed VM image, but it came with no network
connection enabled.

(Between every step I mention, I googled for how to do it...)

So I downloaded the DVD ISO, created a default VM (well, enlarging the
RAM to 2GB), did a bare install, tried to add XFCE...  and it barfed.
Disk full.

Nuked it, started over with an 8GB disk.

This time XFCE installed but wouldn't start. I tried installing XDM.
That wouldn't start either.

Digging reveals that apparently Xfce doesn't depend on X.11. (!)

Installed X.11. Works. Can now start twm or Xfce.

XDM now works but won't start Xfce, or indeed, anything at all.

Dump Xsession, make a minimal new one. Now XDM lets me log in. Woohoo,
a desktop!

Install sudo. Install Firefox. Now we have a working Web connection!

Install Virtualbox guest additions. Modify config file to start them.
And it works, albeit with some errors.

So, I take it back. Apparently I can now install FreeBSD. It was a
significant amount of work over a few hours, though...

-- 
Liam  Proven • Profile: http://lproven.livejournal.com/profile
Email: lpro...@cix.co.uk • GMail/G+/Twitter/Flickr/Facebook: lproven
MSN: lpro...@hotmail.com • Skype/AIM/Yahoo/LinkedIn: liamproven
Cell/Mobiles: +44 7939-087884 (UK) • +420 702 829 053 (ČR)

Re: HP Series-80 computers - PRM-85 board case? ... maybe!

[Dave]

I'm interested as well.
Dave
 

On Monday, June 20, 2016 2:16 PM, "alexmcwhir...@triadic.us" 
 wrote:
 
 

 On 2016-06-20 11:34, Pete Plank wrote:
>> On Jun 20, 2016, at 6:20 AM, martin.heppe...@dlr.de wrote:
>> 
>> I read in this list that there are more people interested in such a 
>> case.
> 
> I don’t have a 3D printer either, but I’m on board for one when
> they’re ready to go - my PRM-85 is still in its anti-static bag.
> 
> Pete

I have a 3d printer, but not any of the boards in question. I don't mind 
helping if there's anything i can do.


 

Re: NetBooting old MacOS 8.x or 7x.

[Cameron Kaiser]

> Due to the news about the MacOS name change, it's becoming quite hard to 
> Google for older MacOS stuff. Was it ever possible to netboot MacOS 8.1 or 
> earlier? I have A/UX 3 running nicely on a Quadra 700, now, but now I want 
> to dual boot it with MacOS, but I don't have a CDROM. Taking out the drive 
> and putting it on my other 68k Mac (a Centris 660AV) and installing MacOS 
> still gives me some weird issues that I suspect are related to having 
> installed it on different hardware.
> 
> If I can't do a network based install, I'll probably just steal a longer 
> SCSI cable, use a molex power splitter to add another 5V power cable, and 
> then install from CDROM while the system is half-open. Then I'll just 
> button it up afterwards. The factor SCSI cable in my Quadra 700 has only 
> one connector for a drive.

In short: no.

In long: NetBoot requires a G4 or a late G3, and that would imply pretty
much only 8.6 and up.

You *can* netboot a *IIgs* from an AppleShare server (over LocalTalk),
and I have in fact done that myself, but I've never seen this functionality
on a 68K Mac or 60x Power Mac and the ROM doesn't know how.

-- 
 personal: http://www.cameronkaiser.com/ --
  Cameron Kaiser * Floodgap Systems * www.floodgap.com * ckai...@floodgap.com
-- I like being single. I'm always there when I need me. -- Art Leo ---

Re: How do they make Verilog code for unknown ICs?

[Swift Griggs]

On Mon, 20 Jun 2016, Eric Christopherson wrote:
> For learning, I really recommend this Coursera MOOC: 
> https://www.coursera.org/learn/build-a-computer/home/welcome

Hmm, I had to sign up with them, but I did it. I wanted to see this 
simulator. It's a very "slick" course with lots of way-cool topics. This 
is definitely awesome.  Thanks.

-Swift

Re: CDC 6600 emulation - was Re: How do they make Verilog code for unknown ICs?

[ben]

On 6/20/2016 2:41 PM, Toby Thain wrote:



This is frankly amazing. Thankyou for the details. Maybe one day I'll be
able to volunteer some help. (Actually if there's anything I can do now,
as an electronics noob but beginning student of digital logic & FPGA,
let me know offlist.)


How about a REAL FPGA board that has 5 volt I/O and 36+ bit wide memory
would make some big computers a reality.
Ben.

Re: How do they make Verilog code for unknown ICs?

[ben]

On 6/20/2016 2:36 PM, Swift Griggs wrote:


So far, it's been great. I'm just finishing up some of the analog stuff on
that same site, and I've greedily skipped ahead a bit to digital. However,
I'm just now getting to TTLs and gates. I have to actually write out
examples or test things physically to really "get it". However, I'm just
plodding along. I have a nice little mess happening on my workbench in the
garage. I'm about to move on past just using simple capacitors, resistors,
and diodes to using some ICs. It's a little intimidating, actually. I
thought I could get to the point I'm at now in about two weeks. It
actually took about five or six weeks (just for an analog refresher). I'm
still a bit shaky on some of that stuff, too. It's hard to test/see
everything. So, some things I just read about, shrug, and keep going.


But of course the real stuff is TOP SECRET, unless you PAY.


-Swift


A good read on LSI in the late 1970's.

http://ai.eecs.umich.edu/people/conway/VLSI/VLSIText/VLSIText.html

Ben.

Re: How do they make Verilog code for unknown ICs?

[Guy Sotomayor Jr]

> On Jun 20, 2016, at 1:56 PM, Swift Griggs  wrote:
> 
> On Mon, 20 Jun 2016, Paul Koning wrote:
>> used to how C or similar languages work.  For example, in this C code:
>>  a = 1;
>>  b = a;
>> a and b will both equal 1 at the end.  But in the VHDL code:
>>  a <= 1;
>>  b <= a;
> 
> Whoa. That makes total sense, though. In the real world, I'm guessing the 
> "less than" just reflects that a signal might not have the level you 
> expect.
> 

The best way to think about the two different assignment operators (<= is an
assignment *not* less-than-or-equal) is that one happens “now” and the other
is resolved on clock edges.

So assuming that a & b are 1 bit wide and that initially both a and b are 0 (or
in verilog terms 1b0).

In the first example, both a and b will be 1b1.  In the second example, at the 
end
of the first clock cycle, a will be 1b1 and b will be 1b0.  At the end of the 
next
clock cycle, a will be 1b1 and b will be 1b1 also.

TTFN - Guy

Re: How do they make Verilog code for unknown ICs?

[Eric Christopherson]

On Mon, Jun 20, 2016, Ian Finder wrote:
> The hardest part of the process is distilling the functional specification
> of the part you are trying to replace. This is the heart of the topic. Some
> ways this can be done:
> > If adequate documentation exists, use it.
> > Observe the part's behavior in-system
> > Build a test bench to observe behavior of part outside of system
> > General leetness
> 
> There is no one approach, it is more art than science.
> 
> For going from a functional specification to a synthesizable model, this is
> simply writing HDL.
> I suggest this book, which covers the basics of this process.
> https://www.amazon.com/Verilog-Digital-System-Design-Verification/dp/0071445641
> 
> If you have no 100-level understanding of digital logic, start here:
> https://www.amazon.com/Contemporary-Logic-Design-Randy-Katz/dp/0201308576
> 
> Thanks,
> 
> - Ian

For learning, I really recommend this Coursera MOOC:
https://www.coursera.org/learn/build-a-computer/home/welcome

It has a part 2, which covers writing programs from machine language up;
I haven't taken that one yet. Part 1 talks about logic gates, boolean
logic, etc. (like in the web book Swift posted the URL of), but it also
lets you dip your toes in an HDL/Verilog-like toy language, and has
simulators (note: they require Java) to run the circuits you design.

> On Mon, Jun 20, 2016 at 1:02 PM, Toby Thain 
> wrote:
> 
> > On 2016-06-20 3:35 PM, Swift Griggs wrote:
> >
> >>
> >> In my recent studies of electronics (I'm a noob for all practical
> >> purposes) I keep seeing folks refer to Verilog almost as a verb. I read
> >> about it in Wikipedia and it sounds pretty interesting. It's basically
> >> described as a coding scheme for electronics, similar to programming but
> >> with extras like signal strength and propagation included. Hey, cool!
> >>
> >> Why are folks referring to "Verilogging" and "doing a verilog" on older
> >> chips. Is there some way you can stuff an IC into a socket or alligator
> >> clip a bunch of tiny leads onto it and then "map" it somehow into Verilog?
> >> Is that what folks who write emulators do?
> >>
> >
> > They firstly go by documentation, and if that fails, reverse engineer,
> > painfully. This is why preserving, archiving, publishing documentation is
> > so incredibly important!
> >
> > > Ie.. they exhaustively dump
> >
> >> Verilog code for all the chips then figure out how to implement that in
> >>
> >
> > You can't in general get Verilog *out* of a chip. It goes the other way.
> > You can compile Verilog into gates and netlists etc.
> >
> > some computer programming language like C ? What do folks do for ROM chips
> >> and PLCs? I'd think they must dump the code and disassemble it. No?
> >>
> >
> > Yes, they do that where possible.
> >
> >
> >> I'm just curious and this is a tough question to answer with Google since
> >> I'm pretty clueless and don't know the right words to search for. I notice
> >>
> >
> > You can google "EDA tools". You can also grab toolchains from major
> > vendors like Altera and play with Verilog/VHDL and simulate the results,
> > too.
> >
> > people talk about correcting their Verilog code, so it must be somewhat of
> >> a manual process. I'm just wondering how someone even gets started with a
> >> process like that.
> >>
> >
> > I'd suggest hitting some textbooks, not Google.
> >
> > Niklaus Wirth's book is fantastic, for people more comfortable in
> > software, if you take it step by step:
> >
> >
> > https://www.amazon.ca/Digital-Circuit-Computer-Science-Students/dp/354058577X

-- 
Eric Christopherson

Re: How do they make Verilog code for unknown ICs?

[ben]

On 6/20/2016 2:24 PM, Ian Finder wrote:

I find most of the open source HDL simulators kind of suck. I think you can
still get ModelSim Web edition for free from altera.


I think you get 1 month free ... then $$$.




I like the CRASH and BURN testing for FPGA's.
What I want is 5 volt I/O FPGA with a flash Boot prom for the FPGA
on tiny 64 pin PCB. This way one can emulate a vintage logic board
or cpu.


This will do mixed language designs of Verilog, VHDL and schematic, and
works rather nicely.


Altera has AHDL as well. Not portable, but less confusing to write logic
in.


Remember, each module is just a set of input and output signals, so the
language really doesn't matter. Mixed language designs are very common.

Yes, you can even build FPGA designs in a schematic editor out of library
modules. No, I don't suggest you should.


With Altera, you had a TTL macro library at one time. Not sure if the 
newest version still supports it.


Ben.

Re: How do they make Verilog code for unknown ICs?

[Guy Sotomayor Jr]

Most of the FPGA companies provide (free) tools that allow you to write in
verilog/VHDL and then simulate and observe the outputs (you can even “drill
down” and see internal signals as well.

It’s fairly easy to write a little bit of code (there are lots of examples on 
the
web) and try it out on the simulator.

If you get an FPGA eval board (I have a number of Digilent Xilinx boards)
you can take your sample code and download it to the eval board and run it.

TTFN - Guy

> On Jun 20, 2016, at 1:47 PM, Swift Griggs  wrote:
> 
> On Mon, 20 Jun 2016, Ian Finder wrote:
>> Some PALs, PLAs, and GALs will yield the fuse map if you try and read them
>> with a programmer. This makes your job really easy. Take the fuse map and
>> compare to the original data sheet. Cool beans.
> 
> That sounds like magic. I'm reading about what "fuse map" is, now. That's 
> a new term for me. 
> 
>> Some have the security bits set- in this case you would use a home-made 
>> test setup to stimulate enough test conditions to build a truth table 
>> that would allow you to infer the underlying logic.
> 
> Hmm, so there is something akin to "copy protection" even at the chip 
> level. Ugh. I'm not surprised.
> 
>> If the part is registered, then things get tricker. For that, I might 
>> take substantial in-system dumps with a logic analyzer (My favorite 
>> beginner LA is the Agilent 16700, which comes with DOOM preinstalled, so 
>> you know it's good stuff)
> 
> Oh, cool. I was just browsing for one a few days ago. I was looking at the 
> ones from Saleae and Tektronix. I'll have to check that out. If they were 
> cool enough to pre-install Doom, I think we have a winner. :-)
> 
>> ROMS are easy- once you read a bit about how HDLs work, you will be able 
>> to build one. Many languages offer functions to help with these (see 
>> readmemh and readmemb in verilog)
> 
> I actually did burn some ROM code in college. I remember it being fairly 
> easy. However, I would look like a stunned fish if someone asked me to 
> reverse engineer one.
> 
>> Things get more complicated quickly- this is a deep topic and not 
>> something that can be covered quickly. I suggest you start with the two 
>> books I linked, and if you like them, there are a lot more around. Any 
>> edition should be suitable- get or find whatever is cheapest.
> 
> Oh good lord, I'm so out of my depth already. However, it's still 
> interesting and I'm still trying (I'm stubborn that way). I've got to get 
> the simplest basics down before I dive in all the way with a "real" book. 
> I'm going to try to stick with my digital logic self-refresh first, but 
> this Verilog business is awfully cool. I will be sorely tempted to come 
> back to this same point, I'm sure.
> 
>> We have not touched yet on practical things, like how to interface 
>> modern 1.8v FPGA I/O lines with 5V TTL logic- that is a topic for 
>> another day.
> 
> Hmm, I never even knew of that problem, but after doing a bunch of analog, 
> I get the impression that would create a lot of hassles, especially if you 
> were just trying to duplicate some already laid-out logic, but it was all 
> at 5V... 
> 
> -Swift

Re: How do they make Verilog code for unknown ICs?

[Swift Griggs]

On Mon, 20 Jun 2016, Ian Finder wrote:
> Some PALs, PLAs, and GALs will yield the fuse map if you try and read them
> with a programmer. This makes your job really easy. Take the fuse map and
> compare to the original data sheet. Cool beans.

That sounds like magic. I'm reading about what "fuse map" is, now. That's 
a new term for me. 

> Some have the security bits set- in this case you would use a home-made 
> test setup to stimulate enough test conditions to build a truth table 
> that would allow you to infer the underlying logic.

Hmm, so there is something akin to "copy protection" even at the chip 
level. Ugh. I'm not surprised.
 
> If the part is registered, then things get tricker. For that, I might 
> take substantial in-system dumps with a logic analyzer (My favorite 
> beginner LA is the Agilent 16700, which comes with DOOM preinstalled, so 
> you know it's good stuff)

Oh, cool. I was just browsing for one a few days ago. I was looking at the 
ones from Saleae and Tektronix. I'll have to check that out. If they were 
cool enough to pre-install Doom, I think we have a winner. :-)

> ROMS are easy- once you read a bit about how HDLs work, you will be able 
> to build one. Many languages offer functions to help with these (see 
> readmemh and readmemb in verilog)

I actually did burn some ROM code in college. I remember it being fairly 
easy. However, I would look like a stunned fish if someone asked me to 
reverse engineer one.

> Things get more complicated quickly- this is a deep topic and not 
> something that can be covered quickly. I suggest you start with the two 
> books I linked, and if you like them, there are a lot more around. Any 
> edition should be suitable- get or find whatever is cheapest.

Oh good lord, I'm so out of my depth already. However, it's still 
interesting and I'm still trying (I'm stubborn that way). I've got to get 
the simplest basics down before I dive in all the way with a "real" book. 
I'm going to try to stick with my digital logic self-refresh first, but 
this Verilog business is awfully cool. I will be sorely tempted to come 
back to this same point, I'm sure.

> We have not touched yet on practical things, like how to interface 
> modern 1.8v FPGA I/O lines with 5V TTL logic- that is a topic for 
> another day.

Hmm, I never even knew of that problem, but after doing a bunch of analog, 
I get the impression that would create a lot of hassles, especially if you 
were just trying to duplicate some already laid-out logic, but it was all 
at 5V... 

-Swift

Re: CDC 6600 emulation - was Re: How do they make Verilog code for unknown ICs?

[Ian Finder]

Paul wrote:
>>> I'm thinking I'll stop trying OCR and simply type the wire lists
instead; that's likely to be faster in the long run.

If you need someone to help, I'd be happy to transcribe some shit while
watching TV if you send me the docs and desired schema. I'm no stranger to
this sort of process :)

On Mon, Jun 20, 2016 at 1:35 PM, Paul Koning  wrote:

>
> > On Jun 20, 2016, at 4:22 PM, Toby Thain 
> wrote:
> >
> > On 2016-06-20 4:17 PM, Paul Koning wrote:
> >> ...A hardware model can
> > be used to replicate what old hardware did; for example, I have a
> > partial CDC 6600 model that shows how it boots, and that model includes
> > propagation delays on some signals (which are critical to correct
> > operation in certain spots).
> >>
> >
> > This is probably of great interest to more than just me.
> >
> > Any more details? Going to publish?
>
> Sure.  You can see it at svn://akdesign.dyndns.org/dtcyber/trunk; most is
> in the vhdl subdirectory but it uses some pieces from the top level.  Very
> much work in progress.
>
> It's derived from the 6600 wire lists on bitsavers.  I OCRed them (what a
> pain), wrote VHDL models (gate level structural models) of each 6000 series
> module, and a Python script builds a structural model out of those elements
> interconnected by the wires from the wire lists.  "Sufficiently long" wires
> have their delay explicitly modeled.
>
> I currently have chassis 1 (PPUs) working, at least to the point where I
> can do a deadstart, have that load from the deadstart panel, and execute
> some instructions.  I've used it to grok some magic related to deadstart
> that's part of the lore but not documented.  I also have the 6612 display
> controller working, so I can see how the text display on the console tubes
> works.  Unfortunately I don't have a good SPICE model for the analog parts,
> so I don't yet know why the character shapes are changed by the circuitry
> in the manner that the photos show.
>
> The CPU is work in progress.  I'm trying to get exchange to work.  It's
> hard; even more than the PPUs, the CPU relies on hairy timing in certain
> spots.  It appears that the wire lists are not all the same rev, and there
> are also some typos in them.
>
> Some day, if things go really well, this may result in a gate level
> accurate FPGA 6600.  I'm thinking I'll stop trying OCR and simply type the
> wire lists instead; that's likely to be faster in the long run.
>
> paul
>
>


-- 
   Ian Finder
   (206) 395-MIPS
   ian.fin...@gmail.com

Re: CDC 6600 emulation - was Re: How do they make Verilog code for unknown ICs?

[Toby Thain]

On 2016-06-20 4:35 PM, Paul Koning wrote:



On Jun 20, 2016, at 4:22 PM, Toby Thain  wrote:

On 2016-06-20 4:17 PM, Paul Koning wrote:

...A hardware model can

be used to replicate what old hardware did; for example, I have a
partial CDC 6600 model that shows how it boots, and that model includes
propagation delays on some signals (which are critical to correct
operation in certain spots).




This is probably of great interest to more than just me.

Any more details? Going to publish?


Sure.  You can see it at svn://akdesign.dyndns.org/dtcyber/trunk; ...
Some day, if things go really well, this may result in a gate level accurate 
FPGA 6600.  I'm thinking I'll stop trying OCR and simply type the wire lists 
instead; that's likely to be faster in the long run.




This is frankly amazing. Thankyou for the details. Maybe one day I'll be 
able to volunteer some help. (Actually if there's anything I can do now, 
as an electronics noob but beginning student of digital logic & FPGA, 
let me know offlist.)



--Toby



paul

Re: How do they make Verilog code for unknown ICs?

[Swift Griggs]

On Mon, 20 Jun 2016, Ian Finder wrote:
> The hardest part of the process is distilling the functional 
> specification of the part you are trying to replace. This is the heart 
> of the topic.

Hmm, okay so that's pretty much what I expected. They start with what that 
particular chip or ROM etc.. _does_ then they re-implement as a process of 
discovery. Does that sound accurate?

> There is no one approach, it is more art than science.

That's also what I expected. I guess as I was reading through other 
material, I got the impression that it might be more deterministic, but my 
gut feeling was right, I think. Nothing is ever *that* easy.

> For going from a functional specification to a synthesizable model, this 
> is simply writing HDL. I suggest this book, which covers the basics of 
> this process. 
> https://www.amazon.com/Verilog-Digital-System-Design-Verification/dp/0071445641

Whoa. That's a pricey sucker. I'm probably not going to be able to make 
use of Verilog for a little bit yet. I'm still designing all my little 
"homework assignment" type projects on paper or using a tool I found in 
pkgsrc called "The Eagle Layout Editor." It's got some nice features (at 
least for me so far). I'll probably go with the Wirth book since it's a 
bit cheaper, but I still appreciate your suggestion.

> If you have no 100-level understanding of digital logic, start here: 
> https://www.amazon.com/Contemporary-Logic-Design-Randy-Katz/dp/0201308576

I have about a 100-level understanding, now. I took a digital logic class 
in college and I still have my book. It's "Fundamentals of Digital Design" 
I believe (or something very close to that). It was a while back, though.  
I understand boolean logic, changing base for numbering systems, etc.. 
However, I have a breathtaking lack of experience in applying that stuff 
to "real" digital logic. I'm just using online tutorials and guides for 
the moment, but the main one I focus on is this one:

http://www.learningelectronics.net/vol_4/index.html

So far, it's been great. I'm just finishing up some of the analog stuff on 
that same site, and I've greedily skipped ahead a bit to digital. However, 
I'm just now getting to TTLs and gates. I have to actually write out 
examples or test things physically to really "get it". However, I'm just 
plodding along. I have a nice little mess happening on my workbench in the 
garage. I'm about to move on past just using simple capacitors, resistors, 
and diodes to using some ICs. It's a little intimidating, actually. I 
thought I could get to the point I'm at now in about two weeks. It 
actually took about five or six weeks (just for an analog refresher). I'm 
still a bit shaky on some of that stuff, too. It's hard to test/see 
everything. So, some things I just read about, shrug, and keep going.

-Swift

Re: CDC 6600 emulation - was Re: How do they make Verilog code for unknown ICs?

[Paul Koning]

> On Jun 20, 2016, at 4:22 PM, Toby Thain  wrote:
> 
> On 2016-06-20 4:17 PM, Paul Koning wrote:
>> ...A hardware model can
> be used to replicate what old hardware did; for example, I have a
> partial CDC 6600 model that shows how it boots, and that model includes
> propagation delays on some signals (which are critical to correct
> operation in certain spots).
>> 
> 
> This is probably of great interest to more than just me.
> 
> Any more details? Going to publish?

Sure.  You can see it at svn://akdesign.dyndns.org/dtcyber/trunk; most is in 
the vhdl subdirectory but it uses some pieces from the top level.  Very much 
work in progress.

It's derived from the 6600 wire lists on bitsavers.  I OCRed them (what a 
pain), wrote VHDL models (gate level structural models) of each 6000 series 
module, and a Python script builds a structural model out of those elements 
interconnected by the wires from the wire lists.  "Sufficiently long" wires 
have their delay explicitly modeled.

I currently have chassis 1 (PPUs) working, at least to the point where I can do 
a deadstart, have that load from the deadstart panel, and execute some 
instructions.  I've used it to grok some magic related to deadstart that's part 
of the lore but not documented.  I also have the 6612 display controller 
working, so I can see how the text display on the console tubes works.  
Unfortunately I don't have a good SPICE model for the analog parts, so I don't 
yet know why the character shapes are changed by the circuitry in the manner 
that the photos show.

The CPU is work in progress.  I'm trying to get exchange to work.  It's hard; 
even more than the PPUs, the CPU relies on hairy timing in certain spots.  It 
appears that the wire lists are not all the same rev, and there are also some 
typos in them.

Some day, if things go really well, this may result in a gate level accurate 
FPGA 6600.  I'm thinking I'll stop trying OCR and simply type the wire lists 
instead; that's likely to be faster in the long run.

paul

Re: How do they make Verilog code for unknown ICs?

[Ian Finder]

I find most of the open source HDL simulators kind of suck. I think you can
still get ModelSim Web edition for free from altera.

This will do mixed language designs of Verilog, VHDL and schematic, and
works rather nicely.

Remember, each module is just a set of input and output signals, so the
language really doesn't matter. Mixed language designs are very common.

Yes, you can even build FPGA designs in a schematic editor out of library
modules. No, I don't suggest you should.



On Monday, June 20, 2016, Paul Koning  wrote:

>
> > On Jun 20, 2016, at 4:17 PM, Paul Koning  > wrote:
> >
> >
> >> On Jun 20, 2016, at 3:35 PM, Swift Griggs  > wrote:
> >>
> >> In my recent studies of electronics (I'm a noob for all practical
> >> purposes) I keep seeing folks refer to Verilog almost as a verb. I read
> >> about it in Wikipedia and it sounds pretty interesting. It's basically
> >> described as a coding scheme for electronics, similar to programming but
> >> with extras like signal strength and propagation included. Hey, cool!
> >
> > Verilog and VHDL are two "hardware description languages".  You can
> think of them as programming languages to describe hardware behavior.
> Another way to look at them is as languages designed to let you talk easily
> about lots of things that happen at the same time -- which is what happens
> in hardware.
>
> I forgot to mention: at least for VHDL, there's an open source simulator.
> In other words, a program that accepts VHDL input and lets you "run" the
> simulated hardware.  You can feed it inputs in various ways, and observe
> its behavior -- for example as waveform traces on a waveform display, like
> an oscilloscope.  Look for GHDL.  It's a GCC front end; it takes your VHDL
> code and compiles it, then it's linked with a support library to make an
> executable program.  Since it's GCC based you can do neat things, like run
> it on various hardware platforms.  Or link in C functions to do stuff, like
> simulate external peripherals connected to your hardware model.
>
> I haven't looked for open source Verilog simulators.
>
> paul
>
>
>

-- 
   Ian Finder
   (206) 395-MIPS
   ian.fin...@gmail.com

CDC 6600 emulation - was Re: How do they make Verilog code for unknown ICs?

[Toby Thain]

On 2016-06-20 4:17 PM, Paul Koning wrote:

...A hardware model can

be used to replicate what old hardware did; for example, I have a
partial CDC 6600 model that shows how it boots, and that model includes
propagation delays on some signals (which are critical to correct
operation in certain spots).




This is probably of great interest to more than just me.

Any more details? Going to publish?

--Toby

Re: How do they make Verilog code for unknown ICs?

[Paul Koning]

> On Jun 20, 2016, at 4:17 PM, Paul Koning  wrote:
> 
> 
>> On Jun 20, 2016, at 3:35 PM, Swift Griggs  wrote:
>> 
>> In my recent studies of electronics (I'm a noob for all practical 
>> purposes) I keep seeing folks refer to Verilog almost as a verb. I read 
>> about it in Wikipedia and it sounds pretty interesting. It's basically 
>> described as a coding scheme for electronics, similar to programming but 
>> with extras like signal strength and propagation included. Hey, cool! 
> 
> Verilog and VHDL are two "hardware description languages".  You can think of 
> them as programming languages to describe hardware behavior.  Another way to 
> look at them is as languages designed to let you talk easily about lots of 
> things that happen at the same time -- which is what happens in hardware.

I forgot to mention: at least for VHDL, there's an open source simulator.  In 
other words, a program that accepts VHDL input and lets you "run" the simulated 
hardware.  You can feed it inputs in various ways, and observe its behavior -- 
for example as waveform traces on a waveform display, like an oscilloscope.  
Look for GHDL.  It's a GCC front end; it takes your VHDL code and compiles it, 
then it's linked with a support library to make an executable program.  Since 
it's GCC based you can do neat things, like run it on various hardware 
platforms.  Or link in C functions to do stuff, like simulate external 
peripherals connected to your hardware model.

I haven't looked for open source Verilog simulators.

paul

Re: How do they make Verilog code for unknown ICs?

[Paul Koning]

> On Jun 20, 2016, at 3:35 PM, Swift Griggs  wrote:
> 
> In my recent studies of electronics (I'm a noob for all practical 
> purposes) I keep seeing folks refer to Verilog almost as a verb. I read 
> about it in Wikipedia and it sounds pretty interesting. It's basically 
> described as a coding scheme for electronics, similar to programming but 
> with extras like signal strength and propagation included. Hey, cool! 

Verilog and VHDL are two "hardware description languages".  You can think of 
them as programming languages to describe hardware behavior.  Another way to 
look at them is as languages designed to let you talk easily about lots of 
things that happen at the same time -- which is what happens in hardware.

VHDL borrows a lot from Ada; if you know Ada then VHDL will look somewhat 
familiar.  It originated in the US DoD.  Verilog appears to be originally a 
commercial product.  At this point, there are lots of implementations of both, 
and both are in wide use.  I only know (some) VHDL, so I can't really comment 
on similarities, differences, and plus/minuses.

One key thing in hardware is that you have "signals" which change as a result 
of some input event, and that change is visible at a later time.  But not 
immediately.  This can be confusing if you're a programmer and used to how C or 
similar languages work.  For example, in this C code:
a = 1;
b = a;

a and b will both equal 1 at the end.  But in the VHDL code:
a <= 1;
b <= a;

(where a and b are signals, as indicated by the fact that signal assignment 
operators are used), a will show up as 1 at the end of the current cycle, and b 
will at that time show up with the value that a had at the start of this cycle. 
 So this is very much NOT the same thing as the C code.  But it fits hardware, 
where signals have to propagate and new things happen as a result of previous 
actions at previous points in time.

VHDL and Verilog can be used to model hardware operation; they can also be used 
to describe hardware.  These are not quite the same.  A model can, for example, 
talk about actual delays.  A hardware description does not; such a 
"synthesizable" model is a subset of the full language.  This is a common way 
to design what goes into an FPGA.  A hardware model can be used to replicate 
what old hardware did; for example, I have a partial CDC 6600 model that shows 
how it boots, and that model includes propagation delays on some signals (which 
are critical to correct operation in certain spots).

Reverse engineering a design into VHDL or Verilog is just like reverse 
engineering a program into C.  Both can be very hard if you don't have much 
information.  For example, if all you have is a complex IC spec sheet, it is 
likely to be rather difficult.  If you have internals, it becomes more 
feasible. 

There are plenty of textbooks on the topic.  I would recommend the (large) book 
by Peter Ashenden on VHDL.  He also has a book on Verilog; given how he treated 
VHDL I expect that one is good too but I don't have it.

paul

Re: How do they make Verilog code for unknown ICs?

[Ian Finder]

To expand on my response-

Some PALs, PLAs, and GALs will yield the fuse map if you try and read them
with a programmer. This makes your job really easy. Take the fuse map and
compare to the original data sheet. Cool beans.
Some have the security bits set- in this case you would use a home-made
test setup to stimulate enough test conditions to build a truth table that
would allow you to infer the underlying logic.

If the part is registered, then things get tricker. For that, I might take
substantial in-system dumps with a logic analyzer (My favorite beginner LA
is the Agilent 16700, which comes with DOOM preinstalled, so you know it's
good stuff)

ROMS are easy- once you read a bit about how HDLs work, you will be able to
build one. Many languages offer functions to help with these (see readmemh
and readmemb in verilog)

Things get more complicated quickly- this is a deep topic and not something
that can be covered quickly. I suggest you start with the two books I
linked, and if you like them, there are a lot more around. Any edition
should be suitable- get or find whatever is cheapest.

We have not touched yet on practical things, like how to interface modern
1.8v FPGA I/O lines with 5V TTL logic- that is a topic for another day.

Cheers,

- Ian

On Mon, Jun 20, 2016 at 1:07 PM, Ian Finder  wrote:

> The hardest part of the process is distilling the functional specification
> of the part you are trying to replace. This is the heart of the topic. Some
> ways this can be done:
> > If adequate documentation exists, use it.
> > Observe the part's behavior in-system
> > Build a test bench to observe behavior of part outside of system
> > General leetness
>
> There is no one approach, it is more art than science.
>
> For going from a functional specification to a synthesizable model, this
> is simply writing HDL.
> I suggest this book, which covers the basics of this process.
>
> https://www.amazon.com/Verilog-Digital-System-Design-Verification/dp/0071445641
>
> If you have no 100-level understanding of digital logic, start here:
> https://www.amazon.com/Contemporary-Logic-Design-Randy-Katz/dp/0201308576
>
> Thanks,
>
> - Ian
>
>
>
>
>
> On Mon, Jun 20, 2016 at 1:02 PM, Toby Thain 
> wrote:
>
>> On 2016-06-20 3:35 PM, Swift Griggs wrote:
>>
>>>
>>> In my recent studies of electronics (I'm a noob for all practical
>>> purposes) I keep seeing folks refer to Verilog almost as a verb. I read
>>> about it in Wikipedia and it sounds pretty interesting. It's basically
>>> described as a coding scheme for electronics, similar to programming but
>>> with extras like signal strength and propagation included. Hey, cool!
>>>
>>> Why are folks referring to "Verilogging" and "doing a verilog" on older
>>> chips. Is there some way you can stuff an IC into a socket or alligator
>>> clip a bunch of tiny leads onto it and then "map" it somehow into
>>> Verilog?
>>> Is that what folks who write emulators do?
>>>
>>
>> They firstly go by documentation, and if that fails, reverse engineer,
>> painfully. This is why preserving, archiving, publishing documentation is
>> so incredibly important!
>>
>> > Ie.. they exhaustively dump
>>
>>> Verilog code for all the chips then figure out how to implement that in
>>>
>>
>> You can't in general get Verilog *out* of a chip. It goes the other way.
>> You can compile Verilog into gates and netlists etc.
>>
>> some computer programming language like C ? What do folks do for ROM chips
>>> and PLCs? I'd think they must dump the code and disassemble it. No?
>>>
>>
>> Yes, they do that where possible.
>>
>>
>>> I'm just curious and this is a tough question to answer with Google since
>>> I'm pretty clueless and don't know the right words to search for. I
>>> notice
>>>
>>
>> You can google "EDA tools". You can also grab toolchains from major
>> vendors like Altera and play with Verilog/VHDL and simulate the results,
>> too.
>>
>> people talk about correcting their Verilog code, so it must be somewhat of
>>> a manual process. I'm just wondering how someone even gets started with a
>>> process like that.
>>>
>>
>> I'd suggest hitting some textbooks, not Google.
>>
>> Niklaus Wirth's book is fantastic, for people more comfortable in
>> software, if you take it step by step:
>>
>>
>> https://www.amazon.ca/Digital-Circuit-Computer-Science-Students/dp/354058577X
>>
>> --Toby
>>
>>
>>> -Swift
>>>
>>>
>>
>
>
> --
>Ian Finder
>(206) 395-MIPS
>ian.fin...@gmail.com
>



-- 
   Ian Finder
   (206) 395-MIPS
   ian.fin...@gmail.com

Re: How do they make Verilog code for unknown ICs?

[Ian Finder]

The hardest part of the process is distilling the functional specification
of the part you are trying to replace. This is the heart of the topic. Some
ways this can be done:
> If adequate documentation exists, use it.
> Observe the part's behavior in-system
> Build a test bench to observe behavior of part outside of system
> General leetness

There is no one approach, it is more art than science.

For going from a functional specification to a synthesizable model, this is
simply writing HDL.
I suggest this book, which covers the basics of this process.
https://www.amazon.com/Verilog-Digital-System-Design-Verification/dp/0071445641

If you have no 100-level understanding of digital logic, start here:
https://www.amazon.com/Contemporary-Logic-Design-Randy-Katz/dp/0201308576

Thanks,

- Ian





On Mon, Jun 20, 2016 at 1:02 PM, Toby Thain 
wrote:

> On 2016-06-20 3:35 PM, Swift Griggs wrote:
>
>>
>> In my recent studies of electronics (I'm a noob for all practical
>> purposes) I keep seeing folks refer to Verilog almost as a verb. I read
>> about it in Wikipedia and it sounds pretty interesting. It's basically
>> described as a coding scheme for electronics, similar to programming but
>> with extras like signal strength and propagation included. Hey, cool!
>>
>> Why are folks referring to "Verilogging" and "doing a verilog" on older
>> chips. Is there some way you can stuff an IC into a socket or alligator
>> clip a bunch of tiny leads onto it and then "map" it somehow into Verilog?
>> Is that what folks who write emulators do?
>>
>
> They firstly go by documentation, and if that fails, reverse engineer,
> painfully. This is why preserving, archiving, publishing documentation is
> so incredibly important!
>
> > Ie.. they exhaustively dump
>
>> Verilog code for all the chips then figure out how to implement that in
>>
>
> You can't in general get Verilog *out* of a chip. It goes the other way.
> You can compile Verilog into gates and netlists etc.
>
> some computer programming language like C ? What do folks do for ROM chips
>> and PLCs? I'd think they must dump the code and disassemble it. No?
>>
>
> Yes, they do that where possible.
>
>
>> I'm just curious and this is a tough question to answer with Google since
>> I'm pretty clueless and don't know the right words to search for. I notice
>>
>
> You can google "EDA tools". You can also grab toolchains from major
> vendors like Altera and play with Verilog/VHDL and simulate the results,
> too.
>
> people talk about correcting their Verilog code, so it must be somewhat of
>> a manual process. I'm just wondering how someone even gets started with a
>> process like that.
>>
>
> I'd suggest hitting some textbooks, not Google.
>
> Niklaus Wirth's book is fantastic, for people more comfortable in
> software, if you take it step by step:
>
>
> https://www.amazon.ca/Digital-Circuit-Computer-Science-Students/dp/354058577X
>
> --Toby
>
>
>> -Swift
>>
>>
>


-- 
   Ian Finder
   (206) 395-MIPS
   ian.fin...@gmail.com

Re: How do they make Verilog code for unknown ICs?

[Guy Sotomayor Jr]

What you can do (and I’ve seen it done) is define verilog modules that
provide the functions of the IC and use that in their designs.  I’ve seen
at least two interesting classic computer recreations using this approach
(re-implemenation of the CADR lisp machine in verilog and an IBM 360/30
in verilog).

ROMs are easy (just instantiate a lookup table).  PLCs are just combinatorial
equations which are relatively easy with the verilog “assign” statement.

TTFN - Guy

> On Jun 20, 2016, at 12:35 PM, Swift Griggs  wrote:
> 
> 
> In my recent studies of electronics (I'm a noob for all practical 
> purposes) I keep seeing folks refer to Verilog almost as a verb. I read 
> about it in Wikipedia and it sounds pretty interesting. It's basically 
> described as a coding scheme for electronics, similar to programming but 
> with extras like signal strength and propagation included. Hey, cool! 
> 
> Why are folks referring to "Verilogging" and "doing a verilog" on older 
> chips. Is there some way you can stuff an IC into a socket or alligator 
> clip a bunch of tiny leads onto it and then "map" it somehow into Verilog? 
> Is that what folks who write emulators do? Ie.. they exhaustively dump 
> Verilog code for all the chips then figure out how to implement that in 
> some computer programming language like C ? What do folks do for ROM chips 
> and PLCs? I'd think they must dump the code and disassemble it. No? 
> 
> I'm just curious and this is a tough question to answer with Google since 
> I'm pretty clueless and don't know the right words to search for. I notice 
> people talk about correcting their Verilog code, so it must be somewhat of 
> a manual process. I'm just wondering how someone even gets started with a 
> process like that. 
> 
> -Swift

Re: How do they make Verilog code for unknown ICs?

[Toby Thain]

On 2016-06-20 3:35 PM, Swift Griggs wrote:


In my recent studies of electronics (I'm a noob for all practical
purposes) I keep seeing folks refer to Verilog almost as a verb. I read
about it in Wikipedia and it sounds pretty interesting. It's basically
described as a coding scheme for electronics, similar to programming but
with extras like signal strength and propagation included. Hey, cool!

Why are folks referring to "Verilogging" and "doing a verilog" on older
chips. Is there some way you can stuff an IC into a socket or alligator
clip a bunch of tiny leads onto it and then "map" it somehow into Verilog?
Is that what folks who write emulators do?


They firstly go by documentation, and if that fails, reverse engineer, 
painfully. This is why preserving, archiving, publishing documentation 
is so incredibly important!


> Ie.. they exhaustively dump

Verilog code for all the chips then figure out how to implement that in


You can't in general get Verilog *out* of a chip. It goes the other way. 
You can compile Verilog into gates and netlists etc.



some computer programming language like C ? What do folks do for ROM chips
and PLCs? I'd think they must dump the code and disassemble it. No?


Yes, they do that where possible.



I'm just curious and this is a tough question to answer with Google since
I'm pretty clueless and don't know the right words to search for. I notice


You can google "EDA tools". You can also grab toolchains from major 
vendors like Altera and play with Verilog/VHDL and simulate the results, 
too.



people talk about correcting their Verilog code, so it must be somewhat of
a manual process. I'm just wondering how someone even gets started with a
process like that.


I'd suggest hitting some textbooks, not Google.

Niklaus Wirth's book is fantastic, for people more comfortable in 
software, if you take it step by step:


https://www.amazon.ca/Digital-Circuit-Computer-Science-Students/dp/354058577X

--Toby



-Swift

How do they make Verilog code for unknown ICs?

[Swift Griggs]

In my recent studies of electronics (I'm a noob for all practical 
purposes) I keep seeing folks refer to Verilog almost as a verb. I read 
about it in Wikipedia and it sounds pretty interesting. It's basically 
described as a coding scheme for electronics, similar to programming but 
with extras like signal strength and propagation included. Hey, cool! 

Why are folks referring to "Verilogging" and "doing a verilog" on older 
chips. Is there some way you can stuff an IC into a socket or alligator 
clip a bunch of tiny leads onto it and then "map" it somehow into Verilog? 
Is that what folks who write emulators do? Ie.. they exhaustively dump 
Verilog code for all the chips then figure out how to implement that in 
some computer programming language like C ? What do folks do for ROM chips 
and PLCs? I'd think they must dump the code and disassemble it. No? 

I'm just curious and this is a tough question to answer with Google since 
I'm pretty clueless and don't know the right words to search for. I notice 
people talk about correcting their Verilog code, so it must be somewhat of 
a manual process. I'm just wondering how someone even gets started with a 
process like that. 

-Swift

Re: HP Series-80 computers - PRM-85 board case? ... maybe!

[alexmcwhirter]

On 2016-06-20 11:34, Pete Plank wrote:

On Jun 20, 2016, at 6:20 AM, martin.heppe...@dlr.de wrote:

I read in this list that there are more people interested in such a 
case.


I don’t have a 3D printer either, but I’m on board for one when
they’re ready to go - my PRM-85 is still in its anti-static bag.

Pete


I have a 3d printer, but not any of the boards in question. I don't mind 
helping if there's anything i can do.

RE: Quadra 660AV what's with the "PowerPC" label?

[Jay West]

This has drifted too far off topic.

J

RE: HP Series-80 computers - PRM-85 board case? ... maybe!

[Rik Bos]

> -Oorspronkelijk bericht-
> Van: cctalk [mailto:cctalk-boun...@classiccmp.org] Namens Jay West
> Verzonden: maandag 20 juni 2016 19:41
> Aan: 'General Discussion: On-Topic and Off-Topic Posts'
> Onderwerp: RE: HP Series-80 computers - PRM-85 board case? ... maybe!
> 
> I'll chime in as a 3rd person wanting a case for my PRM-85, and I know for 
> sure
> two other listmembers (who are not the two who mentioned it just now) who
> will definitely want one.
> 
> So probably 5 takers.
> 
> Anyone with a 3d printer want to make one for us?
> 
> J
You can count me in too, so it will be 6..

-Rik 

NetBooting old MacOS 8.x or 7x.

[Swift Griggs]

Due to the news about the MacOS name change, it's becoming quite hard to 
Google for older MacOS stuff. Was it ever possible to netboot MacOS 8.1 or 
earlier? I have A/UX 3 running nicely on a Quadra 700, now, but now I want 
to dual boot it with MacOS, but I don't have a CDROM. Taking out the drive 
and putting it on my other 68k Mac (a Centris 660AV) and installing MacOS 
still gives me some weird issues that I suspect are related to having 
installed it on different hardware.

If I can't do a network based install, I'll probably just steal a longer 
SCSI cable, use a molex power splitter to add another 5V power cable, and 
then install from CDROM while the system is half-open. Then I'll just 
button it up afterwards. The factor SCSI cable in my Quadra 700 has only 
one connector for a drive.

-Swift

Re: Quadra 660AV what's with the "PowerPC" label?

[Swift Griggs]

On Sat, 18 Jun 2016, Stefan Skoglund (lokal anv?ndare) wrote:
> What i don't like about systemd is: the fud about how easy it is to 
> write systemd unit files vs old shell script init.d/ditos .

In most simple cases, their argument is that it's easier to write a unit 
file because you don't need to know shell script. However, as you point 
out, that all starts to fall apart when the unit files, which ARE 
basically the same format as Windows INI files (square bracket section 
header with key-value pairs following). That's because INI files aren't a 
Turing complete language and what you start seeing is edge cases where, 
even using unit files, you still need management scripts. So, that leaves 
you shaking your head asking why did Linux do all this crap in the first 
place, if most of their "benefits" start to disintegrate as soon as your 
init-need gets the least bit complicated.

> Writing correct unit files for something as complicated as NFS and 
> especially if running in an split NFS3/NFS4 environment with 
> Kerberos-authenticated id mapping between server and client is NOT 
> simple.

That's a great example, but only one that someone who digs in and 
discovers things at a low level will notice. Most of the loud voices on 
the pro-systemd side are people who don't interact with Linux at that 
level. They are just overjoyed that it boots 2 seconds quicker. Nevermind 
that ALL of the other alternative init systems boot faster than init. It's 
easy to do once you bootgraph everything (and init could easily be 
extended to do the same, and has been in some experimental cases).

> Systemd doesn't ease the complexity of describing dependencies,

As you know, you have to trace each unit-file's "wants" back to another 
unit file and keep going until you hit one without any dependencies. It's 
about the same turd hunt as looking at LSM tags (nothing lost, nothing 
gained). That's just my opinion based on working with both. As you say, it 
doesn't ease the process, nonetheless.

> and i also have a suspicion that the systemd design wasn't enough well 
> defined for something else to happen (good and consistent design results 
> in better documentation) - so the users got to have to do a bit of 
> frustrating trial-and-error while writing their own unit files.

I've heard that before from RHEL customers who were a bit shocked (and 
didn't know anything about the systemd controversy).

> > > forcing a cgroup policy on everything.  Okay, perhaps systemd is the 
> > > first program to actually *use* cgroups but if at some point in the 
> > > future you want to play around with it, well ... sorry.  systemd is 
> > > in control there.

Also, just for fun, my comment on cgroups is that they were just fine and 
working great well before systemd. Systemd forces everything to be 
potentially managed by cgroups (ie.. systemd is process ID 1). So, some 
would say this is better & easier. Me? I preferred the method of dorking 
with the cgconfig, cgcreate, cgset, and raw control interfaces where 
needed in /sys. That works great for /proc and the utilities that use it. 
I don't need systemd to mitigate this process for me (and I don't like 
it). Zero of the benefits of cgroups are tied directly to systemd (but 
boy, don't ask the systemd guys to admit that), nor do they need to be, 
nor is it impossible to put init under cgroups control (in fact it's quite 
easy). Putting an abstraction layer around something means that someone 
who's an "expert" now has to learn the abstraction layer AND the actual 
tool. Having now done both, I at least feel comfortable stating my 
position.

> Which also affects something which i'm working with now namely cfengine, 
> cgroup's requires cfengine's performer cf-agent if it wan't to rerun 
> cf-serverd (the policy file server in cfengine, but cf-serverd has other 
> usage too) to start cf-serverd via systemctl enable/start.

Yep, so you end up having to bifurcate your unit files, write scripts, or 
some other "ugly" method (ugly in the eyes of systemd folks) that systemd 
didn't really factor into reality before rolling out.

> GNOME's adoption of systemd helps a bit.

They've adopted each other. I, for one, always hated GNOME anyway, (as 
Liam suspected). Birds of a feather sure flocked together in this case. 
However, that's a good thing. I like when things I dislike clump together. 
It makes them easier to avoid.

> It isn't good enough if the host is an virtual machine on esv4, that 
> really requires something which can handle clock drift in a sane way ie 
> ntpd.

Well, some of the freakout is over the fact that parts of NTP are some 
magical stuff and the maintainer is attempting to bow out. However, it 
doesn't detract from your very valid point.

> One functionality of questionable (or not so much) functionality is the 
> hails and whistles socket activation. IN the cause of NFS it would 
> require a new network protocol.

Well, it wouldn't surprise me if Lennart just plunged 

RE: General *NIX ramble thread - was Re: Quadra 660AV what's with the "PowerPC" label?

[Jay West]

Ian wrote...

Changing thread title and invoking filter.

Thanks, duly noted.

J

General *NIX ramble thread - was Re: Quadra 660AV what's with the "PowerPC" label?

[Ian Finder]

Changing thread title and invoking filter.

Thanks,

- Ian

On Mon, Jun 20, 2016 at 10:50 AM, Swift Griggs 
wrote:

> > And yet, now that significant chunks of the Linux underpinnings are
> > being combined into one purpose-written close-knit chunk, designed by a
> > single team, the same sort of people that praise *BSD for its conceptual
> > unity are harshly damning the thing bringing comparable unity to Linux.
> > Odd, that.
>
> It's not the same thing, IMO. People aren't slamming Linux+systemd for
> unifying their team (I've not even seen the harshest systemd critics
> mention this even in passing). They aren't upset because of the greater
> "conceptual unity", either. They are upset because it's breaking faith
> with "the unix way" (creating a giant all-consuming mega-daemon with
> equally heinous binary opaque supporting-crap ala journald) and going
> their own way (a hard right toward Bloatville with a couple of stops near
> Lake Clueless if you ask me), and they are, in the opinion of many, being
> jerks with the implementation of their planned schism.
>
> -Swift
>
>


-- 
   Ian Finder
   (206) 395-MIPS
   ian.fin...@gmail.com

Re: Quadra 660AV what's with the "PowerPC" label?

[Swift Griggs]

> And yet, now that significant chunks of the Linux underpinnings are 
> being combined into one purpose-written close-knit chunk, designed by a 
> single team, the same sort of people that praise *BSD for its conceptual 
> unity are harshly damning the thing bringing comparable unity to Linux. 
> Odd, that.

It's not the same thing, IMO. People aren't slamming Linux+systemd for 
unifying their team (I've not even seen the harshest systemd critics 
mention this even in passing). They aren't upset because of the greater 
"conceptual unity", either. They are upset because it's breaking faith 
with "the unix way" (creating a giant all-consuming mega-daemon with 
equally heinous binary opaque supporting-crap ala journald) and going 
their own way (a hard right toward Bloatville with a couple of stops near 
Lake Clueless if you ask me), and they are, in the opinion of many, being 
jerks with the implementation of their planned schism.

-Swift

RE: HP Series-80 computers - PRM-85 board case? ... maybe!

[Jay West]

I'll chime in as a 3rd person wanting a case for my PRM-85, and I know for sure 
two other listmembers (who are not the two who mentioned it just now) who will 
definitely want one.

So probably 5 takers.

Anyone with a 3d printer want to make one for us?

J

Re: DL11 M7800

[Noel Chiappa]

> From: Paul Birkel

>> I will upload the content to the CHW (and add the DB9 pinouts, too).

> Yes, please.

OK, done; see:

  http://gunkies.org/wiki/DEC_asynchronous_serial_line_pinout

and it references the new:

  http://gunkies.org/wiki/EIA_RS-232_serial_line_interface

I'd be grateful for any feedback on how I can improve the page(s) - more data
to add, thinks to explain better, etc.

Note: I added the DB9 pinouts, _but_ I have never made an actual DEC->DB9
cable, and am unlikely to (see below), so these have not been experimentally
tested. I'm pretty sure they're right (I checked them against some online
tables), but 'the difference between theory and practise', etc, etc. So if
someone does make any DB9 cables from this page, and can confirm that they
works, I'd be very grateful! :-)

I personally don't recommend making DEC->DB9 cables. DB25P<->DB9S adaptors are
cheap and easy to find on eBay, and if you make everything DB25, all you'll
need are a few DB25P<->DB9S adaptors to connect to PCs, and all your other
cabling activity (e.g. connecting one PDP-11 to another) will be simple, since
everything will be standardized on DB25s; no having to keep two kinds of every
cable.

Noel

Re: Y Combinator is restoring one of Alan Kay's Xerox Alto machines

[Al Kossow]

http://www.righto.com/2016/06/y-combinators-xerox-alto-restoring.html
https://news.ycombinator.com/item?id=11929396
http://ed-thelen.org/RestoreAlto/index.html

On 6/20/16 8:51 AM, Al Kossow wrote:
> I post just went up on Saturday. It's nice that both CHM and LCM folks
> are helping with this.
> 
> 
> On 6/20/16 8:41 AM, Liam Proven wrote:
>> http://www.righto.com/2016/06/y-combinators-xerox-alto-restoring.html
>>
>> Found via:
>>
>> http://www.osnews.com/story/29261/Xerox_Alto_restoring_the_legendary_1970s_GUI_computer
>>
>> There are 2 videos up so far, with disassemblies that may interest CCmpers.
>>
>> Some people from the list are involved, including Al Kossow, but I
>> haven't seen the link posted.
>>
> 

Y Combinator is restoring one of Alan Kay's Xerox Alto machines

[Liam Proven]

http://www.righto.com/2016/06/y-combinators-xerox-alto-restoring.html

Found via:

http://www.osnews.com/story/29261/Xerox_Alto_restoring_the_legendary_1970s_GUI_computer

There are 2 videos up so far, with disassemblies that may interest CCmpers.

Some people from the list are involved, including Al Kossow, but I
haven't seen the link posted.

-- 
Liam Proven • Profile: http://lproven.livejournal.com/profile
Email: lpro...@cix.co.uk • GMail/G+/Twitter/Flickr/Facebook: lproven
MSN: lpro...@hotmail.com • Skype/AIM/Yahoo/LinkedIn: liamproven
Cell/Mobiles: +44 7939-087884 (UK) • +420 702 829 053 (ČR)

Re: HP Series-80 computers - PRM-85 board case? ... maybe!

[Pete Plank]

> On Jun 20, 2016, at 6:20 AM, martin.heppe...@dlr.de wrote:
> 
> I read in this list that there are more people interested in such a case.

I don’t have a 3D printer either, but I’m on board for one when they’re ready 
to go - my PRM-85 is still in its anti-static bag.

Pete

Re: HP Series-80 computers - PRM-85 board case? ... maybe!

[Alexandre Souza]

   Marlin, why not try to find a hackerspace in your area, they usually 
have 3D printers and willing to help.


---




- Original Message - 
From: 

To: 
Sent: Monday, June 20, 2016 10:20 AM
Subject: HP Series-80 computers - PRM-85 board case? ... maybe!


Hi,

I own PRM-85 boards for my HP-85 and 86 machines. While they are very useful 
extension modules for these computers, they lack a proper case. I hate to 
destroy a working interface or memory module just for the case.

I read in this list that there are more people interested in such a case.

So I designed a replica case for 3D printing, but did not yet try it out.

I do not own a 3D printer and the commercial services calculate between $20 
to $100 for one shell (upper/lower).
This is a bit expensive for some trials, as I expect that the 3D design 
would need some iterative refinement to obtain a "perfect" case.


So: if someone owning a 3D printer and a PRM-85 board is interested in 
helping me to refine the design by making a test print I could supply the 
STL files for upper and lower shells. As a "thank-you" I would expect 
feedback to improve the design.


Regards,
Martin

Martin {.} Hepperle {at} mh-aerotools {dot} de

HP Series-80 computers - PRM-85 board case? ... maybe!

[Martin.Hepperle]

Hi,

I own PRM-85 boards for my HP-85 and 86 machines. While they are very useful 
extension modules for these computers, they lack a proper case. I hate to 
destroy a working interface or memory module just for the case.
I read in this list that there are more people interested in such a case.

So I designed a replica case for 3D printing, but did not yet try it out.

I do not own a 3D printer and the commercial services calculate between $20 to 
$100 for one shell (upper/lower).
This is a bit expensive for some trials, as I expect that the 3D design would 
need some iterative refinement to obtain a "perfect" case.

So: if someone owning a 3D printer and a PRM-85 board is interested in helping 
me to refine the design by making a test print I could supply the STL files for 
upper and lower shells. As a "thank-you" I would expect feedback to improve the 
design.

Regards,
Martin

Martin {.} Hepperle {at} mh-aerotools {dot} de

Re: Eckert - Faster, Faster; books in general

[Grumpyx]

Can read it online:

https://catalog.hathitrust.org/Record/000476266

On Thu, Jun 16, 2016 at 9:28 PM, Brian Walenz  wrote:

> Is there an electronic copy of this floating around?  My (ex-library) copy
> is missing all of chapter 11, "What is there to calculate?.  (And the last
> page of the previous chapter).  The pages weren't ripped out, they were
> missing when it was bound.  Very annoying, I enjoyed the book right up
> until it crashed, so to speak.
>
> Two, also ex-library, copies are listed on Amazon, and I hesitate to get
> another copy with the same problem.  There are others, of course, at
> outrageous prices.  Or maybe I don't realize the significance of '1st
> edition, not ex-library'.
>
> Just to make any discussion a bit more interesting, what would you suggest
> along similar lines?  The two giant books on IBM (detailing "pre-360", and
> "360") were quite fun too.
>
> bri
>

Re: Monitor refresh rate query

[Peter Corlett]

On Mon, Jun 20, 2016 at 07:12:35AM -0400, Noel Chiappa wrote:
[...]
> Although how a monitor is supposed to tell whether a signal is interlaced, or
> non-interlaced, is not clear - there's certainly no pin on the VGA connector
> which says so! :-)

It's encoded in the sync signal. The timings are tweaked such that the beam of
a dumb CRT will be pushed down a half-line on alternate fields.

Re: Monitor refresh rate query

[Noel Chiappa]

> I'm puzzled as to how one could drive both interlaced and
> non-interlaced monitors off the same video signal - wouldn't the
> interlaced one need a video signal which has 'odd lines, then a
> vertical retrace, then even lines, then a vertical retrace'?

So to sort of answer my own question, interlaced and non-interlaced video
signals are indeed different.

It turn out that 1024x768 was defined by IBM as XGA, and it was originally an
interlaced format - although a non- interlaced version was done later. So my
laptop quite possibly really is producing interlaced video...

Although how a monitor is supposed to tell whether a signal is interlaced, or
non-interlaced, is not clear - there's certainly no pin on the VGA connector
which says so! :-)

> Anyway, so which one is the one which is the number to look at when
> considering if the refresh rate is so high it might be dangerous to an
> old CRT monitor?
> E.g. my HP M50 manual says "Setting the screen resolution/refresh rate
> combination higher than 1024x768 at 60 Hz can damage the display." 

Since the monitor I'm using is called an "Ultra VGA 1024", I'm going to assume
it can handle 1042x768, and just stop worrying about it... If it melts down
the monitor, it melts down the monitor! :-)


> From: Jochen Kunz

> Sounds like an interlaced video mode. No surprise that the LCD can't do
> this.

Yes, as soon as I realized it probably really was interlaced video, it became
obvious why none of my LCD monitors would display it.

Noel

Any extra DEC monitors in Europe?

[Paul Anderson]

I have a friend looking for 2 DEC VRC21-KA  monitors in Europe.

I have one here, but will pack it only as a last resort.

If you have one of two you want to sell or trade, please let me know off
list. Also where you are located.

Thanks, Paul

Re: Monitor refresh rate query

[Jochen Kunz]

Am 17.06.16 um 17:36 schrieb Noel Chiappa:
> The first couple of LCD's I plugged in, 
[...]
> Finally I found one that _did_ give me the numbers,
> and it said the retrace was 35.6 Khz / 44 Hz.
[...]
> So I finally found an old CRT monitor that worked - but now I have another
> problem! It reports the video as being 35.6 Khz / 87 Hz!
Sounds like an interlaced video mode. No surprise that the LCD can't do
this. Interlaceing was common for 1024x768 XGA back in the days.
-- 

tschüß,
   Jochen