Re: Shipping a Flexowriter
Wow! Complete with the matching desk and in perfect cosmetic condition. What a find. Congratulations! Marc On Mar 21, 2018, at 10:55 AM, Kyle Owen via cctalk wrote: I ended up going with PakMail and was not disappointed. It arrived safe and sound yesterday, and though the cost of shipping was almost as much as the unit itself, I felt much better about paying a little more to make sure it arrived without damage. Pictures are here: https://imgur.com/a/xW480 Looking forward to getting it going! Thanks for the suggestions, Kyle
Re: DEC Field Guide > equivalent available for Data General?
Hi all, thanks for your comments. They has helped a lot, to understand the DG numbering schema, and will help identifying the modules. Many Greetings Ulrich
Remnants of local Commodore Users' Group being offered for free
This is in Eugene, OR. I received the following email on the local Freecycle-type list: I have all of the "Lane County Commodore Users Group" (LCCUG) inventory including (but not limited to) the following : Keyboards, one monitor, transformers, two disc players for 5 1/2 inch floppies, cassette tape player, games, a whole lot of instructions, dozens of empty discs, dozens of full discs, and much more. Plus a 25-plus pound lap top (SX-64) ! More than a regular car trunk can hold . Many items in original boxes. LCCUG is no longer exists. For a classic computer buff this would be a gold mine. It is amazing what this old computer was able to do - 30 years ago! 18th and Chambers area - Eugene. jimsav97...@yahoo.com --- I have nothing to do with this offer. FYI --Chuck
Re: FPGA implementations of DEC processors
On 3/22/18 9:40 AM, Jan Adelsbach via cctalk wrote: > Here is mine for the list, a PDP-1 (and some optional PDP-1D features) in > Verilog: > If you want to make your brain hurt, try supporting the MIT PDP-1X
Re: FPGA implementations of DEC processors
On 03/22/2018 05:47 AM, Zane Healy via cctalk wrote: I’ve been working on updating my DEC emulation site, that includes the FPGA section. That might help you find some, I’m sure that I have plenty of gaps. http://www.avanthar.com/healyzh/decemulation/pdp_fpga.html Zane Here is mine for the list, a PDP-1 (and some optional PDP-1D features) in Verilog: https://github.com/Jside/pdp1 It is a behavioral implementation rather than a gate-by-gate one. So it is easy to read and debug but not accurate in the instruction "pipeline" or timings. - Jan
Re: PDP8/e programmers consoles
On Wed, Mar 21, 2018 at 8:04 PM, Charles Dickman wrote: > On Tue, Mar 20, 2018 at 11:27 AM, Doug Ingraham via cctalk > > I guess you can be the first! Best wishes. > > Not sure I want to go there... > I hear you there. I built a front panel for a box I have been calling the FPG-8. Modeled after the Straight 8 front panel. I probably have 100 hours into it at the point I stalled out. Next step is silk screening the glass face plate. Electrically the panel works. Can do a walking 1's of the LED's Can sense all the switches. Now that I have a 3D printer I am thinking about a redo of the switches. They are just toggle switches right now. If I tilt them down so when on the handle sticks straight out (~20 degrees) and add a plastic handle cover resembling the DEC ones it will look really close. So expect a few hundred man hours in making a PCB front panel for omnibus with all the bells and whistles. Sometimes the things that seem easiest turn out to be difficult. > If you have ever looked at the DEC part number listing on bitsaver's > you will be amazed at all the specials that were done. And that was > what I was really interested in. Did DEC ever make a fancy panel that > displayed all the registers? The original designer had it in mind > since he displays a selected register at runtime during TS1 and when > the processor is stopped since that is TS1. As far as I know there are only 3 front panel variants made for omnibus. 1) lamp 8/e panel. (found on e f m lab-8 and DECSet 8000) 2) LED 8/e panel. (almost the same as 1) (Found on e, f, m, probably Lab-8 and possibly on DECSet 8000.) 3) 7 segment LED panel with keypad on 8/a. (Still only shows one at a time.) Minor variants of these but none that display all registers/states at the same time. Yes you could do this but the panel size would probably have to increase. I am sure part of the reason they did it the way they did was to cut costs. More lamps would have added considerably to the cost. And very little additional gain to functionally. Most of the "specials" were probably just different screens on front panels with the underlying hardware unchanged. That is certainly true of the Lab-8 and DECSet 8k. Best wishes! -- Doug Ingraham PDP-8 SN 1175
Re: FPGA implementations of DEC processors
Sent from my iPod > On Mar 22, 2018, at 2:35 AM, Angelo Papenhoff via cctalk > wrote: > >> On 21/03/18, Zane Healy via cctalk wrote: >> I’ve been working on updating my DEC emulation site, that includes the FPGA >> section. That might help you find some, I’m sure that I have plenty of gaps. >> >> http://www.avanthar.com/healyzh/decemulation/pdp_fpga.html >> > > I'd like to add mine to the list: > I've done a PDP-6 (not tested very much, but that should change soon): > https://github.com/aap/pdp6/tree/master/verilog > > ...and am currently working on a KA10: > https://github.com/aap/pdp10 > > My goal is to stay as close to the original schematics as possible. > That means I'm simulating delay elements with counters and stuff like > that. Also note that these two projects are the only experience with > HDLs that I have. Don't expect them to be very professional. > > aap Thanks! I’m traveling for work this week so it will take a while to update. Zane
Re: FPGA implementations of DEC processors
On 21/03/18, Zane Healy via cctalk wrote: > I’ve been working on updating my DEC emulation site, that includes the FPGA > section. That might help you find some, I’m sure that I have plenty of gaps. > > http://www.avanthar.com/healyzh/decemulation/pdp_fpga.html > I'd like to add mine to the list: I've done a PDP-6 (not tested very much, but that should change soon): https://github.com/aap/pdp6/tree/master/verilog ...and am currently working on a KA10: https://github.com/aap/pdp10 My goal is to stay as close to the original schematics as possible. That means I'm simulating delay elements with counters and stuff like that. Also note that these two projects are the only experience with HDLs that I have. Don't expect them to be very professional. aap
Re: FPGA implementations of DEC processors
> So what are the really good FPGA DEC processors? http://www.fpgaretrocomputing.org/pdp10x/