RE: Replacement for a DEC 7474 Chip
You are right, I thought I remembered someone else saying on this thread that he couldn't find a datasheet for the 7474 so I didn't look, but actually I found one quite easily! From: Paul Koning Sent: 16 May 2022 22:08 To: r...@jarratt.me.uk; Robert Jarratt ; cctalk@classiccmp.org Cc: Rick Murphy Subject: Re: Replacement for a DEC 7474 Chip On May 16, 2022, at 4:59 PM, Rob Jarratt via cctalk mailto:cctalk@classiccmp.org> > wrote: I have several 7474s, including one marked DEC 7474. Sadly, I fear that shipping from the US is likely to be prohibitive. I have ordered some 7474s. However I am getting a bit lost in the discussion now. From a simple fan out point of view, would an S be sufficient to replace it? I can think of two ways to answer that: (1) ask and see if you get an answer, hopefullly a correct one, (2) find the data sheet for the 74x74 you're looking at, and the devices it is driving, and do the calculation. Sum up the max input currents of the driven devices, compare with the min output current of the 74x74. If the output current is >= the load current, you have the needed fanout. paul
An IBM 1410 puzzlement...
I have a puzzlement with my IBM 1410 FPGA implementation.
ALD page 42.10.10.1, ILD figure 89
The symptom is this: The CPU runs and can execute instructions. So,
stuff is generally working.
Starting the address set process, the console appropriately prints the
"B" prompt (to set the instruction address into the IAR, B means
"BRANCH") or the "#" prompt to set other addresses. Normal stops print
the "S" as expected, errors print the "E" as expected and single cycle
or I/E mode print the "C" as expected.
However, starting a display operation (to display memory), which ought
to print a "D", prints an invalid parity "F" character - Bit 2 is picked
when it should not be. I have verified that "-S Special Char B" is
active (active low)
I first saw this on real FPGA hardware, and then confirmed it / did some
troubleshooting under simulation.
Here is what I found:
Looking at the ALD, a "D" is printed when
+S ADDRESS SET ROUTINE is active
+S DISPLAY ROUTINE is active
The Console Matrix at position 30 or 35
All of those conditions are satisfied. Address Set is appropriately
active because a display operation starts off by entering an address
(even though I don't have console input implemented yet, that is not
involved at this point). And, indeed "-S SPECIAL CHAR D" is active
(active low), as expected.
Looking at the ALD, a "B" is printed when
+ +S ADDRESS SET ROUTINE is active
+ The console's address set select rotary switch is NORMAL (it is)
(It will print '#' for other positions of this switch)
The Console Matrix at position 30 or 35
And, indeed, all of these conditions are satisfied as well, and indeed
"-S SPECIAL CHAR B" is active (active low) as well.
The FE instructional materials confirm that ADDRESS SET ROUTINE should
be active when starting a display operation, consistent with the ALD and
the ILD - because both then proceed to allow the operator to input an
address.
So, this feels like a bug - an implementation error that was later
corrected. The ALD I have is pretty early - 6-15-1961, with just one
ECO, and that ECO ("B") isn't on any of the gates on that ALD (this is
not unusual), so this is probably essentially the original ALD.
The fix would be pretty easy: to include "+S DISPLAY ROUTINE" onto the
wired or / "DOT" at coordinate 1B (to inhibit "B") and also to add a
wired or / "DOT" with "+S DISPLAY ROUTINE" at the output of gate 2I.
In both cases, the signal "+S DISPLAY ROUTINE" would then inhibit the
"B" or "#" (depending upon how the relevant switch is set.)
But I'm just really surprised at the whole thing. Not really asking
anyone to do anything, necessarily, but if anyone wants to confirm I'm
not nuts (or demonstrate to me that I am nuts), feel free.
[I am also experiencing it printing a "." when the mode switch is in CE,
which isn't right either - but haven't looked at that. It should be
printing a "#", regardless of the setting of the Address Entry switch -
I won't be surprised if the same kind of thing is going on there, as
this also involves the "address set routine" and matrix position 35 -
and a "." is a "#" plus bits B and A - so the evidence is pretty strong
there]
The documents:
1415 Console CE:
http://bitsavers.org/pdf/ibm/1410/CE_Instruction_Reference_Maintenance/1415_Console/
ILD (see Figure 89, page 95 of the PDF below) [ILDs read pretty much
like modern logic diagrams]
http://bitsavers.org/pdf/ibm/1410/drawings/R23-2936-0_1410_InstructionalLogicDiagrams.pdf
The ALD 42.10.10.1 (page 60 of the PDF below) [ALDs are tricker, because
of "DOT-ted" connections, and the logic family (RTL NAND *mostly*).
http://bitsavers.org/pdf/ibm/1410/drawings/1410_SYSTEM_VOL_X.pdf
JRJ
Re: Replacement for a DEC 7474 Chip
> On May 16, 2022, at 4:59 PM, Rob Jarratt via cctalk > wrote: > >> I have several 7474s, including one marked DEC 7474. Sadly, I fear that >> shipping from the US is likely to be prohibitive. > > I have ordered some 7474s. However I am getting a bit lost in the discussion > now. From a simple fan out point of view, would an S be sufficient to replace > it? I can think of two ways to answer that: (1) ask and see if you get an answer, hopefullly a correct one, (2) find the data sheet for the 74x74 you're looking at, and the devices it is driving, and do the calculation. Sum up the max input currents of the driven devices, compare with the min output current of the 74x74. If the output current is >= the load current, you have the needed fanout. paul
RE: Replacement for a DEC 7474 Chip
> -Original Message- > From: cctalk On Behalf Of Rick Murphy via > cctalk > Sent: 16 May 2022 17:28 > To: cctalk@classiccmp.org > Subject: Re: Replacement for a DEC 7474 Chip > > On 5/15/2022 4:16 AM, Eric Smith via cctalk wrote: > > On Sat, May 14, 2022, 16:09 ben via cctalk wrote: > > > >> On 2022-05-14 11:50 a.m., Nigel Johnson Ham via cctalk wrote: > >>> AFAIR LS can only drive one unit TTL load. > paul > >> LS is 4 TTL, 4 ma low. > >> Was there a trick of forcing the output of D flip flip to clear it? I > >> was wondering if this is what kills all the 7474's? > >> > > I don't think that worked on any TTL (or CMOS) 74x74 flip flops, > > except maybe by accident if you shorted the output enough to draw Vcc > > down (or ground up) enough to disrupt the FF, and then you have other > problems. > > > > Despite the logic diagram showing feedback from the outputs, all 74x74 > > have buffered outputs. The recent TI data sheets show an equivalent > > schematic only for the 74LS74. I can't at the moment find one for the 7474. > > > > It seems likely to me that early pre-TTL logic families like RTL might > > have had FFs with unbuffered outputs, but I haven't checked. > > I have several 7474s, including one marked DEC 7474. Sadly, I fear that > shipping from the US is likely to be prohibitive. I have ordered some 7474s. However I am getting a bit lost in the discussion now. From a simple fan out point of view, would an S be sufficient to replace it? > > -Rick
Re: Replacement for a DEC 7474 Chip
On 2022-May-15, at 3:53 PM, Eric Smith wrote: > I specifically said 74x74. Early TTL flipflops were very crude by comparison. On Mon, May 16, 2022 at 11:28 AM Brent Hilpert via cctalk < cctalk@classiccmp.org> wrote: > pre-TTL != early TTL > No, but 7470, 7472, 7473, and 74948 were _very_ early and were also very crude, as were their later L and H variants. 7474 was slightly later, and less crude. It should also be noted that the 7400 series was NOT the first commerical TTL integrated circuits. The earlier TTL flip-flops were even more crude, but I imagine the engineers that used them were nevertheless delighted at the advance over RTL and DTL.
Re: Replacement for a DEC 7474 Chip
On 2022-May-15, at 3:53 PM, Eric Smith wrote:
> On Sun, May 15, 2022, 13:03 Brent Hilpert via cctalk
> wrote:
> On 2022-May-15, at 1:16 AM, Eric Smith via cctalk wrote:
> > On Sat, May 14, 2022, 16:09 ben via cctalk wrote:
> >> On 2022-05-14 11:50 a.m., Nigel Johnson Ham via cctalk wrote:
> >>> AFAIR LS can only drive one unit TTL load.
> paul
> >> LS is 4 TTL, 4 ma low.
> >> Was there a trick of forcing the output of D flip flip
> >> to clear it? I was wondering if this is what kills all
> >> the 7474's?
> >
> > I don't think that worked on any TTL (or CMOS) 74x74 flip flops, except
> > maybe by accident if you shorted the output enough to draw Vcc down (or
> > ground up) enough to disrupt the FF, and then you have other problems.
> >
> > Despite the logic diagram showing feedback from the outputs, all 74x74 have
> > buffered outputs.
>
> Per TI schematics from 1969: 74 standard, H and L series flip-flops are
> unbuffered. Or at least many of them are/were, in their then-original form.
> Including 7475, 7490, etc. The output transistors connect both to the pins
> and wrap back to form the FF or other purposes.
>
> Collector-triggering was discussed a some years ago on the list in regards to
> a pdp8 front panel where DEC used collector-triggering on 74175's (IMO, bad
> design practice). From (my) empirical tests at the time, it turned out some
> 74S (Schottky) parts could be collector-triggered. However, between standard,
> LS, and S types, behaviour could vary with manufacturer and production date.
>
>
> > The recent TI data sheets show an equivalent schematic
> > only for the 74LS74. I can't at the moment find one for the 7474.
>
> > It seems likely to me that early pre-TTL logic families like RTL might have
> > had FFs with unbuffered outputs, but I haven't checked.
> I specifically said 74x74. Early TTL flipflops were very crude by comparison.
S = { "", "L", "H", "S", "LS", "F", "AS", "ALS", "AC", "ABT", etc. }
x ∈ S
"", "L", "H", "S" ∈ S
"L", "H", "S" != ""
7474: x == ""
pre-TTL != early TTL
Re: Replacement for a DEC 7474 Chip
On 5/15/2022 4:16 AM, Eric Smith via cctalk wrote: On Sat, May 14, 2022, 16:09 ben via cctalk wrote: On 2022-05-14 11:50 a.m., Nigel Johnson Ham via cctalk wrote: AFAIR LS can only drive one unit TTL load. paul LS is 4 TTL, 4 ma low. Was there a trick of forcing the output of D flip flip to clear it? I was wondering if this is what kills all the 7474's? I don't think that worked on any TTL (or CMOS) 74x74 flip flops, except maybe by accident if you shorted the output enough to draw Vcc down (or ground up) enough to disrupt the FF, and then you have other problems. Despite the logic diagram showing feedback from the outputs, all 74x74 have buffered outputs. The recent TI data sheets show an equivalent schematic only for the 74LS74. I can't at the moment find one for the 7474. It seems likely to me that early pre-TTL logic families like RTL might have had FFs with unbuffered outputs, but I haven't checked. I have several 7474s, including one marked DEC 7474. Sadly, I fear that shipping from the US is likely to be prohibitive. -Rick
Re: Identifying an 1802 system
> On 05/15/2022 11:02 PM John Ball via cctech wrote: > > > I just received a machine that someone found at a Vancouver second hand > store that I basically told them to buy on the single fact I don't own any > COSMAC machines and I've now had a chance to take it apart and photograph > the boards. It seems to be some sort of a kit system that the previous owner > put into a custom enclosure along with a power supply, a cassette interface I suggest asking over at cosmacelf.com. There is a lot of Cosmac info and expertise there, not just about Elfs (elves?). One thing that comes to mind is a series of boards and kits that were developed by a Canadian user group that sounds much like you describe. Development of those were tracked in their newsletter, Ipso Facto: http://cosmacelf.com/publications/newsletters/ipso-facto/ Some of the people who developed those systems are members of the forum at cosmacelf.com. Will
