Re: IBM 360/30 in verilog

[Mark Linimon]

On Tue, Jul 12, 2016 at 01:43:38PM +1000, ste...@malikoff.com wrote:
> everyone in it striking that characteristic 60s/70s IBM-photo-pose, eg.
> someone leaning over a table, another reaching for a console knob, one
> changing a tape and at least two people earnestly discussing a printout.

Although not at IBM, in the late 70s/early 80s I was the "model" for a
photo that went into an annual report.

The photographers are the ones that insist on the pose.

They insisted that I be "doing something" even though that "something"
was to act like I was pressing a button on a machine that was not complete
yet, and which if pressed would have done nothing whatsoever.  This,
despite my insistence that this pose was clearly nonsense.

mcl

Re: IBM 360/30 in verilog

[ben]

On 7/11/2016 4:53 AM, Paul Birkel wrote:

-Original Message-
From: cctalk [mailto:cctalk-boun...@classiccmp.org] On Behalf Of Camiel 
Vanderhoeven
Sent: Monday, July 11, 2016 4:31 AM
To: General Discussion: On-Topic and Off-Topic Posts
Subject: Re: IBM 360/30 in verilog (was: How do they make Verilog code for 
unknown ICs?)

And I'm very close to having a 360/65 in VHDL.
-

Sweet :->.  What FPGA platform are you using?  Lawrence used a Spartan 3.  Don't know how 
close to "full" he pushed it.

paul



How ever very few PLATFORMS have *CORE* memory.
Ducks...
Ben.

Re: IBM 360/30 in verilog

[Jon Elson]

On 07/12/2016 12:34 AM, Camiel Vanderhoeven wrote:
Most weren't sold, but leased. The ALDs would be used by 
the IBM CE, not the customers themselves. I don't know if 
machines that were sold rather than leased came with ALDs 
or if IBM kept these, I suspect the latter to be the case. 
Absolutely, the ALDs went with the machines, whether sold or 
leased.  The ALDs contained machine specific info for the 
emulators loaded into it, as well as all ECOs applied at the 
factory and in the field.  So, you could have 2 identical 
models at an installation, and there would be TWO ALD carts, 
with serial numbers on them, so they knew which one applied 
to which box.


Jon

Re: IBM 360/30 in verilog

[Ian S. King]

...and the /20 was developed at Sindelfingen, which was one reason it was
the redheaded stepchild (but very popular nonetheless, due to its lower
cost).

On Tue, Jul 12, 2016 at 6:01 AM, Camiel Vanderhoeven 
wrote:

> On Tue, Jul 12, 2016 at 1:24 PM,   wrote:
> > Camiel said:
> >> IBM UK Laboratories in Hursley was a software facility, the model 40 was
> >> developed in Poughkeepsie, like the others. Secondary production sites
> were
> >> in Mainz, Germany, and Japan.
> >
> > Yes, the wiki does say that, but I am sure Hursley was involved in
> designing
> > hardware as well, for instance TROS. This PDF by Pugh states that a team
> at Hursley
> > were designing the Model 40:
> http://ed-thelen.org/Pugh-Technology_Transfer.pdf
> > As a CE, my dad was there to study the hardware only.
>
> You're quite right, I was wrong. Both hardware and software
> development took place at Hursley. According to Pugh, Johnson, and
> Palmer's "IBM's 360 and early 370 systems", the /30 (then called NPL
> 101) was developed at Endicott, the /40 (NPL 250) at Hursley, and the
> larger models at Poughkeepsie.
>



-- 
Ian S. King, MSIS, MSCS, Ph.D. Candidate
The Information School 
Dissertation: "Why the Conversation Mattered: Constructing a Sociotechnical
Narrative Through a Design Lens

Archivist, Voices From the Rwanda Tribunal 
Value Sensitive Design Research Lab 

University of Washington

There is an old Vulcan saying: "Only Nixon could go to China."

Re: IBM 360/30 in verilog

[Camiel Vanderhoeven]

On Tue, Jul 12, 2016 at 2:07 PM, Dave Wade <dave.g4...@gmail.com> wrote:
>
>> -Original Message-
>> From: cctalk [mailto:cctalk-boun...@classiccmp.org] On Behalf Of Camiel
>> Vanderhoeven
>> Sent: 12 July 2016 09:56
>> To: General Discussion: On-Topic and Off-Topic Posts
>> <cctalk@classiccmp.org>
>> Subject: RE: IBM 360/30 in verilog
>>
>> Op 12 jul. 2016 10:14 a.m. schreef "Dave Wade" <dave.g4...@gmail.com>:
>> >
>> > > -Original Message-
>> > > From: cctalk [mailto:cctalk-boun...@classiccmp.org] On Behalf Of
>> > > Curious Marc
>> > > Sent: 12 July 2016 08:58
>> > > To: General Discussion: On-Topic and Off-Topic Posts
>> > > <cctalk@classiccmp.org>
>> > > Subject: Re: IBM 360/30 in verilog
>> > >
>> > > Darn. My hopes are shattered. Lots of Verilog in my future, that is
>> > > if
>> we
>> > can
>> > > find 360/50 ALDs...
>> > > Marc
>> > >
>> >
>> > It actually might be easier to produce a generic S/360 clone in FPGA
>> > using the POP rather than individual ALU's.
>> > Having built a very simple CPU (in VHDL not Verilog) and planning to
>> > start on a more complex (Ferranti Pegasus) Of course it wouldn't be
>> > cycle accurate, but perhaps that wouldn't be important.
>>
>> Sure, a generic one would be simpler, but the point of doing an accurate one
>> of a specific model (65 in my case) is to accurately drive the panel that 
>> shows
>> the  internal registers and opening of gates.
>
> I think you are correct. I had assumed that the panel only displayed the 
> normal 360 registers, in which case
> the VHDL could easily route these to a panel, but on reading the 360/65 
> Functional Characteristics
>
> http://bitsavers.informatik.uni-stuttgart.de/pdf/ibm/360/funcChar/A22-6884-3_360-65_funcChar.pdf
>
> I can see several registers are displayed that are not mentioned or defined 
> elsewhere so you would need a
> Set of ALDs for the 65 (or possibly a 67 as that’s basically the same 
> machine) to get a full panel display. It would
> Also be nice to see what is on the roller selector switchs as that page in 
> the manual has not scanned very well..

I have a pdf file I created that shows the layout of the roller bars;
I don't think the link can take attachments, but if you want I could
email you a copy directly.

Camiel.

RE: IBM 360/30 in verilog

[Dave Wade]

> -Original Message-
> From: cctalk [mailto:cctalk-boun...@classiccmp.org] On Behalf Of Camiel
> Vanderhoeven
> Sent: 12 July 2016 14:06
> To: General Discussion: On-Topic and Off-Topic Posts
> <cctalk@classiccmp.org>
> Subject: Re: IBM 360/30 in verilog
> 
> On Tue, Jul 12, 2016 at 2:07 PM, Dave Wade <dave.g4...@gmail.com>
> wrote:
> >
> >> -Original Message-
> >> From: cctalk [mailto:cctalk-boun...@classiccmp.org] On Behalf Of
> >> Camiel Vanderhoeven
> >> Sent: 12 July 2016 09:56
> >> To: General Discussion: On-Topic and Off-Topic Posts
> >> <cctalk@classiccmp.org>
> >> Subject: RE: IBM 360/30 in verilog
> >>
> >> Op 12 jul. 2016 10:14 a.m. schreef "Dave Wade"
> <dave.g4...@gmail.com>:
> >> >
> >> > > -Original Message-
> >> > > From: cctalk [mailto:cctalk-boun...@classiccmp.org] On Behalf Of
> >> > > Curious Marc
> >> > > Sent: 12 July 2016 08:58
> >> > > To: General Discussion: On-Topic and Off-Topic Posts
> >> > > <cctalk@classiccmp.org>
> >> > > Subject: Re: IBM 360/30 in verilog
> >> > >
> >> > > Darn. My hopes are shattered. Lots of Verilog in my future, that
> >> > > is if
> >> we
> >> > can
> >> > > find 360/50 ALDs...
> >> > > Marc
> >> > >
> >> >
> >> > It actually might be easier to produce a generic S/360 clone in
> >> > FPGA using the POP rather than individual ALU's.
> >> > Having built a very simple CPU (in VHDL not Verilog) and planning
> >> > to start on a more complex (Ferranti Pegasus) Of course it wouldn't
> >> > be cycle accurate, but perhaps that wouldn't be important.
> >>
> >> Sure, a generic one would be simpler, but the point of doing an
> >> accurate one of a specific model (65 in my case) is to accurately
> >> drive the panel that shows the  internal registers and opening of gates.
> >
> > I think you are correct. I had assumed that the panel only displayed
> > the normal 360 registers, in which case the VHDL could easily route
> > these to a panel, but on reading the 360/65 Functional Characteristics
> >
> > http://bitsavers.informatik.uni-stuttgart.de/pdf/ibm/360/funcChar/A22-
> > 6884-3_360-65_funcChar.pdf
> >
> > I can see several registers are displayed that are not mentioned or
> > defined elsewhere so you would need a Set of ALDs for the 65 (or
> > possibly a 67 as that’s basically the same machine) to get a full panel
> display. It would Also be nice to see what is on the roller selector switchs 
> as
> that page in the manual has not scanned very well..
> 
> I have a pdf file I created that shows the layout of the roller bars; I don't
> think the link can take attachments, but if you want I could email you a copy
> directly.
> 
> Camiel.

A direct reply would be very nice. 

Dave

Re: IBM 360/30 in verilog

[Camiel Vanderhoeven]

On Tue, Jul 12, 2016 at 1:24 PM,   wrote:
> Camiel said:
>> IBM UK Laboratories in Hursley was a software facility, the model 40 was
>> developed in Poughkeepsie, like the others. Secondary production sites were
>> in Mainz, Germany, and Japan.
>
> Yes, the wiki does say that, but I am sure Hursley was involved in designing
> hardware as well, for instance TROS. This PDF by Pugh states that a team at 
> Hursley
> were designing the Model 40: http://ed-thelen.org/Pugh-Technology_Transfer.pdf
> As a CE, my dad was there to study the hardware only.

You're quite right, I was wrong. Both hardware and software
development took place at Hursley. According to Pugh, Johnson, and
Palmer's "IBM's 360 and early 370 systems", the /30 (then called NPL
101) was developed at Endicott, the /40 (NPL 250) at Hursley, and the
larger models at Poughkeepsie.

Re: IBM 360/30 in verilog

[Pete Lancashire]

Time to dust of the 50 panel hidden in the basement.

-pete



On Tue, Jul 12, 2016 at 1:55 AM, Camiel Vanderhoeven
<iamcam...@gmail.com> wrote:
> Op 12 jul. 2016 10:14 a.m. schreef "Dave Wade" <dave.g4...@gmail.com>:
>>
>> > -Original Message-
>> > From: cctalk [mailto:cctalk-boun...@classiccmp.org] On Behalf Of Curious
>> > Marc
>> > Sent: 12 July 2016 08:58
>> > To: General Discussion: On-Topic and Off-Topic Posts
>> > <cctalk@classiccmp.org>
>> > Subject: Re: IBM 360/30 in verilog
>> >
>> > Darn. My hopes are shattered. Lots of Verilog in my future, that is if
> we
>> can
>> > find 360/50 ALDs...
>> > Marc
>> >
>>
>> It actually might be easier to produce a generic S/360 clone in FPGA using
>> the POP rather than individual ALU's.
>> Having built a very simple CPU (in VHDL not Verilog) and planning to start
>> on a more complex (Ferranti Pegasus)
>> Of course it wouldn't be cycle accurate, but perhaps that wouldn't be
>> important.
>
> Sure, a generic one would be simpler, but the point of doing an accurate
> one of a specific model (65 in my case) is to accurately drive the panel
> that shows the  internal registers and opening of gates.
>

Re: IBM 360/30 in verilog

[Guy Sotomayor Jr]

POP = Principles of Operations.  It is the 360/370 *bible*.  It describes (in 
detail) how
the architecture works (including all instructions).  It specifies what are 
“architectural”
(ie can be counted on by all models) and what are “implementation” specific.

Changes to the POP were *very* restricted…that is, the architecture committee 
needed
a long and detailed justification for any change to the POP and most didn’t 
make it in.

TTFN - Guy

> On Jul 12, 2016, at 2:04 AM, Curious Marc  wrote:
> 
> What's a POP? As long as it emulates all the registers connected to light and 
> switches that might do for me, but I was assuming these would very specific 
> to the CPU detailed innards.
> Marc
> 
>> On Jul 12, 2016, at 5:14 PM, Dave Wade  wrote:
>> 
>> It actually might be easier to produce a generic S/360 clone in FPGA using
>> the POP rather than individual ALU's.
>> Having built a very simple CPU (in VHDL not Verilog) and planning to start
>> on a more complex (Ferranti Pegasus)
>> Of course it wouldn't be cycle accurate, but perhaps that wouldn't be
>> important.

Re: IBM 360/30 in verilog

[Ian S. King]

It is my understanding - from conversations with numerous IBM engineers and
retirees - that ALDs are 'as-built' documents related to a particular
machine and were indeed kept with the machine at the customer site.
Otherwise, the poor CE would have to haul around a rack of ALDs for each
machine being serviced!  It's easy to underestimate the physical bulk of
these documents when printed and in binders.  -- Ian

On Tue, Jul 12, 2016 at 7:30 AM, Paul Koning <paulkon...@comcast.net> wrote:

>
> > On Jul 12, 2016, at 6:00 AM, Paul Birkel <pbir...@gmail.com> wrote:
> >
> > Principles of Operation, I believe.  Example:
> >
> >
> http://bitsavers.informatik.uni-stuttgart.de/pdf/ibm/360/princOps/A22-6821-0
> > _360PrincOps.pdf
> >
> > -Original Message-
> > From: cctalk [mailto:cctalk-boun...@classiccmp.org] On Behalf Of Curious
> > Marc
> > Sent: Tuesday, July 12, 2016 5:04 AM
> > To: General Discussion: On-Topic and Off-Topic Posts
> > Subject: Re: IBM 360/30 in verilog
> >
> > What's a POP? As long as it emulates all the registers connected to light
> > and switches that might do for me, but I was assuming these would very
> > specific to the CPU detailed innards.
> > Marc
> >
> >> On Jul 12, 2016, at 5:14 PM, Dave Wade <dave.g4...@gmail.com> wrote:
> >>
> >> It actually might be easier to produce a generic S/360 clone in FPGA
> >> using the POP rather than individual ALU's.
> >> Having built a very simple CPU (in VHDL not Verilog) and planning to
> >> start on a more complex (Ferranti Pegasus) Of course it wouldn't be
> >> cycle accurate, but perhaps that wouldn't be important.
>
> It depends on what you're trying to emulate.  If you want an instruction
> level simulator, sort of a SIMH in silicon, then going from the POP or
> analogous documents (processor reference manuals, computer family
> architecture manuals such as DEC published for the PDP-11 and VAX) will do
> nicely.  Such an approach is not going to show you the peculiarities of a
> particular implementation, details too deep for the sort of documentation
> you're using, let alone implementation bugs.
>
> By way of analogy, if you build a CDC 6000 emulation using that approach,
> it won't do the "zero written to memory at PC at deadstart time" property,
> because that is nowhere documented or explained in any printed document I
> have ever seen.  But it's part of the unwritten lore of that machine.  If
> you build a gate level model from the engineering drawings, you can see it
> clearly (and you can readily discover its cause).
>
> Building an accurate model from a POP requires a great deal of
> intellectual effort, to understand all the critical details sufficiently to
> model them in behavioral models.  You can perhaps lift them from existing
> software emulators (SIMH, Hercules) and get "close enough".  Debugging
> would be hard, especially if the documentation isn't quite accurate enough
> to allow all the diagnostics to pass.
>
> A gate level model constructed from the engineering drawings is more
> cumbersome in certain ways, almost certainly less efficient in FPGA
> resources -- but it's much more a mechanical process.  If the drawings are
> accurate (that's an "if" indeed), then the model will be accurate.  The
> diagnostics should pass without major effort, serving more as confirmation
> tools than as debugging aids.
>
> paul
>
>
>


-- 
Ian S. King, MSIS, MSCS, Ph.D. Candidate
The Information School <http://ischool.uw.edu>
Dissertation: "Why the Conversation Mattered: Constructing a Sociotechnical
Narrative Through a Design Lens

Archivist, Voices From the Rwanda Tribunal <http://tribunalvoices.org>
Value Sensitive Design Research Lab <http://vsdesign.org>

University of Washington

There is an old Vulcan saying: "Only Nixon could go to China."

Re: IBM 360/30 in verilog

[Paul Koning]

> On Jul 12, 2016, at 6:00 AM, Paul Birkel <pbir...@gmail.com> wrote:
> 
> Principles of Operation, I believe.  Example:
> 
> http://bitsavers.informatik.uni-stuttgart.de/pdf/ibm/360/princOps/A22-6821-0
> _360PrincOps.pdf
> 
> -Original Message-
> From: cctalk [mailto:cctalk-boun...@classiccmp.org] On Behalf Of Curious
> Marc
> Sent: Tuesday, July 12, 2016 5:04 AM
> To: General Discussion: On-Topic and Off-Topic Posts
> Subject: Re: IBM 360/30 in verilog
> 
> What's a POP? As long as it emulates all the registers connected to light
> and switches that might do for me, but I was assuming these would very
> specific to the CPU detailed innards.
> Marc
> 
>> On Jul 12, 2016, at 5:14 PM, Dave Wade <dave.g4...@gmail.com> wrote:
>> 
>> It actually might be easier to produce a generic S/360 clone in FPGA 
>> using the POP rather than individual ALU's.
>> Having built a very simple CPU (in VHDL not Verilog) and planning to 
>> start on a more complex (Ferranti Pegasus) Of course it wouldn't be 
>> cycle accurate, but perhaps that wouldn't be important.

It depends on what you're trying to emulate.  If you want an instruction level 
simulator, sort of a SIMH in silicon, then going from the POP or analogous 
documents (processor reference manuals, computer family architecture manuals 
such as DEC published for the PDP-11 and VAX) will do nicely.  Such an approach 
is not going to show you the peculiarities of a particular implementation, 
details too deep for the sort of documentation you're using, let alone 
implementation bugs.

By way of analogy, if you build a CDC 6000 emulation using that approach, it 
won't do the "zero written to memory at PC at deadstart time" property, because 
that is nowhere documented or explained in any printed document I have ever 
seen.  But it's part of the unwritten lore of that machine.  If you build a 
gate level model from the engineering drawings, you can see it clearly (and you 
can readily discover its cause).

Building an accurate model from a POP requires a great deal of intellectual 
effort, to understand all the critical details sufficiently to model them in 
behavioral models.  You can perhaps lift them from existing software emulators 
(SIMH, Hercules) and get "close enough".  Debugging would be hard, especially 
if the documentation isn't quite accurate enough to allow all the diagnostics 
to pass.

A gate level model constructed from the engineering drawings is more cumbersome 
in certain ways, almost certainly less efficient in FPGA resources -- but it's 
much more a mechanical process.  If the drawings are accurate (that's an "if" 
indeed), then the model will be accurate.  The diagnostics should pass without 
major effort, serving more as confirmation tools than as debugging aids.

paul

RE: IBM 360/30 in verilog

[Dave Wade]

> -Original Message-
> From: cctalk [mailto:cctalk-boun...@classiccmp.org] On Behalf Of Camiel
> Vanderhoeven
> Sent: 12 July 2016 09:56
> To: General Discussion: On-Topic and Off-Topic Posts
> <cctalk@classiccmp.org>
> Subject: RE: IBM 360/30 in verilog
> 
> Op 12 jul. 2016 10:14 a.m. schreef "Dave Wade" <dave.g4...@gmail.com>:
> >
> > > -Original Message-
> > > From: cctalk [mailto:cctalk-boun...@classiccmp.org] On Behalf Of
> > > Curious Marc
> > > Sent: 12 July 2016 08:58
> > > To: General Discussion: On-Topic and Off-Topic Posts
> > > <cctalk@classiccmp.org>
> > > Subject: Re: IBM 360/30 in verilog
> > >
> > > Darn. My hopes are shattered. Lots of Verilog in my future, that is
> > > if
> we
> > can
> > > find 360/50 ALDs...
> > > Marc
> > >
> >
> > It actually might be easier to produce a generic S/360 clone in FPGA
> > using the POP rather than individual ALU's.
> > Having built a very simple CPU (in VHDL not Verilog) and planning to
> > start on a more complex (Ferranti Pegasus) Of course it wouldn't be
> > cycle accurate, but perhaps that wouldn't be important.
> 
> Sure, a generic one would be simpler, but the point of doing an accurate one
> of a specific model (65 in my case) is to accurately drive the panel that 
> shows
> the  internal registers and opening of gates.

I think you are correct. I had assumed that the panel only displayed the normal 
360 registers, in which case 
the VHDL could easily route these to a panel, but on reading the 360/65 
Functional Characteristics 

http://bitsavers.informatik.uni-stuttgart.de/pdf/ibm/360/funcChar/A22-6884-3_360-65_funcChar.pdf

I can see several registers are displayed that are not mentioned or defined 
elsewhere so you would need a
Set of ALDs for the 65 (or possibly a 67 as that’s basically the same machine) 
to get a full panel display. It would
Also be nice to see what is on the roller selector switchs as that page in the 
manual has not scanned very well..

Dave

RE: IBM 360/30 in verilog

[Dave Wade]

> -Original Message-
> From: cctalk [mailto:cctalk-boun...@classiccmp.org] On Behalf Of Camiel
> Vanderhoeven
> Sent: 12 July 2016 06:35
> To: General Discussion: On-Topic and Off-Topic Posts
> <cctalk@classiccmp.org>
> Subject: Re: IBM 360/30 in verilog
> 
> Op 12 jul. 2016 5:50 a.m. schreef <ste...@malikoff.com>:
> >
> > Jon said:
> > > LOTS of model /40s were sold in the US.  EVERY one had its own set
> > > of ALDs, with the serial number of the CPU on them.
> > > They not only recorded the general info for the model, but they had
> > > specific changes to reflect the exact configuration of THAT machine.
> >
> > I didn't know that every machine came with a set of ALDs but you are
> > right that a lot of /40's were sold stateside. My dad was re-posted
> > directly from Hursley to Poughkeepsie in '65 which I was where some
> > (or
> > all?) the /40s were assembled.
> > One of the IBM Journals (75 years?) has a large colour photo of a row
> > of 40s on the final assembly floor at Poughkeepsie, everyone in it
> > striking that characteristic 60s/70s IBM-photo-pose, eg. someone
> > leaning over a table, another reaching for a console knob, one
> > changing a tape and at least two people earnestly discussing a printout.
> 
> Most weren't sold, but leased. The ALDs would be used by the IBM CE, not
> the customers themselves. I don't know if machines that were sold rather
> than leased came with ALDs or if IBM kept these, I suspect the latter to be
> the case.

I would actually expect IBM to supply the ALD's with a machine when bought. 
Under anti-trust legislation they had to supply enough information for a third 
party to maintain the machine. I am pretty sure the ALD's for the 7090 formerly 
at GCHQ (UK Snooping agency) latterly at Manchester University Medical School 
went to the National Museum of Computing when Dr. Clarke died..

http://www.ukuug.org/newsletter/linux-newsletter/linux@uk12/dclark.shtml

this machine was maintained by Ferranti so I assume they had the ALD's..

Dave 

Re: IBM 360/30 in verilog

[steven]

Camiel said:
> IBM UK Laboratories in Hursley was a software facility, the model 40 was
> developed in Poughkeepsie, like the others. Secondary production sites were
> in Mainz, Germany, and Japan.

Yes, the wiki does say that, but I am sure Hursley was involved in designing
hardware as well, for instance TROS. This PDF by Pugh states that a team at 
Hursley
were designing the Model 40: http://ed-thelen.org/Pugh-Technology_Transfer.pdf
As a CE, my dad was there to study the hardware only.

Re: IBM 360/30 in verilog

[Camiel Vanderhoeven]

Op 12 jul. 2016 4:10 a.m. schreef :
>
> Mike said:
> > On Tue, Jul 12, 2016 at 10:36 AM,   wrote:
> >> Al said:
> >>> On 7/11/16 9:14 AM, Jon Elson wrote:
>  The microcode was in the ALD drawings, and might even be in
bitsavers archive, if they have the right manual.
> >>>
> >>> 360 CPU ALDs are extremely difficult to find.
> >>> If the 65 set could be scanned, I'd be happy to upload them to
bitsavers.
> >>
> >> Indeed they must be. I've been looking for /40 ALDs for some time but
haven't struck any. I wonder if they're
> >> scarce becase the 40 was a AFAIK a british-developed 360. My dad was
posted to Hursley to learn the /40 in 64-65.

IBM UK Laboratories in Hursley was a software facility, the model 40 was
developed in Poughkeepsie, like the others. Secondary production sites were
in Mainz, Germany, and Japan.

RE: IBM 360/30 in verilog

[Camiel Vanderhoeven]

Op 12 jul. 2016 10:14 a.m. schreef "Dave Wade" <dave.g4...@gmail.com>:
>
> > -Original Message-
> > From: cctalk [mailto:cctalk-boun...@classiccmp.org] On Behalf Of Curious
> > Marc
> > Sent: 12 July 2016 08:58
> > To: General Discussion: On-Topic and Off-Topic Posts
> > <cctalk@classiccmp.org>
> > Subject: Re: IBM 360/30 in verilog
> >
> > Darn. My hopes are shattered. Lots of Verilog in my future, that is if
we
> can
> > find 360/50 ALDs...
> > Marc
> >
>
> It actually might be easier to produce a generic S/360 clone in FPGA using
> the POP rather than individual ALU's.
> Having built a very simple CPU (in VHDL not Verilog) and planning to start
> on a more complex (Ferranti Pegasus)
> Of course it wouldn't be cycle accurate, but perhaps that wouldn't be
> important.

Sure, a generic one would be simpler, but the point of doing an accurate
one of a specific model (65 in my case) is to accurately drive the panel
that shows the  internal registers and opening of gates.

Re: IBM 360/30 in verilog

[Camiel Vanderhoeven]

Op 12 jul. 2016 5:50 a.m. schreef :
>
> Jon said:
> > LOTS of model /40s were sold in the US.  EVERY one had its
> > own set of ALDs, with the serial number of the CPU on them.
> > They not only recorded the general info for the model, but
> > they had specific changes to reflect the exact configuration
> > of THAT machine.
>
> I didn't know that every machine came with a set of ALDs but you are
> right that a lot of /40's were sold stateside. My dad was re-posted
> directly from Hursley to Poughkeepsie in '65 which I was where some (or
> all?) the /40s were assembled.
> One of the IBM Journals (75 years?) has a large colour photo of a row
> of 40s on the final assembly floor at Poughkeepsie, everyone in it
> striking that characteristic 60s/70s IBM-photo-pose, eg. someone leaning
> over a table, another reaching for a console knob, one changing a tape and
> at least two people earnestly discussing a printout.

Most weren't sold, but leased. The ALDs would be used by the IBM CE, not
the customers themselves. I don't know if machines that were sold rather
than leased came with ALDs or if IBM kept these, I suspect the latter to be
the case.

Re: IBM 360/30 in verilog

[Curious Marc]

What's a POP? As long as it emulates all the registers connected to light and 
switches that might do for me, but I was assuming these would very specific to 
the CPU detailed innards.
Marc

> On Jul 12, 2016, at 5:14 PM, Dave Wade  wrote:
> 
> It actually might be easier to produce a generic S/360 clone in FPGA using
> the POP rather than individual ALU's.
> Having built a very simple CPU (in VHDL not Verilog) and planning to start
> on a more complex (Ferranti Pegasus)
> Of course it wouldn't be cycle accurate, but perhaps that wouldn't be
> important.

RE: IBM 360/30 in verilog

[Dave Wade]

> -Original Message-
> From: cctalk [mailto:cctalk-boun...@classiccmp.org] On Behalf Of Curious
> Marc
> Sent: 12 July 2016 08:58
> To: General Discussion: On-Topic and Off-Topic Posts
> <cctalk@classiccmp.org>
> Subject: Re: IBM 360/30 in verilog
> 
> Darn. My hopes are shattered. Lots of Verilog in my future, that is if we
can
> find 360/50 ALDs...
> Marc
> 

It actually might be easier to produce a generic S/360 clone in FPGA using
the POP rather than individual ALU's.
Having built a very simple CPU (in VHDL not Verilog) and planning to start
on a more complex (Ferranti Pegasus)
Of course it wouldn't be cycle accurate, but perhaps that wouldn't be
important.

> > On Jul 12, 2016, at 11:31 AM, Jon Elson <el...@pico-systems.com> wrote:
> >
> >> On 07/11/2016 07:35 PM, Curious Marc wrote:
> >> Thanks for the detailed answer. I see the front panels look remarkably
> similar though. Short of redoing a 360/50 on an FPGA (I'd need to retire
to
> have enough time for this one!), could I use the /50 panel with the /65
> emulator?
> > Not really!  The 360/50 had 4 "rollers" for 4 rows of lights, and one
row of
> data switches, and 2 rows of dedicated lights.
> >
> > The 360/65 had 6 rollers with 6 rows of lights, plus TWO rows of data
> switches, and pretty much no dedicated lights other than associated with
the
> rollers.
> >
> > Both had a row of address switches under the data switches.
> >
> > So, yes, in GENERAL, they had a similar look and layout, but in detail,
there
> was a lot different, some of it specifically related to the memory word
width.
> >
> > The only machine that looked really different was the 360/30, that had a
> panel more reminiscent of the 1401.
> > And, of course, the 360/85, which was really a prototype of the 370/165.
> As far as software was concerned, it was just a really fast 360, but the
> hardware was MUCH more advanced.
> >
> > Jon

Re: IBM 360/30 in verilog

[Curious Marc]

Darn. My hopes are shattered. Lots of Verilog in my future, that is if we can 
find 360/50 ALDs...
Marc

> On Jul 12, 2016, at 11:31 AM, Jon Elson  wrote:
> 
>> On 07/11/2016 07:35 PM, Curious Marc wrote:
>> Thanks for the detailed answer. I see the front panels look remarkably 
>> similar though. Short of redoing a 360/50 on an FPGA (I'd need to retire to 
>> have enough time for this one!), could I use the /50 panel with the /65 
>> emulator?
> Not really!  The 360/50 had 4 "rollers" for 4 rows of lights, and one row of 
> data switches, and 2 rows of dedicated lights.
> 
> The 360/65 had 6 rollers with 6 rows of lights, plus TWO rows of data 
> switches, and pretty much no dedicated lights other than associated with the 
> rollers.
> 
> Both had a row of address switches under the data switches.
> 
> So, yes, in GENERAL, they had a similar look and layout, but in detail, there 
> was a lot different, some of it specifically related to the memory word width.
> 
> The only machine that looked really different was the 360/30, that had a 
> panel more reminiscent of the 1401.
> And, of course, the 360/85, which was really a prototype of the 370/165.  As 
> far as software was concerned, it was just a really fast 360, but the 
> hardware was MUCH more advanced.
> 
> Jon

Re: IBM 360/30 in verilog

[steven]

Jon said:
> LOTS of model /40s were sold in the US.  EVERY one had its
> own set of ALDs, with the serial number of the CPU on them.
> They not only recorded the general info for the model, but
> they had specific changes to reflect the exact configuration
> of THAT machine.

I didn't know that every machine came with a set of ALDs but you are
right that a lot of /40's were sold stateside. My dad was re-posted
directly from Hursley to Poughkeepsie in '65 which I was where some (or
all?) the /40s were assembled.
One of the IBM Journals (75 years?) has a large colour photo of a row
of 40s on the final assembly floor at Poughkeepsie, everyone in it
striking that characteristic 60s/70s IBM-photo-pose, eg. someone leaning
over a table, another reaching for a console knob, one changing a tape and
at least two people earnestly discussing a printout.

Steve.

Re: IBM 360/30 in verilog

[Jon Elson]

On 07/11/2016 07:35 PM, Curious Marc wrote:

Thanks for the detailed answer. I see the front panels look remarkably similar 
though. Short of redoing a 360/50 on an FPGA (I'd need to retire to have enough 
time for this one!), could I use the /50 panel with the /65 emulator?

Not really!  The 360/50 had 4 "rollers" for 4 rows of 
lights, and one row of data switches, and 2 rows of 
dedicated lights.


The 360/65 had 6 rollers with 6 rows of lights, plus TWO 
rows of data switches, and pretty much no dedicated lights 
other than associated with the rollers.


Both had a row of address switches under the data switches.

So, yes, in GENERAL, they had a similar look and layout, but 
in detail, there was a lot different, some of it 
specifically related to the memory word width.


The only machine that looked really different was the 
360/30, that had a panel more reminiscent of the 1401.
And, of course, the 360/85, which was really a prototype of 
the 370/165.  As far as software was concerned, it was just 
a really fast 360, but the hardware was MUCH more advanced.


Jon

Re: IBM 360/30 in verilog

[Jon Elson]

On 07/11/2016 05:36 PM, ste...@malikoff.com wrote:


Indeed they must be. I've been looking for /40 ALDs for some time but haven't 
struck any. I wonder if they're
scarce becase the 40 was a AFAIK a british-developed 360. My dad was posted to 
Hursley to learn the /40 in 64-65.
LOTS of model /40s were sold in the US.  EVERY one had its 
own set of ALDs, with the serial number of the CPU on them.  
They not only recorded the general info for the model, but 
they had specific changes to reflect the exact configuration 
of THAT machine.


Jon

Re: IBM 360/30 in verilog

[steven]

Mike said:
> On Tue, Jul 12, 2016 at 10:36 AM,   wrote:
>> Al said:
>>> On 7/11/16 9:14 AM, Jon Elson wrote:
 The microcode was in the ALD drawings, and might even be in bitsavers 
 archive, if they have the right manual.
>>>
>>> 360 CPU ALDs are extremely difficult to find.
>>> If the 65 set could be scanned, I'd be happy to upload them to bitsavers.
>>
>> Indeed they must be. I've been looking for /40 ALDs for some time but 
>> haven't struck any. I wonder if they're
>> scarce becase the 40 was a AFAIK a british-developed 360. My dad was posted 
>> to Hursley to learn the /40 in 64-65.
>>
>> The only Model 40 docs I have left are less than a dozen pages of 'IBM 
>> SYSTEM/360 MODEL 40 DEVELOPMENT MANUAL'
>> from March 1965 from 'IBM BRITISH LABORATORIES'.
>> Why do I have these? Dad used to bring home Model 40 binders in the late 60s 
>> so my brother and I had a good
>> supply of paper to scribble and paint on as kids. All the pages I have left 
>> have drawings on the blank side
>> and that was why my parents kept them :)
>>
>> Steve.
>
> I have some 360 ALDs - and I think they may include 40. About to go on
> holiday with kids; ping me from time to time and I'll check!

That would be great thanks Mike. In the meantime if anyone's interested I can 
scan those few 'ModForty' (as my Dad
always used to refer to it as) pages. The original side, not the drawn-on side..

Steve

Re: IBM 360/30 in verilog

[Mike Ross]

On Tue, Jul 12, 2016 at 10:36 AM,   wrote:
> Al said:
>> On 7/11/16 9:14 AM, Jon Elson wrote:
>>> The microcode was in the ALD drawings, and might even be in bitsavers 
>>> archive, if they have the right manual.
>>
>> 360 CPU ALDs are extremely difficult to find.
>> If the 65 set could be scanned, I'd be happy to upload them to bitsavers.
>
> Indeed they must be. I've been looking for /40 ALDs for some time but haven't 
> struck any. I wonder if they're
> scarce becase the 40 was a AFAIK a british-developed 360. My dad was posted 
> to Hursley to learn the /40 in 64-65.
>
> The only Model 40 docs I have left are less than a dozen pages of 'IBM 
> SYSTEM/360 MODEL 40 DEVELOPMENT MANUAL'
> from March 1965 from 'IBM BRITISH LABORATORIES'.
> Why do I have these? Dad used to bring home Model 40 binders in the late 60s 
> so my brother and I had a good
> supply of paper to scribble and paint on as kids. All the pages I have left 
> have drawings on the blank side
> and that was why my parents kept them :)
>
> Steve.

I have some 360 ALDs - and I think they may include 40. About to go on
holiday with kids; ping me from time to time and I'll check!

Mike

http://www.corestore.org
'No greater love hath a man than he lay down his life for his brother.
Not for millions, not for glory, not for fame.
For one person, in the dark, where no one will ever know or see.'

Re: IBM 360/30 in verilog

[Curious Marc]

Thanks for the detailed answer. I see the front panels look remarkably similar 
though. Short of redoing a 360/50 on an FPGA (I'd need to retire to have enough 
time for this one!), could I use the /50 panel with the /65 emulator?
Marc

> On Jul 12, 2016, at 1:11 AM, Jon Elson  wrote:
> 
>> On 07/11/2016 06:40 AM, Curious Marc wrote:
>> No kidding! That's a massive effort. How close is that to a 360/50? I have a 
>> front panel that needs a brain, could sure use that!
> 360/50 is a 32-bit machine, the real thing has a core memory "local store" 
> and (3, IIRC) built-in channels.  it does not allow memory interleaving.
> 
> The 360/65 has a 64-bit path to memory, and does permit interleaving.  it 
> also allows two /65s to be put together in a multiprocessor system.  There 
> are a few additional instructions to communicate between CPUs.  The 65 has 
> solid state local store, and a 56-bit ALU, so it can do double-precision 
> floating-point arithmetic without having to double up the cycles, as the /50 
> does.  The /65 has no built-in channels.
> 
> Jon

Re: IBM 360/30 in verilog

[Curious Marc]

I haven't looked yet, but are the 360/50 ALDs available anywhere?
Marc


> On Jul 12, 2016, at 2:00 AM, Al Kossow  wrote:
> 
> 
> 
>> On 7/11/16 9:14 AM, Jon Elson wrote:
>> 
>> The microcode was in the ALD drawings, and might even be in bitsavers 
>> archive, if they have the right manual.
> 
> 360 CPU ALDs are extremely difficult to find.
> If the 65 set could be scanned, I'd be happy to upload them to bitsavers.
> 
> 
> 

Re: IBM 360/30 in verilog

[steven]

Al said:
> On 7/11/16 9:14 AM, Jon Elson wrote:
>> The microcode was in the ALD drawings, and might even be in bitsavers 
>> archive, if they have the right manual.
>
> 360 CPU ALDs are extremely difficult to find.
> If the 65 set could be scanned, I'd be happy to upload them to bitsavers.

Indeed they must be. I've been looking for /40 ALDs for some time but haven't 
struck any. I wonder if they're
scarce becase the 40 was a AFAIK a british-developed 360. My dad was posted to 
Hursley to learn the /40 in 64-65.

The only Model 40 docs I have left are less than a dozen pages of 'IBM 
SYSTEM/360 MODEL 40 DEVELOPMENT MANUAL'
from March 1965 from 'IBM BRITISH LABORATORIES'.
Why do I have these? Dad used to bring home Model 40 binders in the late 60s so 
my brother and I had a good
supply of paper to scribble and paint on as kids. All the pages I have left 
have drawings on the blank side
and that was why my parents kept them :)

Steve.

RE: IBM 360/30 in verilog

[Jay West]

That should be "very soon", as that was part of the reason for the server 
maintenance last week to lay some groundwork. Stay tuned

Re: IBM 360/30 in verilog

[Al Kossow]

On 7/11/16 10:46 AM, Camiel Vanderhoeven wrote:
> Hi Al,
> 
> I have a 7201-2 set that I scanned. They're ~64 MB TIF files per sheet,
> about ~150GB in total.

I'll have to wait until Jay increases the amount of disk space available to 
bitsavers.

Re: IBM 360/30 in verilog (was: How do they make Verilog code for unknown ICs?)

[Camiel Vanderhoeven]

> > And I'm very close to having a 360/65 in VHDL.
>
> Was the microcode derived from the engineering drawings?

Yes, from hand-corrected OCR scans.

To be precise, the ALDs and microcode I'm using are not for a plain 2065,
but for a 7201-02, the variant that was used in the 9020 complex. I'm
making modifications that I hope make it work like a 2065 again.

> From memory, the 65 is the bigger brother to the 50 with a wider memory
bus.

And a bigger ALU, so the microcode for floating point operations is very
different I believe.

Camiel

RE: IBM 360/30 in verilog (was: How do they make Verilog code for unknown ICs?)

[Camiel Vanderhoeven]

> And I'm very close to having a 360/65 in VHDL.
> -
>
> Sweet :->.  What FPGA platform are you using?  Lawrence used a Spartan
3.  Don't know how close to "full" he pushed it.

I'm using the XUPV5 PCIE board (Xilinx Virtex-5 XC5VLX110T); currently
about 60% occupied, but the design needs lots of debugging. I'm only
implementing the CPU on the FPGA, transcribing from the IBM ALDs. I/O
channels will be provided by the Hercules emulator (with its cpu ripped
out) on the system the PCIe card is plugged into.

Re: IBM 360/30 in verilog

[Jon Elson]

On 07/11/2016 06:40 AM, Curious Marc wrote:

No kidding! That's a massive effort. How close is that to a 360/50? I have a 
front panel that needs a brain, could sure use that!

360/50 is a 32-bit machine, the real thing has a core memory 
"local store" and (3, IIRC) built-in channels.  it does not 
allow memory interleaving.


The 360/65 has a 64-bit path to memory, and does permit 
interleaving.  it also allows two /65s to be put together in 
a multiprocessor system.  There are a few additional 
instructions to communicate between CPUs.  The 65 has solid 
state local store, and a 56-bit ALU, so it can do 
double-precision floating-point arithmetic without having to 
double up the cycles, as the /50 does.  The /65 has no 
built-in channels.


Jon

Re: IBM 360/30 in verilog (was: How do they make Verilog code for unknown ICs?)

[Al Kossow]

On 7/11/16 1:31 AM, Camiel Vanderhoeven wrote:
> And I'm very close to having a 360/65 in VHDL.
> Op 11 jul. 2016 2:44 a.m. schreef "Curious Marc" :
> 

Was the microcode derived from the engineering drawings?

>From memory, the 65 is the bigger brother to the 50 with a wider memory bus.
It was also the base machine for their first machine with paging, the model 67.

Re: IBM 360/30 in verilog (was: How do they make Verilog code for unknown ICs?)

[Curious Marc]

No kidding! That's a massive effort. How close is that to a 360/50? I have a 
front panel that needs a brain, could sure use that!
Marc

Sent from my iPhone

> On Jul 11, 2016, at 5:31 PM, Camiel Vanderhoeven <iamcam...@gmail.com> wrote:
> 
> And I'm very close to having a 360/65 in VHDL.
> Op 11 jul. 2016 2:44 a.m. schreef "Curious Marc" <curiousma...@gmail.com>:
> 
>> And Carl Claunch has an IBM 1130 in VHDL.
>> Marc
>> 
>> Sent from my iPad
>> 
>>>> On Jul 10, 2016, at 10:23 PM, Lawrence Wilkinson <ljw-cct...@ljw.me.uk>
>>> wrote:
>>> 
>>> That'll be me, I guess, It's in VHDL. URL in sig.
>>> 
>>>> On 10/07/16 15:21, Paul Birkel wrote:
>>>> -Original Message-
>>>> From: cctalk [mailto:cctalk-boun...@classiccmp.org] On Behalf Of Guy
>> Sotomayor Jr
>>>> Sent: Monday, June 20, 2016 4:04 PM
>>>> To: General Discussion: On-Topic and Off-Topic Posts
>>>> Subject: Re: How do they make Verilog code for unknown ICs?
>>>> 
>>>> What you can do (and I’ve seen it done) is define verilog modules that
>> provide the functions of the IC and use that in their designs.  I’ve seen
>> at least two interesting classic computer recreations using this approach
>> (re-implemenation of the CADR lisp machine in verilog and an IBM 360/30 in
>> verilog).
>>>> 
>>>> ROMs are easy (just instantiate a lookup table).  PLCs are just
>> combinatorial equations which are relatively easy with the verilog “assign”
>> statement.
>>>> 
>>>> TTFN - Guy
>>>> 
>>>> 
>>>> 
>>>> Do you have a pointer to that "IBM 360/30 in Verilog", Guy?
>>>> 
>>>> -
>>>> paul
>>> 
>>> --
>>> Lawrence Wilkinson  lawrence at ljw.me.uk
>>> The IBM 360/30 page   http://www.ljw.me.uk/ibm360
>> 

RE: IBM 360/30 in verilog (was: How do they make Verilog code for unknown ICs?)

[Paul Birkel]

-Original Message-
From: cctalk [mailto:cctalk-boun...@classiccmp.org] On Behalf Of Camiel 
Vanderhoeven
Sent: Monday, July 11, 2016 4:31 AM
To: General Discussion: On-Topic and Off-Topic Posts
Subject: Re: IBM 360/30 in verilog (was: How do they make Verilog code for 
unknown ICs?)

And I'm very close to having a 360/65 in VHDL.
-

Sweet :->.  What FPGA platform are you using?  Lawrence used a Spartan 3.  
Don't know how close to "full" he pushed it.

paul

Re: IBM 360/30 in verilog (was: How do they make Verilog code for unknown ICs?)

[Camiel Vanderhoeven]

And I'm very close to having a 360/65 in VHDL.
Op 11 jul. 2016 2:44 a.m. schreef "Curious Marc" <curiousma...@gmail.com>:

> And Carl Claunch has an IBM 1130 in VHDL.
> Marc
>
> Sent from my iPad
>
> > On Jul 10, 2016, at 10:23 PM, Lawrence Wilkinson <ljw-cct...@ljw.me.uk>
> wrote:
> >
> > That'll be me, I guess, It's in VHDL. URL in sig.
> >
> >> On 10/07/16 15:21, Paul Birkel wrote:
> >> -Original Message-
> >> From: cctalk [mailto:cctalk-boun...@classiccmp.org] On Behalf Of Guy
> Sotomayor Jr
> >> Sent: Monday, June 20, 2016 4:04 PM
> >> To: General Discussion: On-Topic and Off-Topic Posts
> >> Subject: Re: How do they make Verilog code for unknown ICs?
> >>
> >> What you can do (and I’ve seen it done) is define verilog modules that
> provide the functions of the IC and use that in their designs.  I’ve seen
> at least two interesting classic computer recreations using this approach
> (re-implemenation of the CADR lisp machine in verilog and an IBM 360/30 in
> verilog).
> >>
> >> ROMs are easy (just instantiate a lookup table).  PLCs are just
> combinatorial equations which are relatively easy with the verilog “assign”
> statement.
> >>
> >> TTFN - Guy
> >>
> >> 
> >>
> >> Do you have a pointer to that "IBM 360/30 in Verilog", Guy?
> >>
> >> -
> >> paul
> >
> > --
> > Lawrence Wilkinson  lawrence at ljw.me.uk
> > The IBM 360/30 page   http://www.ljw.me.uk/ibm360
> >
> >
>

Re: IBM 360/30 in verilog (was: How do they make Verilog code for unknown ICs?)

[Curious Marc]

And Carl Claunch has an IBM 1130 in VHDL.
Marc

Sent from my iPad

> On Jul 10, 2016, at 10:23 PM, Lawrence Wilkinson <ljw-cct...@ljw.me.uk> wrote:
> 
> That'll be me, I guess, It's in VHDL. URL in sig.
> 
>> On 10/07/16 15:21, Paul Birkel wrote:
>> -Original Message-
>> From: cctalk [mailto:cctalk-boun...@classiccmp.org] On Behalf Of Guy 
>> Sotomayor Jr
>> Sent: Monday, June 20, 2016 4:04 PM
>> To: General Discussion: On-Topic and Off-Topic Posts
>> Subject: Re: How do they make Verilog code for unknown ICs?
>> 
>> What you can do (and I’ve seen it done) is define verilog modules that 
>> provide the functions of the IC and use that in their designs.  I’ve seen at 
>> least two interesting classic computer recreations using this approach 
>> (re-implemenation of the CADR lisp machine in verilog and an IBM 360/30 in 
>> verilog).
>> 
>> ROMs are easy (just instantiate a lookup table).  PLCs are just 
>> combinatorial equations which are relatively easy with the verilog “assign” 
>> statement.
>> 
>> TTFN - Guy
>> 
>> 
>> 
>> Do you have a pointer to that "IBM 360/30 in Verilog", Guy?
>> 
>> -
>> paul
> 
> -- 
> Lawrence Wilkinson  lawrence at ljw.me.uk
> The IBM 360/30 page   http://www.ljw.me.uk/ibm360
> 
> 

Re: IBM 360/30 in verilog (was: How do they make Verilog code for unknown ICs?)

[Lawrence Wilkinson]

That'll be me, I guess, It's in VHDL. URL in sig.

On 10/07/16 15:21, Paul Birkel wrote:

-Original Message-
From: cctalk [mailto:cctalk-boun...@classiccmp.org] On Behalf Of Guy Sotomayor 
Jr
Sent: Monday, June 20, 2016 4:04 PM
To: General Discussion: On-Topic and Off-Topic Posts
Subject: Re: How do they make Verilog code for unknown ICs?

What you can do (and I’ve seen it done) is define verilog modules that provide 
the functions of the IC and use that in their designs.  I’ve seen at least two 
interesting classic computer recreations using this approach (re-implemenation 
of the CADR lisp machine in verilog and an IBM 360/30 in verilog).

ROMs are easy (just instantiate a lookup table).  PLCs are just combinatorial 
equations which are relatively easy with the verilog “assign” statement.

TTFN - Guy



Do you have a pointer to that "IBM 360/30 in Verilog", Guy?

-
paul



--
Lawrence Wilkinson  lawrence at ljw.me.uk
The IBM 360/30 page   http://www.ljw.me.uk/ibm360

IBM 360/30 in verilog (was: How do they make Verilog code for unknown ICs?)

[Paul Birkel]

-Original Message-
From: cctalk [mailto:cctalk-boun...@classiccmp.org] On Behalf Of Guy Sotomayor 
Jr
Sent: Monday, June 20, 2016 4:04 PM
To: General Discussion: On-Topic and Off-Topic Posts
Subject: Re: How do they make Verilog code for unknown ICs?

What you can do (and I’ve seen it done) is define verilog modules that provide 
the functions of the IC and use that in their designs.  I’ve seen at least two 
interesting classic computer recreations using this approach (re-implemenation 
of the CADR lisp machine in verilog and an IBM 360/30 in verilog).

ROMs are easy (just instantiate a lookup table).  PLCs are just combinatorial 
equations which are relatively easy with the verilog “assign” statement.

TTFN - Guy



Do you have a pointer to that "IBM 360/30 in Verilog", Guy?

-
paul