Re: Strange third party board in PDP-11/45
> > So, my guess was wrong there. I had _assumed_ that when doing a memory > operation, the CPU started a cycle on both busses, to minimize the delay on > the UNIBUS cycle if the MS11 on the FastBus didn't have that location. (I > had > previously checked, and there is an 'I have that location' signal which the > MS11 sends back, making the concept of a cache possible.) > > Well, no. In the "KB11-A CPU Maintenance Manual" (DEC-11-HKBB-D), section > 7.7.1 ("Bus Control Introduction"), it says: > > If the address applies to a Fastbus device, that device will respond in > time > to inhibit the UNIBUS MSYN signal > > (It turns out the KB11-A is very clever; it has to delay for a bit after > asserting the address, etc, signals on the UNIBUS, for de-skew, before it > can > assert MSYN, and during that delay, in parallel, it checks to see if the > MS11 > has that location.) > > So my theory about what that double-card does (prevent an MSYN sent to main > memory on a cache hit) is apparently wrong. > > > Which leaves the question of what that card _does_ do... > > The cache _does_ need to have the A and B UNIBUS tied together, so that it > can > snoop UNIBUS memory cycles (which are on the A UNIBUS) via the B UNIBUS > (which > is what it has access to on the backplane), _but_ it doesn't need a special > card, with i) active logic, and b) a cable back to the main board, to do > that > - a regular M9200 will do that. > > The cable back to the main card, and the logic on the two dual-width cards, > mean it wants to interfere somehow in the connection between the A and B > UNIBUS. But if not the MSYN thing, what else could it be? I have pondered > that question, but I can't think of anything. > > It can't be doing anything with interrupts or DMA, I would think, so no > grant > interception. So what else could it be? Anyone have any ideas? > Here are some pictures of the mysterious bus intercept or whatever board: https://i.imgur.com/rZOS0qt.jpg https://i.imgur.com/6eMfCo4.jpg https://i.imgur.com/Jodpiue.jpg /Mattis > > Noel >
Re: Strange third party board in PDP-11/45
> As to what _else_ it is doing, and why it has the cable to the main > card... I think that it must intercept MSYN from the processor and only > let it pass if there's no hit in the cache. > (To explain why it would need to do that... normally with the MS11, > there's a static partitioning between FastBus memory and UNIBUS A > memory. So when the CPU goes to do a memory cycle, it can put the > address out on both the UNIBUS and FastBus, with the certainty that it > will only get a reply on one. So, my guess was wrong there. I had _assumed_ that when doing a memory operation, the CPU started a cycle on both busses, to minimize the delay on the UNIBUS cycle if the MS11 on the FastBus didn't have that location. (I had previously checked, and there is an 'I have that location' signal which the MS11 sends back, making the concept of a cache possible.) Well, no. In the "KB11-A CPU Maintenance Manual" (DEC-11-HKBB-D), section 7.7.1 ("Bus Control Introduction"), it says: If the address applies to a Fastbus device, that device will respond in time to inhibit the UNIBUS MSYN signal (It turns out the KB11-A is very clever; it has to delay for a bit after asserting the address, etc, signals on the UNIBUS, for de-skew, before it can assert MSYN, and during that delay, in parallel, it checks to see if the MS11 has that location.) So my theory about what that double-card does (prevent an MSYN sent to main memory on a cache hit) is apparently wrong. Which leaves the question of what that card _does_ do... The cache _does_ need to have the A and B UNIBUS tied together, so that it can snoop UNIBUS memory cycles (which are on the A UNIBUS) via the B UNIBUS (which is what it has access to on the backplane), _but_ it doesn't need a special card, with i) active logic, and b) a cable back to the main board, to do that - a regular M9200 will do that. The cable back to the main card, and the logic on the two dual-width cards, mean it wants to interfere somehow in the connection between the A and B UNIBUS. But if not the MSYN thing, what else could it be? I have pondered that question, but I can't think of anything. It can't be doing anything with interrupts or DMA, I would think, so no grant interception. So what else could it be? Anyone have any ideas? Noel
Re: Strange third party board in PDP-11/45
> From: Mattis Lind > I will take a picture of the boards in more detail so we can figure out > what they are doing later on. Thanks, that would be really useful. > My understanding is that slot 1AB and slot 26 AB is tied to each > other. So if there would be no expansion unibus there should be a M930 > in each of these slots. The same goes for slots 27AB and 28AB. Right, that's my understanding too. There's a diagram in the "PDP-11/45 Maintenance Reference Manual" (October, '73 edition, on pg. 60 - pg. 66 of the PDF), which gives: - slot 1 - UNIBUS A termination - slot 26 - UNIBUS A cable - slot 27 - UNIBUS B cable - slot 28 - UNIBUS B termination and my read is that the slot 26 cable is 'out to any UNIBUS memory, etc', while the slot 27 cable is 'in from the other machine in the dual-processor system'. (There's an interesting discussion in, IIRC, an RH11-AB - the dual-UNIBUS controller for the MASSBUS - tutorial manual which talks about the M9300, which is a terminator which can produce an NPG in response to an NPR; that is used when people want to attach the RH11-AB's second UNIBUS to the UNIBUS B, when there's no CPU on it. So the M9300 would go in slot 27, and the cable out to the RH11 in slot 28.) > I cannot see how a device in slot 26AB or 27AB would be able to > intercept MSYN here. Not _in_ slot 26 or 27, it's in the cable _between_ them! :-) Look at the common case, where UNIBUS A and B are connected: MSYN comes out of the CPU in slot 26, is jumpered across to slot 27 by the M9200, is carried across the backplane to slot 28, and then out (on either a BC11 or an M920). That dual-card thingy that comes with the Cache/45 would allow (if my surmise about what's going on is correct :-) the Cache/45 to place itself _between_ the MYSN out of the CPU (in slot 26) and the 'MSYN out to the rest of the system' (in slot 27). That does mean no separate UNIBUS A and B. But if my supposition as to how the Cache/45 works (that it fills itself by snooping on UNIBUS B in the MS11 controller slot) is correct, UNIBUS A and B would have to be connected together _anyway_, for that to work. (I _can_ imagine how to do it all without joining the two UNIBI together, but I will skip that for now.) Noel
Re: Strange third party board in PDP-11/45
> > The sandwiched dual boards are sitting in 27 / 26 AB. The board in > 27AB > > was empty (quick glance), while the board in 26AB has a few TTL chips > > on it. Slot 26AB is the Unibus A slot, Slot 27 AB should be a > > terminator on Unibus B. > > I'm more interested in _what_ the two boards are doing! :-) > > I will take a picture of the boards in more detail so we can figure out what they are doing later on. > It seems they must be jumpering UNIBUS A and UNIBUS B together. (Which I > didn't expect, but maybe... will have to ponder.) > > As to what _else_ it is doing, and why it has the cable to the main > card... I > think that it must intercept MSYN from the processor and only let it pass > if > there's no hit in the cache. > > (To explain why it would need to do that... normally with the MS11, > there's a > static partitioning between FastBus memory and UNIBUS A memory. So when the > CPU goes to do a memory cycle, it can put the address out on both the > UNIBUS > and FastBus, with the certainty that it will only get a reply on one. But > with > the cache, if there's a hit, it would in theory get a reply on both, which > might confuse it. Or if it takes the cache copy, and terminates the UNIBUS > cycle, that might confuse the memory.) > > Or maybe I'm confused, because now that I think about it, UNIBUS A goes > straight from the CPU to the UNIBUS A out slot, so the Able board couldn't > intercept MSYN? I guess I need to understand the fine details of the > UNIBUS A > and B stuff, maybe it will make sense at that point. > > Oh, wait a moment: slot 26 is UNIBUS A out, slot 27 is 'UNIBUS B in', and > slot > 28 is UNIBUS B 'termination'. (27 is 'in' because when the M9200 is > installed > in 26/27 to join the two UNIBI together, obviously one has to connect an > 'out' > to an 'in'... and then 28 is not 'UNIBUS B termination', it's 'UNIBUS out' > to > the rest of the system. > > OK, so that works - MSYN coming out of slot 26 is intercepted by the dual > double-card, and is only allowed to pass on cache miss. Yeah, that sounds > like > it should work. > I am not sure I follow you entirely. My understanding is that slot 1AB and slot 26 AB is tied to each other. So if there would be no expansion unibus there should be a M930 in each of these slots. The same goes for slots 27AB and 28AB. It corresponds with what I see on page 111 in http://bitsavers.informatik.uni-stuttgart.de/pdf/dec/pdp11/1145/1145_System_Engineering_Drawings_Jun74.pdf if I am not missing something. I cannot see how a device in slot 26AB or 27AB would be able to intercept MSYN here. What it could do though is to force some signals active (low). > > > The hex ABLE/ ACT board sits in slot 21 which is the memory > controller > > board for the MS11. > > One of two; the other is slot 16. > > > > From: Paul Birkel > > > I wonder whether this CACHE/45 can coexist with MS11 memory on the > > Fastbus itself > > According to that marketing thing you found, "User may optimize hit ratio > by > upper/lower limit switch settings", so one would have to configure the > Cache/45 to not cache the block that the 'other' MS11 controller thinks it > owns... otherwise both might respond to requests for addresses in that > range :-) > > Noel >
Re: Strange third party board in PDP-11/45
> From: Mattis Lind > Here is how it is connected: Thanks for that - very informative! > The sandwiched dual boards are sitting in 27 / 26 AB. The board in 27AB > was empty (quick glance), while the board in 26AB has a few TTL chips > on it. Slot 26AB is the Unibus A slot, Slot 27 AB should be a > terminator on Unibus B. I'm more interested in _what_ the two boards are doing! :-) It seems they must be jumpering UNIBUS A and UNIBUS B together. (Which I didn't expect, but maybe... will have to ponder.) As to what _else_ it is doing, and why it has the cable to the main card... I think that it must intercept MSYN from the processor and only let it pass if there's no hit in the cache. (To explain why it would need to do that... normally with the MS11, there's a static partitioning between FastBus memory and UNIBUS A memory. So when the CPU goes to do a memory cycle, it can put the address out on both the UNIBUS and FastBus, with the certainty that it will only get a reply on one. But with the cache, if there's a hit, it would in theory get a reply on both, which might confuse it. Or if it takes the cache copy, and terminates the UNIBUS cycle, that might confuse the memory.) Or maybe I'm confused, because now that I think about it, UNIBUS A goes straight from the CPU to the UNIBUS A out slot, so the Able board couldn't intercept MSYN? I guess I need to understand the fine details of the UNIBUS A and B stuff, maybe it will make sense at that point. Oh, wait a moment: slot 26 is UNIBUS A out, slot 27 is 'UNIBUS B in', and slot 28 is UNIBUS B 'termination'. (27 is 'in' because when the M9200 is installed in 26/27 to join the two UNIBI together, obviously one has to connect an 'out' to an 'in'... and then 28 is not 'UNIBUS B termination', it's 'UNIBUS out' to the rest of the system. OK, so that works - MSYN coming out of slot 26 is intercepted by the dual double-card, and is only allowed to pass on cache miss. Yeah, that sounds like it should work. > The hex ABLE/ ACT board sits in slot 21 which is the memory controller > board for the MS11. One of two; the other is slot 16. > From: Paul Birkel > I wonder whether this CACHE/45 can coexist with MS11 memory on the > Fastbus itself According to that marketing thing you found, "User may optimize hit ratio by upper/lower limit switch settings", so one would have to configure the Cache/45 to not cache the block that the 'other' MS11 controller thinks it owns... otherwise both might respond to requests for addresses in that range :-) Noel
Re: Strange third party board in PDP-11/45
At one time DEC left it up to the branches whether or not to maintain non-DEC parts. The switch would help by disabling the device while running diags and doing other maintenance. Nobody wanted to be liable if a non-DEC board had to be pulled. Paul On Mon, Jul 23, 2018 at 11:57 PM, Paul Birkel via cctalk < cctalk@classiccmp.org> wrote: > -Original Message- > From: Paul Birkel [mailto:pbir...@gmail.com] > Sent: Monday, July 23, 2018 2:36 AM > To: General Discussion: On-Topic and Off-Topic Posts > Subject: RE: Strange third party board in PDP-11/45 > > ... > > From the ABLE marketing literature: > > CACHE/ 45 (CACHE BUFFER MEMORY) INSTALLS IN: PDP-11/45, -11/50 and -11/55 > CAPACITY: 2048 byte (1 K word). > ENHANCEMENT FACTOR: Run time reductions to 50% (100% speed improvement) are > achievable. > CACHE PARITY: Automatically goes off-line in event of any data error. > RANGE SELECTION: User may optimize hit ratio by upper/lower limit switch > settings. > SPECIAL FEATURE: Cache/ 45 can be enabled via software or console switches. > > Presumably that's what Mattis has in-hand. > > - > > https://books.google.com/books?id=hYD3sny2NzEC&pg=PA23&; > lpg=PA23&dq=ABLE+Comp > uter+technology+ACT+DEC+%22CACHE/45%22&source=bl&ots= > b15iACJbMd&sig=oLMrJMn2 > qEFmxiKSMIhpLF5qYnk&hl=en&sa=X&ved=2ahUKEwjcyvzi87TcAhVOw1kKHdc5A > 8kQ6AEwAHoE > CAIQAQ#v=onepage&q=ABLE%20Computer%20technology%20ACT% > 20DEC%20%22CACHE%2F45% > 22&f=false > > Computerworld, Page 23, July 26, 1976 > > ACT Has PDP-11/45 Buffer > SANTA ANA, Calif. - Able Computer Technology (ACT) has a 2K-byte cache > buffer for use with the Digital Equipment Corp. POP-11/45. > The Cache/45 is contained on a single printed circuit board that plugs into > the > system's chassis. > Buffer control is provided over every core memory address location on the > Unibus. A switch within the memory buffer permits a choice of either > on-line > or off-line operation, the company said. > The buffer costs $7 ,000. ACT is at I 538-E Chestnut St., Santa Ana, Calif. > 92705. > > (Somewhat strange use of the expressions "on-line" and "off-line" > operation, > IMO.) > > I presume that the reason for "single printed circuit board" is that only a > single "normal" slot is occupied. > > paul > >
RE: Strange third party board in PDP-11/45
-Original Message- From: Paul Birkel [mailto:pbir...@gmail.com] Sent: Monday, July 23, 2018 2:36 AM To: General Discussion: On-Topic and Off-Topic Posts Subject: RE: Strange third party board in PDP-11/45 ... >From the ABLE marketing literature: CACHE/ 45 (CACHE BUFFER MEMORY) INSTALLS IN: PDP-11/45, -11/50 and -11/55 CAPACITY: 2048 byte (1 K word). ENHANCEMENT FACTOR: Run time reductions to 50% (100% speed improvement) are achievable. CACHE PARITY: Automatically goes off-line in event of any data error. RANGE SELECTION: User may optimize hit ratio by upper/lower limit switch settings. SPECIAL FEATURE: Cache/ 45 can be enabled via software or console switches. Presumably that's what Mattis has in-hand. - https://books.google.com/books?id=hYD3sny2NzEC&pg=PA23&lpg=PA23&dq=ABLE+Comp uter+technology+ACT+DEC+%22CACHE/45%22&source=bl&ots=b15iACJbMd&sig=oLMrJMn2 qEFmxiKSMIhpLF5qYnk&hl=en&sa=X&ved=2ahUKEwjcyvzi87TcAhVOw1kKHdc5A8kQ6AEwAHoE CAIQAQ#v=onepage&q=ABLE%20Computer%20technology%20ACT%20DEC%20%22CACHE%2F45% 22&f=false Computerworld, Page 23, July 26, 1976 ACT Has PDP-11/45 Buffer SANTA ANA, Calif. - Able Computer Technology (ACT) has a 2K-byte cache buffer for use with the Digital Equipment Corp. POP-11/45. The Cache/45 is contained on a single printed circuit board that plugs into the system's chassis. Buffer control is provided over every core memory address location on the Unibus. A switch within the memory buffer permits a choice of either on-line or off-line operation, the company said. The buffer costs $7 ,000. ACT is at I 538-E Chestnut St., Santa Ana, Calif. 92705. (Somewhat strange use of the expressions "on-line" and "off-line" operation, IMO.) I presume that the reason for "single printed circuit board" is that only a single "normal" slot is occupied. paul
Re: Strange third party board in PDP-11/45
Message: 1 Date: Sun, 22 Jul 2018 09:22:25 -0400 (EDT) From: j...@mercury.lcs.mit.edu (Noel Chiappa) To: cctalk@classiccmp.org Cc: j...@mercury.lcs.mit.edu Subject: Re: Strange third party board in PDP-11/45 Message-ID: <20180722132225.49a0b18c...@mercury.lcs.mit.edu> > From: Paul Birkel > ABLE Computer Technology. Their first product was PN 10001 ... the > A.C.T. Univerter This board is not shown in any of the Able brochures we have: http://bitsavers.trailing-edge.com/pdf/able/brochures/ However, Able info is _very_ thin on the ground, now... Noel There was a Univerter and Qniverter (sp) which were used to translate from unibus to qbus.Very useful boards and used one to translate from vax730, vms 4.3 to a qbus expansion box, so I could use an RQDX3 and RD53 as vms boot. Just set up the dipswitches and it works automagically at power on. May have docs somewhere, but not sure where... Chris
RE: Strange third party board in PDP-11/45
-Original Message- From: cctalk [mailto:cctalk-boun...@classiccmp.org] On Behalf Of Mattis Lind via cctalk Sent: Monday, July 23, 2018 2:36 AM To: Noel Chiappa; General Discussion: On-Topic and Off-Topic Posts Subject: Re: Strange third party board in PDP-11/45 Here is how it is connected: https://i.imgur.com/4TEZoiO.jpg The sandwiched dual boards are i sitting in 27 / 26 AB. The board in 27AB was empty (quick glance), while the board in 26AB has a few TTL chips on it. Slot 26AB is the Unibus A slot, Slot 27 AB should be a terminator on Unibus B. (maybe there were terminating resistors on the second board. Didn't check in detail) Slot 28AB is Unibus B and goes to the DD11-C and the RK11-D backplanes. The hex ABLE/ ACT board sits in slot 21 which is the memory controller board for the MS11. It very much looks like it is a Cache board. But why have some one written "Not used" (Används ej) on it? I'll hope I find the documentation for it! /Mattis - I wonder whether this CACHE/45 can coexist with MS11 memory on the Fastbus itself, or is designed to _replace_ MS11 memory by accelerating access to Unibus-based memory? The available product literature doesn't clarify either way. paul
Re: Strange third party board in PDP-11/45
> > > Studying the MS11 Maint Manual, the MS11 controller has access to the full > address and data from both the CPU (FastBus) and UNIBUS B. (The FastBus > actually has two uni-directional data busses; in and out.) So all that > info, > this hypothetical cache board can get from the slot it is plugged into > (assuming the cache is plugged into one of the controller slots), over its > connector pins. > > The connectors on the back of the card, and two small boards, must be for > listening to UNIBUS A (in configurations in which the two UNIBI aren't > joined > together)? (I'm too lazy to check the slot numbers are see what they > actually > are.) > > And there is indeed a signal which the MS11 uses to tell the CPU it has the > location the CPU is asking for, so it's theoretically possible to build a > cache > card that plugs into a FastBus slot. > Here is how it is connected: https://i.imgur.com/4TEZoiO.jpg The sandwiched dual boards are i sitting in 27 / 26 AB. The board in 27AB was empty (quick glance), while the board in 26AB has a few TTL chips on it. Slot 26AB is the Unibus A slot, Slot 27 AB should be a terminator on Unibus B. (maybe there were terminating resistors on the second board. Didn't check in detail) Slot 28AB is Unibus B and goes to the DD11-C and the RK11-D backplanes. The hex ABLE/ ACT board sits in slot 21 which is the memory controller board for the MS11. It very much looks like it is a Cache board. But why have some one written "Not used" (Används ej) on it? I'll hope I find the documentation for it! /Mattis > > Noel > >
RE: Strange third party board in PDP-11/45
-Original Message- From: cctalk [mailto:cctalk-boun...@classiccmp.org] On Behalf Of Noel Chiappa via cctalk Sent: Sunday, July 22, 2018 2:07 PM To: cctalk@classiccmp.org Cc: j...@mercury.lcs.mit.edu Subject: Re: Strange third party board in PDP-11/45 - MS11-B Engineering Drawings About all we're missing are the MS11-A/C data board engineering drawings. (The control board is in the MS11-B prints.) - Note that the schematics clearly show that the memory controller has direct access to both the Fastbus and Unibus B, and thus slot 21 (and 16) is wired for the purpose. So why have OTT cables to both slots 26 /27 AB? Perhaps the narrow cable goes to slot 27 to pick up some additional Unibus B signals, and the wider cable to slot 26 to pick up a larger set of Unibus A signals equivalent to those to which it already has direct access for Unibus B).. Is this the way that those OTT cables are wired Mattis? >From the ABLE marketing literature: CACHE/ 45 (CACHE BUFFER MEMORY) INSTALLS IN: PDP-11/45, -11/50 and -11/55 CAPACITY: 2048 byte (1 K word). ENHANCEMENT FACTOR: Run time reductions to 50% (100% speed improvement) are achievable. CACHE PARITY: Automatically goes off-line in event of any data error. RANGE SELECTION: User may optimize hit ratio by upper/lower limit switch settings. SPECIAL FEATURE: Cache/ 45 can be enabled via software or console switches. Presumably that's what Mattis has in-hand. -
Re: Strange third party board in PDP-11/45
> We're actually pretty well off, there; we have: > - MS11 Maintenance Manual (DEC-11-HMSAA-D-D) > - MS11 MOS Memory Troubleshooting Guide (DEC-11-HMSTS-A-D) > - MS11-B Engineering Drawings There's also a little bit about the MS11-C (not covered in the documents above) in EK-11045-MM-007. There is a later rev of the MS11 manuals, which does cover the MS11-C; Chuck McManis had both of them: EK-MS11A-MM-006 MS11-A,B,C memory systems maintenance manual EK-MS11A-OP-001 MS11-A,B,C memory systems users's manual but when I contacted him about them a while back, he wasn't sure if he still had them, or if he'd given them to Al K to scan and put up (he was on the road at the time, so couldn't check if he still had them). Al, are they in your queue somewhere? (No rush to do them, if so; I just want to make sure we know where they are.) > If the board is a cache, how does it get filled? It would have to listen > to the UNIBUS the memory is on. ... Note that there has to be a signal > from FastBus ... which tells the CPU if the MS11 has a given address or > not ... so the cache board could use that line to tell the CPU whether > or not the location in question is in the cache. Studying the MS11 Maint Manual, the MS11 controller has access to the full address and data from both the CPU (FastBus) and UNIBUS B. (The FastBus actually has two uni-directional data busses; in and out.) So all that info, this hypothetical cache board can get from the slot it is plugged into (assuming the cache is plugged into one of the controller slots), over its connector pins. The connectors on the back of the card, and two small boards, must be for listening to UNIBUS A (in configurations in which the two UNIBI aren't joined together)? (I'm too lazy to check the slot numbers are see what they actually are.) And there is indeed a signal which the MS11 uses to tell the CPU it has the location the CPU is asking for, so it's theoretically possible to build a cache card that plugs into a FastBus slot. Noel
Re: Strange third party board in PDP-11/45
> From: Paul Birkel > Unfortunately there's not much documentation for the MS11. ??? We're actually pretty well off, there; we have: - MS11 Maintenance Manual (DEC-11-HMSAA-D-D) - MS11 MOS Memory Troubleshooting Guide (DEC-11-HMSTS-A-D) - MS11-B Engineering Drawings About all we're missing are the MS11-A/C data board engineering drawings. (The control board is in the MS11-B prints.) > From: Mattis Lind > This could mean that 16 bit data is in the L chips while the faster > chips are used for a 10 bit cache tag. Sounds plausible. > And of course those two I/O connectors don't belong on a cache. > ... > Those IO connectors are connected to two double height boards in 26 /27 > AB. They are also made by ACT and contain a few TTL chips. If the board is a cache, how does it get filled? It would have to listen to the UNIBUS the memory is on. So I'm guessing that's that those connectors and boards are for. Note that there has to be a signal from FastBus (anyone know the correct capitalization for that?) which tells the CPU if the MS11 has a given address or not (given the way the MS11 can be configured as to size and address), so the cache board could use that line to tell the CPU whether or not the location in question is in the cache. Noel
Re: Strange third party board in PDP-11/45
> From: Paul Birkel > ABLE Computer Technology. Their first product was PN 10001 ... the > A.C.T. Univerter This board is not shown in any of the Able brochures we have: http://bitsavers.trailing-edge.com/pdf/able/brochures/ However, Able info is _very_ thin on the ground, now... Noel
Re: Strange third party board in PDP-11/45
well, I was close. they all sound alike with brain fog. I still have a bunch of it, some marked ACT, some ABLE. On Sun, Jul 22, 2018 at 1:36 AM, Paul Birkel via cctalk < cctalk@classiccmp.org> wrote: > ACT is parked on the upper-right under the handle. > Several variants of "10003" are marked near the left handle. > And it's copyrighted 1976. > > ACT = ABLE Computer Technology. > > Their first product was PN 10001 (copyright 1976), the A.C.T. Univerter; > see "Able_Univerter_Nov81.pdf" on Bitsavers. > http://bitsavers.trailing-edge.com/pdf/able/Able_Univerter_Nov81.pdf > > -Original Message- > From: cctalk [mailto:cctalk-boun...@classiccmp.org] On Behalf Of Bob > Smith via cctalk > Sent: Saturday, July 21, 2018 4:44 PM > To: Mattis Lind; General Discussion: On-Topic and Off-Topic Posts > Subject: Re: Strange third party board in PDP-11/45 > > any identification number sn front or back? can tell from just that shot. > > > On Sat, Jul 21, 2018 at 2:37 PM, Mattis Lind via cctalk > wrote: > > This board was sitting in slot 21 of the backplane in a 11/45 > > > > https://i.imgur.com/ZYWZQCo.jpg > > > > What kind of board is this? > > > > It has 26 bipolar RAMS. Fairchild 93415 1kbit SRAM. > > > > The manufacturer might be ACT whatever that is. > > > > My guess is that it is some kind of cache board? It is connected to both > > unibuses in the machine. > > > > Better ideas? Documentation? > > > > /Mattis > >
RE: Strange third party board in PDP-11/45
ACT is parked on the upper-right under the handle. Several variants of "10003" are marked near the left handle. And it's copyrighted 1976. ACT = ABLE Computer Technology. Their first product was PN 10001 (copyright 1976), the A.C.T. Univerter; see "Able_Univerter_Nov81.pdf" on Bitsavers. http://bitsavers.trailing-edge.com/pdf/able/Able_Univerter_Nov81.pdf -Original Message- From: cctalk [mailto:cctalk-boun...@classiccmp.org] On Behalf Of Bob Smith via cctalk Sent: Saturday, July 21, 2018 4:44 PM To: Mattis Lind; General Discussion: On-Topic and Off-Topic Posts Subject: Re: Strange third party board in PDP-11/45 any identification number sn front or back? can tell from just that shot. On Sat, Jul 21, 2018 at 2:37 PM, Mattis Lind via cctalk wrote: > This board was sitting in slot 21 of the backplane in a 11/45 > > https://i.imgur.com/ZYWZQCo.jpg > > What kind of board is this? > > It has 26 bipolar RAMS. Fairchild 93415 1kbit SRAM. > > The manufacturer might be ACT whatever that is. > > My guess is that it is some kind of cache board? It is connected to both > unibuses in the machine. > > Better ideas? Documentation? > > /Mattis
Re: Strange third party board in PDP-11/45
I think it's Applied Computer Technologies, and I think they made cache and several other options. They were popular back in the day. I have a bunch of their boards here. Paul On Sat, Jul 21, 2018 at 1:37 PM, Mattis Lind via cctalk < cctalk@classiccmp.org> wrote: > This board was sitting in slot 21 of the backplane in a 11/45 > > https://i.imgur.com/ZYWZQCo.jpg > > What kind of board is this? > > It has 26 bipolar RAMS. Fairchild 93415 1kbit SRAM. > > The manufacturer might be ACT whatever that is. > > My guess is that it is some kind of cache board? It is connected to both > unibuses in the machine. > > Better ideas? Documentation? > > /Mattis >
Re: Strange third party board in PDP-11/45
any identification number sn front or back? can tell from just that shot. On Sat, Jul 21, 2018 at 2:37 PM, Mattis Lind via cctalk wrote: > This board was sitting in slot 21 of the backplane in a 11/45 > > https://i.imgur.com/ZYWZQCo.jpg > > What kind of board is this? > > It has 26 bipolar RAMS. Fairchild 93415 1kbit SRAM. > > The manufacturer might be ACT whatever that is. > > My guess is that it is some kind of cache board? It is connected to both > unibuses in the machine. > > Better ideas? Documentation? > > /Mattis