Re: (V)HDL Toolsets

[David Bridgham via cctech]

On 5/20/20 10:22 PM, Jay Jaeger via cctech wrote:
> I'd be interesting in hearing from folks what toolsets they have used
> for HDL (VHDL in particular).


I've been using Verilog rather than VHDL but I started with Quartus for
a little while then moved over to Vivado which I like a little better. 
I agree with Peter's point that I sure wish the bitstreams were open so
that a crop of open-source tools could be developed and we'd have a bit
more choice.  Along these lines, I've been wondering if I ought to take
a closer look at SymbiFlow, but I have digressed.

What I really use more often though is the Icarus Verilog simulator. 
Besides Verilog testbenches, I've been running the PDP-10 diagnostics
under Icarus.  I even wrote a PDP-10 disassembler in Verilog so it
disassembles and prints out the instructions as it executes them.

I also came across Verilator, a Verilog to C++ compiler.  It makes for
faster running simulations but so far I'm only using it for its 'lint'
function which is pretty nice.  It catches logic loops that just put
Icarus into infinite loops.

Re: Unibus disk controller with modern storage

[David Bridgham]

On 10/19/2016 06:48 PM, shad wrote:
>
> One of my retrocomputing dream is to design an Unibus universal board,
> probably based on FPGA because of precise timing requirements,
> to emulate one or more disk/tape interfaces, and possibly something more.
> The real storage could be based on SD card

You mean, perhaps, something like this?

http://pdp10.froghouse.org/qsic/html/overview.html

Noel and I started working on this project about a year ago.  I've been
away all summer, working in the wilds in Alaska, so the project stalled
for the last six months.  I'm home now and getting back into normal life
so it's time to restart.  Here's a quick status report on how far we got.

Noel wire-wrapped two prototype boards with the bus drivers and level
converters.  We have those cabled to a ZTEX FPGA module for
development.  I was working on the Verilog in the FPGA.  We got to the
point where we had all the basic QBUS bus cycles working: device
register reads and writes, bus grant, DMA reads and writes, and
interrupt cycles.  We hacked up a quick and dirty RK11 using just
internal FPGA memory for the "disk" storage and wrote some C code to
exercise all those QBUS operations.  It seems solid.  The short video of
the indicator panel on that website above is running that exerciser program.

Where we're sitting now is that the next step is to wire up an SD card
and start writing the Verilog to access it.  It's a little daunting
though not as daunting as implementing the USB protocols in the FPGA. 
I'm hoping that doing the SD card will pave the way for more complex
things like USB.

Dave