[PATCH] D109825: [AArch64]Enabling Cortex-A510 Support

2021-09-15 Thread Dave Green via Phabricator via cfe-commits 
dmgreen requested changes to this revision.
dmgreen added a comment.
This revision now requires changes to proceed.

> As I did the downstream work for this, I'm happy with it to go in in this 
> form.

This doesn't seem.. wise. Please make sure the reviews you do are at a 
sufficient quality, and it is probably best not to review patches you write 
yourself.




Comment at: llvm/include/llvm/Support/AArch64TargetParser.def:179
   AArch64::AEK_DOTPROD ))
+AARCH64_CPU_NAME("cortex-a510", ARMV8_3A, FK_CRYPTO_NEON_FP_ARMV8, false,
+ (AArch64::AEK_MTE | AArch64::AEK_SVE2 |

Why is this 8.3? The TRM 
(https://developer.arm.com/documentation/101604/0003/The-Cortex-A510--core) 
describes it as implementing the 9.0-A architecture.



Comment at: llvm/lib/Target/AArch64/AArch64.td:1055
 
+def ProcCortexA510 : SubtargetFeature<"cortex-a510", "ARMProcFamily",
+  "CortexA510", "Cortex-A510 ARM 
processors", [

This should be in some sort of order, next to the Cortex-A55. It should 
probably be called ProcA510 for consistency too.



Comment at: llvm/lib/Target/AArch64/AArch64.td:1214
 def : ProcessorModel<"neoverse-v1", CortexA57Model, [ProcNeoverseV1]>;
+def : ProcessorModel<"cortex-a510", CortexA57Model, [ProcCortexA510]>;
 def : ProcessorModel<"exynos-m3", ExynosM3Model, [ProcExynosM3]>;

Ordering. Please use the CortexA55Model. This is not an out of order core like 
the A57.



Comment at: llvm/lib/Target/AArch64/AArch64Subtarget.cpp:196
 break;
+  case CortexA510:
+PrefFunctionLogAlignment = 4;

This can be the same case block as the A53 and A55.


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[PATCH] D109825: [AArch64]Enabling Cortex-A510 Support

2021-09-15 Thread Mark Murray via Phabricator via cfe-commits 
MarkMurrayARM accepted this revision.
MarkMurrayARM added a comment.
This revision is now accepted and ready to land.

As I did the downstream work for this, I'm happy with it to go in in this form.


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[PATCH] D109234: [PGO] Change ThinLTO test for targets with loop unrolling disabled

2021-09-15 Thread Thomas Preud'homme via Phabricator via cfe-commits 
thopre added inline comments.



Comment at: clang/test/CodeGen/pgo-sample-thinlto-summary.c:3-4
+// RUN: %clang_cc1 -mllvm -debug-pass=Structure -O2 
-fno-experimental-new-pass-manager 
-fprofile-sample-use=%S/Inputs/pgo-sample-thinlto-summary.prof %s -emit-llvm 
-flto=thin -o - 2>&1 | FileCheck %s -check-prefix=THINLTO-OLDPM
+// RUN: %clang_cc1 -mllvm -debug-pass=Structure -O2 
-fexperimental-new-pass-manager -fdebug-pass-manager 
-fprofile-sample-use=%S/Inputs/pgo-sample-thinlto-summary.prof %s -emit-llvm -o 
- 2>&1 | FileCheck %s -check-prefix=SAMPLEPGO
+// RUN: %clang_cc1 -mllvm -debug-pass=Structure -O2 
-fexperimental-new-pass-manager -fdebug-pass-manager 
-fprofile-sample-use=%S/Inputs/pgo-sample-thinlto-summary.prof %s -emit-llvm 
-flto=thin -o - 2>&1 | FileCheck %s -check-prefix=THINLTO
 

While we now need to explicitely request the old pass manager, the new pass 
manager is the default so we don't need to be explicit.


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[PATCH] D109234: [PGO] Change ThinLTO test for targets with loop unrolling disabled

2021-09-15 Thread Sherwin via Phabricator via cfe-commits 
sherwin-dc added inline comments.



Comment at: clang/test/CodeGen/pgo-sample-thinlto-summary.c:27
+// THINLTO-OLDPM-NOT:   PGOIndirectCallPromotion
+// THINLTO-OLDPM:   Unroll loops
+// THINLTO-OLDPM-NOT:   Unroll loops

When printing out passes with the old PM 'Unroll loops' is printed out twice 
with sample PGO and once with thin LTO.


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[PATCH] D109752: [clang-format] Top-level unwrapped lines don't follow a left brace

2021-09-15 Thread MyDeveloperDay via Phabricator via cfe-commits 
MyDeveloperDay accepted this revision.
MyDeveloperDay added a comment.
This revision is now accepted and ready to land.

I guess this will prevent member functions in classes being treated as K 
functions right? if thats the case them this LGTM


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[PATCH] D109234: [PGO] Change ThinLTO test for targets with loop unrolling disabled

2021-09-15 Thread Sherwin via Phabricator via cfe-commits 
sherwin-dc updated this revision to Diff 372696.
sherwin-dc added a comment.

- Modify test to correctly indicate old/new PM


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Files:
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Index: clang/test/CodeGen/pgo-sample-thinlto-summary.c
===
--- clang/test/CodeGen/pgo-sample-thinlto-summary.c
+++ clang/test/CodeGen/pgo-sample-thinlto-summary.c
@@ -1,9 +1,7 @@
-// RUN: %clang_cc1 -O2 
-fprofile-sample-use=%S/Inputs/pgo-sample-thinlto-summary.prof %s -emit-llvm -o 
- 2>&1 | FileCheck %s -check-prefix=SAMPLEPGO
-// RUN: %clang_cc1 -O2 
-fprofile-sample-use=%S/Inputs/pgo-sample-thinlto-summary.prof %s -emit-llvm 
-flto=thin -o - 2>&1 | FileCheck %s -check-prefix=THINLTO
-// RUN: %clang_cc1 -O2 -fexperimental-new-pass-manager 
-fprofile-sample-use=%S/Inputs/pgo-sample-thinlto-summary.prof %s -emit-llvm -o 
- 2>&1 | FileCheck %s -check-prefix=SAMPLEPGO
-// RUN: %clang_cc1 -O2 -fexperimental-new-pass-manager 
-fprofile-sample-use=%S/Inputs/pgo-sample-thinlto-summary.prof %s -emit-llvm 
-flto=thin -o - 2>&1 | FileCheck %s -check-prefix=THINLTO
-// Checks if hot call is inlined by normal compile, but not inlined by
-// thinlto compile.
+// RUN: %clang_cc1 -mllvm -debug-pass=Structure -O2 
-fno-experimental-new-pass-manager 
-fprofile-sample-use=%S/Inputs/pgo-sample-thinlto-summary.prof %s -emit-llvm -o 
- 2>&1 | FileCheck %s -check-prefix=SAMPLEPGO-OLDPM
+// RUN: %clang_cc1 -mllvm -debug-pass=Structure -O2 
-fno-experimental-new-pass-manager 
-fprofile-sample-use=%S/Inputs/pgo-sample-thinlto-summary.prof %s -emit-llvm 
-flto=thin -o - 2>&1 | FileCheck %s -check-prefix=THINLTO-OLDPM
+// RUN: %clang_cc1 -mllvm -debug-pass=Structure -O2 
-fexperimental-new-pass-manager -fdebug-pass-manager 
-fprofile-sample-use=%S/Inputs/pgo-sample-thinlto-summary.prof %s -emit-llvm -o 
- 2>&1 | FileCheck %s -check-prefix=SAMPLEPGO
+// RUN: %clang_cc1 -mllvm -debug-pass=Structure -O2 
-fexperimental-new-pass-manager -fdebug-pass-manager 
-fprofile-sample-use=%S/Inputs/pgo-sample-thinlto-summary.prof %s -emit-llvm 
-flto=thin -o - 2>&1 | FileCheck %s -check-prefix=THINLTO
 
 int baz(int);
 int g;
@@ -13,6 +11,25 @@
 g += baz(i);
 }
 
+// Checks that loop unroll and icp are invoked by normal compile, but not 
thinlto compile.
+
+// SAMPLEPGO:   Running pass: PGOIndirectCallPromotion on [module]
+// SAMPLEPGO:   Running pass: LoopUnrollPass on bar
+
+// SAMPLEPGO-OLDPM: PGOIndirectCallPromotion
+// SAMPLEPGO-OLDPM: Unroll loops
+// SAMPLEPGO-OLDPM: Unroll loops
+
+// THINLTO-NOT: Running pass: PGOIndirectCallPromotion on [module]
+// THINLTO-NOT: Running pass: LoopUnrollPass on bar
+
+// THINLTO-OLDPM-NOT:   PGOIndirectCallPromotion
+// THINLTO-OLDPM:   Unroll loops
+// THINLTO-OLDPM-NOT:   Unroll loops
+
+
+// Checks if hot call is inlined by normal compile, but not inlined by
+// thinlto compile.
 // SAMPLEPGO-LABEL: define {{(dso_local )?}}void @bar
 // THINLTO-LABEL: define {{(dso_local )?}}void @bar
 // SAMPLEPGO-NOT: call{{.*}}foo
@@ -20,27 +37,4 @@
 void bar(int n) {
   for (int i = 0; i < n; i++)
 foo(i);
-}
-
-// Checks if loop unroll is invoked by normal compile, but not thinlto compile.
-// SAMPLEPGO-LABEL: define {{(dso_local )?}}void @unroll
-// THINLTO-LABEL: define {{(dso_local )?}}void @unroll
-// SAMPLEPGO: call{{.*}}baz
-// SAMPLEPGO: call{{.*}}baz
-// THINLTO: call{{.*}}baz
-// THINLTO-NOT: call{{.*}}baz
-void unroll() {
-  for (int i = 0; i < 2; i++)
-baz(i);
-}
-
-// Checks that icp is not invoked for ThinLTO, but invoked for normal 
samplepgo.
-// SAMPLEPGO-LABEL: define {{(dso_local )?}}void @icp
-// THINLTO-LABEL: define {{(dso_local )?}}void @icp
-// SAMPLEPGO: if.true.direct_targ
-// FIXME: the following condition needs to be reversed once
-//LTOPreLinkDefaultPipeline is customized.
-// THINLTO-NOT: if.true.direct_targ
-void icp(void (*p)()) {
-  p();
-}
+}
\ No newline at end of file


Index: clang/test/CodeGen/pgo-sample-thinlto-summary.c
===
--- clang/test/CodeGen/pgo-sample-thinlto-summary.c
+++ clang/test/CodeGen/pgo-sample-thinlto-summary.c
@@ -1,9 +1,7 @@
-// RUN: %clang_cc1 -O2 -fprofile-sample-use=%S/Inputs/pgo-sample-thinlto-summary.prof %s -emit-llvm -o - 2>&1 | FileCheck %s -check-prefix=SAMPLEPGO
-// RUN: %clang_cc1 -O2 -fprofile-sample-use=%S/Inputs/pgo-sample-thinlto-summary.prof %s -emit-llvm -flto=thin -o - 2>&1 | FileCheck %s -check-prefix=THINLTO
-// RUN: %clang_cc1 -O2 -fexperimental-new-pass-manager -fprofile-sample-use=%S/Inputs/pgo-sample-thinlto-summary.prof %s -emit-llvm -o - 2>&1 | FileCheck %s -check-prefix=SAMPLEPGO
-// RUN: %clang_cc1 -O2 -fexperimental-new-pass-manager

[PATCH] D109825: [AArch64]Enabling Cortex-A510 Support

2021-09-15 Thread Mubashar Ahmad via Phabricator via cfe-commits 
mubashar_ created this revision.
mubashar_ added a reviewer: MarkMurrayARM.
Herald added subscribers: hiraditya, kristof.beyls.
mubashar_ requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

This patch enables support for Cortex-A510 CPUs.


Repository:
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Files:
  clang/docs/ReleaseNotes.rst
  clang/test/Driver/aarch64-cpus.c
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64Subtarget.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -983,6 +983,14 @@
  AArch64::AEK_DOTPROD | AArch64::AEK_RCPC |
  AArch64::AEK_SSBS,
  "8.2-A"),
+ARMCPUTestParams("cortex-a510", "armv8.3-a", "crypto-neon-fp-armv8",
+ AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
+ AArch64::AEK_FP | AArch64::AEK_SIMD |
+ AArch64::AEK_RAS | AArch64::AEK_LSE |
+ AArch64::AEK_RDM | AArch64::AEK_RCPC |
+ AArch64::AEK_SVE2 | AArch64::AEK_SVE2BITPERM |
+ AArch64::AEK_DOTPROD | AArch64::AEK_MTE,
+ "8.3-A"),
 ARMCPUTestParams("cyclone", "armv8-a", "crypto-neon-fp-armv8",
  AArch64::AEK_NONE | AArch64::AEK_CRYPTO |
  AArch64::AEK_FP | AArch64::AEK_SIMD,
@@ -1164,7 +1172,7 @@
  AArch64::AEK_LSE | AArch64::AEK_RDM,
  "8.2-A")));
 
-static constexpr unsigned NumAArch64CPUArchs = 48;
+static constexpr unsigned NumAArch64CPUArchs = 49;
 
 TEST(TargetParserTest, testAArch64CPUArchList) {
   SmallVector List;
Index: llvm/lib/Target/AArch64/AArch64Subtarget.h
===
--- llvm/lib/Target/AArch64/AArch64Subtarget.h
+++ llvm/lib/Target/AArch64/AArch64Subtarget.h
@@ -59,6 +59,7 @@
 CortexA77,
 CortexA78,
 CortexA78C,
+CortexA510,
 CortexR82,
 CortexX1,
 ExynosM3,
Index: llvm/lib/Target/AArch64/AArch64Subtarget.cpp
===
--- llvm/lib/Target/AArch64/AArch64Subtarget.cpp
+++ llvm/lib/Target/AArch64/AArch64Subtarget.cpp
@@ -193,6 +193,9 @@
 // FIXME: remove this to enable 64-bit SLP if performance looks good.
 MinVectorRegisterBitWidth = 128;
 break;
+  case CortexA510:
+PrefFunctionLogAlignment = 4;
+break;
   }
 }
 
Index: llvm/lib/Target/AArch64/AArch64.td
===
--- llvm/lib/Target/AArch64/AArch64.td
+++ llvm/lib/Target/AArch64/AArch64.td
@@ -1052,6 +1052,26 @@
   FeatureSSBS,
   FeatureSVE]>;
 
+def ProcCortexA510 : SubtargetFeature<"cortex-a510", "ARMProcFamily",
+  "CortexA510", "Cortex-A510 ARM processors", [
+  HasV8_3aOps,
+  FeatureCrypto,
+  FeatureFPARMv8,
+  FeatureFuseAES,
+  FeatureNEON,
+  FeaturePerfMon,
+  FeaturePostRAScheduler,
+  FeatureSPE,
+  FeatureAM,
+  FeatureMPAM,
+  FeatureETE,
+  FeatureMTE,
+  FeatureSVE2,
+  FeatureSVE2BitPerm,
+  FeatureFullFP16,
+  FeatureFP16FML,
+  FeatureDotProd]>;
+
 def ProcSaphira  : SubtargetFeature<"saphira", "ARMProcFamily", "Saphira",
"Qualcomm Saphira processors", [
FeatureCrypto,
@@ -1191,6 +1211,7 @@
 def : ProcessorModel<"neoverse-n1", CortexA57Model, [ProcNeoverseN1]>;
 def : ProcessorModel<"neoverse-n2", CortexA57Model, [ProcNeoverseN2]>;
 def : ProcessorModel<"neoverse-v1", CortexA57Model, [ProcNeoverseV1]>;
+def : ProcessorModel<"cortex-a510", CortexA57Model, [ProcCortexA510]>;
 def : ProcessorModel<"exynos-m3", ExynosM3Model, [ProcExynosM3]>;
 def : ProcessorModel<"exynos-m4", ExynosM4Model, [ProcExynosM4]>;
 def : ProcessorModel<"exynos-m5", ExynosM5Model, [ProcExynosM4]>;

[PATCH] D108643: Introduce _BitInt, deprecate _ExtInt

2021-09-15 Thread Erich Keane via Phabricator via cfe-commits 
erichkeane added a comment.

> Okay. Sorry if I came down on you personally, I know what it's like to be in 
> the middle on things like this

Thank you, I very much appreciate that.

> I'm not sure if there's a way to get LLVM to treat loaded values as only 
> having N valid bits.
>
> Do you have resources on the patterns of code that you expect to see for 
> `_BitInt` types?  Like, what operations are most important here?
>
> If addition, subtraction, and comparison are the most important operations — 
> especially if we don't consider shifts or multiplication important — the best 
> ABI might actually be to keep the value left-shifted.

I don't have any such resources.  Our users treat them as 'just integers', and 
my understanding is that is the design intent we brought to WG14.  There is 
SOME experimentation to use these as 'Big Ints' as well.


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[PATCH] D105191: [Clang][OpenMP] Add support for Static Device Libraries

2021-09-15 Thread Jon Chesterfield via Phabricator via cfe-commits 
JonChesterfield added a comment.

In D105191#3001508 , @saiislam wrote:

> PS: We (mulit-company OpenMP-dev meetings) have been tracking this feature 
> for a while and we would very much like it to be picked for llvm-13.

I think llvm-13 is on -final now so I think we've missed the train for big 
feature work. That's not so bad, 14 branches in ~6 months.


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[PATCH] D105191: [Clang][OpenMP] Add support for Static Device Libraries

2021-09-15 Thread Saiyedul Islam via Phabricator via cfe-commits 
saiislam added a comment.

In D105191#3001056 , @ye-luo wrote:

> 1. modf works now.
>
> 2. if I modify the complile.sh
>
>   clang++ -fopenmp -fopenmp-targets=nvptx64 -c classA.cpp
>   rm -f libmylib.a
>   ar qc libmylib.a classA.o
>   ranlib libmylib.a
>   clang++ -fopenmp -fopenmp-targets=nvptx64 main.cpp -L. -lmylib
>   ./a.out
>
> doesn't work. I think the solution is adding sm_XX to the module name 
> regardless of user command line.
>
> 3,  directly linking static archive doesn't work.
>
>   clang++ -fopenmp -fopenmp-targets=nvptx64 main.cpp libmylib.a
>
> CMake generates this style of link line. So this really needs to work.
>
> only the following case works right now.
>
>   clang++ -fopenmp -fopenmp-targets=nvptx64 main.cpp -L. -lmylib

Thanks for confirming that modf and this patch works with -l/-L options.

The option of adding sm_XX in Bundle Entry ID when user hasn't used -march 
flag, comes under command line simplification. I have a bunch of upcoming 
patches which will significantly simplify OpenMP command line for GPU 
offloading. But, don't you think this feature is different than supporting 
static device libraries and should be dealt separately?

Our plan was always to support SDLs using -l and -L options, as described in 
Greg Rodgers's presentation about static device libraries 
 in last year's LLVM-CTH Workshop. 
It was also discussed in multi company meetings. We can explore supporting 
direct linking of SDLs as described by you, but it seems to me that it is out 
of scope of this patch. What do you think?

PS: We (mulit-company OpenMP-dev meetings) have been tracking this feature for 
a while and we would very much like it to be picked for llvm-13.


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[PATCH] D109078: [clang][driver][AIX] Add system libc++ header paths to driver

2021-09-15 Thread Zarko Todorovski via Phabricator via cfe-commits 
ZarkoCA accepted this revision.
ZarkoCA added a comment.
This revision is now accepted and ready to land.

Thanks, LGTM.


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[PATCH] D109157: [ARM] Mitigate the cve-2021-35465 security vulnurability.

2021-09-15 Thread Sam Elliott via Phabricator via cfe-commits 
lenary accepted this revision.
lenary added a comment.
This revision is now accepted and ready to land.

LGTM, but the most recent way of implementing this (using target features) was 
something I suggested to Alexandros based on @ostannard's feedback about LTO. I 
think it is cleaner, and this patch is good, but a re-review from others would 
be helpful.


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[PATCH] D104556: [InstrProfiling] Make CountersPtr in __profd_ relative

2021-09-15 Thread Philippe Antoine via Phabricator via cfe-commits 
catenacyber added a comment.

Should we still bump `INSTR_PROF_RAW_VERSION ` so that we are able to 
distinguish profraw files produced by clang13 and the ones produced by clang14 ?

Right now, both produce `LLVM raw profile data, version 7`


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[PATCH] D109157: [ARM] Mitigate the cve-2021-35465 security vulnurability.

2021-09-15 Thread Alexandros Lamprineas via Phabricator via cfe-commits 
labrinea updated this revision to Diff 372677.
labrinea added a comment.

Changes in this revision:

- added `-verify-machineinstrs` to the tests
- that yield two bugs that I had to address:

  *** Bad machine code: Explicit operand marked as def ***
  - function:func
  - basic block: %bb.0 entry (0x890b6d8)
  - instruction: $d3 = VSTRD $sp, 6, 14, $noreg
  - operand 0:   $d3



  *** Bad machine code: Explicit definition marked as use ***
  - function:non_secure_call
  - basic block: %bb.0  (0x8e0bed8)
  - instruction: t2MRS_M $r12, 20, 14, $noreg
  - operand 0:   $r12


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  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Arch/ARM.cpp
  clang/test/Driver/arm-cmse-cve-2021-35465.c
  llvm/lib/Target/ARM/ARM.td
  llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
  llvm/lib/Target/ARM/ARMSubtarget.h
  llvm/test/CodeGen/ARM/cmse-cve-2021-35465-return.ll
  llvm/test/CodeGen/ARM/cmse-cve-2021-35465.ll
  llvm/test/CodeGen/ARM/cmse-vlldm-no-reorder.mir

Index: llvm/test/CodeGen/ARM/cmse-vlldm-no-reorder.mir
===
--- llvm/test/CodeGen/ARM/cmse-vlldm-no-reorder.mir
+++ llvm/test/CodeGen/ARM/cmse-vlldm-no-reorder.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=thumbv8m.main -mcpu=cortex-m33 --float-abi=hard --run-pass=arm-pseudo %s -o - | \
+# RUN: llc -mtriple=thumbv8m.main -mcpu=cortex-m33 -mattr=-fix-cmse-cve-2021-35465 --float-abi=hard --run-pass=arm-pseudo %s -o - | \
 # RUN: FileCheck %s
 --- |
   ; ModuleID = 'cmse-vlldm-no-reorder.ll'
@@ -109,4 +109,4 @@
 # CHECK-NEXT:  $s0 = VMOVSR $r12, 14 /* CC::al */, $noreg
 # CHECK-NEXT:  $sp = tADDspi $sp, 34, 14 /* CC::al */, $noreg
 # CHECK-NEXT:  $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11
- 
\ No newline at end of file
+ 
Index: llvm/test/CodeGen/ARM/cmse-cve-2021-35465.ll
===
--- /dev/null
+++ llvm/test/CodeGen/ARM/cmse-cve-2021-35465.ll
@@ -0,0 +1,119 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+;
+; RUN: llc %s -o - -mtriple=thumbv8m.main -verify-machineinstrs \
+; RUN:   -mattr=+fp-armv8d16sp,+fix-cmse-cve-2021-35465 | \
+; RUN:   FileCheck %s --check-prefix=CHECK-8M-FP-CVE-2021-35465
+;
+; RUN: llc %s -o - -mtriple=thumbv8m.main -mcpu=cortex-m33 -verify-machineinstrs | \
+; RUN:   FileCheck %s --check-prefix=CHECK-8M-FP-CVE-2021-35465
+;
+; RUN: llc %s -o - -mtriple=thumbv8m.main -mcpu=cortex-m35p -verify-machineinstrs | \
+; RUN:   FileCheck %s --check-prefix=CHECK-8M-FP-CVE-2021-35465
+;
+; RUN: llc %s -o - -mtriple=thumbv8m.main -verify-machineinstrs \
+; RUN:   -mattr=-fpregs,+fix-cmse-cve-2021-35465 | \
+; RUN:   FileCheck %s --check-prefix=CHECK-8M-NOFP-CVE-2021-35465
+;
+; RUN: llc %s -o - -mtriple=thumbv8m.main -mcpu=cortex-m33 -mattr=-fpregs -verify-machineinstrs | \
+; RUN:   FileCheck %s --check-prefix=CHECK-8M-NOFP-CVE-2021-35465
+;
+; RUN: llc %s -o - -mtriple=thumbv8m.main -mcpu=cortex-m35p -mattr=-fpregs -verify-machineinstrs | \
+; RUN:   FileCheck %s --check-prefix=CHECK-8M-NOFP-CVE-2021-35465
+;
+; RUN: llc %s -o - -mtriple=thumbv8.1m.main -verify-machineinstrs \
+; RUN:   -mattr=+fp-armv8d16sp,+fix-cmse-cve-2021-35465 | \
+; RUN:   FileCheck %s --check-prefix=CHECK-81M-CVE-2021-35465
+;
+; RUN: llc %s -o - -mtriple=thumbv8.1m.main -mcpu=cortex-m55 -verify-machineinstrs | \
+; RUN:   FileCheck %s --check-prefix=CHECK-81M-CVE-2021-35465
+;
+; RUN: llc %s -o - -mtriple=thumbv8.1m.main -verify-machineinstrs \
+; RUN:   -mattr=-fpregs,+fix-cmse-cve-2021-35465 | \
+; RUN:   FileCheck %s --check-prefix=CHECK-81M-CVE-2021-35465
+;
+; RUN: llc %s -o - -mtriple=thumbv8.1m.main -mcpu=cortex-m55 -mattr=-fpregs -verify-machineinstrs | \
+; RUN:   FileCheck %s --check-prefix=CHECK-81M-CVE-2021-35465
+;
+
+define void @non_secure_call(void ()* %fptr) {
+; CHECK-8M-FP-CVE-2021-35465-LABEL: non_secure_call:
+; CHECK-8M-FP-CVE-2021-35465:   @ %bb.0:
+; CHECK-8M-FP-CVE-2021-35465-NEXT:push {r7, lr}
+; CHECK-8M-FP-CVE-2021-35465-NEXT:push.w {r4, r5, r6, r7, r8, r9, r10, r11}
+; CHECK-8M-FP-CVE-2021-35465-NEXT:bic r0, r0, #1
+; CHECK-8M-FP-CVE-2021-35465-NEXT:sub sp, #136
+; CHECK-8M-FP-CVE-2021-35465-NEXT:vlstm sp
+; CHECK-8M-FP-CVE-2021-35465-NEXT:mov r1, r0
+; CHECK-8M-FP-CVE-2021-35465-NEXT:mov r2, r0
+; CHECK-8M-FP-CVE-2021-35465-NEXT:mov r3, r0
+; CHECK-8M-FP-CVE-2021-35465-NEXT:mov r4, r0
+; CHECK-8M-FP-CVE-2021-35465-NEXT:mov r5, r0
+; CHECK-8M-FP-CVE-2021-35465-NEXT:mov r6, r0
+; CHECK-8M-FP-CVE-2021-35465-NEXT:mov r7, r0
+; CHECK-8M-FP-CVE-2021-35465-NEXT:mov r8, r0
+; CHECK-8M-FP-CVE-2021-35465-NEXT:mov r9, r0
+; CHECK-8M-FP-CVE-2021-35465-NEXT:mov r10, r0
+;

[PATCH] D109506: [clangd] Print current request context along with the stack trace

2021-09-15 Thread Sam McCall via Phabricator via cfe-commits 
sammccall added a comment.

This is mostly LG with nits, but I think the code-completion handler is wrong, 
and the tests as written won't build on windows.

In D109506#2992201 , @sammccall wrote:

> Oops, forgot one thing: you probably want to instrument the preamble-building 
> in TUScheduler (or in Preamble.cpp?), the background indexing, and code 
> completion.
> Those all run the clang parser and should be a rich source of clang bugs.

You've added code completion (i.e. runWithPreamble), but not preamble-building 
or background-indexing.
This is fine, we can add the others later - just wanted to make sure we're on 
the same page.

In D109506#398 , @0x1eaf wrote:

> I've tried making an integration test in addition to the unit test, but I 
> couldn't find a way to make lit ignore the crashed process exit status:
> : 'RUN: at line 2';   yes '[' | head -n 5 | sh -c "clangd 
> --input-style=delimited 2>&1 || true"
> Exit Code: 141

I think this is related to the fact that tests run with `set -o pipefail`, and 
`yes` fails when `head` closes the pipe.
`not yes` doesn't seem to help because SIGPIPE is actually caught by the shell 
rather than `yes`, thus the 141 code. (Hey, signals again!)
This seems to work: `(yes '[' || :) | head -n 5 | clangd 
--input-style=delimited`

(It is in principle possbile to disable pipefail in lit tests but awkward on a 
per-test level and nobody does it.)




Comment at: clang-tools-extra/clangd/TUScheduler.cpp:556
 
+  /// For calling from ThreadCrashReporter callback.
+  void dumpCurrentRequest(llvm::raw_ostream ) const;

Probably worth commenting "May only call from worker thread" or so.

(Unfortunately we have unusual concurrency constraints on the members - some 
such as FileInputs are locked when written on the worker thread, locked when 
read from other threads, unlocked when read from the worker thread, and never 
written from other threads. Because it's confusing it's probably worth being 
explicit).



Comment at: clang-tools-extra/clangd/TUScheduler.cpp:1382
+void ASTWorker::dumpCurrentRequest(llvm::raw_ostream ) const {
+  auto  = CurrentRequest ? CurrentRequest->Name : "";
+  OS << "Signalled during AST action: " << ActionName << "\n";

nit: I'd prefer an explicit type over `auto&` here. Probably StringRef?

(I'm not actually sure what type we're getting and whether the reference is 
dangling).



Comment at: clang-tools-extra/clangd/TUScheduler.cpp:1639
+ThreadCrashReporter ScopedReporter(
+[]() { Worker->dumpCurrentRequest(llvm::errs()); });
 std::shared_ptr Preamble;

This doesn't seem right.
This code runs on the PreambleThreads threadpool, not on the worker thread. So 
a) the state of the worker thread isn't really relevant and b) we're accessing 
it in a non-threadsafe way.

Instead we need to dump Name, Command, Contents etc separately again.
Maybe dumpCurrentRequest should be a free helper function that takes the 
individual parameters instead.



Comment at: clang-tools-extra/clangd/support/ThreadCrashReporter.cpp:28
+
+  // Traverse to the top of the reporter stack.
+  ThreadCrashReporter *Reporter = CurrentReporter;

I'm not sure the FIFO behavior is much (or at all) better than LIFO[1], and it 
seems like it adds a bit of complexity (we'd only need the  `Next` pointer, and 
there'd be less confusion direction of next vs previous).

[1] (insert joke about python having tracebacks instead of backtraces, because 
they're backwards...)



Comment at: clang-tools-extra/clangd/support/ThreadCrashReporter.h:23
+
+  /// Copies the std::function and sets the copy as current thread-local
+  /// callback. Asserts if the current thread's callback is already set.

Some mention of constraints on the passed function?

e.g. "The callback is likely to be invoked in a signal handler. Most LLVM 
signal handling is not strictly async-signal-safe. However reporters should 
avoid accessing data structures likely to be in a bad state on crash."



Comment at: clang-tools-extra/clangd/support/ThreadCrashReporter.h:25
+  /// callback. Asserts if the current thread's callback is already set.
+  ThreadCrashReporter(const SignalCallback );
+  /// Resets the currrent thread's callback to nullptr.

doesn't seem to be any need for a copy here, pass by value and move instead?
(And probably use `llvm::unique_function` to avoid the copyable requirement)



Comment at: clang-tools-extra/clangd/support/ThreadCrashReporter.h:35
+
+  /// Callback to install via sys::AddSignalHandler(), the argument is ignored.
+  /// Any signal filtering is the responsibility of the caller.

This should first have a comment saying what it actually does!
"Calls all

[PATCH] D109707: [HIP] [AlwaysInliner] Disable AlwaysInliner to eliminate undefined symbols

2021-09-15 Thread Anshil Gandhi via Phabricator via cfe-commits 
gandhi21299 updated this revision to Diff 372573.
gandhi21299 added a comment.

- converted the HIP test into a CUDA test


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109707/new/

https://reviews.llvm.org/D109707

Files:
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/test/CodeGenCUDA/amdgpu-alias-undef-symbols.cu
  llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp


Index: llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
===
--- llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -691,7 +691,7 @@
   PM.addPass(GlobalDCEPass());
 }
 if (EarlyInlineAll && !EnableFunctionCalls)
-  PM.addPass(AMDGPUAlwaysInlinePass());
+  PM.addPass(AMDGPUAlwaysInlinePass(false));
   });
 
   PB.registerCGSCCOptimizerLateEPCallback(
Index: clang/test/CodeGenCUDA/amdgpu-alias-undef-symbols.cu
===
--- /dev/null
+++ clang/test/CodeGenCUDA/amdgpu-alias-undef-symbols.cu
@@ -0,0 +1,16 @@
+// RUN: %clang --offload-arch=gfx906 --cuda-device-only -x hip -emit-llvm -S 
-o - %s \
+// RUN:   -fgpu-rdc -O3 -mllvm -amdgpu-early-inline-all=true -mllvm 
-amdgpu-function-calls=false | \
+// RUN:   FileCheck %s
+
+#include "Inputs/cuda.h"
+
+// CHECK: %struct.B = type { i8 }
+struct B {
+
+  // CHECK: @_ZN1BC1Ei = hidden unnamed_addr alias void (%struct.B*, i32), 
void (%struct.B*, i32)* @_ZN1BC2Ei
+  __device__ B(int x);
+};
+
+__device__ B::B(int x) {
+
+}
Index: clang/lib/Driver/ToolChains/Clang.cpp
===
--- clang/lib/Driver/ToolChains/Clang.cpp
+++ clang/lib/Driver/ToolChains/Clang.cpp
@@ -5084,9 +5084,9 @@
   }
 
   // Enable -mconstructor-aliases except on darwin, where we have to work 
around
-  // a linker bug (see ), and CUDA/AMDGPU device code,
-  // where aliases aren't supported.
-  if (!RawTriple.isOSDarwin() && !RawTriple.isNVPTX() && !RawTriple.isAMDGPU())
+  // a linker bug (see ), and CUDA device code, where
+  // aliases aren't supported.
+  if (!RawTriple.isOSDarwin() && !RawTriple.isNVPTX())
 CmdArgs.push_back("-mconstructor-aliases");
 
   // Darwin's kernel doesn't support guard variables; just die if we


Index: llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
===
--- llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -691,7 +691,7 @@
   PM.addPass(GlobalDCEPass());
 }
 if (EarlyInlineAll && !EnableFunctionCalls)
-  PM.addPass(AMDGPUAlwaysInlinePass());
+  PM.addPass(AMDGPUAlwaysInlinePass(false));
   });
 
   PB.registerCGSCCOptimizerLateEPCallback(
Index: clang/test/CodeGenCUDA/amdgpu-alias-undef-symbols.cu
===
--- /dev/null
+++ clang/test/CodeGenCUDA/amdgpu-alias-undef-symbols.cu
@@ -0,0 +1,16 @@
+// RUN: %clang --offload-arch=gfx906 --cuda-device-only -x hip -emit-llvm -S -o - %s \
+// RUN:   -fgpu-rdc -O3 -mllvm -amdgpu-early-inline-all=true -mllvm -amdgpu-function-calls=false | \
+// RUN:   FileCheck %s
+
+#include "Inputs/cuda.h"
+
+// CHECK: %struct.B = type { i8 }
+struct B {
+
+  // CHECK: @_ZN1BC1Ei = hidden unnamed_addr alias void (%struct.B*, i32), void (%struct.B*, i32)* @_ZN1BC2Ei
+  __device__ B(int x);
+};
+
+__device__ B::B(int x) {
+
+}
Index: clang/lib/Driver/ToolChains/Clang.cpp
===
--- clang/lib/Driver/ToolChains/Clang.cpp
+++ clang/lib/Driver/ToolChains/Clang.cpp
@@ -5084,9 +5084,9 @@
   }
 
   // Enable -mconstructor-aliases except on darwin, where we have to work around
-  // a linker bug (see ), and CUDA/AMDGPU device code,
-  // where aliases aren't supported.
-  if (!RawTriple.isOSDarwin() && !RawTriple.isNVPTX() && !RawTriple.isAMDGPU())
+  // a linker bug (see ), and CUDA device code, where
+  // aliases aren't supported.
+  if (!RawTriple.isOSDarwin() && !RawTriple.isNVPTX())
 CmdArgs.push_back("-mconstructor-aliases");
 
   // Darwin's kernel doesn't support guard variables; just die if we
___
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[PATCH] D109707: [HIP] [AlwaysInliner] Disable AlwaysInliner to eliminate undefined symbols

2021-09-15 Thread Anshil Gandhi via Phabricator via cfe-commits 
gandhi21299 updated this revision to Diff 372551.
gandhi21299 added a comment.

- added the include header for HIP runtime


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109707/new/

https://reviews.llvm.org/D109707

Files:
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/test/CodeGen/amdgpu-alias-undef-symbols.hip
  llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp


Index: llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
===
--- llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -691,7 +691,7 @@
   PM.addPass(GlobalDCEPass());
 }
 if (EarlyInlineAll && !EnableFunctionCalls)
-  PM.addPass(AMDGPUAlwaysInlinePass());
+  PM.addPass(AMDGPUAlwaysInlinePass(false));
   });
 
   PB.registerCGSCCOptimizerLateEPCallback(
Index: clang/test/CodeGen/amdgpu-alias-undef-symbols.hip
===
--- /dev/null
+++ clang/test/CodeGen/amdgpu-alias-undef-symbols.hip
@@ -0,0 +1,16 @@
+// RUN: %clang --offload-arch=gfx906 --cuda-device-only -emit-llvm -S -o - %s \
+// RUN:   -fgpu-rdc -O3 -mllvm -amdgpu-early-inline-all=true -mllvm 
-amdgpu-function-calls=false | \
+// RUN:   FileCheck %s
+
+#include "hip/hip_runtime.h"
+
+// CHECK: %struct.B = type { i8 }
+struct B {
+
+  // CHECK: @_ZN1BC1Ei = hidden unnamed_addr alias void (%struct.B*, i32), 
void (%struct.B*, i32)* @_ZN1BC2Ei
+  __device__ B(int x);
+};
+
+__device__ B::B(int x) {
+
+}
Index: clang/lib/Driver/ToolChains/Clang.cpp
===
--- clang/lib/Driver/ToolChains/Clang.cpp
+++ clang/lib/Driver/ToolChains/Clang.cpp
@@ -5084,9 +5084,9 @@
   }
 
   // Enable -mconstructor-aliases except on darwin, where we have to work 
around
-  // a linker bug (see ), and CUDA/AMDGPU device code,
-  // where aliases aren't supported.
-  if (!RawTriple.isOSDarwin() && !RawTriple.isNVPTX() && !RawTriple.isAMDGPU())
+  // a linker bug (see ), and CUDA device code, where
+  // aliases aren't supported.
+  if (!RawTriple.isOSDarwin() && !RawTriple.isNVPTX())
 CmdArgs.push_back("-mconstructor-aliases");
 
   // Darwin's kernel doesn't support guard variables; just die if we


Index: llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
===
--- llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -691,7 +691,7 @@
   PM.addPass(GlobalDCEPass());
 }
 if (EarlyInlineAll && !EnableFunctionCalls)
-  PM.addPass(AMDGPUAlwaysInlinePass());
+  PM.addPass(AMDGPUAlwaysInlinePass(false));
   });
 
   PB.registerCGSCCOptimizerLateEPCallback(
Index: clang/test/CodeGen/amdgpu-alias-undef-symbols.hip
===
--- /dev/null
+++ clang/test/CodeGen/amdgpu-alias-undef-symbols.hip
@@ -0,0 +1,16 @@
+// RUN: %clang --offload-arch=gfx906 --cuda-device-only -emit-llvm -S -o - %s \
+// RUN:   -fgpu-rdc -O3 -mllvm -amdgpu-early-inline-all=true -mllvm -amdgpu-function-calls=false | \
+// RUN:   FileCheck %s
+
+#include "hip/hip_runtime.h"
+
+// CHECK: %struct.B = type { i8 }
+struct B {
+
+  // CHECK: @_ZN1BC1Ei = hidden unnamed_addr alias void (%struct.B*, i32), void (%struct.B*, i32)* @_ZN1BC2Ei
+  __device__ B(int x);
+};
+
+__device__ B::B(int x) {
+
+}
Index: clang/lib/Driver/ToolChains/Clang.cpp
===
--- clang/lib/Driver/ToolChains/Clang.cpp
+++ clang/lib/Driver/ToolChains/Clang.cpp
@@ -5084,9 +5084,9 @@
   }
 
   // Enable -mconstructor-aliases except on darwin, where we have to work around
-  // a linker bug (see ), and CUDA/AMDGPU device code,
-  // where aliases aren't supported.
-  if (!RawTriple.isOSDarwin() && !RawTriple.isNVPTX() && !RawTriple.isAMDGPU())
+  // a linker bug (see ), and CUDA device code, where
+  // aliases aren't supported.
+  if (!RawTriple.isOSDarwin() && !RawTriple.isNVPTX())
 CmdArgs.push_back("-mconstructor-aliases");
 
   // Darwin's kernel doesn't support guard variables; just die if we
___
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[PATCH] D109157: [ARM] Mitigate the cve-2021-35465 security vulnurability.

2021-09-15 Thread Alexandros Lamprineas via Phabricator via cfe-commits 
labrinea updated this revision to Diff 372674.
labrinea added a comment.

Changes in this revision:

- Replaced the backend option that enables the mitigation with a subtarget 
feature so that it works with LTO (@lenary thanks for the offline hint)
- Enabled the subtarget feature on the affected CPUs


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109157/new/

https://reviews.llvm.org/D109157

Files:
  clang/docs/ClangCommandLineReference.rst
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Arch/ARM.cpp
  clang/test/Driver/arm-cmse-cve-2021-35465.c
  llvm/lib/Target/ARM/ARM.td
  llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
  llvm/lib/Target/ARM/ARMSubtarget.h
  llvm/test/CodeGen/ARM/cmse-cve-2021-35465-return.ll
  llvm/test/CodeGen/ARM/cmse-cve-2021-35465.ll
  llvm/test/CodeGen/ARM/cmse-vlldm-no-reorder.mir

Index: llvm/test/CodeGen/ARM/cmse-vlldm-no-reorder.mir
===
--- llvm/test/CodeGen/ARM/cmse-vlldm-no-reorder.mir
+++ llvm/test/CodeGen/ARM/cmse-vlldm-no-reorder.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=thumbv8m.main -mcpu=cortex-m33 --float-abi=hard --run-pass=arm-pseudo %s -o - | \
+# RUN: llc -mtriple=thumbv8m.main -mcpu=cortex-m33 -mattr=-fix-cmse-cve-2021-35465 --float-abi=hard --run-pass=arm-pseudo %s -o - | \
 # RUN: FileCheck %s
 --- |
   ; ModuleID = 'cmse-vlldm-no-reorder.ll'
@@ -109,4 +109,4 @@
 # CHECK-NEXT:  $s0 = VMOVSR $r12, 14 /* CC::al */, $noreg
 # CHECK-NEXT:  $sp = tADDspi $sp, 34, 14 /* CC::al */, $noreg
 # CHECK-NEXT:  $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11
- 
\ No newline at end of file
+ 
Index: llvm/test/CodeGen/ARM/cmse-cve-2021-35465.ll
===
--- /dev/null
+++ llvm/test/CodeGen/ARM/cmse-cve-2021-35465.ll
@@ -0,0 +1,119 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+;
+; RUN: llc %s -o - -mtriple=thumbv8m.main \
+; RUN:   -mattr=+fp-armv8d16sp,+fix-cmse-cve-2021-35465 | \
+; RUN:   FileCheck %s --check-prefix=CHECK-8M-FP-CVE-2021-35465
+;
+; RUN: llc %s -o - -mtriple=thumbv8m.main -mcpu=cortex-m33 | \
+; RUN:   FileCheck %s --check-prefix=CHECK-8M-FP-CVE-2021-35465
+;
+; RUN: llc %s -o - -mtriple=thumbv8m.main -mcpu=cortex-m35p | \
+; RUN:   FileCheck %s --check-prefix=CHECK-8M-FP-CVE-2021-35465
+;
+; RUN: llc %s -o - -mtriple=thumbv8m.main \
+; RUN:   -mattr=-fpregs,+fix-cmse-cve-2021-35465 | \
+; RUN:   FileCheck %s --check-prefix=CHECK-8M-NOFP-CVE-2021-35465
+;
+; RUN: llc %s -o - -mtriple=thumbv8m.main -mcpu=cortex-m33 -mattr=-fpregs | \
+; RUN:   FileCheck %s --check-prefix=CHECK-8M-NOFP-CVE-2021-35465
+;
+; RUN: llc %s -o - -mtriple=thumbv8m.main -mcpu=cortex-m35p -mattr=-fpregs | \
+; RUN:   FileCheck %s --check-prefix=CHECK-8M-NOFP-CVE-2021-35465
+;
+; RUN: llc %s -o - -mtriple=thumbv8.1m.main \
+; RUN:   -mattr=+fp-armv8d16sp,+fix-cmse-cve-2021-35465 | \
+; RUN:   FileCheck %s --check-prefix=CHECK-81M-CVE-2021-35465
+;
+; RUN: llc %s -o - -mtriple=thumbv8.1m.main -mcpu=cortex-m55 | \
+; RUN:   FileCheck %s --check-prefix=CHECK-81M-CVE-2021-35465
+;
+; RUN: llc %s -o - -mtriple=thumbv8.1m.main \
+; RUN:   -mattr=-fpregs,+fix-cmse-cve-2021-35465 | \
+; RUN:   FileCheck %s --check-prefix=CHECK-81M-CVE-2021-35465
+;
+; RUN: llc %s -o - -mtriple=thumbv8.1m.main -mcpu=cortex-m55 -mattr=-fpregs | \
+; RUN:   FileCheck %s --check-prefix=CHECK-81M-CVE-2021-35465
+;
+
+define void @non_secure_call(void ()* %fptr) {
+; CHECK-8M-FP-CVE-2021-35465-LABEL: non_secure_call:
+; CHECK-8M-FP-CVE-2021-35465:   @ %bb.0:
+; CHECK-8M-FP-CVE-2021-35465-NEXT:push {r7, lr}
+; CHECK-8M-FP-CVE-2021-35465-NEXT:push.w {r4, r5, r6, r7, r8, r9, r10, r11}
+; CHECK-8M-FP-CVE-2021-35465-NEXT:bic r0, r0, #1
+; CHECK-8M-FP-CVE-2021-35465-NEXT:sub sp, #136
+; CHECK-8M-FP-CVE-2021-35465-NEXT:vlstm sp
+; CHECK-8M-FP-CVE-2021-35465-NEXT:mov r1, r0
+; CHECK-8M-FP-CVE-2021-35465-NEXT:mov r2, r0
+; CHECK-8M-FP-CVE-2021-35465-NEXT:mov r3, r0
+; CHECK-8M-FP-CVE-2021-35465-NEXT:mov r4, r0
+; CHECK-8M-FP-CVE-2021-35465-NEXT:mov r5, r0
+; CHECK-8M-FP-CVE-2021-35465-NEXT:mov r6, r0
+; CHECK-8M-FP-CVE-2021-35465-NEXT:mov r7, r0
+; CHECK-8M-FP-CVE-2021-35465-NEXT:mov r8, r0
+; CHECK-8M-FP-CVE-2021-35465-NEXT:mov r9, r0
+; CHECK-8M-FP-CVE-2021-35465-NEXT:mov r10, r0
+; CHECK-8M-FP-CVE-2021-35465-NEXT:mov r11, r0
+; CHECK-8M-FP-CVE-2021-35465-NEXT:mov r12, r0
+; CHECK-8M-FP-CVE-2021-35465-NEXT:msr apsr_nzcvq{{g?}}, r0
+; CHECK-8M-FP-CVE-2021-35465-NEXT:blxns r0
+; CHECK-8M-FP-CVE-2021-35465-NEXT:mrs r12, control
+; CHECK-8M-FP-CVE-2021-35465-NEXT:tst.w r12, #8
+; CHECK-8M-FP-CVE-2021-35465-NEXT:it ne
+; CHECK-8M-FP-CVE-2021-35465-NEXT:vmovne.f32 s0, s0
+; CHECK-8M-FP-CVE-2021-35465-NEXT:vlldm sp
+; CHECK-8M-FP-CVE-2021-35465-NEXT:add sp, #136
+;

[PATCH] D109607: [X86] Refactor GetSSETypeAtOffset to fix pr51813

2021-09-15 Thread Pengfei Wang via Phabricator via cfe-commits 
pengfei updated this revision to Diff 372664.
pengfei marked 2 inline comments as done.
pengfei added a comment.

Address Yuanke's comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109607/new/

https://reviews.llvm.org/D109607

Files:
  clang/lib/CodeGen/TargetInfo.cpp
  clang/test/CodeGen/X86/avx512fp16-abi.c

Index: clang/test/CodeGen/X86/avx512fp16-abi.c
===
--- clang/test/CodeGen/X86/avx512fp16-abi.c
+++ clang/test/CodeGen/X86/avx512fp16-abi.c
@@ -1,11 +1,12 @@
-// RUN: %clang_cc1 -triple x86_64-linux -emit-llvm  -target-feature +avx512fp16 < %s | FileCheck %s --check-prefixes=CHECK
+// RUN: %clang_cc1 -triple x86_64-linux -emit-llvm  -target-feature +avx512fp16 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -triple x86_64-linux -emit-llvm  -target-feature +avx512fp16 -x c++ -std=c++11 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-CPP
 
 struct half1 {
   _Float16 a;
 };
 
 struct half1 h1(_Float16 a) {
-  // CHECK: define{{.*}}half @h1
+  // CHECK: define{{.*}}half @
   struct half1 x;
   x.a = a;
   return x;
@@ -17,7 +18,7 @@
 };
 
 struct half2 h2(_Float16 a, _Float16 b) {
-  // CHECK: define{{.*}}<2 x half> @h2
+  // CHECK: define{{.*}}<2 x half> @
   struct half2 x;
   x.a = a;
   x.b = b;
@@ -31,7 +32,7 @@
 };
 
 struct half3 h3(_Float16 a, _Float16 b, _Float16 c) {
-  // CHECK: define{{.*}}<4 x half> @h3
+  // CHECK: define{{.*}}<4 x half> @
   struct half3 x;
   x.a = a;
   x.b = b;
@@ -47,7 +48,7 @@
 };
 
 struct half4 h4(_Float16 a, _Float16 b, _Float16 c, _Float16 d) {
-  // CHECK: define{{.*}}<4 x half> @h4
+  // CHECK: define{{.*}}<4 x half> @
   struct half4 x;
   x.a = a;
   x.b = b;
@@ -62,7 +63,7 @@
 };
 
 struct floathalf fh(float a, _Float16 b) {
-  // CHECK: define{{.*}}<4 x half> @fh
+  // CHECK: define{{.*}}<4 x half> @
   struct floathalf x;
   x.a = a;
   x.b = b;
@@ -76,7 +77,7 @@
 };
 
 struct floathalf2 fh2(float a, _Float16 b, _Float16 c) {
-  // CHECK: define{{.*}}<4 x half> @fh2
+  // CHECK: define{{.*}}<4 x half> @
   struct floathalf2 x;
   x.a = a;
   x.b = b;
@@ -90,7 +91,7 @@
 };
 
 struct halffloat hf(_Float16 a, float b) {
-  // CHECK: define{{.*}}<4 x half> @hf
+  // CHECK: define{{.*}}<4 x half> @
   struct halffloat x;
   x.a = a;
   x.b = b;
@@ -104,7 +105,7 @@
 };
 
 struct half2float h2f(_Float16 a, _Float16 b, float c) {
-  // CHECK: define{{.*}}<4 x half> @h2f
+  // CHECK: define{{.*}}<4 x half> @
   struct half2float x;
   x.a = a;
   x.b = b;
@@ -120,7 +121,7 @@
 };
 
 struct floathalf3 fh3(float a, _Float16 b, _Float16 c, _Float16 d) {
-  // CHECK: define{{.*}}{ <4 x half>, half } @fh3
+  // CHECK: define{{.*}}{ <4 x half>, half } @
   struct floathalf3 x;
   x.a = a;
   x.b = b;
@@ -138,7 +139,7 @@
 };
 
 struct half5 h5(_Float16 a, _Float16 b, _Float16 c, _Float16 d, _Float16 e) {
-  // CHECK: define{{.*}}{ <4 x half>, half } @h5
+  // CHECK: define{{.*}}{ <4 x half>, half } @
   struct half5 x;
   x.a = a;
   x.b = b;
@@ -147,3 +148,52 @@
   x.e = e;
   return x;
 }
+
+struct float2 {
+  struct {} s;
+  float a;
+  float b;
+};
+
+float pr51813(struct float2 s) {
+  // CHECK-C: define{{.*}} @pr51813(<2 x float>
+  // CHECK-CPP: define{{.*}} @_Z7pr518136float2(double {{.*}}, float
+  return s.a;
+}
+
+struct float3 {
+  float a;
+  struct {} s;
+  float b;
+};
+
+float pr51813_2(struct float3 s) {
+  // CHECK-C: define{{.*}} @pr51813_2(<2 x float>
+  // CHECK-CPP: define{{.*}} @_Z9pr51813_26float3(double {{.*}}, float
+  return s.a;
+}
+
+struct shalf2 {
+  struct {} s;
+  _Float16 a;
+  _Float16 b;
+};
+
+_Float16 sf2(struct shalf2 s) {
+  // CHECK-C: define{{.*}} @sf2(<2 x half>
+  // CHECK-CPP: define{{.*}} @_Z3sf26shalf2(double {{.*}}
+  return s.a;
+};
+
+struct halfs2 {
+  _Float16 a;
+  struct {} s1;
+  _Float16 b;
+  struct {} s2;
+};
+
+_Float16 fs2(struct shalf2 s) {
+  // CHECK-C: define{{.*}} @fs2(<2 x half>
+  // CHECK-CPP: define{{.*}} @_Z3fs26shalf2(double {{.*}}
+  return s.a;
+};
Index: clang/lib/CodeGen/TargetInfo.cpp
===
--- clang/lib/CodeGen/TargetInfo.cpp
+++ clang/lib/CodeGen/TargetInfo.cpp
@@ -3377,52 +3377,18 @@
   return false;
 }
 
-/// ContainsFloatAtOffset - Return true if the specified LLVM IR type has a
-/// float member at the specified offset.  For example, {int,{float}} has a
-/// float at offset 4.  It is conservatively correct for this routine to return
-/// false.
-static bool ContainsFloatAtOffset(llvm::Type *IRType, unsigned IROffset,
-  const llvm::DataLayout ) {
-  // Base case if we find a float.
-  if (IROffset == 0 && IRType->isFloatTy())
-return true;
-
-  // If this is a struct, recurse into the field at the specified offset.
-  if (llvm::StructType *STy = dyn_cast(IRType)) {
-const llvm::StructLayout *SL = TD.getStructLayout(STy);
-unsigned Elt =

[PATCH] D109002: [OpenCL] Supports optional image types in C++ for OpenCL 2021

2021-09-15 Thread Justas Janickas via Phabricator via cfe-commits 
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Topotuna marked an inline comment as done.
Closed by commit rG3b9470a6c46d: [OpenCL] Supports optional image types in C++ 
for OpenCL 2021 (authored by Topotuna).

Changed prior to commit:
  https://reviews.llvm.org/D109002?vs=370237=372662#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109002/new/

https://reviews.llvm.org/D109002

Files:
  clang/lib/Sema/SemaType.cpp
  clang/test/SemaOpenCL/unsupported-image.cl


Index: clang/test/SemaOpenCL/unsupported-image.cl
===
--- clang/test/SemaOpenCL/unsupported-image.cl
+++ clang/test/SemaOpenCL/unsupported-image.cl
@@ -1,6 +1,8 @@
 // RUN: %clang_cc1 -triple spir-unknown-unknown -verify -cl-std=CL3.0 
-cl-ext=-__opencl_c_images,-__opencl_c_read_write_images,-cl_khr_3d_image_writes,-__opencl_c_3d_image_writes
 %s
 // RUN: %clang_cc1 -triple spir-unknown-unknown -verify -cl-std=CL3.0 
-cl-ext=+__opencl_c_images,+__opencl_c_read_write_images,+cl_khr_3d_image_writes,+__opencl_c_3d_image_writes
 %s
 // RUN: %clang_cc1 -triple spir-unknown-unknown -verify -cl-std=CL3.0 
-cl-ext=+__opencl_c_images,+__opencl_c_read_write_images,-cl_khr_3d_image_writes,-__opencl_c_3d_image_writes
 %s
+// RUN: %clang_cc1 -triple spir-unknown-unknown -verify -cl-std=clc++2021 
-cl-ext=-__opencl_c_images,-__opencl_c_read_write_images,-cl_khr_3d_image_writes,-__opencl_c_3d_image_writes
 %s
+// RUN: %clang_cc1 -triple spir-unknown-unknown -verify -cl-std=clc++2021 
-cl-ext=+__opencl_c_images %s
 
 #if defined(__opencl_c_images) && defined(__opencl_c_3d_image_writes)
 //expected-no-diagnostics
Index: clang/lib/Sema/SemaType.cpp
===
--- clang/lib/Sema/SemaType.cpp
+++ clang/lib/Sema/SemaType.cpp
@@ -1732,7 +1732,12 @@
 
   if (S.getLangOpts().OpenCL) {
 const auto  = S.getOpenCLOptions();
+// FIXME: both variables IsOpenCLC30 and IsOpenCLC30Compatible should be
+// unified into one when __opencl_c_3d_image_writes option is enabled in
+// C++ for OpenCL 2021
 bool IsOpenCLC30 = (S.getLangOpts().OpenCLVersion == 300);
+bool IsOpenCLC30Compatible =
+S.getLangOpts().getOpenCLCompatibleVersion() == 300;
 // OpenCL C v3.0 s6.3.3 - OpenCL image types require __opencl_c_images
 // support.
 // OpenCL C v3.0 s6.2.1 - OpenCL 3d image write types requires support
@@ -1741,7 +1746,7 @@
 // that support OpenCL 3.0, cl_khr_3d_image_writes must be returned when 
and
 // only when the optional feature is supported
 if ((Result->isImageType() || Result->isSamplerT()) &&
-(IsOpenCLC30 &&
+(IsOpenCLC30Compatible &&
  !OpenCLOptions.isSupported("__opencl_c_images", S.getLangOpts( {
   S.Diag(DS.getTypeSpecTypeLoc(), diag::err_opencl_requires_extension)
   << 0 << Result << "__opencl_c_images";


Index: clang/test/SemaOpenCL/unsupported-image.cl
===
--- clang/test/SemaOpenCL/unsupported-image.cl
+++ clang/test/SemaOpenCL/unsupported-image.cl
@@ -1,6 +1,8 @@
 // RUN: %clang_cc1 -triple spir-unknown-unknown -verify -cl-std=CL3.0 -cl-ext=-__opencl_c_images,-__opencl_c_read_write_images,-cl_khr_3d_image_writes,-__opencl_c_3d_image_writes %s
 // RUN: %clang_cc1 -triple spir-unknown-unknown -verify -cl-std=CL3.0 -cl-ext=+__opencl_c_images,+__opencl_c_read_write_images,+cl_khr_3d_image_writes,+__opencl_c_3d_image_writes %s
 // RUN: %clang_cc1 -triple spir-unknown-unknown -verify -cl-std=CL3.0 -cl-ext=+__opencl_c_images,+__opencl_c_read_write_images,-cl_khr_3d_image_writes,-__opencl_c_3d_image_writes %s
+// RUN: %clang_cc1 -triple spir-unknown-unknown -verify -cl-std=clc++2021 -cl-ext=-__opencl_c_images,-__opencl_c_read_write_images,-cl_khr_3d_image_writes,-__opencl_c_3d_image_writes %s
+// RUN: %clang_cc1 -triple spir-unknown-unknown -verify -cl-std=clc++2021 -cl-ext=+__opencl_c_images %s
 
 #if defined(__opencl_c_images) && defined(__opencl_c_3d_image_writes)
 //expected-no-diagnostics
Index: clang/lib/Sema/SemaType.cpp
===
--- clang/lib/Sema/SemaType.cpp
+++ clang/lib/Sema/SemaType.cpp
@@ -1732,7 +1732,12 @@
 
   if (S.getLangOpts().OpenCL) {
 const auto  = S.getOpenCLOptions();
+// FIXME: both variables IsOpenCLC30 and IsOpenCLC30Compatible should be
+// unified into one when __opencl_c_3d_image_writes option is enabled in
+// C++ for OpenCL 2021
 bool IsOpenCLC30 = (S.getLangOpts().OpenCLVersion == 300);
+bool IsOpenCLC30Compatible =
+S.getLangOpts().getOpenCLCompatibleVersion() == 300;
 // OpenCL C v3.0 s6.3.3 - OpenCL image types require __opencl_c_images
 // support.
 // OpenCL C v3.0 s6.2.1 - OpenCL 3d image write types requires support
@@

[clang] 3b9470a - [OpenCL] Supports optional image types in C++ for OpenCL 2021

2021-09-15 Thread Justas Janickas via cfe-commits 

Author: Justas Janickas
Date: 2021-09-15T10:03:47+01:00
New Revision: 3b9470a6c46d0ecdb586a5a1e9223ea0c832337c

URL: 
https://github.com/llvm/llvm-project/commit/3b9470a6c46d0ecdb586a5a1e9223ea0c832337c
DIFF: 
https://github.com/llvm/llvm-project/commit/3b9470a6c46d0ecdb586a5a1e9223ea0c832337c.diff

LOG: [OpenCL] Supports optional image types in C++ for OpenCL 2021

Adds support for a feature macro `__opencl_c_images` in C++ for
OpenCL 2021 enabling a respective optional core feature from
OpenCL 3.0.

This change aims to achieve compatibility between C++ for OpenCL
2021 and OpenCL 3.0.

Differential Revision: https://reviews.llvm.org/D109002

Added: 


Modified: 
clang/lib/Sema/SemaType.cpp
clang/test/SemaOpenCL/unsupported-image.cl

Removed: 




diff  --git a/clang/lib/Sema/SemaType.cpp b/clang/lib/Sema/SemaType.cpp
index dcf18d3b4ba3d..f7f428c1e6d8d 100644
--- a/clang/lib/Sema/SemaType.cpp
+++ b/clang/lib/Sema/SemaType.cpp
@@ -1732,7 +1732,12 @@ static QualType 
ConvertDeclSpecToType(TypeProcessingState ) {
 
   if (S.getLangOpts().OpenCL) {
 const auto  = S.getOpenCLOptions();
+// FIXME: both variables IsOpenCLC30 and IsOpenCLC30Compatible should be
+// unified into one when __opencl_c_3d_image_writes option is enabled in
+// C++ for OpenCL 2021
 bool IsOpenCLC30 = (S.getLangOpts().OpenCLVersion == 300);
+bool IsOpenCLC30Compatible =
+S.getLangOpts().getOpenCLCompatibleVersion() == 300;
 // OpenCL C v3.0 s6.3.3 - OpenCL image types require __opencl_c_images
 // support.
 // OpenCL C v3.0 s6.2.1 - OpenCL 3d image write types requires support
@@ -1741,7 +1746,7 @@ static QualType ConvertDeclSpecToType(TypeProcessingState 
) {
 // that support OpenCL 3.0, cl_khr_3d_image_writes must be returned when 
and
 // only when the optional feature is supported
 if ((Result->isImageType() || Result->isSamplerT()) &&
-(IsOpenCLC30 &&
+(IsOpenCLC30Compatible &&
  !OpenCLOptions.isSupported("__opencl_c_images", S.getLangOpts( {
   S.Diag(DS.getTypeSpecTypeLoc(), diag::err_opencl_requires_extension)
   << 0 << Result << "__opencl_c_images";

diff  --git a/clang/test/SemaOpenCL/unsupported-image.cl 
b/clang/test/SemaOpenCL/unsupported-image.cl
index 40772460e54d1..8db3f61b0146b 100644
--- a/clang/test/SemaOpenCL/unsupported-image.cl
+++ b/clang/test/SemaOpenCL/unsupported-image.cl
@@ -1,6 +1,8 @@
 // RUN: %clang_cc1 -triple spir-unknown-unknown -verify -cl-std=CL3.0 
-cl-ext=-__opencl_c_images,-__opencl_c_read_write_images,-cl_khr_3d_image_writes,-__opencl_c_3d_image_writes
 %s
 // RUN: %clang_cc1 -triple spir-unknown-unknown -verify -cl-std=CL3.0 
-cl-ext=+__opencl_c_images,+__opencl_c_read_write_images,+cl_khr_3d_image_writes,+__opencl_c_3d_image_writes
 %s
 // RUN: %clang_cc1 -triple spir-unknown-unknown -verify -cl-std=CL3.0 
-cl-ext=+__opencl_c_images,+__opencl_c_read_write_images,-cl_khr_3d_image_writes,-__opencl_c_3d_image_writes
 %s
+// RUN: %clang_cc1 -triple spir-unknown-unknown -verify -cl-std=clc++2021 
-cl-ext=-__opencl_c_images,-__opencl_c_read_write_images,-cl_khr_3d_image_writes,-__opencl_c_3d_image_writes
 %s
+// RUN: %clang_cc1 -triple spir-unknown-unknown -verify -cl-std=clc++2021 
-cl-ext=+__opencl_c_images %s
 
 #if defined(__opencl_c_images) && defined(__opencl_c_3d_image_writes)
 //expected-no-diagnostics



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[PATCH] D109362: [SystemZ][z/OS] Add GOFF Support to the DataLayout

2021-09-15 Thread Ulrich Weigand via Phabricator via cfe-commits 
uweigand added a comment.

In D109362#3000284 , @anirudhp wrote:

> In D109362#2999688 , @uweigand 
> wrote:
>
>> Looking at the common code parts, it seems the behavior of MM_GOFF is 
>> actually identical to MM_ELF.   Is this correct?   If so, do we really need 
>> a different format type here?
>
> At a future point, we will be changing the local and global prefixes. At that 
> point we would still need a separate `MM_GOFF` field. I feel it would be a 
> bit better to enforce it from now itself.

I see.  Is there a reason why we cannot use the "correct" prefixes to begin 
with?


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[PATCH] D109607: [X86] Refactor GetSSETypeAtOffset to fix pr51813

2021-09-15 Thread LuoYuanke via Phabricator via cfe-commits 
LuoYuanke added inline comments.



Comment at: clang/test/CodeGen/X86/avx512fp16-abi.c:153
+struct float2 {
+  struct {} s;
+  float a;

Add a test case for "{ struct {}; half; struct {}; half;}?


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[PATCH] D109607: [X86] Refactor GetSSETypeAtOffset to fix pr51813

2021-09-15 Thread LuoYuanke via Phabricator via cfe-commits 
LuoYuanke added inline comments.



Comment at: clang/lib/CodeGen/TargetInfo.cpp:3421
+if (T0->isHalfTy())
+  T1 = getFPTypeAtOffset(IRType, IROffset + 4, TD);
+// If we can't get a second FP type, return a simple half or float.

Not quite understanding why "+4". Would you comments on it?


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[PATCH] D109812: [compiler-rt] Move -fno-omit-frame-pointer check to common config-ix

2021-09-15 Thread Michał Górny via Phabricator via cfe-commits 
mgorny created this revision.
mgorny added reviewers: tstellar, cryptoad.
Herald added a subscriber: dberris.
mgorny requested review of this revision.

9ee64c374605683ae80b9641d5312a72c2a67336 
 has 
started using
COMPILER_RT_HAS_OMIT_FRAME_POINTER_FLAG inside scudo.  However,
the relevant CMake check was performed in builtin-config-ix.cmake,
so the definition was missing when builtins were not built.  Move
the check to config-ix.cmake, so that it runs unconditionally of
the components being built.

Fixes PR#51847


https://reviews.llvm.org/D109812

Files:
  compiler-rt/cmake/builtin-config-ix.cmake
  compiler-rt/cmake/config-ix.cmake


Index: compiler-rt/cmake/config-ix.cmake
===
--- compiler-rt/cmake/config-ix.cmake
+++ compiler-rt/cmake/config-ix.cmake
@@ -61,6 +61,7 @@
 
 # CodeGen options.
 check_c_compiler_flag(-ffreestanding 
COMPILER_RT_HAS_FFREESTANDING_FLAG)
+check_c_compiler_flag(-fomit-frame-pointer   
COMPILER_RT_HAS_OMIT_FRAME_POINTER_FLAG)
 check_c_compiler_flag(-std=c11   COMPILER_RT_HAS_STD_C11_FLAG)
 check_cxx_compiler_flag(-fPICCOMPILER_RT_HAS_FPIC_FLAG)
 check_cxx_compiler_flag(-fPIECOMPILER_RT_HAS_FPIE_FLAG)
Index: compiler-rt/cmake/builtin-config-ix.cmake
===
--- compiler-rt/cmake/builtin-config-ix.cmake
+++ compiler-rt/cmake/builtin-config-ix.cmake
@@ -10,7 +10,6 @@
 builtin_check_c_compiler_flag(-fno-builtin  
COMPILER_RT_HAS_FNO_BUILTIN_FLAG)
 builtin_check_c_compiler_flag(-std=c11  
COMPILER_RT_HAS_STD_C11_FLAG)
 builtin_check_c_compiler_flag(-fvisibility=hidden   
COMPILER_RT_HAS_VISIBILITY_HIDDEN_FLAG)
-builtin_check_c_compiler_flag(-fomit-frame-pointer  
COMPILER_RT_HAS_OMIT_FRAME_POINTER_FLAG)
 builtin_check_c_compiler_flag(-ffreestanding
COMPILER_RT_HAS_FREESTANDING_FLAG)
 builtin_check_c_compiler_flag(-fxray-instrument 
COMPILER_RT_HAS_XRAY_COMPILER_FLAG)
 


Index: compiler-rt/cmake/config-ix.cmake
===
--- compiler-rt/cmake/config-ix.cmake
+++ compiler-rt/cmake/config-ix.cmake
@@ -61,6 +61,7 @@
 
 # CodeGen options.
 check_c_compiler_flag(-ffreestanding COMPILER_RT_HAS_FFREESTANDING_FLAG)
+check_c_compiler_flag(-fomit-frame-pointer   COMPILER_RT_HAS_OMIT_FRAME_POINTER_FLAG)
 check_c_compiler_flag(-std=c11   COMPILER_RT_HAS_STD_C11_FLAG)
 check_cxx_compiler_flag(-fPICCOMPILER_RT_HAS_FPIC_FLAG)
 check_cxx_compiler_flag(-fPIECOMPILER_RT_HAS_FPIE_FLAG)
Index: compiler-rt/cmake/builtin-config-ix.cmake
===
--- compiler-rt/cmake/builtin-config-ix.cmake
+++ compiler-rt/cmake/builtin-config-ix.cmake
@@ -10,7 +10,6 @@
 builtin_check_c_compiler_flag(-fno-builtin  COMPILER_RT_HAS_FNO_BUILTIN_FLAG)
 builtin_check_c_compiler_flag(-std=c11  COMPILER_RT_HAS_STD_C11_FLAG)
 builtin_check_c_compiler_flag(-fvisibility=hidden   COMPILER_RT_HAS_VISIBILITY_HIDDEN_FLAG)
-builtin_check_c_compiler_flag(-fomit-frame-pointer  COMPILER_RT_HAS_OMIT_FRAME_POINTER_FLAG)
 builtin_check_c_compiler_flag(-ffreestandingCOMPILER_RT_HAS_FREESTANDING_FLAG)
 builtin_check_c_compiler_flag(-fxray-instrument COMPILER_RT_HAS_XRAY_COMPILER_FLAG)
 
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[PATCH] D109739: [X86][InlineAsm][Bugfix] Use mem size information (*word ptr) for "global variable + registers" memory expression in inline asm.

2021-09-15 Thread Xiang Zhang via Phabricator via cfe-commits 
This revision was automatically updated to reflect the committed changes.
Closed by commit rG1f1c71aeacc1: [X86][InlineAsm] Use mem size information 
(*word ptr) for global variable +… (authored by xiangzhangllvm).
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109739/new/

https://reviews.llvm.org/D109739

Files:
  clang/test/CodeGen/X86/ms_fmul.c
  llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp


Index: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
===
--- llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -1759,7 +1759,7 @@
   // registers in a mmory expression, and though unaccessible via rip/eip.
   if (IsGlobalLV && (BaseReg || IndexReg)) {
 Operands.push_back(
-X86Operand::CreateMem(getPointerWidth(), Disp, Start, End));
+X86Operand::CreateMem(getPointerWidth(), Disp, Start, End, Size));
 return false;
   }
   // Otherwise, we set the base register to a non-zero value
Index: clang/test/CodeGen/X86/ms_fmul.c
===
--- /dev/null
+++ clang/test/CodeGen/X86/ms_fmul.c
@@ -0,0 +1,21 @@
+// REQUIRES: x86-registered-target
+
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown -fasm-blocks -emit-llvm %s 
-o - | FileCheck %s
+// RUN: %clang_cc1 -triple i386-unknown-unknown -fasm-blocks -emit-llvm %s -o 
- | FileCheck %s
+
+// This test is designed to check if we use the mem size info for parsing MS
+// InlineAsm which use a global variable and one/two registers in a memory
+// expression. If we not use this mem size info, there will be error of
+// ambiguous operand size for some instructions. (e.g. 'fmul')
+__attribute__((aligned (16)))
+static const unsigned int static_const_table[] = { 0x0080, };
+
+
+void __attribute__ ((naked)) foo(void)
+{__asm{
+fmul qword ptr [static_const_table + 0x00f0 +edx]
+ret
+}}
+
+// CHECK-LABEL: foo
+// CHECK: call void asm sideeffect inteldialect "fmul qword ptr 
static_const_table[edx + $$240]\0A\09ret"


Index: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
===
--- llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -1759,7 +1759,7 @@
   // registers in a mmory expression, and though unaccessible via rip/eip.
   if (IsGlobalLV && (BaseReg || IndexReg)) {
 Operands.push_back(
-X86Operand::CreateMem(getPointerWidth(), Disp, Start, End));
+X86Operand::CreateMem(getPointerWidth(), Disp, Start, End, Size));
 return false;
   }
   // Otherwise, we set the base register to a non-zero value
Index: clang/test/CodeGen/X86/ms_fmul.c
===
--- /dev/null
+++ clang/test/CodeGen/X86/ms_fmul.c
@@ -0,0 +1,21 @@
+// REQUIRES: x86-registered-target
+
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown -fasm-blocks -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple i386-unknown-unknown -fasm-blocks -emit-llvm %s -o - | FileCheck %s
+
+// This test is designed to check if we use the mem size info for parsing MS
+// InlineAsm which use a global variable and one/two registers in a memory
+// expression. If we not use this mem size info, there will be error of
+// ambiguous operand size for some instructions. (e.g. 'fmul')
+__attribute__((aligned (16)))
+static const unsigned int static_const_table[] = { 0x0080, };
+
+
+void __attribute__ ((naked)) foo(void)
+{__asm{
+fmul qword ptr [static_const_table + 0x00f0 +edx]
+ret
+}}
+
+// CHECK-LABEL: foo
+// CHECK: call void asm sideeffect inteldialect "fmul qword ptr static_const_table[edx + $$240]\0A\09ret"
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[clang] 1f1c71a - [X86][InlineAsm] Use mem size information (*word ptr) for "global variable + registers" memory expression in inline asm.

2021-09-15 Thread Xiang1 Zhang via cfe-commits 

Author: Xiang1 Zhang
Date: 2021-09-15T16:11:14+08:00
New Revision: 1f1c71aeacc1c4eab385c074714508b6e7121f73

URL: 
https://github.com/llvm/llvm-project/commit/1f1c71aeacc1c4eab385c074714508b6e7121f73
DIFF: 
https://github.com/llvm/llvm-project/commit/1f1c71aeacc1c4eab385c074714508b6e7121f73.diff

LOG: [X86][InlineAsm] Use mem size information (*word ptr) for "global variable 
+ registers" memory expression in inline asm.

Differential Revision: https://reviews.llvm.org/D109739

Added: 
clang/test/CodeGen/X86/ms_fmul.c

Modified: 
llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp

Removed: 




diff  --git a/clang/test/CodeGen/X86/ms_fmul.c 
b/clang/test/CodeGen/X86/ms_fmul.c
new file mode 100644
index ..a0a1be9e217c
--- /dev/null
+++ b/clang/test/CodeGen/X86/ms_fmul.c
@@ -0,0 +1,21 @@
+// REQUIRES: x86-registered-target
+
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown -fasm-blocks -emit-llvm %s 
-o - | FileCheck %s
+// RUN: %clang_cc1 -triple i386-unknown-unknown -fasm-blocks -emit-llvm %s -o 
- | FileCheck %s
+
+// This test is designed to check if we use the mem size info for parsing MS
+// InlineAsm which use a global variable and one/two registers in a memory
+// expression. If we not use this mem size info, there will be error of
+// ambiguous operand size for some instructions. (e.g. 'fmul')
+__attribute__((aligned (16)))
+static const unsigned int static_const_table[] = { 0x0080, };
+
+
+void __attribute__ ((naked)) foo(void)
+{__asm{
+fmul qword ptr [static_const_table + 0x00f0 +edx]
+ret
+}}
+
+// CHECK-LABEL: foo
+// CHECK: call void asm sideeffect inteldialect "fmul qword ptr 
static_const_table[edx + $$240]\0A\09ret"

diff  --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp 
b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
index d96a6be5d92e..f849ebfe76e2 100644
--- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -1759,7 +1759,7 @@ bool X86AsmParser::CreateMemForMSInlineAsm(
   // registers in a mmory expression, and though unaccessible via rip/eip.
   if (IsGlobalLV && (BaseReg || IndexReg)) {
 Operands.push_back(
-X86Operand::CreateMem(getPointerWidth(), Disp, Start, End));
+X86Operand::CreateMem(getPointerWidth(), Disp, Start, End, Size));
 return false;
   }
   // Otherwise, we set the base register to a non-zero value



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