[PATCH] D155540: [clangd] Remove extra dependancies for clangd

[Ahsan Saghir via Phabricator via cfe-commits]

saghir added a comment.

Thank you for the review and your comments @sammccall and @mstorsjo. As I 
understand there is no strong opinion here either way. I think we can leave 
things as they are for now. I am going to abandon this patch. If someone else 
feels strongly about removing them, they can put up a patch in future for this.


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[PATCH] D155111: [clangd] Fix build failures observed on build bots for missing libs

[Ahsan Saghir via Phabricator via cfe-commits]

saghir added a comment.

In D155111#4495131 , @mstorsjo wrote:

> To clarify the issue - the kind of builds that seems to be broken is builds 
> with `BUILD_SHARED_LIBS=ON`. The reason is that these libraries are needed is 
> because the `clangd` target includes 
> `$`, so all the dependencies of 
> `clangDaemonTweaks` would need to be included here as well. Please include 
> that in the commit message description. (Is there a way to pull in those 
> instead of duplicating the list?)
>
> This looks mostly ok to me, but it does add slightly more libraries than 
> what's needed. As the list of libraries that now are linked into `clangdMain` 
> is the list of libraries that previously was linked for the two components 
> that now are `clangd` and `clangdMain`, so some of the dependencies only need 
> to be moved, not duplicated.
>
> A more minimal set of dependencies, which seems to link successfully with 
> `BUILD_SHARED_LIBS=ON`, is achieved with this diff on top of current git main:
>
>   diff --git a/clang-tools-extra/clangd/tool/CMakeLists.txt 
> b/clang-tools-extra/clangd/tool/CMakeLists.txt
>   index ddf9c2488819..6c21175d7687 100644
>   --- a/clang-tools-extra/clangd/tool/CMakeLists.txt
>   +++ b/clang-tools-extra/clangd/tool/CMakeLists.txt
>   @@ -26,11 +26,7 @@ clang_target_link_libraries(clangdMain
>  clangBasic
>  clangFormat
>  clangFrontend
>   -  clangLex
>   -  clangSema
>  clangTooling
>   -  clangToolingCore
>   -  clangToolingRefactoring
>  clangToolingSyntax
>  )
>
>   @@ -44,7 +40,20 @@ target_link_libraries(clangdMain
>  ${CLANGD_XPC_LIBS}
>  )
>
>   +clang_target_link_libraries(clangd
>   +  PRIVATE
>   +  clangAST
>   +  clangBasic
>   +  clangLex
>   +  clangSema
>   +  clangToolingCore
>   +  clangToolingRefactoring
>   +  clangToolingSyntax
>   +  )
>   +
>target_link_libraries(clangd
>  PRIVATE
>  clangdMain
>   +  clangDaemon
>   +  clangdSupport
>  )
>
> Not sure if it's good hygiene to only link specifically to exactly those 
> libraries that are needed and nothing else, or if it's just making things 
> slightly more brittle?

Thanks for reviewing and providing suggestions. I have put up a follow up patch 
for review: https://reviews.llvm.org/D155540


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[PATCH] D155540: [clangd] Move dependancies for clangd

[Ahsan Saghir via Phabricator via cfe-commits]

saghir created this revision.
Herald added subscribers: kadircet, arphaman.
Herald added a project: All.
saghir requested review of this revision.
Herald added subscribers: cfe-commits, MaskRay, ilya-biryukov.
Herald added a project: clang-tools-extra.

This patch moves dependancies for clangd instead of duplicating them.
This is a follow up patch to 915659bfa1e9fe2e2c748ac84d33881e248f9ad5 
,
which was added to fix build failure with BUILD_SHARED_LIBS=ON.


Repository:
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Files:
  clang-tools-extra/clangd/tool/CMakeLists.txt


Index: clang-tools-extra/clangd/tool/CMakeLists.txt
===
--- clang-tools-extra/clangd/tool/CMakeLists.txt
+++ clang-tools-extra/clangd/tool/CMakeLists.txt
@@ -26,11 +26,7 @@
   clangBasic
   clangFormat
   clangFrontend
-  clangLex
-  clangSema
   clangTooling
-  clangToolingCore
-  clangToolingRefactoring
   clangToolingSyntax
   )
 
@@ -48,11 +44,8 @@
   PRIVATE
   clangAST
   clangBasic
-  clangFormat
-  clangFrontend
   clangLex
   clangSema
-  clangTooling
   clangToolingCore
   clangToolingRefactoring
   clangToolingSyntax


Index: clang-tools-extra/clangd/tool/CMakeLists.txt
===
--- clang-tools-extra/clangd/tool/CMakeLists.txt
+++ clang-tools-extra/clangd/tool/CMakeLists.txt
@@ -26,11 +26,7 @@
   clangBasic
   clangFormat
   clangFrontend
-  clangLex
-  clangSema
   clangTooling
-  clangToolingCore
-  clangToolingRefactoring
   clangToolingSyntax
   )
 
@@ -48,11 +44,8 @@
   PRIVATE
   clangAST
   clangBasic
-  clangFormat
-  clangFrontend
   clangLex
   clangSema
-  clangTooling
   clangToolingCore
   clangToolingRefactoring
   clangToolingSyntax
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[PATCH] D155111: [clangd] Fix build failures observed on build bots for missing libs

[Ahsan Saghir via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG915659bfa1e9: [clangd] Fix build failures observed on build 
bots for missing libs (authored by saghir).

Repository:
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Files:
  clang-tools-extra/clangd/tool/CMakeLists.txt


Index: clang-tools-extra/clangd/tool/CMakeLists.txt
===
--- clang-tools-extra/clangd/tool/CMakeLists.txt
+++ clang-tools-extra/clangd/tool/CMakeLists.txt
@@ -44,7 +44,23 @@
   ${CLANGD_XPC_LIBS}
   )
 
+clang_target_link_libraries(clangd
+  PRIVATE
+  clangAST
+  clangBasic
+  clangFormat
+  clangFrontend
+  clangLex
+  clangSema
+  clangTooling
+  clangToolingCore
+  clangToolingRefactoring
+  clangToolingSyntax
+  )
+
 target_link_libraries(clangd
   PRIVATE
   clangdMain
+  clangDaemon
+  clangdSupport
   )


Index: clang-tools-extra/clangd/tool/CMakeLists.txt
===
--- clang-tools-extra/clangd/tool/CMakeLists.txt
+++ clang-tools-extra/clangd/tool/CMakeLists.txt
@@ -44,7 +44,23 @@
   ${CLANGD_XPC_LIBS}
   )
 
+clang_target_link_libraries(clangd
+  PRIVATE
+  clangAST
+  clangBasic
+  clangFormat
+  clangFrontend
+  clangLex
+  clangSema
+  clangTooling
+  clangToolingCore
+  clangToolingRefactoring
+  clangToolingSyntax
+  )
+
 target_link_libraries(clangd
   PRIVATE
   clangdMain
+  clangDaemon
+  clangdSupport
   )
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[PATCH] D155111: [clangd] Fix build failures observed on build bots for missing libs

[Ahsan Saghir via Phabricator via cfe-commits]

saghir added a comment.

@mstorsjo @ivanmurashko Can you please take a look at this? This is blocking 
our builds on the PowerPC buildbots. Thanks a lot for your time!


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[PATCH] D155111: [clangd] Fix build failures observed on build bots for missing libs

[Ahsan Saghir via Phabricator via cfe-commits]

saghir added a comment.

This is to fix failures in the build bot: 
https://lab.llvm.org/buildbot/#/builders/57/builds/28356


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[PATCH] D155111: [clangd] Fix build failures observed on build bots for missing libs

[Ahsan Saghir via Phabricator via cfe-commits]

saghir created this revision.
Herald added subscribers: kadircet, arphaman.
Herald added a project: All.
saghir requested review of this revision.
Herald added subscribers: cfe-commits, MaskRay, ilya-biryukov.
Herald added a project: clang-tools-extra.

This was broken by 56ac9d46a7c1468d587ccec02a781e52d0bb298a 
.
There were some changes made to fix it in
a20d57e83441a69fa2bab86593b18cc0402095d2 
, but that 
did not quite
fix everything.


Repository:
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https://reviews.llvm.org/D155111

Files:
  clang-tools-extra/clangd/tool/CMakeLists.txt


Index: clang-tools-extra/clangd/tool/CMakeLists.txt
===
--- clang-tools-extra/clangd/tool/CMakeLists.txt
+++ clang-tools-extra/clangd/tool/CMakeLists.txt
@@ -44,7 +44,23 @@
   ${CLANGD_XPC_LIBS}
   )
 
+clang_target_link_libraries(clangd
+  PRIVATE
+  clangAST
+  clangBasic
+  clangFormat
+  clangFrontend
+  clangLex
+  clangSema
+  clangTooling
+  clangToolingCore
+  clangToolingRefactoring
+  clangToolingSyntax
+  )
+
 target_link_libraries(clangd
   PRIVATE
   clangdMain
+  clangDaemon
+  clangdSupport
   )


Index: clang-tools-extra/clangd/tool/CMakeLists.txt
===
--- clang-tools-extra/clangd/tool/CMakeLists.txt
+++ clang-tools-extra/clangd/tool/CMakeLists.txt
@@ -44,7 +44,23 @@
   ${CLANGD_XPC_LIBS}
   )
 
+clang_target_link_libraries(clangd
+  PRIVATE
+  clangAST
+  clangBasic
+  clangFormat
+  clangFrontend
+  clangLex
+  clangSema
+  clangTooling
+  clangToolingCore
+  clangToolingRefactoring
+  clangToolingSyntax
+  )
+
 target_link_libraries(clangd
   PRIVATE
   clangdMain
+  clangDaemon
+  clangdSupport
   )
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[PATCH] D113642: [PowerPC] Provide XL-compatible vec_round implementation

[Ahsan Saghir via Phabricator via cfe-commits]

saghir accepted this revision.
saghir added a comment.
This revision is now accepted and ready to land.

LGTM.


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[PATCH] D114088: [PowerPC] Add BCD add/sub/cmp builtins

[Ahsan Saghir via Phabricator via cfe-commits]

saghir accepted this revision.
saghir added a comment.
This revision is now accepted and ready to land.

LGTM.


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[PATCH] D113306: [PowerPC] Allow MMA built-ins to accept non-void pointers and arrays

[Ahsan Saghir via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG4c8b8e0154f0: [PowerPC] Allow MMA built-ins to accept 
non-void pointers and arrays (authored by saghir).

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Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/Sema/ppc-pair-mma-types.c


Index: clang/test/Sema/ppc-pair-mma-types.c
===
--- clang/test/Sema/ppc-pair-mma-types.c
+++ clang/test/Sema/ppc-pair-mma-types.c
@@ -339,20 +339,20 @@
 
 void testRestrictQualifiedPointer1(int *__restrict acc) {
   vector float arr[4];
-  __builtin_mma_disassemble_acc((void *)arr, acc); // expected-error {{passing 
'int *restrict' to parameter of incompatible type '__vector_quad *'}}
+  __builtin_mma_disassemble_acc(arr, acc); // expected-error {{passing 'int 
*restrict' to parameter of incompatible type '__vector_quad *'}}
 }
 
 void testRestrictQualifiedPointer2(__vector_quad *__restrict acc) {
   vector float arr[4];
-  __builtin_mma_disassemble_acc((void *)arr, acc);
+  __builtin_mma_disassemble_acc(arr, acc);
 }
 
 void testVolatileQualifiedPointer1(int *__volatile acc) {
   vector float arr[4];
-  __builtin_mma_disassemble_acc((void *)arr, acc); // expected-error {{passing 
'int *volatile' to parameter of incompatible type '__vector_quad *'}}
+  __builtin_mma_disassemble_acc(arr, acc); // expected-error {{passing 'int 
*volatile' to parameter of incompatible type '__vector_quad *'}}
 }
 
 void testVolatileQualifiedPointer2(__vector_quad *__volatile acc) {
   vector float arr[4];
-  __builtin_mma_disassemble_acc((void *)arr, acc);
+  __builtin_mma_disassemble_acc(arr, acc);
 }
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -7553,11 +7553,11 @@
   StrippedRVType = StrippedRVType.getCanonicalType().getUnqualifiedType();
 
 // The only case where the argument type and expected type are allowed to
-// mismatch is if the argument type is a non-void pointer and expected type
-// is a void pointer.
+// mismatch is if the argument type is a non-void pointer (or array) and
+// expected type is a void pointer.
 if (StrippedRVType != ExpectedType)
   if (!(ExpectedType->isVoidPointerType() &&
-StrippedRVType->isPointerType()))
+(StrippedRVType->isPointerType() || 
StrippedRVType->isArrayType(
 return Diag(Arg->getBeginLoc(),
 diag::err_typecheck_convert_incompatible)
<< PassedType << ExpectedType << 1 << 0 << 0;
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -15171,8 +15171,12 @@
const CallExpr *E) {
   SmallVector Ops;
 
-  for (unsigned i = 0, e = E->getNumArgs(); i != e; i++)
-Ops.push_back(EmitScalarExpr(E->getArg(i)));
+  for (unsigned i = 0, e = E->getNumArgs(); i != e; i++) {
+if (E->getArg(i)->getType()->isArrayType())
+  Ops.push_back(EmitArrayToPointerDecay(E->getArg(i)).getPointer());
+else
+  Ops.push_back(EmitScalarExpr(E->getArg(i)));
+  }
 
   Intrinsic::ID ID = Intrinsic::not_intrinsic;
 


Index: clang/test/Sema/ppc-pair-mma-types.c
===
--- clang/test/Sema/ppc-pair-mma-types.c
+++ clang/test/Sema/ppc-pair-mma-types.c
@@ -339,20 +339,20 @@
 
 void testRestrictQualifiedPointer1(int *__restrict acc) {
   vector float arr[4];
-  __builtin_mma_disassemble_acc((void *)arr, acc); // expected-error {{passing 'int *restrict' to parameter of incompatible type '__vector_quad *'}}
+  __builtin_mma_disassemble_acc(arr, acc); // expected-error {{passing 'int *restrict' to parameter of incompatible type '__vector_quad *'}}
 }
 
 void testRestrictQualifiedPointer2(__vector_quad *__restrict acc) {
   vector float arr[4];
-  __builtin_mma_disassemble_acc((void *)arr, acc);
+  __builtin_mma_disassemble_acc(arr, acc);
 }
 
 void testVolatileQualifiedPointer1(int *__volatile acc) {
   vector float arr[4];
-  __builtin_mma_disassemble_acc((void *)arr, acc); // expected-error {{passing 'int *volatile' to parameter of incompatible type '__vector_quad *'}}
+  __builtin_mma_disassemble_acc(arr, acc); // expected-error {{passing 'int *volatile' to parameter of incompatible type '__vector_quad *'}}
 }
 
 void testVolatileQualifiedPointer2(__vector_quad *__volatile acc) {
   vector float arr[4];
-  __builtin_mma_disassemble_acc((void *)arr, acc);
+  __builtin_mma_disassemble_acc(arr, acc);
 }
Index: clang/lib/Sema/SemaChecking.cpp
===
--- 

[PATCH] D113306: [PowerPC] Allow MMA built-ins to accept non-void pointers and arrays

[Ahsan Saghir via Phabricator via cfe-commits]

saghir created this revision.
Herald added subscribers: shchenz, kbarton, nemanjai.
saghir requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Calls to MMA builtins that take pointer to void
do not accept other pointers/arrays whereas normal
functions with the same parameter do. This patch
allows MMA built-ins to accept non-void pointers
and arrays.


Repository:
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https://reviews.llvm.org/D113306

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/Sema/ppc-pair-mma-types.c


Index: clang/test/Sema/ppc-pair-mma-types.c
===
--- clang/test/Sema/ppc-pair-mma-types.c
+++ clang/test/Sema/ppc-pair-mma-types.c
@@ -339,20 +339,20 @@
 
 void testRestrictQualifiedPointer1(int *__restrict acc) {
   vector float arr[4];
-  __builtin_mma_disassemble_acc((void *)arr, acc); // expected-error {{passing 
'int *restrict' to parameter of incompatible type '__vector_quad *'}}
+  __builtin_mma_disassemble_acc(arr, acc); // expected-error {{passing 'int 
*restrict' to parameter of incompatible type '__vector_quad *'}}
 }
 
 void testRestrictQualifiedPointer2(__vector_quad *__restrict acc) {
   vector float arr[4];
-  __builtin_mma_disassemble_acc((void *)arr, acc);
+  __builtin_mma_disassemble_acc(arr, acc);
 }
 
 void testVolatileQualifiedPointer1(int *__volatile acc) {
   vector float arr[4];
-  __builtin_mma_disassemble_acc((void *)arr, acc); // expected-error {{passing 
'int *volatile' to parameter of incompatible type '__vector_quad *'}}
+  __builtin_mma_disassemble_acc(arr, acc); // expected-error {{passing 'int 
*volatile' to parameter of incompatible type '__vector_quad *'}}
 }
 
 void testVolatileQualifiedPointer2(__vector_quad *__volatile acc) {
   vector float arr[4];
-  __builtin_mma_disassemble_acc((void *)arr, acc);
+  __builtin_mma_disassemble_acc(arr, acc);
 }
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -7431,11 +7431,11 @@
   StrippedRVType = StrippedRVType.getCanonicalType().getUnqualifiedType();
 
 // The only case where the argument type and expected type are allowed to
-// mismatch is if the argument type is a non-void pointer and expected type
-// is a void pointer.
+// mismatch is if the argument type is a non-void pointer (or array) and
+// expected type is a void pointer.
 if (StrippedRVType != ExpectedType)
   if (!(ExpectedType->isVoidPointerType() &&
-StrippedRVType->isPointerType()))
+(StrippedRVType->isPointerType() || 
StrippedRVType->isArrayType(
 return Diag(Arg->getBeginLoc(),
 diag::err_typecheck_convert_incompatible)
<< PassedType << ExpectedType << 1 << 0 << 0;
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -15166,8 +15166,12 @@
const CallExpr *E) {
   SmallVector Ops;
 
-  for (unsigned i = 0, e = E->getNumArgs(); i != e; i++)
-Ops.push_back(EmitScalarExpr(E->getArg(i)));
+  for (unsigned i = 0, e = E->getNumArgs(); i != e; i++) {
+if (E->getArg(i)->getType()->isArrayType())
+  Ops.push_back(EmitArrayToPointerDecay(E->getArg(i)).getPointer());
+else
+  Ops.push_back(EmitScalarExpr(E->getArg(i)));
+  }
 
   Intrinsic::ID ID = Intrinsic::not_intrinsic;
 


Index: clang/test/Sema/ppc-pair-mma-types.c
===
--- clang/test/Sema/ppc-pair-mma-types.c
+++ clang/test/Sema/ppc-pair-mma-types.c
@@ -339,20 +339,20 @@
 
 void testRestrictQualifiedPointer1(int *__restrict acc) {
   vector float arr[4];
-  __builtin_mma_disassemble_acc((void *)arr, acc); // expected-error {{passing 'int *restrict' to parameter of incompatible type '__vector_quad *'}}
+  __builtin_mma_disassemble_acc(arr, acc); // expected-error {{passing 'int *restrict' to parameter of incompatible type '__vector_quad *'}}
 }
 
 void testRestrictQualifiedPointer2(__vector_quad *__restrict acc) {
   vector float arr[4];
-  __builtin_mma_disassemble_acc((void *)arr, acc);
+  __builtin_mma_disassemble_acc(arr, acc);
 }
 
 void testVolatileQualifiedPointer1(int *__volatile acc) {
   vector float arr[4];
-  __builtin_mma_disassemble_acc((void *)arr, acc); // expected-error {{passing 'int *volatile' to parameter of incompatible type '__vector_quad *'}}
+  __builtin_mma_disassemble_acc(arr, acc); // expected-error {{passing 'int *volatile' to parameter of incompatible type '__vector_quad *'}}
 }
 
 void testVolatileQualifiedPointer2(__vector_quad *__volatile acc) {
   vector float arr[4];
-  __builtin_mma_disassemble_acc((void *)arr, acc);
+  

[PATCH] D106550: [PowerPC] Allow MMA built-ins to accept restrict and volatile qualified pointers

[Ahsan Saghir via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG564e082d0954: [PowerPC] Allow MMA built-ins to accept 
restrict and volatile qualified pointers (authored by saghir).

Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106550/new/

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Files:
  clang/lib/Sema/SemaChecking.cpp
  clang/test/Sema/ppc-pair-mma-types.c


Index: clang/test/Sema/ppc-pair-mma-types.c
===
--- clang/test/Sema/ppc-pair-mma-types.c
+++ clang/test/Sema/ppc-pair-mma-types.c
@@ -336,3 +336,23 @@
   __vector_pair vp = __builtin_vsx_lxvp(l, v); // expected-error {{passing 
'__vector int' (vector of 4 'int' values) to parameter of incompatible type 
'const __vector_pair *'}}
   __builtin_vsx_stxvp(vp, l, s);   // expected-error {{passing 
'unsigned short' to parameter of incompatible type 'const __vector_pair *'}}
 }
+
+void testRestrictQualifiedPointer1(int *__restrict acc) {
+  vector float arr[4];
+  __builtin_mma_disassemble_acc((void *)arr, acc); // expected-error {{passing 
'int *restrict' to parameter of incompatible type '__vector_quad *'}}
+}
+
+void testRestrictQualifiedPointer2(__vector_quad *__restrict acc) {
+  vector float arr[4];
+  __builtin_mma_disassemble_acc((void *)arr, acc);
+}
+
+void testVolatileQualifiedPointer1(int *__volatile acc) {
+  vector float arr[4];
+  __builtin_mma_disassemble_acc((void *)arr, acc); // expected-error {{passing 
'int *volatile' to parameter of incompatible type '__vector_quad *'}}
+}
+
+void testVolatileQualifiedPointer2(__vector_quad *__volatile acc) {
+  vector float arr[4];
+  __builtin_mma_disassemble_acc((void *)arr, acc);
+}
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -7527,13 +7527,23 @@
 }
 
 Expr *Arg = TheCall->getArg(ArgNum);
-QualType ArgType = Arg->getType();
-
-if ((ExpectedType->isVoidPointerType() && !ArgType->isPointerType()) ||
-(!ExpectedType->isVoidPointerType() &&
-   ArgType.getCanonicalType() != ExpectedType))
-  return Diag(Arg->getBeginLoc(), diag::err_typecheck_convert_incompatible)
- << ArgType << ExpectedType << 1 << 0 << 0;
+QualType PassedType = Arg->getType();
+QualType StrippedRVType = PassedType.getCanonicalType();
+
+// Strip Restrict/Volatile qualifiers.
+if (StrippedRVType.isRestrictQualified() ||
+StrippedRVType.isVolatileQualified())
+  StrippedRVType = StrippedRVType.getCanonicalType().getUnqualifiedType();
+
+// The only case where the argument type and expected type are allowed to
+// mismatch is if the argument type is a non-void pointer and expected type
+// is a void pointer.
+if (StrippedRVType != ExpectedType)
+  if (!(ExpectedType->isVoidPointerType() &&
+StrippedRVType->isPointerType()))
+return Diag(Arg->getBeginLoc(),
+diag::err_typecheck_convert_incompatible)
+   << PassedType << ExpectedType << 1 << 0 << 0;
 
 // If the value of the Mask is not 0, we have a constraint in the size of
 // the integer argument so here we ensure the argument is a constant that


Index: clang/test/Sema/ppc-pair-mma-types.c
===
--- clang/test/Sema/ppc-pair-mma-types.c
+++ clang/test/Sema/ppc-pair-mma-types.c
@@ -336,3 +336,23 @@
   __vector_pair vp = __builtin_vsx_lxvp(l, v); // expected-error {{passing '__vector int' (vector of 4 'int' values) to parameter of incompatible type 'const __vector_pair *'}}
   __builtin_vsx_stxvp(vp, l, s);   // expected-error {{passing 'unsigned short' to parameter of incompatible type 'const __vector_pair *'}}
 }
+
+void testRestrictQualifiedPointer1(int *__restrict acc) {
+  vector float arr[4];
+  __builtin_mma_disassemble_acc((void *)arr, acc); // expected-error {{passing 'int *restrict' to parameter of incompatible type '__vector_quad *'}}
+}
+
+void testRestrictQualifiedPointer2(__vector_quad *__restrict acc) {
+  vector float arr[4];
+  __builtin_mma_disassemble_acc((void *)arr, acc);
+}
+
+void testVolatileQualifiedPointer1(int *__volatile acc) {
+  vector float arr[4];
+  __builtin_mma_disassemble_acc((void *)arr, acc); // expected-error {{passing 'int *volatile' to parameter of incompatible type '__vector_quad *'}}
+}
+
+void testVolatileQualifiedPointer2(__vector_quad *__volatile acc) {
+  vector float arr[4];
+  __builtin_mma_disassemble_acc((void *)arr, acc);
+}
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -7527,13 +7527,23 @@
 }
 
 Expr *Arg = TheCall->getArg(ArgNum);
- 

[PATCH] D106550: [PowerPC] Allow MMA built-ins to accept restrict and volatile qualified pointers

[Ahsan Saghir via Phabricator via cfe-commits]

saghir updated this revision to Diff 375629.
saghir added a comment.

Stripped RV qualifiers for Sema checking.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106550/new/

https://reviews.llvm.org/D106550

Files:
  clang/lib/Sema/SemaChecking.cpp
  clang/test/Sema/ppc-pair-mma-types.c


Index: clang/test/Sema/ppc-pair-mma-types.c
===
--- clang/test/Sema/ppc-pair-mma-types.c
+++ clang/test/Sema/ppc-pair-mma-types.c
@@ -336,3 +336,23 @@
   __vector_pair vp = __builtin_vsx_lxvp(l, v); // expected-error {{passing 
'__vector int' (vector of 4 'int' values) to parameter of incompatible type 
'const __vector_pair *'}}
   __builtin_vsx_stxvp(vp, l, s);   // expected-error {{passing 
'unsigned short' to parameter of incompatible type 'const __vector_pair *'}}
 }
+
+void testRestrictQualifiedPointer1(int *__restrict acc) {
+  vector float arr[4];
+  __builtin_mma_disassemble_acc((void *)arr, acc); // expected-error {{passing 
'int *restrict' to parameter of incompatible type '__vector_quad *'}}
+}
+
+void testRestrictQualifiedPointer2(__vector_quad *__restrict acc) {
+  vector float arr[4];
+  __builtin_mma_disassemble_acc((void *)arr, acc);
+}
+
+void testVolatileQualifiedPointer1(int *__volatile acc) {
+  vector float arr[4];
+  __builtin_mma_disassemble_acc((void *)arr, acc); // expected-error {{passing 
'int *volatile' to parameter of incompatible type '__vector_quad *'}}
+}
+
+void testVolatileQualifiedPointer2(__vector_quad *__volatile acc) {
+  vector float arr[4];
+  __builtin_mma_disassemble_acc((void *)arr, acc);
+}
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -7472,13 +7472,23 @@
 }
 
 Expr *Arg = TheCall->getArg(ArgNum);
-QualType ArgType = Arg->getType();
-
-if ((ExpectedType->isVoidPointerType() && !ArgType->isPointerType()) ||
-(!ExpectedType->isVoidPointerType() &&
-   ArgType.getCanonicalType() != ExpectedType))
-  return Diag(Arg->getBeginLoc(), diag::err_typecheck_convert_incompatible)
- << ArgType << ExpectedType << 1 << 0 << 0;
+QualType PassedType = Arg->getType();
+QualType StrippedRVType = PassedType.getCanonicalType();
+
+// Strip Restrict/Volatile qualifiers.
+if (StrippedRVType.isRestrictQualified() ||
+StrippedRVType.isVolatileQualified())
+  StrippedRVType = StrippedRVType.getCanonicalType().getUnqualifiedType();
+
+// The only case where the argument type and expected type are allowed to
+// mismatch is if the argument type is a non-void pointer and expected type
+// is a void pointer.
+if (StrippedRVType != ExpectedType)
+  if (!(ExpectedType->isVoidPointerType() &&
+StrippedRVType->isPointerType()))
+return Diag(Arg->getBeginLoc(),
+diag::err_typecheck_convert_incompatible)
+   << PassedType << ExpectedType << 1 << 0 << 0;
 
 // If the value of the Mask is not 0, we have a constraint in the size of
 // the integer argument so here we ensure the argument is a constant that


Index: clang/test/Sema/ppc-pair-mma-types.c
===
--- clang/test/Sema/ppc-pair-mma-types.c
+++ clang/test/Sema/ppc-pair-mma-types.c
@@ -336,3 +336,23 @@
   __vector_pair vp = __builtin_vsx_lxvp(l, v); // expected-error {{passing '__vector int' (vector of 4 'int' values) to parameter of incompatible type 'const __vector_pair *'}}
   __builtin_vsx_stxvp(vp, l, s);   // expected-error {{passing 'unsigned short' to parameter of incompatible type 'const __vector_pair *'}}
 }
+
+void testRestrictQualifiedPointer1(int *__restrict acc) {
+  vector float arr[4];
+  __builtin_mma_disassemble_acc((void *)arr, acc); // expected-error {{passing 'int *restrict' to parameter of incompatible type '__vector_quad *'}}
+}
+
+void testRestrictQualifiedPointer2(__vector_quad *__restrict acc) {
+  vector float arr[4];
+  __builtin_mma_disassemble_acc((void *)arr, acc);
+}
+
+void testVolatileQualifiedPointer1(int *__volatile acc) {
+  vector float arr[4];
+  __builtin_mma_disassemble_acc((void *)arr, acc); // expected-error {{passing 'int *volatile' to parameter of incompatible type '__vector_quad *'}}
+}
+
+void testVolatileQualifiedPointer2(__vector_quad *__volatile acc) {
+  vector float arr[4];
+  __builtin_mma_disassemble_acc((void *)arr, acc);
+}
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -7472,13 +7472,23 @@
 }
 
 Expr *Arg = TheCall->getArg(ArgNum);
-QualType ArgType = Arg->getType();
-
-if ((ExpectedType->isVoidPointerType() && !ArgType->isPointerType()) ||
-

[PATCH] D107647: [PowerPC] MMA - Add __builtin_vsx_build_pair and __builtin_mma_build_acc builtins

[Ahsan Saghir via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG593b074a096c: [PowerPC] MMA - Add __builtin_vsx_build_pair 
and __builtin_mma_build_acc… (authored by saghir).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107647/new/

https://reviews.llvm.org/D107647

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-build-pair-mma.c
  clang/test/Sema/ppc-pair-mma-types.c
  clang/test/SemaCXX/ppc-pair-mma-types.cpp

Index: clang/test/SemaCXX/ppc-pair-mma-types.cpp
===
--- clang/test/SemaCXX/ppc-pair-mma-types.cpp
+++ clang/test/SemaCXX/ppc-pair-mma-types.cpp
@@ -370,6 +370,7 @@
 return *vpp; // expected-error {{invalid use of PPC MMA type}}
   };
   auto f3 = [](vector unsigned char vc) { __vector_pair vp; __builtin_vsx_assemble_pair(, vc, vc); return vp; }; // expected-error {{invalid use of PPC MMA type}}
+  auto f4 = [](vector unsigned char vc) { __vector_pair vp; __builtin_vsx_build_pair(, vc, vc); return vp; }; // expected-error {{invalid use of PPC MMA type}}
 }
 
 // cast
Index: clang/test/Sema/ppc-pair-mma-types.c
===
--- clang/test/Sema/ppc-pair-mma-types.c
+++ clang/test/Sema/ppc-pair-mma-types.c
@@ -249,6 +249,7 @@
   __vector_pair vp1 = *vpp;
   __vector_pair vp2;
   __builtin_vsx_assemble_pair(, vc, vc);
+  __builtin_vsx_build_pair(, vc, vc);
   __vector_pair vp3;
   __vector_quad vq;
   __builtin_mma_xvf64ger(, vp3, vc);
Index: clang/test/CodeGen/builtins-ppc-build-pair-mma.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-build-pair-mma.c
@@ -0,0 +1,51 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -O3 -triple powerpc64le-unknown-unknown -target-cpu pwr10 \
+// RUN: -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK-LE
+// RUN: %clang_cc1 -O3 -triple powerpc64-unknown-unknown -target-cpu pwr10 \
+// RUN: -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK-BE
+
+// CHECK-LE-LABEL: @test1(
+// CHECK-LE-NEXT:  entry:
+// CHECK-LE-NEXT:[[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> [[VC4:%.*]], <16 x i8> [[VC3:%.*]], <16 x i8> [[VC2:%.*]], <16 x i8> [[VC1:%.*]])
+// CHECK-LE-NEXT:[[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
+// CHECK-LE-NEXT:store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa [[TBAA2:![0-9]+]]
+// CHECK-LE-NEXT:ret void
+//
+// CHECK-BE-LABEL: @test1(
+// CHECK-BE-NEXT:  entry:
+// CHECK-BE-NEXT:[[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> [[VC1:%.*]], <16 x i8> [[VC2:%.*]], <16 x i8> [[VC3:%.*]], <16 x i8> [[VC4:%.*]])
+// CHECK-BE-NEXT:[[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
+// CHECK-BE-NEXT:store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa [[TBAA2:![0-9]+]]
+// CHECK-BE-NEXT:ret void
+//
+void test1(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc1, vector unsigned char vc2,
+vector unsigned char vc3, vector unsigned char vc4, unsigned char *resp) {
+  __vector_quad vq = *((__vector_quad *)vqp);
+  __vector_pair vp = *((__vector_pair *)vpp);
+  __vector_quad res;
+  __builtin_mma_build_acc(, vc1, vc2, vc3, vc4);
+  *((__vector_quad *)resp) = res;
+}
+
+// CHECK-LE-LABEL: @test2(
+// CHECK-LE-NEXT:  entry:
+// CHECK-LE-NEXT:[[TMP0:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> [[VC2:%.*]], <16 x i8> [[VC1:%.*]])
+// CHECK-LE-NEXT:[[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <256 x i1>*
+// CHECK-LE-NEXT:store <256 x i1> [[TMP0]], <256 x i1>* [[TMP1]], align 32, !tbaa [[TBAA6:![0-9]+]]
+// CHECK-LE-NEXT:ret void
+//
+// CHECK-BE-LABEL: @test2(
+// CHECK-BE-NEXT:  entry:
+// CHECK-BE-NEXT:[[TMP0:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> [[VC1:%.*]], <16 x i8> [[VC2:%.*]])
+// CHECK-BE-NEXT:[[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <256 x i1>*
+// CHECK-BE-NEXT:store <256 x i1> [[TMP0]], <256 x i1>* [[TMP1]], align 32, !tbaa [[TBAA6:![0-9]+]]
+// CHECK-BE-NEXT:ret void
+//
+void test2(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc1,
+vector unsigned char vc2, unsigned char *resp) {
+  __vector_quad vq = *((__vector_quad *)vqp);
+  __vector_pair vp = *((__vector_pair *)vpp);
+  __vector_pair res;
+  __builtin_vsx_build_pair(, vc1, vc2);
+  *((__vector_pair *)resp) = res;
+}
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -15910,6 +15910,17 @@
   }
   return Call;
 }
+if (BuiltinID == 

[PATCH] D107647: [PowerPC] MMA - Add __builtin_vsx_build_pair and __builtin_mma_build_acc builtins

[Ahsan Saghir via Phabricator via cfe-commits]

saghir updated this revision to Diff 375443.
saghir added a comment.

Addressed review comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107647/new/

https://reviews.llvm.org/D107647

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-build-pair-mma.c
  clang/test/Sema/ppc-pair-mma-types.c
  clang/test/SemaCXX/ppc-pair-mma-types.cpp

Index: clang/test/SemaCXX/ppc-pair-mma-types.cpp
===
--- clang/test/SemaCXX/ppc-pair-mma-types.cpp
+++ clang/test/SemaCXX/ppc-pair-mma-types.cpp
@@ -370,6 +370,7 @@
 return *vpp; // expected-error {{invalid use of PPC MMA type}}
   };
   auto f3 = [](vector unsigned char vc) { __vector_pair vp; __builtin_vsx_assemble_pair(, vc, vc); return vp; }; // expected-error {{invalid use of PPC MMA type}}
+  auto f4 = [](vector unsigned char vc) { __vector_pair vp; __builtin_vsx_build_pair(, vc, vc); return vp; }; // expected-error {{invalid use of PPC MMA type}}
 }
 
 // cast
Index: clang/test/Sema/ppc-pair-mma-types.c
===
--- clang/test/Sema/ppc-pair-mma-types.c
+++ clang/test/Sema/ppc-pair-mma-types.c
@@ -249,6 +249,7 @@
   __vector_pair vp1 = *vpp;
   __vector_pair vp2;
   __builtin_vsx_assemble_pair(, vc, vc);
+  __builtin_vsx_build_pair(, vc, vc);
   __vector_pair vp3;
   __vector_quad vq;
   __builtin_mma_xvf64ger(, vp3, vc);
Index: clang/test/CodeGen/builtins-ppc-build-pair-mma.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-build-pair-mma.c
@@ -0,0 +1,51 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -O3 -triple powerpc64le-unknown-unknown -target-cpu pwr10 \
+// RUN: -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK-LE
+// RUN: %clang_cc1 -O3 -triple powerpc64-unknown-unknown -target-cpu pwr10 \
+// RUN: -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK-BE
+
+// CHECK-LE-LABEL: @test1(
+// CHECK-LE-NEXT:  entry:
+// CHECK-LE-NEXT:[[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> [[VC4:%.*]], <16 x i8> [[VC3:%.*]], <16 x i8> [[VC2:%.*]], <16 x i8> [[VC1:%.*]])
+// CHECK-LE-NEXT:[[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
+// CHECK-LE-NEXT:store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa [[TBAA2:![0-9]+]]
+// CHECK-LE-NEXT:ret void
+//
+// CHECK-BE-LABEL: @test1(
+// CHECK-BE-NEXT:  entry:
+// CHECK-BE-NEXT:[[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> [[VC1:%.*]], <16 x i8> [[VC2:%.*]], <16 x i8> [[VC3:%.*]], <16 x i8> [[VC4:%.*]])
+// CHECK-BE-NEXT:[[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
+// CHECK-BE-NEXT:store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa [[TBAA2:![0-9]+]]
+// CHECK-BE-NEXT:ret void
+//
+void test1(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc1, vector unsigned char vc2,
+vector unsigned char vc3, vector unsigned char vc4, unsigned char *resp) {
+  __vector_quad vq = *((__vector_quad *)vqp);
+  __vector_pair vp = *((__vector_pair *)vpp);
+  __vector_quad res;
+  __builtin_mma_build_acc(, vc1, vc2, vc3, vc4);
+  *((__vector_quad *)resp) = res;
+}
+
+// CHECK-LE-LABEL: @test2(
+// CHECK-LE-NEXT:  entry:
+// CHECK-LE-NEXT:[[TMP0:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> [[VC2:%.*]], <16 x i8> [[VC1:%.*]])
+// CHECK-LE-NEXT:[[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <256 x i1>*
+// CHECK-LE-NEXT:store <256 x i1> [[TMP0]], <256 x i1>* [[TMP1]], align 32, !tbaa [[TBAA6:![0-9]+]]
+// CHECK-LE-NEXT:ret void
+//
+// CHECK-BE-LABEL: @test2(
+// CHECK-BE-NEXT:  entry:
+// CHECK-BE-NEXT:[[TMP0:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> [[VC1:%.*]], <16 x i8> [[VC2:%.*]])
+// CHECK-BE-NEXT:[[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <256 x i1>*
+// CHECK-BE-NEXT:store <256 x i1> [[TMP0]], <256 x i1>* [[TMP1]], align 32, !tbaa [[TBAA6:![0-9]+]]
+// CHECK-BE-NEXT:ret void
+//
+void test2(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc1,
+vector unsigned char vc2, unsigned char *resp) {
+  __vector_quad vq = *((__vector_quad *)vqp);
+  __vector_pair vp = *((__vector_pair *)vpp);
+  __vector_pair res;
+  __builtin_vsx_build_pair(, vc1, vc2);
+  *((__vector_pair *)resp) = res;
+}
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -15910,6 +15910,17 @@
   }
   return Call;
 }
+if (BuiltinID == PPC::BI__builtin_vsx_build_pair ||
+BuiltinID == PPC::BI__builtin_mma_build_acc) {
+  // Reverse the order of the operands for LE, so the
+  // same builtin call can be 

[PATCH] D106550: [PowerPC] Allow MMA built-ins to accept restrict and volatile qualified pointers

[Ahsan Saghir via Phabricator via cfe-commits]

saghir updated this revision to Diff 374529.
saghir added a comment.

Changed approach for Sema checks.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106550/new/

https://reviews.llvm.org/D106550

Files:
  clang/lib/Sema/SemaChecking.cpp
  clang/test/Sema/ppc-pair-mma-types.c


Index: clang/test/Sema/ppc-pair-mma-types.c
===
--- clang/test/Sema/ppc-pair-mma-types.c
+++ clang/test/Sema/ppc-pair-mma-types.c
@@ -335,3 +335,23 @@
   __vector_pair vp = __builtin_vsx_lxvp(ll, v); // expected-error {{passing 
'__vector int' (vector of 4 'int' values) to parameter of incompatible type 
'const __vector_pair *'}}
   __builtin_vsx_stxvp(vp, ll, s);   // expected-error {{passing 
'unsigned short' to parameter of incompatible type 'const __vector_pair *'}}
 }
+
+void testRestrictQualifiedPointer1(int *__restrict acc) {
+  vector float arr[4];
+  __builtin_mma_disassemble_acc((void*)arr, acc); // expected-error {{passing 
'int *restrict' to parameter of incompatible type '__vector_quad *'}}
+}
+
+void testRestrictQualifiedPointer2(__vector_quad *__restrict acc) {
+  vector float arr[4];
+  __builtin_mma_disassemble_acc((void*)arr, acc);
+}
+
+void testVolatileQualifiedPointer1(int *__volatile acc) {
+  vector float arr[4];
+  __builtin_mma_disassemble_acc((void*)arr, acc); // expected-error {{passing 
'int *volatile' to parameter of incompatible type '__vector_quad *'}}
+}
+
+void testVolatileQualifiedPointer2(__vector_quad *__volatile acc) {
+  vector float arr[4];
+  __builtin_mma_disassemble_acc((void*)arr, acc);
+}
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -7436,10 +7436,15 @@
 
 Expr *Arg = TheCall->getArg(ArgNum);
 QualType ArgType = Arg->getType();
+bool IsRestrictOrVolatile =
+ArgType.isRestrictQualified() || ArgType.isVolatileQualified();
 
 if ((ExpectedType->isVoidPointerType() && !ArgType->isPointerType()) ||
 (!ExpectedType->isVoidPointerType() &&
-   ArgType.getCanonicalType() != ExpectedType))
+ ((IsRestrictOrVolatile &&
+   ArgType.getCanonicalType().getUnqualifiedType() != ExpectedType) ||
+  (!IsRestrictOrVolatile &&
+   ArgType.getCanonicalType() != ExpectedType
   return Diag(Arg->getBeginLoc(), diag::err_typecheck_convert_incompatible)
  << ArgType << ExpectedType << 1 << 0 << 0;
 


Index: clang/test/Sema/ppc-pair-mma-types.c
===
--- clang/test/Sema/ppc-pair-mma-types.c
+++ clang/test/Sema/ppc-pair-mma-types.c
@@ -335,3 +335,23 @@
   __vector_pair vp = __builtin_vsx_lxvp(ll, v); // expected-error {{passing '__vector int' (vector of 4 'int' values) to parameter of incompatible type 'const __vector_pair *'}}
   __builtin_vsx_stxvp(vp, ll, s);   // expected-error {{passing 'unsigned short' to parameter of incompatible type 'const __vector_pair *'}}
 }
+
+void testRestrictQualifiedPointer1(int *__restrict acc) {
+  vector float arr[4];
+  __builtin_mma_disassemble_acc((void*)arr, acc); // expected-error {{passing 'int *restrict' to parameter of incompatible type '__vector_quad *'}}
+}
+
+void testRestrictQualifiedPointer2(__vector_quad *__restrict acc) {
+  vector float arr[4];
+  __builtin_mma_disassemble_acc((void*)arr, acc);
+}
+
+void testVolatileQualifiedPointer1(int *__volatile acc) {
+  vector float arr[4];
+  __builtin_mma_disassemble_acc((void*)arr, acc); // expected-error {{passing 'int *volatile' to parameter of incompatible type '__vector_quad *'}}
+}
+
+void testVolatileQualifiedPointer2(__vector_quad *__volatile acc) {
+  vector float arr[4];
+  __builtin_mma_disassemble_acc((void*)arr, acc);
+}
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -7436,10 +7436,15 @@
 
 Expr *Arg = TheCall->getArg(ArgNum);
 QualType ArgType = Arg->getType();
+bool IsRestrictOrVolatile =
+ArgType.isRestrictQualified() || ArgType.isVolatileQualified();
 
 if ((ExpectedType->isVoidPointerType() && !ArgType->isPointerType()) ||
 (!ExpectedType->isVoidPointerType() &&
-   ArgType.getCanonicalType() != ExpectedType))
+ ((IsRestrictOrVolatile &&
+   ArgType.getCanonicalType().getUnqualifiedType() != ExpectedType) ||
+  (!IsRestrictOrVolatile &&
+   ArgType.getCanonicalType() != ExpectedType
   return Diag(Arg->getBeginLoc(), diag::err_typecheck_convert_incompatible)
  << ArgType << ExpectedType << 1 << 0 << 0;
 
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[PATCH] D106550: [PowerPC] Allow MMA built-ins to accept restrict qualified pointers

[Ahsan Saghir via Phabricator via cfe-commits]

saghir updated this revision to Diff 372505.
saghir added a comment.

update test case name to be consistent with existing ones.


Repository:
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Files:
  clang/lib/Sema/SemaChecking.cpp
  clang/test/Sema/ppc-pair-mma-types.c


Index: clang/test/Sema/ppc-pair-mma-types.c
===
--- clang/test/Sema/ppc-pair-mma-types.c
+++ clang/test/Sema/ppc-pair-mma-types.c
@@ -335,3 +335,23 @@
   __vector_pair vp = __builtin_vsx_lxvp(ll, v); // expected-error {{passing 
'__vector int' (vector of 4 'int' values) to parameter of incompatible type 
'const __vector_pair *'}}
   __builtin_vsx_stxvp(vp, ll, s);   // expected-error {{passing 
'unsigned short' to parameter of incompatible type 'const __vector_pair *'}}
 }
+
+void testRestrictQualifiedPointer1(int *__restrict acc) {
+  vector float arr[4];
+  __builtin_mma_disassemble_acc((void*)arr, acc); // expected-error {{passing 
'int *restrict' to parameter of incompatible type '__vector_quad *'}}
+}
+
+void testRestrictQualifiedPointer2(__vector_quad *__restrict acc) {
+  vector float arr[4];
+  __builtin_mma_disassemble_acc((void*)arr, acc);
+}
+
+void testVolatileQualifiedPointer1(int *__volatile acc) {
+  vector float arr[4];
+  __builtin_mma_disassemble_acc((void*)arr, acc); // expected-error {{passing 
'int *volatile' to parameter of incompatible type '__vector_quad *'}}
+}
+
+void testVolatileQualifiedPointer2(__vector_quad *__volatile acc) {
+  vector float arr[4];
+  __builtin_mma_disassemble_acc((void*)arr, acc);
+}
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -7437,9 +7437,19 @@
 Expr *Arg = TheCall->getArg(ArgNum);
 QualType ArgType = Arg->getType();
 
-if ((ExpectedType->isVoidPointerType() && !ArgType->isPointerType()) ||
-(!ExpectedType->isVoidPointerType() &&
-   ArgType.getCanonicalType() != ExpectedType))
+// Checks to see if the argument type is valid.
+bool IsValidType = true;
+if (ExpectedType->isVoidPointerType() && !ArgType->isPointerType())
+  IsValidType = false;
+else if (!ExpectedType->isVoidPointerType()) {
+  if ((ArgType.isRestrictQualified() || ArgType.isVolatileQualified()) &&
+  ArgType.getCanonicalType().getUnqualifiedType() == ExpectedType)
+IsValidType = true;
+  else if (ArgType.getCanonicalType() != ExpectedType)
+IsValidType = false;
+}
+
+if (!IsValidType)
   return Diag(Arg->getBeginLoc(), diag::err_typecheck_convert_incompatible)
  << ArgType << ExpectedType << 1 << 0 << 0;
 


Index: clang/test/Sema/ppc-pair-mma-types.c
===
--- clang/test/Sema/ppc-pair-mma-types.c
+++ clang/test/Sema/ppc-pair-mma-types.c
@@ -335,3 +335,23 @@
   __vector_pair vp = __builtin_vsx_lxvp(ll, v); // expected-error {{passing '__vector int' (vector of 4 'int' values) to parameter of incompatible type 'const __vector_pair *'}}
   __builtin_vsx_stxvp(vp, ll, s);   // expected-error {{passing 'unsigned short' to parameter of incompatible type 'const __vector_pair *'}}
 }
+
+void testRestrictQualifiedPointer1(int *__restrict acc) {
+  vector float arr[4];
+  __builtin_mma_disassemble_acc((void*)arr, acc); // expected-error {{passing 'int *restrict' to parameter of incompatible type '__vector_quad *'}}
+}
+
+void testRestrictQualifiedPointer2(__vector_quad *__restrict acc) {
+  vector float arr[4];
+  __builtin_mma_disassemble_acc((void*)arr, acc);
+}
+
+void testVolatileQualifiedPointer1(int *__volatile acc) {
+  vector float arr[4];
+  __builtin_mma_disassemble_acc((void*)arr, acc); // expected-error {{passing 'int *volatile' to parameter of incompatible type '__vector_quad *'}}
+}
+
+void testVolatileQualifiedPointer2(__vector_quad *__volatile acc) {
+  vector float arr[4];
+  __builtin_mma_disassemble_acc((void*)arr, acc);
+}
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -7437,9 +7437,19 @@
 Expr *Arg = TheCall->getArg(ArgNum);
 QualType ArgType = Arg->getType();
 
-if ((ExpectedType->isVoidPointerType() && !ArgType->isPointerType()) ||
-(!ExpectedType->isVoidPointerType() &&
-   ArgType.getCanonicalType() != ExpectedType))
+// Checks to see if the argument type is valid.
+bool IsValidType = true;
+if (ExpectedType->isVoidPointerType() && !ArgType->isPointerType())
+  IsValidType = false;
+else if (!ExpectedType->isVoidPointerType()) {
+  if ((ArgType.isRestrictQualified() || ArgType.isVolatileQualified()) &&
+  ArgType.getCanonicalType().getUnqualifiedType() 

[PATCH] D109624: [clang] Make the driver not diagnose errors on nonexistent linker inputs

[Ahsan Saghir via Phabricator via cfe-commits]

saghir added a comment.

In D109624#2998665 , @thakis wrote:

> In D109624#2998550 , @saghir wrote:
>
>> Hi, this change also breaks Power PC bots:
>>
>> 1. 
>> https://lab.llvm.org/buildbot/#/builders/19/builds/6451/steps/24/logs/stdio
>> 2. 
>> https://lab.llvm.org/buildbot/#/builders/18/builds/2443/steps/23/logs/stdio
>>
>> It fails consistently on our bots. Can you please take a look?
>>
>> Thanks!
>
> This will hopefully be better after b7bac5a172e51ed065b3b4dc64cc2d8831e8081c 
> .

Yes, my local build succeeded. One of the bots is green already, and the other 
one is building but should be fine too. Thanks for the prompt fix!


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[PATCH] D109624: [clang] Make the driver not diagnose errors on nonexistent linker inputs

[Ahsan Saghir via Phabricator via cfe-commits]

saghir added a comment.

Hi, this change also breaks Power PC bots:

1. https://lab.llvm.org/buildbot/#/builders/19/builds/6451/steps/24/logs/stdio
2. https://lab.llvm.org/buildbot/#/builders/18/builds/2443/steps/23/logs/stdio

It fails consistently on our bots. Can you please take a look?

Thanks!


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[PATCH] D106550: [PowerPC] Allow MMA built-ins to accept restrict qualified pointers

[Ahsan Saghir via Phabricator via cfe-commits]

saghir updated this revision to Diff 372151.
saghir added a comment.

Addressed review comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106550/new/

https://reviews.llvm.org/D106550

Files:
  clang/lib/Sema/SemaChecking.cpp
  clang/test/Sema/ppc-pair-mma-types.c


Index: clang/test/Sema/ppc-pair-mma-types.c
===
--- clang/test/Sema/ppc-pair-mma-types.c
+++ clang/test/Sema/ppc-pair-mma-types.c
@@ -335,3 +335,23 @@
   __vector_pair vp = __builtin_vsx_lxvp(ll, v); // expected-error {{passing 
'__vector int' (vector of 4 'int' values) to parameter of incompatible type 
'const __vector_pair *'}}
   __builtin_vsx_stxvp(vp, ll, s);   // expected-error {{passing 
'unsigned short' to parameter of incompatible type 'const __vector_pair *'}}
 }
+
+void testRestrictQualifiedPointer1(int *__restrict acc) {
+  vector float arr[4];
+  __builtin_mma_disassemble_acc((void*)arr, acc); // expected-error {{passing 
'int *restrict' to parameter of incompatible type '__vector_quad *'}}
+}
+
+void testRestrictQualifiedPointer2(__vector_quad *__restrict acc) {
+  vector float arr[4];
+  __builtin_mma_disassemble_acc((void*)arr, acc);
+}
+
+void VolatileQualifiedPointer1(int *__volatile acc) {
+  vector float arr[4];
+  __builtin_mma_disassemble_acc((void*)arr, acc); // expected-error {{passing 
'int *volatile' to parameter of incompatible type '__vector_quad *'}}
+}
+
+void testVolatileQualifiedPointer2(__vector_quad *__volatile acc) {
+  vector float arr[4];
+  __builtin_mma_disassemble_acc((void*)arr, acc);
+}
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -7437,9 +7437,19 @@
 Expr *Arg = TheCall->getArg(ArgNum);
 QualType ArgType = Arg->getType();
 
-if ((ExpectedType->isVoidPointerType() && !ArgType->isPointerType()) ||
-(!ExpectedType->isVoidPointerType() &&
-   ArgType.getCanonicalType() != ExpectedType))
+// Checks to see if the argument type is valid.
+bool IsValidType = true;
+if (ExpectedType->isVoidPointerType() && !ArgType->isPointerType())
+  IsValidType = false;
+else if (!ExpectedType->isVoidPointerType()) {
+  if ((ArgType.isRestrictQualified() || ArgType.isVolatileQualified()) &&
+  ArgType.getCanonicalType().getUnqualifiedType() == ExpectedType)
+IsValidType = true;
+  else if (ArgType.getCanonicalType() != ExpectedType)
+IsValidType = false;
+}
+
+if (!IsValidType)
   return Diag(Arg->getBeginLoc(), diag::err_typecheck_convert_incompatible)
  << ArgType << ExpectedType << 1 << 0 << 0;
 


Index: clang/test/Sema/ppc-pair-mma-types.c
===
--- clang/test/Sema/ppc-pair-mma-types.c
+++ clang/test/Sema/ppc-pair-mma-types.c
@@ -335,3 +335,23 @@
   __vector_pair vp = __builtin_vsx_lxvp(ll, v); // expected-error {{passing '__vector int' (vector of 4 'int' values) to parameter of incompatible type 'const __vector_pair *'}}
   __builtin_vsx_stxvp(vp, ll, s);   // expected-error {{passing 'unsigned short' to parameter of incompatible type 'const __vector_pair *'}}
 }
+
+void testRestrictQualifiedPointer1(int *__restrict acc) {
+  vector float arr[4];
+  __builtin_mma_disassemble_acc((void*)arr, acc); // expected-error {{passing 'int *restrict' to parameter of incompatible type '__vector_quad *'}}
+}
+
+void testRestrictQualifiedPointer2(__vector_quad *__restrict acc) {
+  vector float arr[4];
+  __builtin_mma_disassemble_acc((void*)arr, acc);
+}
+
+void VolatileQualifiedPointer1(int *__volatile acc) {
+  vector float arr[4];
+  __builtin_mma_disassemble_acc((void*)arr, acc); // expected-error {{passing 'int *volatile' to parameter of incompatible type '__vector_quad *'}}
+}
+
+void testVolatileQualifiedPointer2(__vector_quad *__volatile acc) {
+  vector float arr[4];
+  __builtin_mma_disassemble_acc((void*)arr, acc);
+}
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -7437,9 +7437,19 @@
 Expr *Arg = TheCall->getArg(ArgNum);
 QualType ArgType = Arg->getType();
 
-if ((ExpectedType->isVoidPointerType() && !ArgType->isPointerType()) ||
-(!ExpectedType->isVoidPointerType() &&
-   ArgType.getCanonicalType() != ExpectedType))
+// Checks to see if the argument type is valid.
+bool IsValidType = true;
+if (ExpectedType->isVoidPointerType() && !ArgType->isPointerType())
+  IsValidType = false;
+else if (!ExpectedType->isVoidPointerType()) {
+  if ((ArgType.isRestrictQualified() || ArgType.isVolatileQualified()) &&
+  ArgType.getCanonicalType().getUnqualifiedType() == ExpectedType)
+IsValidType = 

[PATCH] D107647: [PowerPC] MMA - Add __builtin_vsx_build_pair and __builtin_mma_build_acc builtins

[Ahsan Saghir via Phabricator via cfe-commits]

saghir updated this revision to Diff 372149.
saghir added a comment.

Addressed review comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107647/new/

https://reviews.llvm.org/D107647

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-build-pair-mma.c
  clang/test/Sema/ppc-pair-mma-types.c
  clang/test/SemaCXX/ppc-pair-mma-types.cpp

Index: clang/test/SemaCXX/ppc-pair-mma-types.cpp
===
--- clang/test/SemaCXX/ppc-pair-mma-types.cpp
+++ clang/test/SemaCXX/ppc-pair-mma-types.cpp
@@ -370,6 +370,7 @@
 return *vpp; // expected-error {{invalid use of PPC MMA type}}
   };
   auto f3 = [](vector unsigned char vc) { __vector_pair vp; __builtin_vsx_assemble_pair(, vc, vc); return vp; }; // expected-error {{invalid use of PPC MMA type}}
+  auto f4 = [](vector unsigned char vc) { __vector_pair vp; __builtin_vsx_build_pair(, vc, vc); return vp; }; // expected-error {{invalid use of PPC MMA type}}
 }
 
 // cast
Index: clang/test/Sema/ppc-pair-mma-types.c
===
--- clang/test/Sema/ppc-pair-mma-types.c
+++ clang/test/Sema/ppc-pair-mma-types.c
@@ -249,6 +249,7 @@
   __vector_pair vp1 = *vpp;
   __vector_pair vp2;
   __builtin_vsx_assemble_pair(, vc, vc);
+  __builtin_vsx_build_pair(, vc, vc);
   __vector_pair vp3;
   __vector_quad vq;
   __builtin_mma_xvf64ger(, vp3, vc);
Index: clang/test/CodeGen/builtins-ppc-build-pair-mma.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-build-pair-mma.c
@@ -0,0 +1,51 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -O3 -triple powerpc64le-unknown-unknown -target-cpu pwr10 \
+// RUN: -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK-LE
+// RUN: %clang_cc1 -O3 -triple powerpc64-unknown-unknown -target-cpu pwr10 \
+// RUN: -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK-BE
+
+// CHECK-LE-LABEL: @test1(
+// CHECK-LE-NEXT:  entry:
+// CHECK-LE-NEXT:[[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> [[VC4:%.*]], <16 x i8> [[VC3:%.*]], <16 x i8> [[VC2:%.*]], <16 x i8> [[VC1:%.*]])
+// CHECK-LE-NEXT:[[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
+// CHECK-LE-NEXT:store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa [[TBAA2:![0-9]+]]
+// CHECK-LE-NEXT:ret void
+//
+// CHECK-BE-LABEL: @test1(
+// CHECK-BE-NEXT:  entry:
+// CHECK-BE-NEXT:[[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> [[VC1:%.*]], <16 x i8> [[VC2:%.*]], <16 x i8> [[VC3:%.*]], <16 x i8> [[VC4:%.*]])
+// CHECK-BE-NEXT:[[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
+// CHECK-BE-NEXT:store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa [[TBAA2:![0-9]+]]
+// CHECK-BE-NEXT:ret void
+//
+void test1(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc1, vector unsigned char vc2,
+vector unsigned char vc3, vector unsigned char vc4, unsigned char *resp) {
+  __vector_quad vq = *((__vector_quad *)vqp);
+  __vector_pair vp = *((__vector_pair *)vpp);
+  __vector_quad res;
+  __builtin_mma_build_acc(, vc1, vc2, vc3, vc4);
+  *((__vector_quad *)resp) = res;
+}
+
+// CHECK-LE-LABEL: @test2(
+// CHECK-LE-NEXT:  entry:
+// CHECK-LE-NEXT:[[TMP0:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> [[VC2:%.*]], <16 x i8> [[VC1:%.*]])
+// CHECK-LE-NEXT:[[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <256 x i1>*
+// CHECK-LE-NEXT:store <256 x i1> [[TMP0]], <256 x i1>* [[TMP1]], align 32, !tbaa [[TBAA6:![0-9]+]]
+// CHECK-LE-NEXT:ret void
+//
+// CHECK-BE-LABEL: @test2(
+// CHECK-BE-NEXT:  entry:
+// CHECK-BE-NEXT:[[TMP0:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> [[VC1:%.*]], <16 x i8> [[VC2:%.*]])
+// CHECK-BE-NEXT:[[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <256 x i1>*
+// CHECK-BE-NEXT:store <256 x i1> [[TMP0]], <256 x i1>* [[TMP1]], align 32, !tbaa [[TBAA6:![0-9]+]]
+// CHECK-BE-NEXT:ret void
+//
+void test2(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc1,
+vector unsigned char vc2, unsigned char *resp) {
+  __vector_quad vq = *((__vector_quad *)vqp);
+  __vector_pair vp = *((__vector_pair *)vpp);
+  __vector_pair res;
+  __builtin_vsx_build_pair(, vc1, vc2);
+  *((__vector_pair *)resp) = res;
+}
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -15879,6 +15879,21 @@
   }
   return Call;
 }
+if (BuiltinID == PPC::BI__builtin_vsx_build_pair ||
+BuiltinID == PPC::BI__builtin_mma_build_acc) {
+  // Reverse the order of the operands for LE, so the
+  // same builtin call can be 

[PATCH] D109126: [PowerPC] [NFC] Add Big-Endian checks for existing MMA tests

[Ahsan Saghir via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG203cd01b54dd: [PowerPC] [NFC] Add Big-Endian checks for 
existing MMA tests (authored by saghir).

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Files:
  clang/test/CodeGen/builtins-ppc-pair-mma.c
  clang/test/Sema/ppc-pair-mma-types.c
  clang/test/SemaCXX/ppc-pair-mma-types.cpp


Index: clang/test/SemaCXX/ppc-pair-mma-types.cpp
===
--- clang/test/SemaCXX/ppc-pair-mma-types.cpp
+++ clang/test/SemaCXX/ppc-pair-mma-types.cpp
@@ -1,5 +1,7 @@
 // RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -fsyntax-only \
-// RUN:   -fcxx-exceptions -target-cpu future %s -verify
+// RUN:   -fcxx-exceptions -target-cpu pwr10 %s -verify
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -fsyntax-only \
+// RUN:   -fcxx-exceptions -target-cpu pwr10 %s -verify
 
 // vector quad
 
Index: clang/test/Sema/ppc-pair-mma-types.c
===
--- clang/test/Sema/ppc-pair-mma-types.c
+++ clang/test/Sema/ppc-pair-mma-types.c
@@ -1,5 +1,7 @@
 // RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -fsyntax-only \
-// RUN:   -target-cpu future %s -verify
+// RUN:   -target-cpu pwr10 %s -verify
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -fsyntax-only \
+// RUN:   -target-cpu pwr10 %s -verify
 
 // The use of PPC MMA types is strongly restricted. Non-pointer MMA variables
 // can only be declared in functions and a limited number of operations are
Index: clang/test/CodeGen/builtins-ppc-pair-mma.c
===
--- clang/test/CodeGen/builtins-ppc-pair-mma.c
+++ clang/test/CodeGen/builtins-ppc-pair-mma.c
@@ -1,5 +1,8 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-// RUN: %clang_cc1 -O3 -triple powerpc64le-unknown-unknown -target-cpu future 
-emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -O3 -triple powerpc64le-unknown-unknown -target-cpu pwr10 \
+// RUN:  -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -O3 -triple powerpc64-unknown-unknown -target-cpu pwr10 \
+// RUN: -emit-llvm %s -o - | FileCheck %s
 
 // CHECK-LABEL: @test1(
 // CHECK-NEXT:  entry:


Index: clang/test/SemaCXX/ppc-pair-mma-types.cpp
===
--- clang/test/SemaCXX/ppc-pair-mma-types.cpp
+++ clang/test/SemaCXX/ppc-pair-mma-types.cpp
@@ -1,5 +1,7 @@
 // RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -fsyntax-only \
-// RUN:   -fcxx-exceptions -target-cpu future %s -verify
+// RUN:   -fcxx-exceptions -target-cpu pwr10 %s -verify
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -fsyntax-only \
+// RUN:   -fcxx-exceptions -target-cpu pwr10 %s -verify
 
 // vector quad
 
Index: clang/test/Sema/ppc-pair-mma-types.c
===
--- clang/test/Sema/ppc-pair-mma-types.c
+++ clang/test/Sema/ppc-pair-mma-types.c
@@ -1,5 +1,7 @@
 // RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -fsyntax-only \
-// RUN:   -target-cpu future %s -verify
+// RUN:   -target-cpu pwr10 %s -verify
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -fsyntax-only \
+// RUN:   -target-cpu pwr10 %s -verify
 
 // The use of PPC MMA types is strongly restricted. Non-pointer MMA variables
 // can only be declared in functions and a limited number of operations are
Index: clang/test/CodeGen/builtins-ppc-pair-mma.c
===
--- clang/test/CodeGen/builtins-ppc-pair-mma.c
+++ clang/test/CodeGen/builtins-ppc-pair-mma.c
@@ -1,5 +1,8 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-// RUN: %clang_cc1 -O3 -triple powerpc64le-unknown-unknown -target-cpu future -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -O3 -triple powerpc64le-unknown-unknown -target-cpu pwr10 \
+// RUN:  -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -O3 -triple powerpc64-unknown-unknown -target-cpu pwr10 \
+// RUN: -emit-llvm %s -o - | FileCheck %s
 
 // CHECK-LABEL: @test1(
 // CHECK-NEXT:  entry:
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[PATCH] D109126: [PowerPC] [NFC] Add Big-Endian checks for existing MMA tests

[Ahsan Saghir via Phabricator via cfe-commits]

saghir updated this revision to Diff 372143.
saghir added a comment.

Rebased before commit.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109126/new/

https://reviews.llvm.org/D109126

Files:
  clang/test/CodeGen/builtins-ppc-pair-mma.c
  clang/test/Sema/ppc-pair-mma-types.c
  clang/test/SemaCXX/ppc-pair-mma-types.cpp


Index: clang/test/SemaCXX/ppc-pair-mma-types.cpp
===
--- clang/test/SemaCXX/ppc-pair-mma-types.cpp
+++ clang/test/SemaCXX/ppc-pair-mma-types.cpp
@@ -1,5 +1,7 @@
 // RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -fsyntax-only \
-// RUN:   -fcxx-exceptions -target-cpu future %s -verify
+// RUN:   -fcxx-exceptions -target-cpu pwr10 %s -verify
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -fsyntax-only \
+// RUN:   -fcxx-exceptions -target-cpu pwr10 %s -verify
 
 // vector quad
 
Index: clang/test/Sema/ppc-pair-mma-types.c
===
--- clang/test/Sema/ppc-pair-mma-types.c
+++ clang/test/Sema/ppc-pair-mma-types.c
@@ -1,5 +1,7 @@
 // RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -fsyntax-only \
-// RUN:   -target-cpu future %s -verify
+// RUN:   -target-cpu pwr10 %s -verify
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -fsyntax-only \
+// RUN:   -target-cpu pwr10 %s -verify
 
 // The use of PPC MMA types is strongly restricted. Non-pointer MMA variables
 // can only be declared in functions and a limited number of operations are
Index: clang/test/CodeGen/builtins-ppc-pair-mma.c
===
--- clang/test/CodeGen/builtins-ppc-pair-mma.c
+++ clang/test/CodeGen/builtins-ppc-pair-mma.c
@@ -1,5 +1,8 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-// RUN: %clang_cc1 -O3 -triple powerpc64le-unknown-unknown -target-cpu future 
-emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -O3 -triple powerpc64le-unknown-unknown -target-cpu pwr10 \
+// RUN:  -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -O3 -triple powerpc64-unknown-unknown -target-cpu pwr10 \
+// RUN: -emit-llvm %s -o - | FileCheck %s
 
 // CHECK-LABEL: @test1(
 // CHECK-NEXT:  entry:


Index: clang/test/SemaCXX/ppc-pair-mma-types.cpp
===
--- clang/test/SemaCXX/ppc-pair-mma-types.cpp
+++ clang/test/SemaCXX/ppc-pair-mma-types.cpp
@@ -1,5 +1,7 @@
 // RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -fsyntax-only \
-// RUN:   -fcxx-exceptions -target-cpu future %s -verify
+// RUN:   -fcxx-exceptions -target-cpu pwr10 %s -verify
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -fsyntax-only \
+// RUN:   -fcxx-exceptions -target-cpu pwr10 %s -verify
 
 // vector quad
 
Index: clang/test/Sema/ppc-pair-mma-types.c
===
--- clang/test/Sema/ppc-pair-mma-types.c
+++ clang/test/Sema/ppc-pair-mma-types.c
@@ -1,5 +1,7 @@
 // RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -fsyntax-only \
-// RUN:   -target-cpu future %s -verify
+// RUN:   -target-cpu pwr10 %s -verify
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -fsyntax-only \
+// RUN:   -target-cpu pwr10 %s -verify
 
 // The use of PPC MMA types is strongly restricted. Non-pointer MMA variables
 // can only be declared in functions and a limited number of operations are
Index: clang/test/CodeGen/builtins-ppc-pair-mma.c
===
--- clang/test/CodeGen/builtins-ppc-pair-mma.c
+++ clang/test/CodeGen/builtins-ppc-pair-mma.c
@@ -1,5 +1,8 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-// RUN: %clang_cc1 -O3 -triple powerpc64le-unknown-unknown -target-cpu future -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -O3 -triple powerpc64le-unknown-unknown -target-cpu pwr10 \
+// RUN:  -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -O3 -triple powerpc64-unknown-unknown -target-cpu pwr10 \
+// RUN: -emit-llvm %s -o - | FileCheck %s
 
 // CHECK-LABEL: @test1(
 // CHECK-NEXT:  entry:
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[PATCH] D109126: [PowerPC] [NFC] Add Big-Endian checks for existing MMA tests

[Ahsan Saghir via Phabricator via cfe-commits]

saghir updated this revision to Diff 371919.
saghir added a comment.

Rebased.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109126/new/

https://reviews.llvm.org/D109126

Files:
  clang/test/CodeGen/builtins-ppc-pair-mma.c
  clang/test/Sema/ppc-pair-mma-types.c
  clang/test/SemaCXX/ppc-pair-mma-types.cpp


Index: clang/test/SemaCXX/ppc-pair-mma-types.cpp
===
--- clang/test/SemaCXX/ppc-pair-mma-types.cpp
+++ clang/test/SemaCXX/ppc-pair-mma-types.cpp
@@ -1,5 +1,7 @@
 // RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -fsyntax-only \
-// RUN:   -fcxx-exceptions -target-cpu future %s -verify
+// RUN:   -fcxx-exceptions -target-cpu pwr10 %s -verify
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -fsyntax-only \
+// RUN:   -fcxx-exceptions -target-cpu pwr10 %s -verify
 
 // vector quad
 
Index: clang/test/Sema/ppc-pair-mma-types.c
===
--- clang/test/Sema/ppc-pair-mma-types.c
+++ clang/test/Sema/ppc-pair-mma-types.c
@@ -1,5 +1,7 @@
 // RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -fsyntax-only \
-// RUN:   -target-cpu future %s -verify
+// RUN:   -target-cpu pwr10 %s -verify
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -fsyntax-only \
+// RUN:   -target-cpu pwr10 %s -verify
 
 // The use of PPC MMA types is strongly restricted. Non-pointer MMA variables
 // can only be declared in functions and a limited number of operations are
Index: clang/test/CodeGen/builtins-ppc-pair-mma.c
===
--- clang/test/CodeGen/builtins-ppc-pair-mma.c
+++ clang/test/CodeGen/builtins-ppc-pair-mma.c
@@ -1,5 +1,8 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-// RUN: %clang_cc1 -O3 -triple powerpc64le-unknown-unknown -target-cpu future 
-emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -O3 -triple powerpc64le-unknown-unknown -target-cpu pwr10 \
+// RUN:  -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -O3 -triple powerpc64-unknown-unknown -target-cpu pwr10 \
+// RUN: -emit-llvm %s -o - | FileCheck %s
 
 // CHECK-LABEL: @test1(
 // CHECK-NEXT:  entry:


Index: clang/test/SemaCXX/ppc-pair-mma-types.cpp
===
--- clang/test/SemaCXX/ppc-pair-mma-types.cpp
+++ clang/test/SemaCXX/ppc-pair-mma-types.cpp
@@ -1,5 +1,7 @@
 // RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -fsyntax-only \
-// RUN:   -fcxx-exceptions -target-cpu future %s -verify
+// RUN:   -fcxx-exceptions -target-cpu pwr10 %s -verify
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -fsyntax-only \
+// RUN:   -fcxx-exceptions -target-cpu pwr10 %s -verify
 
 // vector quad
 
Index: clang/test/Sema/ppc-pair-mma-types.c
===
--- clang/test/Sema/ppc-pair-mma-types.c
+++ clang/test/Sema/ppc-pair-mma-types.c
@@ -1,5 +1,7 @@
 // RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -fsyntax-only \
-// RUN:   -target-cpu future %s -verify
+// RUN:   -target-cpu pwr10 %s -verify
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -fsyntax-only \
+// RUN:   -target-cpu pwr10 %s -verify
 
 // The use of PPC MMA types is strongly restricted. Non-pointer MMA variables
 // can only be declared in functions and a limited number of operations are
Index: clang/test/CodeGen/builtins-ppc-pair-mma.c
===
--- clang/test/CodeGen/builtins-ppc-pair-mma.c
+++ clang/test/CodeGen/builtins-ppc-pair-mma.c
@@ -1,5 +1,8 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-// RUN: %clang_cc1 -O3 -triple powerpc64le-unknown-unknown -target-cpu future -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -O3 -triple powerpc64le-unknown-unknown -target-cpu pwr10 \
+// RUN:  -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -O3 -triple powerpc64-unknown-unknown -target-cpu pwr10 \
+// RUN: -emit-llvm %s -o - | FileCheck %s
 
 // CHECK-LABEL: @test1(
 // CHECK-NEXT:  entry:
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[PATCH] D109126: [PowerPC] [NFC] Add Big-Endian checks for existing MMA tests

[Ahsan Saghir via Phabricator via cfe-commits]

saghir marked an inline comment as done.
saghir added inline comments.



Comment at: clang/test/CodeGen/builtins-ppc-pair-mma.c:5
+// RUN: %clang_cc1 -O3 -triple powerpc64-unknown-unknown -target-cpu pwr10 \
+// RUN: -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK-BE
 

nemanjai wrote:
> qiucf wrote:
> > Seems just adding `%clang_cc1 -O3 -triple powerpc64-unknown-unknown 
> > -target-cpu pwr10 -emit-llvm %s -o - | FileCheck %s` also makes the test 
> > pass. `CHECK` and `CHECK-BE` contents are the same.
> The existing builtins produce the same IR but I think this is done in 
> preparation for https://reviews.llvm.org/D107647 which will add builtins very 
> similar to these but that produce different IR on LE and BE. The description 
> of the patch should probably mention that.
Since all the builtins in this file produce the same output for LE and BE, it's 
probably better to add checks for the new builtins (having different output for 
LE/BE) in a separate file.


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[PATCH] D109126: [PowerPC] [NFC] Add Big-Endian checks for existing MMA tests

[Ahsan Saghir via Phabricator via cfe-commits]

saghir updated this revision to Diff 371164.
saghir added a comment.

Addressed review comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109126/new/

https://reviews.llvm.org/D109126

Files:
  clang/test/CodeGen/builtins-ppc-pair-mma.c
  clang/test/Sema/ppc-pair-mma-types.c
  clang/test/SemaCXX/ppc-pair-mma-types.cpp


Index: clang/test/SemaCXX/ppc-pair-mma-types.cpp
===
--- clang/test/SemaCXX/ppc-pair-mma-types.cpp
+++ clang/test/SemaCXX/ppc-pair-mma-types.cpp
@@ -1,5 +1,7 @@
 // RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -fsyntax-only \
-// RUN:   -fcxx-exceptions -target-cpu future %s -verify
+// RUN:   -fcxx-exceptions -target-cpu pwr10 %s -verify
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -fsyntax-only \
+// RUN:   -fcxx-exceptions -target-cpu pwr10 %s -verify
 
 // vector quad
 
Index: clang/test/Sema/ppc-pair-mma-types.c
===
--- clang/test/Sema/ppc-pair-mma-types.c
+++ clang/test/Sema/ppc-pair-mma-types.c
@@ -1,5 +1,7 @@
 // RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -fsyntax-only \
-// RUN:   -target-cpu future %s -verify
+// RUN:   -target-cpu pwr10 %s -verify
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -fsyntax-only \
+// RUN:   -target-cpu pwr10 %s -verify
 
 // The use of PPC MMA types is strongly restricted. Non-pointer MMA variables
 // can only be declared in functions and a limited number of operations are
Index: clang/test/CodeGen/builtins-ppc-pair-mma.c
===
--- clang/test/CodeGen/builtins-ppc-pair-mma.c
+++ clang/test/CodeGen/builtins-ppc-pair-mma.c
@@ -1,5 +1,8 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-// RUN: %clang_cc1 -O3 -triple powerpc64le-unknown-unknown -target-cpu future 
-emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -O3 -triple powerpc64le-unknown-unknown -target-cpu pwr10 \
+// RUN:  -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -O3 -triple powerpc64-unknown-unknown -target-cpu pwr10 \
+// RUN: -emit-llvm %s -o - | FileCheck %s
 
 // CHECK-LABEL: @test1(
 // CHECK-NEXT:  entry:


Index: clang/test/SemaCXX/ppc-pair-mma-types.cpp
===
--- clang/test/SemaCXX/ppc-pair-mma-types.cpp
+++ clang/test/SemaCXX/ppc-pair-mma-types.cpp
@@ -1,5 +1,7 @@
 // RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -fsyntax-only \
-// RUN:   -fcxx-exceptions -target-cpu future %s -verify
+// RUN:   -fcxx-exceptions -target-cpu pwr10 %s -verify
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -fsyntax-only \
+// RUN:   -fcxx-exceptions -target-cpu pwr10 %s -verify
 
 // vector quad
 
Index: clang/test/Sema/ppc-pair-mma-types.c
===
--- clang/test/Sema/ppc-pair-mma-types.c
+++ clang/test/Sema/ppc-pair-mma-types.c
@@ -1,5 +1,7 @@
 // RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -fsyntax-only \
-// RUN:   -target-cpu future %s -verify
+// RUN:   -target-cpu pwr10 %s -verify
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -fsyntax-only \
+// RUN:   -target-cpu pwr10 %s -verify
 
 // The use of PPC MMA types is strongly restricted. Non-pointer MMA variables
 // can only be declared in functions and a limited number of operations are
Index: clang/test/CodeGen/builtins-ppc-pair-mma.c
===
--- clang/test/CodeGen/builtins-ppc-pair-mma.c
+++ clang/test/CodeGen/builtins-ppc-pair-mma.c
@@ -1,5 +1,8 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-// RUN: %clang_cc1 -O3 -triple powerpc64le-unknown-unknown -target-cpu future -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -O3 -triple powerpc64le-unknown-unknown -target-cpu pwr10 \
+// RUN:  -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -O3 -triple powerpc64-unknown-unknown -target-cpu pwr10 \
+// RUN: -emit-llvm %s -o - | FileCheck %s
 
 // CHECK-LABEL: @test1(
 // CHECK-NEXT:  entry:
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[PATCH] D109126: [PowerPC] [NFC] Add Big-Endian checks for existing MMA tests

[Ahsan Saghir via Phabricator via cfe-commits]

saghir created this revision.
Herald added subscribers: shchenz, kbarton, nemanjai.
saghir requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

This patch adds Big-Endian checks for the existing MMA test cases.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D109126

Files:
  clang/test/CodeGen/builtins-ppc-pair-mma.c
  clang/test/Sema/ppc-pair-mma-types.c
  clang/test/SemaCXX/ppc-pair-mma-types.cpp

Index: clang/test/SemaCXX/ppc-pair-mma-types.cpp
===
--- clang/test/SemaCXX/ppc-pair-mma-types.cpp
+++ clang/test/SemaCXX/ppc-pair-mma-types.cpp
@@ -1,5 +1,7 @@
 // RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -fsyntax-only \
-// RUN:   -fcxx-exceptions -target-cpu future %s -verify
+// RUN:   -fcxx-exceptions -target-cpu pwr10 %s -verify
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -fsyntax-only \
+// RUN:   -fcxx-exceptions -target-cpu pwr10 %s -verify
 
 // vector quad
 
Index: clang/test/Sema/ppc-pair-mma-types.c
===
--- clang/test/Sema/ppc-pair-mma-types.c
+++ clang/test/Sema/ppc-pair-mma-types.c
@@ -1,5 +1,7 @@
 // RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -fsyntax-only \
-// RUN:   -target-cpu future %s -verify
+// RUN:   -target-cpu pwr10 %s -verify
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -fsyntax-only \
+// RUN:   -target-cpu pwr10 %s -verify
 
 // The use of PPC MMA types is strongly restricted. Non-pointer MMA variables
 // can only be declared in functions and a limited number of operations are
Index: clang/test/CodeGen/builtins-ppc-pair-mma.c
===
--- clang/test/CodeGen/builtins-ppc-pair-mma.c
+++ clang/test/CodeGen/builtins-ppc-pair-mma.c
@@ -1,5 +1,8 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-// RUN: %clang_cc1 -O3 -triple powerpc64le-unknown-unknown -target-cpu future -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -O3 -triple powerpc64le-unknown-unknown -target-cpu pwr10 \
+// RUN: -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -O3 -triple powerpc64-unknown-unknown -target-cpu pwr10 \
+// RUN: -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK-BE
 
 // CHECK-LABEL: @test1(
 // CHECK-NEXT:  entry:
@@ -8,6 +11,13 @@
 // CHECK-NEXT:store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa [[TBAA2:![0-9]+]]
 // CHECK-NEXT:ret void
 //
+// CHECK-BE-LABEL: @test1(
+// CHECK-BE-NEXT:  entry:
+// CHECK-BE-NEXT:[[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]], <16 x i8> [[VC]], <16 x i8> [[VC]])
+// CHECK-BE-NEXT:[[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
+// CHECK-BE-NEXT:store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa [[TBAA2:![0-9]+]]
+// CHECK-BE-NEXT:ret void
+//
 void test1(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
   __vector_quad vq = *((__vector_quad *)vqp);
   __vector_pair vp = *((__vector_pair *)vpp);
@@ -38,6 +48,28 @@
 // CHECK-NEXT:store <16 x i8> [[TMP11]], <16 x i8>* [[TMP13]], align 16
 // CHECK-NEXT:ret void
 //
+// CHECK-BE-LABEL: @test2(
+// CHECK-BE-NEXT:  entry:
+// CHECK-BE-NEXT:[[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
+// CHECK-BE-NEXT:[[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64
+// CHECK-BE-NEXT:[[TMP2:%.*]] = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> [[TMP1]])
+// CHECK-BE-NEXT:[[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <16 x i8>*
+// CHECK-BE-NEXT:[[TMP4:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[TMP2]], 0
+// CHECK-BE-NEXT:store <16 x i8> [[TMP4]], <16 x i8>* [[TMP3]], align 16
+// CHECK-BE-NEXT:[[TMP5:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[TMP2]], 1
+// CHECK-BE-NEXT:[[TMP6:%.*]] = getelementptr inbounds i8, i8* [[RESP]], i64 16
+// CHECK-BE-NEXT:[[TMP7:%.*]] = bitcast i8* [[TMP6]] to <16 x i8>*
+// CHECK-BE-NEXT:store <16 x i8> [[TMP5]], <16 x i8>* [[TMP7]], align 16
+// CHECK-BE-NEXT:[[TMP8:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[TMP2]], 2
+// CHECK-BE-NEXT:[[TMP9:%.*]] = getelementptr inbounds i8, i8* [[RESP]], i64 32
+// CHECK-BE-NEXT:[[TMP10:%.*]] = bitcast i8* [[TMP9]] to <16 x i8>*
+// CHECK-BE-NEXT:store <16 x i8> [[TMP8]], <16 x i8>* [[TMP10]], align 16
+// CHECK-BE-NEXT:[[TMP11:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[TMP2]], 3
+// CHECK-BE-NEXT:[[TMP12:%.*]] = getelementptr inbounds i8, i8* [[RESP]], i64 48
+// CHECK-BE-NEXT:[[TMP13:%.*]] = bitcast i8* [[TMP12]] to <16 x i8>*
+// CHECK-BE-NEXT:store <16 x i8> [[TMP11]], <16 x i8>* [[TMP13]], align 16
+// CHECK-BE-NEXT:

[PATCH] D107647: [PowerPC] MMA - Add __builtin_vsx_build_pair and __builtin_mma_build_acc builtins

[Ahsan Saghir via Phabricator via cfe-commits]

saghir updated this revision to Diff 368176.
saghir added a comment.

Added comments, and re-organized tests.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107647/new/

https://reviews.llvm.org/D107647

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-pair-mma.c
  clang/test/Sema/ppc-pair-mma-types.c
  clang/test/SemaCXX/ppc-pair-mma-types.cpp
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstrPrefix.td
  llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
  llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll

Index: llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
===
--- llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
+++ llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
@@ -51,6 +51,81 @@
   ret void
 }
 
+; build_pair
+declare <256 x i1> @llvm.ppc.vsx.build.pair(<16 x i8>, <16 x i8>)
+define void @build_pair1(<256 x i1>* %ptr, <16 x i8> %vc) {
+; CHECK-LABEL: build_pair1:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vmr v3, v2
+; CHECK-NEXT:stxv v2, 16(r3)
+; CHECK-NEXT:stxv v3, 0(r3)
+; CHECK-NEXT:blr
+;
+; CHECK-NOMMA-LABEL: build_pair1:
+; CHECK-NOMMA:   # %bb.0: # %entry
+; CHECK-NOMMA-NEXT:vmr v3, v2
+; CHECK-NOMMA-NEXT:stxv v2, 16(r3)
+; CHECK-NOMMA-NEXT:stxv v3, 0(r3)
+; CHECK-NOMMA-NEXT:blr
+;
+; CHECK-BE-LABEL: build_pair1:
+; CHECK-BE:   # %bb.0: # %entry
+; CHECK-BE-NEXT:vmr v3, v2
+; CHECK-BE-NEXT:stxv v2, 16(r3)
+; CHECK-BE-NEXT:stxv v2, 0(r3)
+; CHECK-BE-NEXT:blr
+;
+; CHECK-BE-NOMMA-LABEL: build_pair1:
+; CHECK-BE-NOMMA:   # %bb.0: # %entry
+; CHECK-BE-NOMMA-NEXT:vmr v3, v2
+; CHECK-BE-NOMMA-NEXT:stxv v2, 16(r3)
+; CHECK-BE-NOMMA-NEXT:stxv v2, 0(r3)
+; CHECK-BE-NOMMA-NEXT:blr
+entry:
+  %0 = tail call <256 x i1> @llvm.ppc.vsx.build.pair(<16 x i8> %vc, <16 x i8> %vc)
+  store <256 x i1> %0, <256 x i1>* %ptr, align 32
+  ret void
+}
+
+; build_pair
+define void @build_pair2(<256 x i1>* %ptr, <16 x i8> %in1, <16 x i8> %in2) {
+; CHECK-LABEL: build_pair2:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vmr v4, v3
+; CHECK-NEXT:vmr v5, v2
+; CHECK-NEXT:stxv v4, 16(r3)
+; CHECK-NEXT:stxv v5, 0(r3)
+; CHECK-NEXT:blr
+;
+; CHECK-NOMMA-LABEL: build_pair2:
+; CHECK-NOMMA:   # %bb.0: # %entry
+; CHECK-NOMMA-NEXT:vmr v4, v3
+; CHECK-NOMMA-NEXT:vmr v5, v2
+; CHECK-NOMMA-NEXT:stxv v4, 16(r3)
+; CHECK-NOMMA-NEXT:stxv v5, 0(r3)
+; CHECK-NOMMA-NEXT:blr
+;
+; CHECK-BE-LABEL: build_pair2:
+; CHECK-BE:   # %bb.0: # %entry
+; CHECK-BE-NEXT:vmr v4, v3
+; CHECK-BE-NEXT:vmr v5, v2
+; CHECK-BE-NEXT:stxv v2, 16(r3)
+; CHECK-BE-NEXT:stxv v4, 0(r3)
+; CHECK-BE-NEXT:blr
+;
+; CHECK-BE-NOMMA-LABEL: build_pair2:
+; CHECK-BE-NOMMA:   # %bb.0: # %entry
+; CHECK-BE-NOMMA-NEXT:vmr v4, v3
+; CHECK-BE-NOMMA-NEXT:vmr v5, v2
+; CHECK-BE-NOMMA-NEXT:stxv v2, 16(r3)
+; CHECK-BE-NOMMA-NEXT:stxv v4, 0(r3)
+; CHECK-BE-NOMMA-NEXT:blr
+entry:
+%0 = tail call <256 x i1> @llvm.ppc.vsx.build.pair(<16 x i8> %in2, <16 x i8> %in1)
+store <256 x i1> %0, <256 x i1>* %ptr, align 64
+ret void
+}
+
 ; disassemble_pair
 declare { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1>)
 define void @disass_pair(<256 x i1>* %ptr1, <16 x i8>* %ptr2, <16 x i8>* %ptr3) {
Index: llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
===
--- llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
+++ llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
@@ -40,6 +40,77 @@
   ret void
 }
 
+; build_acc
+declare <512 x i1> @llvm.ppc.mma.build.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>)
+define void @build_acc1(<512 x i1>* %ptr, <16 x i8> %vc) {
+; CHECK-LABEL: build_acc1:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vmr v3, v2
+; CHECK-NEXT:xxlor vs0, v2, v2
+; CHECK-NEXT:xxlor vs1, v3, v3
+; CHECK-NEXT:xxlor vs2, v2, v2
+; CHECK-NEXT:xxlor vs3, v3, v3
+; CHECK-NEXT:stxv vs0, 48(r3)
+; CHECK-NEXT:stxv vs1, 32(r3)
+; CHECK-NEXT:stxv vs2, 16(r3)
+; CHECK-NEXT:stxv vs3, 0(r3)
+; CHECK-NEXT:blr
+;
+; CHECK-BE-LABEL: build_acc1:
+; CHECK-BE:   # %bb.0: # %entry
+; CHECK-BE-NEXT:vmr v3, v2
+; CHECK-BE-NEXT:xxlor vs0, v2, v2
+; CHECK-BE-NEXT:xxlor vs1, v3, v3
+; CHECK-BE-NEXT:xxlor vs2, v2, v2
+; CHECK-BE-NEXT:xxlor vs3, v3, v3
+; CHECK-BE-NEXT:stxv vs1, 16(r3)
+; CHECK-BE-NEXT:stxv vs0, 0(r3)
+; CHECK-BE-NEXT:stxv vs3, 48(r3)
+; CHECK-BE-NEXT:stxv vs2, 32(r3)
+; CHECK-BE-NEXT:blr
+entry:
+  %0 = tail call <512 x i1> @llvm.ppc.mma.build.acc(<16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc)
+  store <512 x i1> %0, <512 x i1>* %ptr, align 64
+  ret void
+}
+
+; build_acc
+define void @build_acc2(<512 x i1>* %ptr, <16 x i8> %in1, <16 x i8> 

[PATCH] D107647: [PowerPC] MMA - Add __builtin_vsx_build_pair and __builtin_mma_build_acc builtins

[Ahsan Saghir via Phabricator via cfe-commits]

saghir updated this revision to Diff 368109.
saghir added a comment.

Added some more tests.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107647/new/

https://reviews.llvm.org/D107647

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-pair-mma.c
  clang/test/Sema/ppc-pair-mma-types.c
  clang/test/SemaCXX/ppc-pair-mma-types.cpp
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstrPrefix.td
  llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
  llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll

Index: llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
===
--- llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
+++ llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
@@ -51,6 +51,42 @@
   ret void
 }
 
+; build_pair
+declare <256 x i1> @llvm.ppc.vsx.build.pair(<16 x i8>, <16 x i8>)
+define void @build_pair(<256 x i1>* %ptr, <16 x i8> %vc) {
+; CHECK-LABEL: build_pair:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vmr v3, v2
+; CHECK-NEXT:stxv v2, 16(r3)
+; CHECK-NEXT:stxv v3, 0(r3)
+; CHECK-NEXT:blr
+;
+; CHECK-NOMMA-LABEL: build_pair:
+; CHECK-NOMMA:   # %bb.0: # %entry
+; CHECK-NOMMA-NEXT:vmr v3, v2
+; CHECK-NOMMA-NEXT:stxv v2, 16(r3)
+; CHECK-NOMMA-NEXT:stxv v3, 0(r3)
+; CHECK-NOMMA-NEXT:blr
+;
+; CHECK-BE-LABEL: build_pair:
+; CHECK-BE:   # %bb.0: # %entry
+; CHECK-BE-NEXT:vmr v3, v2
+; CHECK-BE-NEXT:stxv v2, 16(r3)
+; CHECK-BE-NEXT:stxv v2, 0(r3)
+; CHECK-BE-NEXT:blr
+;
+; CHECK-BE-NOMMA-LABEL: build_pair:
+; CHECK-BE-NOMMA:   # %bb.0: # %entry
+; CHECK-BE-NOMMA-NEXT:vmr v3, v2
+; CHECK-BE-NOMMA-NEXT:stxv v2, 16(r3)
+; CHECK-BE-NOMMA-NEXT:stxv v2, 0(r3)
+; CHECK-BE-NOMMA-NEXT:blr
+entry:
+  %0 = tail call <256 x i1> @llvm.ppc.vsx.build.pair(<16 x i8> %vc, <16 x i8> %vc)
+  store <256 x i1> %0, <256 x i1>* %ptr, align 32
+  ret void
+}
+
 ; disassemble_pair
 declare { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1>)
 define void @disass_pair(<256 x i1>* %ptr1, <16 x i8>* %ptr2, <16 x i8>* %ptr3) {
Index: llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
===
--- llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
+++ llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
@@ -40,6 +40,101 @@
   ret void
 }
 
+; build_acc
+declare <512 x i1> @llvm.ppc.mma.build.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>)
+define void @build_acc1(<512 x i1>* %ptr, <16 x i8> %vc) {
+; CHECK-LABEL: build_acc1:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vmr v3, v2
+; CHECK-NEXT:xxlor vs0, v2, v2
+; CHECK-NEXT:xxlor vs1, v3, v3
+; CHECK-NEXT:xxlor vs2, v2, v2
+; CHECK-NEXT:xxlor vs3, v3, v3
+; CHECK-NEXT:stxv vs0, 48(r3)
+; CHECK-NEXT:stxv vs1, 32(r3)
+; CHECK-NEXT:stxv vs2, 16(r3)
+; CHECK-NEXT:stxv vs3, 0(r3)
+; CHECK-NEXT:blr
+;
+; CHECK-BE-LABEL: build_acc1:
+; CHECK-BE:   # %bb.0: # %entry
+; CHECK-BE-NEXT:vmr v3, v2
+; CHECK-BE-NEXT:xxlor vs0, v2, v2
+; CHECK-BE-NEXT:xxlor vs1, v3, v3
+; CHECK-BE-NEXT:xxlor vs2, v2, v2
+; CHECK-BE-NEXT:xxlor vs3, v3, v3
+; CHECK-BE-NEXT:stxv vs1, 16(r3)
+; CHECK-BE-NEXT:stxv vs0, 0(r3)
+; CHECK-BE-NEXT:stxv vs3, 48(r3)
+; CHECK-BE-NEXT:stxv vs2, 32(r3)
+; CHECK-BE-NEXT:blr
+entry:
+  %0 = tail call <512 x i1> @llvm.ppc.mma.build.acc(<16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc)
+  store <512 x i1> %0, <512 x i1>* %ptr, align 64
+  ret void
+}
+
+; build_acc
+define void @build_acc2(<512 x i1>* %ptr, <16 x i8> %in1, <16 x i8> %in2, <16 x i8> %in3, <16 x i8> %in4) {
+; CHECK-LABEL: build_acc2:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xxlor vs0, v5, v5
+; CHECK-NEXT:xxlor vs1, v4, v4
+; CHECK-NEXT:# kill: def $vsrp0 killed $vsrp0 def $uacc0
+; CHECK-NEXT:vmr v4, v3
+; CHECK-NEXT:vmr v5, v2
+; CHECK-NEXT:xxlor vs2, v4, v4
+; CHECK-NEXT:xxlor vs3, v5, v5
+; CHECK-NEXT:stxv vs0, 48(r3)
+; CHECK-NEXT:stxv vs1, 32(r3)
+; CHECK-NEXT:stxv vs2, 16(r3)
+; CHECK-NEXT:stxv vs3, 0(r3)
+; CHECK-NEXT:blr
+;
+; CHECK-BE-LABEL: build_acc2:
+; CHECK-BE:   # %bb.0: # %entry
+; CHECK-BE-NEXT:xxlor vs0, v5, v5
+; CHECK-BE-NEXT:xxlor vs1, v4, v4
+; CHECK-BE-NEXT:# kill: def $vsrp0 killed $vsrp0 def $uacc0
+; CHECK-BE-NEXT:vmr v4, v3
+; CHECK-BE-NEXT:vmr v5, v2
+; CHECK-BE-NEXT:xxlor vs2, v4, v4
+; CHECK-BE-NEXT:xxlor vs3, v5, v5
+; CHECK-BE-NEXT:stxv vs1, 16(r3)
+; CHECK-BE-NEXT:stxv vs0, 0(r3)
+; CHECK-BE-NEXT:stxv vs3, 48(r3)
+; CHECK-BE-NEXT:stxv vs2, 32(r3)
+; CHECK-BE-NEXT:blr
+entry:
+%0 = tail call <512 x i1> @llvm.ppc.mma.build.acc(<16 x i8> %in4, <16 x i8> %in3, <16 x i8> %in2, <16 x i8> %in1)
+store <512 x i1> %0, <512 x i1>* %ptr, align 64
+ret void
+}
+

[PATCH] D107647: [PowerPC] MMA - Remove deprecated built-ins and add new built-ins

[Ahsan Saghir via Phabricator via cfe-commits]

saghir updated this revision to Diff 367530.
saghir added a comment.

Change the implementation to add new builtins and keep the depracated builtins.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107647/new/

https://reviews.llvm.org/D107647

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-pair-mma.c
  clang/test/Sema/ppc-pair-mma-types.c
  clang/test/SemaCXX/ppc-pair-mma-types.cpp
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstrPrefix.td
  llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
  llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll

Index: llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
===
--- llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
+++ llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
@@ -51,6 +51,42 @@
   ret void
 }
 
+; build_pair
+declare <256 x i1> @llvm.ppc.vsx.build.pair(<16 x i8>, <16 x i8>)
+define void @build_pair(<256 x i1>* %ptr, <16 x i8> %vc) {
+; CHECK-LABEL: build_pair:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vmr v3, v2
+; CHECK-NEXT:stxv v2, 16(r3)
+; CHECK-NEXT:stxv v3, 0(r3)
+; CHECK-NEXT:blr
+;
+; CHECK-NOMMA-LABEL: build_pair:
+; CHECK-NOMMA:   # %bb.0: # %entry
+; CHECK-NOMMA-NEXT:vmr v3, v2
+; CHECK-NOMMA-NEXT:stxv v2, 16(r3)
+; CHECK-NOMMA-NEXT:stxv v3, 0(r3)
+; CHECK-NOMMA-NEXT:blr
+;
+; CHECK-BE-LABEL: build_pair:
+; CHECK-BE:   # %bb.0: # %entry
+; CHECK-BE-NEXT:vmr v3, v2
+; CHECK-BE-NEXT:stxv v2, 16(r3)
+; CHECK-BE-NEXT:stxv v2, 0(r3)
+; CHECK-BE-NEXT:blr
+;
+; CHECK-BE-NOMMA-LABEL: build_pair:
+; CHECK-BE-NOMMA:   # %bb.0: # %entry
+; CHECK-BE-NOMMA-NEXT:vmr v3, v2
+; CHECK-BE-NOMMA-NEXT:stxv v2, 16(r3)
+; CHECK-BE-NOMMA-NEXT:stxv v2, 0(r3)
+; CHECK-BE-NOMMA-NEXT:blr
+entry:
+  %0 = tail call <256 x i1> @llvm.ppc.vsx.build.pair(<16 x i8> %vc, <16 x i8> %vc)
+  store <256 x i1> %0, <256 x i1>* %ptr, align 32
+  ret void
+}
+
 ; disassemble_pair
 declare { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1>)
 define void @disass_pair(<256 x i1>* %ptr1, <16 x i8>* %ptr2, <16 x i8>* %ptr3) {
Index: llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
===
--- llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
+++ llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
@@ -40,6 +40,40 @@
   ret void
 }
 
+; build_acc
+declare <512 x i1> @llvm.ppc.mma.build.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>)
+define void @build_acc(<512 x i1>* %ptr, <16 x i8> %vc) {
+; CHECK-LABEL: build_acc:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vmr v3, v2
+; CHECK-NEXT:xxlor vs0, v2, v2
+; CHECK-NEXT:xxlor vs1, v3, v3
+; CHECK-NEXT:xxlor vs2, v2, v2
+; CHECK-NEXT:xxlor vs3, v3, v3
+; CHECK-NEXT:stxv vs0, 48(r3)
+; CHECK-NEXT:stxv vs1, 32(r3)
+; CHECK-NEXT:stxv vs2, 16(r3)
+; CHECK-NEXT:stxv vs3, 0(r3)
+; CHECK-NEXT:blr
+;
+; CHECK-BE-LABEL: build_acc:
+; CHECK-BE:   # %bb.0: # %entry
+; CHECK-BE-NEXT:vmr v3, v2
+; CHECK-BE-NEXT:xxlor vs0, v2, v2
+; CHECK-BE-NEXT:xxlor vs1, v3, v3
+; CHECK-BE-NEXT:xxlor vs2, v2, v2
+; CHECK-BE-NEXT:xxlor vs3, v3, v3
+; CHECK-BE-NEXT:stxv vs1, 16(r3)
+; CHECK-BE-NEXT:stxv vs0, 0(r3)
+; CHECK-BE-NEXT:stxv vs3, 48(r3)
+; CHECK-BE-NEXT:stxv vs2, 32(r3)
+; CHECK-BE-NEXT:blr
+entry:
+  %0 = tail call <512 x i1> @llvm.ppc.mma.build.acc(<16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc)
+  store <512 x i1> %0, <512 x i1>* %ptr, align 64
+  ret void
+}
+
 ; xxmtacc
 declare <512 x i1> @llvm.ppc.mma.xxmtacc(<512 x i1>)
 define void @int_xxmtacc(<512 x i1>* %ptr, <16 x i8> %vc) {
@@ -185,18 +219,18 @@
 ; CHECK-LABEL: testBranch:
 ; CHECK:   # %bb.0: # %entry
 ; CHECK-NEXT:cmplwi r7, 0
-; CHECK-NEXT:beq cr0, .LBB5_2
+; CHECK-NEXT:beq cr0, .LBB6_2
 ; CHECK-NEXT:  # %bb.1: # %if.then
 ; CHECK-NEXT:xxsetaccz acc0
-; CHECK-NEXT:b .LBB5_3
-; CHECK-NEXT:  .LBB5_2: # %if.else
+; CHECK-NEXT:b .LBB6_3
+; CHECK-NEXT:  .LBB6_2: # %if.else
 ; CHECK-NEXT:lxv vs1, 32(r3)
 ; CHECK-NEXT:lxv vs0, 48(r3)
 ; CHECK-NEXT:lxv vs3, 0(r3)
 ; CHECK-NEXT:lxv vs2, 16(r3)
 ; CHECK-NEXT:xxmtacc acc0
 ; CHECK-NEXT:xvi4ger8pp acc0, v2, v2
-; CHECK-NEXT:  .LBB5_3: # %if.end
+; CHECK-NEXT:  .LBB6_3: # %if.end
 ; CHECK-NEXT:xxmfacc acc0
 ; CHECK-NEXT:stxv vs0, 48(r3)
 ; CHECK-NEXT:stxv vs1, 32(r3)
@@ -207,18 +241,18 @@
 ; CHECK-BE-LABEL: testBranch:
 ; CHECK-BE:   # %bb.0: # %entry
 ; CHECK-BE-NEXT:cmplwi r7, 0
-; CHECK-BE-NEXT:beq cr0, .LBB5_2
+; CHECK-BE-NEXT:beq cr0, .LBB6_2
 ; CHECK-BE-NEXT:  # %bb.1: # %if.then
 ; CHECK-BE-NEXT:xxsetaccz acc0
-; CHECK-BE-NEXT:b .LBB5_3
-; CHECK-BE-NEXT:  .LBB5_2: # %if.else
+; CHECK-BE-NEXT:b .LBB6_3
+; 

[PATCH] D107647: Remove depracated built-ins for MMA and replace with new built-ins

[Ahsan Saghir via Phabricator via cfe-commits]

saghir created this revision.
Herald added subscribers: kbarton, hiraditya, nemanjai, qcolombet, MatzeB.
saghir requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D107647

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/test/CodeGen/builtins-ppc-pair-mma.c
  clang/test/Sema/ppc-pair-mma-types.c
  clang/test/SemaCXX/ppc-pair-mma-types.cpp
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstrPrefix.td
  llvm/test/CodeGen/PowerPC/mma-acc-spill.ll
  llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
  llvm/test/CodeGen/PowerPC/mma-outer-product.ll
  llvm/test/CodeGen/PowerPC/mma-phi-accs.ll
  llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
  llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc-bugfix.ll
  llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc.ll

Index: llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc.ll
===
--- llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc.ll
+++ llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc.ll
@@ -254,17 +254,17 @@
   %i48 = bitcast <2 x double> %i44 to <16 x i8>
   %i49 = bitcast <2 x double> %i40 to <16 x i8>
   %i50 = bitcast <2 x double> %i38 to <16 x i8>
-  %i51 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> zeroinitializer, <16 x i8> %i48, <16 x i8> %i49, <16 x i8> %i50)
+  %i51 = tail call <512 x i1> @llvm.ppc.mma.build.acc(<16 x i8> zeroinitializer, <16 x i8> %i48, <16 x i8> %i49, <16 x i8> %i50)
   %i52 = bitcast <2 x double> %i45 to <16 x i8>
   %i53 = bitcast <2 x double> %i41 to <16 x i8>
   %i54 = bitcast <2 x double> %i39 to <16 x i8>
-  %i55 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> zeroinitializer, <16 x i8> %i52, <16 x i8> %i53, <16 x i8> %i54)
+  %i55 = tail call <512 x i1> @llvm.ppc.mma.build.acc(<16 x i8> zeroinitializer, <16 x i8> %i52, <16 x i8> %i53, <16 x i8> %i54)
   %i56 = bitcast <2 x double> %i46 to <16 x i8>
   %i57 = bitcast <2 x double> %i42 to <16 x i8>
-  %i58 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> zeroinitializer, <16 x i8> %i56, <16 x i8> %i57, <16 x i8> %i56)
+  %i58 = tail call <512 x i1> @llvm.ppc.mma.build.acc(<16 x i8> zeroinitializer, <16 x i8> %i56, <16 x i8> %i57, <16 x i8> %i56)
   %i59 = bitcast <2 x double> %i47 to <16 x i8>
   %i60 = bitcast <2 x double> %i43 to <16 x i8>
-  %i61 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> zeroinitializer, <16 x i8> %i59, <16 x i8> %i60, <16 x i8> %i59)
+  %i61 = tail call <512 x i1> @llvm.ppc.mma.build.acc(<16 x i8> zeroinitializer, <16 x i8> %i59, <16 x i8> %i60, <16 x i8> %i59)
   %i62 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i51, <256 x i1> undef, <16 x i8> undef)
   %i63 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i55, <256 x i1> undef, <16 x i8> undef)
   %i64 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i58, <256 x i1> undef, <16 x i8> undef)
@@ -327,7 +327,7 @@
 }
 
 declare <2 x double> @llvm.fma.v2f64(<2 x double>, <2 x double>, <2 x double>)
-declare <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>)
+declare <512 x i1> @llvm.ppc.mma.build.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>)
 declare <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1>, <256 x i1>, <16 x i8>)
 declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1>)
 
Index: llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc-bugfix.ll
===
--- llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc-bugfix.ll
+++ llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc-bugfix.ll
@@ -11,12 +11,12 @@
 ; CHECK-NEXT:xxlor vs3, v2, v2
 ; CHECK-NEXT:stxv vs1, 0(0)
 dmblvi_entry:
-  %0 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> zeroinitializer, <16 x i8> undef, <16 x i8> undef, <16 x i8> zeroinitializer)
+  %0 = tail call <512 x i1> @llvm.ppc.mma.build.acc(<16 x i8> zeroinitializer, <16 x i8> undef, <16 x i8> undef, <16 x i8> zeroinitializer)
   %1 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %0)
   %2 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 2
   store <16 x i8> %2, <16 x i8>* null, align 1
   unreachable
 }
 
-declare <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>)
+declare <512 x i1> @llvm.ppc.mma.build.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>)
 declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1>)
Index: llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
===
--- llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
+++ llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
@@ -16,7 +16,7 @@
 ; when MMA is disabled.
 
 ; assemble_pair
-declare <256 x i1> 

[PATCH] D106550: [PowerPC] Allow MMA builtins to accept restrict qualified pointers

[Ahsan Saghir via Phabricator via cfe-commits]

saghir updated this revision to Diff 364467.
saghir added a comment.

Addressed review comments. Added another test case.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106550/new/

https://reviews.llvm.org/D106550

Files:
  clang/lib/Sema/SemaChecking.cpp
  clang/test/Sema/ppc-pair-mma-types.c


Index: clang/test/Sema/ppc-pair-mma-types.c
===
--- clang/test/Sema/ppc-pair-mma-types.c
+++ clang/test/Sema/ppc-pair-mma-types.c
@@ -333,3 +333,13 @@
   __vector_pair vp = __builtin_vsx_lxvp(ll, v); // expected-error {{passing 
'__vector int' (vector of 4 'int' values) to parameter of incompatible type 
'const __vector_pair *'}}
   __builtin_vsx_stxvp(vp, ll, s);   // expected-error {{passing 
'unsigned short' to parameter of incompatible type 'const __vector_pair *'}}
 }
+
+void testRestrictQualifiedPointer1(int *__restrict acc) {
+  vector float arr[4];
+  __builtin_mma_disassemble_acc((void*)arr, acc); // expected-error {{passing 
'int *restrict' to parameter of incompatible type '__vector_quad *'}}
+}
+
+void testRestrictQualifiedPointer2(__vector_quad *__restrict acc) {
+  vector float arr[4];
+  __builtin_mma_disassemble_acc((void*)arr, acc);
+}
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -7324,9 +7324,22 @@
 Expr *Arg = TheCall->getArg(ArgNum);
 QualType ArgType = Arg->getType();
 
-if ((ExpectedType->isVoidPointerType() && !ArgType->isPointerType()) ||
-(!ExpectedType->isVoidPointerType() &&
-   ArgType.getCanonicalType() != ExpectedType))
+// Checks if the argument type is valid. Returns true if it is valid
+// and false if it is not valid.
+auto IsValidType = [ArgType, ExpectedType]() {
+  if (ExpectedType->isVoidPointerType() && !ArgType->isPointerType())
+return false;
+  if (!ExpectedType->isVoidPointerType()) {
+if (ArgType.isRestrictQualified() &&
+ArgType.getCanonicalType().getUnqualifiedType() == ExpectedType)
+  return true;
+if (ArgType.getCanonicalType() != ExpectedType)
+  return false;
+  }
+  return true;
+};
+
+if (!IsValidType())
   return Diag(Arg->getBeginLoc(), diag::err_typecheck_convert_incompatible)
  << ArgType << ExpectedType << 1 << 0 << 0;
 


Index: clang/test/Sema/ppc-pair-mma-types.c
===
--- clang/test/Sema/ppc-pair-mma-types.c
+++ clang/test/Sema/ppc-pair-mma-types.c
@@ -333,3 +333,13 @@
   __vector_pair vp = __builtin_vsx_lxvp(ll, v); // expected-error {{passing '__vector int' (vector of 4 'int' values) to parameter of incompatible type 'const __vector_pair *'}}
   __builtin_vsx_stxvp(vp, ll, s);   // expected-error {{passing 'unsigned short' to parameter of incompatible type 'const __vector_pair *'}}
 }
+
+void testRestrictQualifiedPointer1(int *__restrict acc) {
+  vector float arr[4];
+  __builtin_mma_disassemble_acc((void*)arr, acc); // expected-error {{passing 'int *restrict' to parameter of incompatible type '__vector_quad *'}}
+}
+
+void testRestrictQualifiedPointer2(__vector_quad *__restrict acc) {
+  vector float arr[4];
+  __builtin_mma_disassemble_acc((void*)arr, acc);
+}
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -7324,9 +7324,22 @@
 Expr *Arg = TheCall->getArg(ArgNum);
 QualType ArgType = Arg->getType();
 
-if ((ExpectedType->isVoidPointerType() && !ArgType->isPointerType()) ||
-(!ExpectedType->isVoidPointerType() &&
-   ArgType.getCanonicalType() != ExpectedType))
+// Checks if the argument type is valid. Returns true if it is valid
+// and false if it is not valid.
+auto IsValidType = [ArgType, ExpectedType]() {
+  if (ExpectedType->isVoidPointerType() && !ArgType->isPointerType())
+return false;
+  if (!ExpectedType->isVoidPointerType()) {
+if (ArgType.isRestrictQualified() &&
+ArgType.getCanonicalType().getUnqualifiedType() == ExpectedType)
+  return true;
+if (ArgType.getCanonicalType() != ExpectedType)
+  return false;
+  }
+  return true;
+};
+
+if (!IsValidType())
   return Diag(Arg->getBeginLoc(), diag::err_typecheck_convert_incompatible)
  << ArgType << ExpectedType << 1 << 0 << 0;
 
___
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[PATCH] D106550: [PowerPC] Allow MMA builtins to accpet restrict qualified pointers

[Ahsan Saghir via Phabricator via cfe-commits]

saghir created this revision.
Herald added subscribers: steven.zhang, shchenz, kbarton, nemanjai.
saghir requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

This patch allows MMA builtins on PowerPC to accept restrict
qualified pointers.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D106550

Files:
  clang/lib/Sema/SemaChecking.cpp
  clang/test/Sema/ppc-pair-mma-types.c


Index: clang/test/Sema/ppc-pair-mma-types.c
===
--- clang/test/Sema/ppc-pair-mma-types.c
+++ clang/test/Sema/ppc-pair-mma-types.c
@@ -333,3 +333,8 @@
   __vector_pair vp = __builtin_vsx_lxvp(ll, v); // expected-error {{passing 
'__vector int' (vector of 4 'int' values) to parameter of incompatible type 
'const __vector_pair *'}}
   __builtin_vsx_stxvp(vp, ll, s);   // expected-error {{passing 
'unsigned short' to parameter of incompatible type 'const __vector_pair *'}}
 }
+
+void testRestrictQualifiedPointer(__vector_quad *__restrict acc) {
+  vector float arr[4];
+  __builtin_mma_disassemble_acc((void*)arr, acc);
+}
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -7303,7 +7303,8 @@
 
 if ((ExpectedType->isVoidPointerType() && !ArgType->isPointerType()) ||
 (!ExpectedType->isVoidPointerType() &&
-   ArgType.getCanonicalType() != ExpectedType))
+ (!ArgType.isRestrictQualified() &&
+  ArgType.getCanonicalType() != ExpectedType)))
   return Diag(Arg->getBeginLoc(), diag::err_typecheck_convert_incompatible)
  << ArgType << ExpectedType << 1 << 0 << 0;
 


Index: clang/test/Sema/ppc-pair-mma-types.c
===
--- clang/test/Sema/ppc-pair-mma-types.c
+++ clang/test/Sema/ppc-pair-mma-types.c
@@ -333,3 +333,8 @@
   __vector_pair vp = __builtin_vsx_lxvp(ll, v); // expected-error {{passing '__vector int' (vector of 4 'int' values) to parameter of incompatible type 'const __vector_pair *'}}
   __builtin_vsx_stxvp(vp, ll, s);   // expected-error {{passing 'unsigned short' to parameter of incompatible type 'const __vector_pair *'}}
 }
+
+void testRestrictQualifiedPointer(__vector_quad *__restrict acc) {
+  vector float arr[4];
+  __builtin_mma_disassemble_acc((void*)arr, acc);
+}
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -7303,7 +7303,8 @@
 
 if ((ExpectedType->isVoidPointerType() && !ArgType->isPointerType()) ||
 (!ExpectedType->isVoidPointerType() &&
-   ArgType.getCanonicalType() != ExpectedType))
+ (!ArgType.isRestrictQualified() &&
+  ArgType.getCanonicalType() != ExpectedType)))
   return Diag(Arg->getBeginLoc(), diag::err_typecheck_convert_incompatible)
  << ArgType << ExpectedType << 1 << 0 << 0;
 
___
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[PATCH] D100482: [PowerPC] Provide MMA builtins for compatibility

[Ahsan Saghir via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG25bbff632d01: [PowerPC] Provide MMA builtins for 
compatibility (authored by saghir).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D100482/new/

https://reviews.llvm.org/D100482

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-pair-mma.c

Index: clang/test/CodeGen/builtins-ppc-pair-mma.c
===
--- clang/test/CodeGen/builtins-ppc-pair-mma.c
+++ clang/test/CodeGen/builtins-ppc-pair-mma.c
@@ -5,7 +5,7 @@
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:[[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]], <16 x i8> [[VC]], <16 x i8> [[VC]])
 // CHECK-NEXT:[[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
-// CHECK-NEXT:store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa !2
+// CHECK-NEXT:store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa [[TBAA2:![0-9]+]]
 // CHECK-NEXT:ret void
 //
 void test1(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
@@ -46,7 +46,7 @@
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:[[TMP0:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]])
 // CHECK-NEXT:[[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <256 x i1>*
-// CHECK-NEXT:store <256 x i1> [[TMP0]], <256 x i1>* [[TMP1]], align 32, !tbaa !6
+// CHECK-NEXT:store <256 x i1> [[TMP0]], <256 x i1>* [[TMP1]], align 32, !tbaa [[TBAA6:![0-9]+]]
 // CHECK-NEXT:ret void
 //
 void test3(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
@@ -78,10 +78,10 @@
 // CHECK-LABEL: @test5(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:[[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
-// CHECK-NEXT:[[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa !2
+// CHECK-NEXT:[[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]]
 // CHECK-NEXT:[[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xxmtacc(<512 x i1> [[TMP1]])
 // CHECK-NEXT:[[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
-// CHECK-NEXT:store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa !2
+// CHECK-NEXT:store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa [[TBAA2]]
 // CHECK-NEXT:ret void
 //
 void test5(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
@@ -94,10 +94,10 @@
 // CHECK-LABEL: @test6(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:[[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
-// CHECK-NEXT:[[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa !2
+// CHECK-NEXT:[[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]]
 // CHECK-NEXT:[[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xxmfacc(<512 x i1> [[TMP1]])
 // CHECK-NEXT:[[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
-// CHECK-NEXT:store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa !2
+// CHECK-NEXT:store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa [[TBAA2]]
 // CHECK-NEXT:ret void
 //
 void test6(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
@@ -111,7 +111,7 @@
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:[[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xxsetaccz()
 // CHECK-NEXT:[[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
-// CHECK-NEXT:store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa !2
+// CHECK-NEXT:store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa [[TBAA2]]
 // CHECK-NEXT:ret void
 //
 void test7(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
@@ -125,7 +125,7 @@
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:[[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvi4ger8(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]])
 // CHECK-NEXT:[[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
-// CHECK-NEXT:store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa !2
+// CHECK-NEXT:store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa [[TBAA2]]
 // CHECK-NEXT:ret void
 //
 void test8(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
@@ -139,7 +139,7 @@
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:[[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvi8ger4(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]])
 // CHECK-NEXT:[[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
-// CHECK-NEXT:store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa !2
+// CHECK-NEXT:store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], 

[PATCH] D100482: [PowerPC] Provide MMA builtins for compatibility

[Ahsan Saghir via Phabricator via cfe-commits]

saghir updated this revision to Diff 342732.
saghir added a comment.

Addressed review comments to add _mma_ version of the built-ins as
aliases to the existing _vsx_ versions.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D100482/new/

https://reviews.llvm.org/D100482

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-pair-mma.c

Index: clang/test/CodeGen/builtins-ppc-pair-mma.c
===
--- clang/test/CodeGen/builtins-ppc-pair-mma.c
+++ clang/test/CodeGen/builtins-ppc-pair-mma.c
@@ -5,7 +5,7 @@
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:[[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]], <16 x i8> [[VC]], <16 x i8> [[VC]])
 // CHECK-NEXT:[[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
-// CHECK-NEXT:store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa !2
+// CHECK-NEXT:store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa [[TBAA2:![0-9]+]]
 // CHECK-NEXT:ret void
 //
 void test1(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
@@ -46,7 +46,7 @@
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:[[TMP0:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]])
 // CHECK-NEXT:[[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <256 x i1>*
-// CHECK-NEXT:store <256 x i1> [[TMP0]], <256 x i1>* [[TMP1]], align 32, !tbaa !6
+// CHECK-NEXT:store <256 x i1> [[TMP0]], <256 x i1>* [[TMP1]], align 32, !tbaa [[TBAA6:![0-9]+]]
 // CHECK-NEXT:ret void
 //
 void test3(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
@@ -78,10 +78,10 @@
 // CHECK-LABEL: @test5(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:[[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
-// CHECK-NEXT:[[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa !2
+// CHECK-NEXT:[[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]]
 // CHECK-NEXT:[[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xxmtacc(<512 x i1> [[TMP1]])
 // CHECK-NEXT:[[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
-// CHECK-NEXT:store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa !2
+// CHECK-NEXT:store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa [[TBAA2]]
 // CHECK-NEXT:ret void
 //
 void test5(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
@@ -94,10 +94,10 @@
 // CHECK-LABEL: @test6(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:[[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
-// CHECK-NEXT:[[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa !2
+// CHECK-NEXT:[[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]]
 // CHECK-NEXT:[[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xxmfacc(<512 x i1> [[TMP1]])
 // CHECK-NEXT:[[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
-// CHECK-NEXT:store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa !2
+// CHECK-NEXT:store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa [[TBAA2]]
 // CHECK-NEXT:ret void
 //
 void test6(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
@@ -111,7 +111,7 @@
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:[[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xxsetaccz()
 // CHECK-NEXT:[[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
-// CHECK-NEXT:store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa !2
+// CHECK-NEXT:store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa [[TBAA2]]
 // CHECK-NEXT:ret void
 //
 void test7(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
@@ -125,7 +125,7 @@
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:[[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvi4ger8(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]])
 // CHECK-NEXT:[[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
-// CHECK-NEXT:store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa !2
+// CHECK-NEXT:store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa [[TBAA2]]
 // CHECK-NEXT:ret void
 //
 void test8(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
@@ -139,7 +139,7 @@
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:[[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvi8ger4(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]])
 // CHECK-NEXT:[[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
-// CHECK-NEXT:store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa !2
+// CHECK-NEXT:store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa [[TBAA2]]
 // CHECK-NEXT:ret void
 //
 

[PATCH] D100482: [PowerPC] Provide MMA builtins for compatability

[Ahsan Saghir via Phabricator via cfe-commits]

saghir updated this revision to Diff 337765.
saghir added a comment.

Fixed spelling.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D100482/new/

https://reviews.llvm.org/D100482

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-pair-mma.c
  clang/test/Sema/ppc-pair-mma-types.c
  clang/test/SemaCXX/ppc-pair-mma-types.cpp
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCInstrPrefix.td
  llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
  llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
  llvm/test/CodeGen/PowerPC/dform-pair-load-store.ll
  llvm/test/CodeGen/PowerPC/loop-p10-pair-prepare.ll
  llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
  llvm/test/CodeGen/PowerPC/mma-outer-product.ll
  llvm/test/CodeGen/PowerPC/mma-phi-accs.ll
  llvm/test/CodeGen/PowerPC/more-dq-form-prepare.ll
  llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll

Index: llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
===
--- llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
+++ llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
@@ -51,6 +51,42 @@
   ret void
 }
 
+; assemble_pair
+declare <256 x i1> @llvm.ppc.mma.assemble.pair(<16 x i8>, <16 x i8>)
+define void @ass_pair1(<256 x i1>* %ptr, <16 x i8> %vc) {
+; CHECK-LABEL: ass_pair1:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vmr v3, v2
+; CHECK-NEXT:stxv v2, 16(r3)
+; CHECK-NEXT:stxv v3, 0(r3)
+; CHECK-NEXT:blr
+;
+; CHECK-NOMMA-LABEL: ass_pair1:
+; CHECK-NOMMA:   # %bb.0: # %entry
+; CHECK-NOMMA-NEXT:vmr v3, v2
+; CHECK-NOMMA-NEXT:stxv v2, 16(r3)
+; CHECK-NOMMA-NEXT:stxv v3, 0(r3)
+; CHECK-NOMMA-NEXT:blr
+;
+; CHECK-BE-LABEL: ass_pair1:
+; CHECK-BE:   # %bb.0: # %entry
+; CHECK-BE-NEXT:vmr v3, v2
+; CHECK-BE-NEXT:stxv v2, 16(r3)
+; CHECK-BE-NEXT:stxv v2, 0(r3)
+; CHECK-BE-NEXT:blr
+;
+; CHECK-BE-NOMMA-LABEL: ass_pair1:
+; CHECK-BE-NOMMA:   # %bb.0: # %entry
+; CHECK-BE-NOMMA-NEXT:vmr v3, v2
+; CHECK-BE-NOMMA-NEXT:stxv v2, 16(r3)
+; CHECK-BE-NOMMA-NEXT:stxv v2, 0(r3)
+; CHECK-BE-NOMMA-NEXT:blr
+entry:
+  %0 = tail call <256 x i1> @llvm.ppc.mma.assemble.pair(<16 x i8> %vc, <16 x i8> %vc)
+  store <256 x i1> %0, <256 x i1>* %ptr, align 32
+  ret void
+}
+
 ; disassemble_pair
 declare { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1>)
 define void @disass_pair(<256 x i1>* %ptr1, <16 x i8>* %ptr2, <16 x i8>* %ptr3) {
@@ -95,6 +131,50 @@
   ret void
 }
 
+; disassemble_pair
+declare { <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.pair(<256 x i1>)
+define void @disass_pair1(<256 x i1>* %ptr1, <16 x i8>* %ptr2, <16 x i8>* %ptr3) {
+; CHECK-LABEL: disass_pair1:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:lxv vs1, 0(r3)
+; CHECK-NEXT:lxv vs0, 16(r3)
+; CHECK-NEXT:stxv vs1, 0(r4)
+; CHECK-NEXT:stxv vs0, 0(r5)
+; CHECK-NEXT:blr
+;
+; CHECK-NOMMA-LABEL: disass_pair1:
+; CHECK-NOMMA:   # %bb.0: # %entry
+; CHECK-NOMMA-NEXT:lxv vs1, 0(r3)
+; CHECK-NOMMA-NEXT:lxv vs0, 16(r3)
+; CHECK-NOMMA-NEXT:stxv vs1, 0(r4)
+; CHECK-NOMMA-NEXT:stxv vs0, 0(r5)
+; CHECK-NOMMA-NEXT:blr
+;
+; CHECK-BE-LABEL: disass_pair1:
+; CHECK-BE:   # %bb.0: # %entry
+; CHECK-BE-NEXT:lxv vs1, 16(r3)
+; CHECK-BE-NEXT:lxv vs0, 0(r3)
+; CHECK-BE-NEXT:stxv vs0, 0(r4)
+; CHECK-BE-NEXT:stxv vs1, 0(r5)
+; CHECK-BE-NEXT:blr
+;
+; CHECK-BE-NOMMA-LABEL: disass_pair1:
+; CHECK-BE-NOMMA:   # %bb.0: # %entry
+; CHECK-BE-NOMMA-NEXT:lxv vs1, 16(r3)
+; CHECK-BE-NOMMA-NEXT:lxv vs0, 0(r3)
+; CHECK-BE-NOMMA-NEXT:stxv vs0, 0(r4)
+; CHECK-BE-NOMMA-NEXT:stxv vs1, 0(r5)
+; CHECK-BE-NOMMA-NEXT:blr
+entry:
+  %0 = load <256 x i1>, <256 x i1>* %ptr1, align 32
+  %1 = tail call { <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.pair(<256 x i1> %0)
+  %2 = extractvalue { <16 x i8>, <16 x i8> } %1, 0
+  %3 = extractvalue { <16 x i8>, <16 x i8> } %1, 1
+  store <16 x i8> %2, <16 x i8>* %ptr2, align 16
+  store <16 x i8> %3, <16 x i8>* %ptr3, align 16
+  ret void
+}
+
 define void @test_ldst_1(<256 x i1>* %vpp, <256 x i1>* %vp2) {
 ; CHECK-LABEL: test_ldst_1:
 ; CHECK:   # %bb.0: # %entry
@@ -127,8 +207,42 @@
   ret void
 }
 
+define void @test_ldst_1a(<256 x i1>* %vpp, <256 x i1>* %vp2) {
+; CHECK-LABEL: test_ldst_1a:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:lxvp vsp0, 0(r3)
+; CHECK-NEXT:stxvp vsp0, 0(r4)
+; CHECK-NEXT:blr
+;
+; CHECK-NOMMA-LABEL: test_ldst_1a:
+; CHECK-NOMMA:   # %bb.0: # %entry
+; CHECK-NOMMA-NEXT:lxvp vsp0, 0(r3)
+; CHECK-NOMMA-NEXT:stxvp vsp0, 0(r4)
+; CHECK-NOMMA-NEXT:blr
+;
+; CHECK-BE-LABEL: test_ldst_1a:
+; CHECK-BE:   # %bb.0: # %entry
+; CHECK-BE-NEXT:lxvp vsp0, 0(r3)
+; CHECK-BE-NEXT:stxvp vsp0, 0(r4)
+; CHECK-BE-NEXT:blr
+;

[PATCH] D96265: [PowerPC] Change target data layout for 16-byte stack alignment

[Ahsan Saghir via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGacce401068e7: [PowerPC] Change target data layout for 
16-byte stack alignment (authored by saghir).

Changed prior to commit:
  https://reviews.llvm.org/D96265?vs=323451=328994#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D96265/new/

https://reviews.llvm.org/D96265

Files:
  clang/lib/Basic/Targets/PPC.h
  clang/test/CodeGen/target-data.c
  lld/test/ELF/common-archive-lookup.s
  llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
  llvm/test/CodeGen/PowerPC/P10-stack-alignment.ll

Index: llvm/test/CodeGen/PowerPC/P10-stack-alignment.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/P10-stack-alignment.ll
@@ -0,0 +1,214 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN:   FileCheck %s --check-prefix=CHECK-LE
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN:   FileCheck %s --check-prefix=CHECK-BE
+; RUN: opt --passes=sroa,loop-vectorize,loop-unroll,instcombine -S \
+; RUN: -vectorizer-maximize-bandwidth --mtriple=powerpc64le-- -mcpu=pwr10 < %s | \
+; RUN: FileCheck %s --check-prefix=CHECK-OPT
+
+target datalayout = "e-m:e-i64:64-n32:64-S128-v256:256:256-v512:512:512"
+
+define dso_local signext i32 @test_32byte_vector() nounwind {
+; CHECK-LE-LABEL: test_32byte_vector:
+; CHECK-LE:   # %bb.0: # %entry
+; CHECK-LE-NEXT:mflr r0
+; CHECK-LE-NEXT:std r30, -16(r1)
+; CHECK-LE-NEXT:mr r30, r1
+; CHECK-LE-NEXT:std r0, 16(r1)
+; CHECK-LE-NEXT:clrldi r0, r1, 59
+; CHECK-LE-NEXT:subfic r0, r0, -96
+; CHECK-LE-NEXT:stdux r1, r1, r0
+; CHECK-LE-NEXT:addis r3, r2, .LCPI0_0@toc@ha
+; CHECK-LE-NEXT:addis r4, r2, .LCPI0_1@toc@ha
+; CHECK-LE-NEXT:addi r3, r3, .LCPI0_0@toc@l
+; CHECK-LE-NEXT:addi r4, r4, .LCPI0_1@toc@l
+; CHECK-LE-NEXT:lvx v2, 0, r3
+; CHECK-LE-NEXT:lvx v3, 0, r4
+; CHECK-LE-NEXT:addi r4, r1, 48
+; CHECK-LE-NEXT:addi r3, r1, 32
+; CHECK-LE-NEXT:stvx v2, 0, r4
+; CHECK-LE-NEXT:stvx v3, 0, r3
+; CHECK-LE-NEXT:bl test
+; CHECK-LE-NEXT:nop
+; CHECK-LE-NEXT:lwa r3, 32(r1)
+; CHECK-LE-NEXT:mr r1, r30
+; CHECK-LE-NEXT:ld r0, 16(r1)
+; CHECK-LE-NEXT:ld r30, -16(r1)
+; CHECK-LE-NEXT:mtlr r0
+; CHECK-LE-NEXT:blr
+;
+; CHECK-BE-LABEL: test_32byte_vector:
+; CHECK-BE:   # %bb.0: # %entry
+; CHECK-BE-NEXT:mflr r0
+; CHECK-BE-NEXT:std r30, -16(r1)
+; CHECK-BE-NEXT:std r0, 16(r1)
+; CHECK-BE-NEXT:clrldi r0, r1, 59
+; CHECK-BE-NEXT:mr r30, r1
+; CHECK-BE-NEXT:subfic r0, r0, -192
+; CHECK-BE-NEXT:stdux r1, r1, r0
+; CHECK-BE-NEXT:lis r3, -8192
+; CHECK-BE-NEXT:li r4, 5
+; CHECK-BE-NEXT:lis r5, -16384
+; CHECK-BE-NEXT:lis r6, -32768
+; CHECK-BE-NEXT:ori r3, r3, 1
+; CHECK-BE-NEXT:rldic r4, r4, 32, 29
+; CHECK-BE-NEXT:ori r5, r5, 1
+; CHECK-BE-NEXT:ori r6, r6, 1
+; CHECK-BE-NEXT:rldic r3, r3, 3, 29
+; CHECK-BE-NEXT:ori r4, r4, 6
+; CHECK-BE-NEXT:rldic r5, r5, 2, 30
+; CHECK-BE-NEXT:rldic r6, r6, 1, 31
+; CHECK-BE-NEXT:std r3, 152(r1)
+; CHECK-BE-NEXT:addi r3, r1, 128
+; CHECK-BE-NEXT:std r4, 144(r1)
+; CHECK-BE-NEXT:std r5, 136(r1)
+; CHECK-BE-NEXT:std r6, 128(r1)
+; CHECK-BE-NEXT:bl test
+; CHECK-BE-NEXT:nop
+; CHECK-BE-NEXT:lwa r3, 128(r1)
+; CHECK-BE-NEXT:mr r1, r30
+; CHECK-BE-NEXT:ld r0, 16(r1)
+; CHECK-BE-NEXT:ld r30, -16(r1)
+; CHECK-BE-NEXT:mtlr r0
+; CHECK-BE-NEXT:blr
+entry:
+  %a = alloca <8 x i32>, align 32
+  %0 = bitcast <8 x i32>* %a to i8*
+  call void @llvm.lifetime.start.p0i8(i64 32, i8* %0)
+  store <8 x i32> , <8 x i32>* %a, align 32
+  call void @test(<8 x i32>* %a)
+  %1 = load <8 x i32>, <8 x i32>* %a, align 32
+  %vecext = extractelement <8 x i32> %1, i32 0
+  %2 = bitcast <8 x i32>* %a to i8*
+  call void @llvm.lifetime.end.p0i8(i64 32, i8* %2)
+  ret i32 %vecext
+}
+
+define dso_local signext i32 @test_32byte_aligned_vector() nounwind {
+; CHECK-LE-LABEL: test_32byte_aligned_vector:
+; CHECK-LE:   # %bb.0: # %entry
+; CHECK-LE-NEXT:mflr r0
+; CHECK-LE-NEXT:std r30, -16(r1)
+; CHECK-LE-NEXT:mr r30, r1
+; CHECK-LE-NEXT:std r0, 16(r1)
+; CHECK-LE-NEXT:clrldi r0, r1, 59
+; CHECK-LE-NEXT:subfic r0, r0, -64
+; CHECK-LE-NEXT:stdux r1, r1, r0
+; CHECK-LE-NEXT:addis r3, r2, .LCPI1_0@toc@ha
+; CHECK-LE-NEXT:addi r3, r3, .LCPI1_0@toc@l
+; CHECK-LE-NEXT:lvx v2, 0, r3
+; CHECK-LE-NEXT:addi r3, r1, 32
+; CHECK-LE-NEXT:stvx v2, 0, r3
+; CHECK-LE-NEXT:bl test1
+; CHECK-LE-NEXT:nop
+; CHECK-LE-NEXT:lwa 

[PATCH] D96265: [PowerPC] Change target data layout for 16-byte stack alignment

[Ahsan Saghir via Phabricator via cfe-commits]

saghir updated this revision to Diff 323451.
saghir added a comment.

Updated tests to add run line for llc and target datalayout.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D96265/new/

https://reviews.llvm.org/D96265

Files:
  clang/lib/Basic/Targets/PPC.h
  clang/test/CodeGen/target-data.c
  lld/test/ELF/common-archive-lookup.s
  llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
  llvm/test/CodeGen/PowerPC/P10-stack-alignment.ll

Index: llvm/test/CodeGen/PowerPC/P10-stack-alignment.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/P10-stack-alignment.ll
@@ -0,0 +1,216 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN:   FileCheck %s --check-prefix=CHECK-LE
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN:   FileCheck %s --check-prefix=CHECK-BE
+; RUN: opt --passes=sroa,loop-vectorize,loop-unroll,instcombine -S \
+; RUN: -vectorizer-maximize-bandwidth --mtriple=powerpc64le-- -mcpu=pwr10 < %s | \
+; RUN: FileCheck %s --check-prefix=CHECK-OPT
+
+target datalayout = "e-m:e-i64:64-n32:64-S128-v256:256:256-v512:512:512"
+
+define dso_local signext i32 @test_32byte_vector() nounwind {
+; CHECK-LE-LABEL: test_32byte_vector:
+; CHECK-LE:   # %bb.0: # %entry
+; CHECK-LE-NEXT:mflr r0
+; CHECK-LE-NEXT:std r30, -16(r1)
+; CHECK-LE-NEXT:mr r30, r1
+; CHECK-LE-NEXT:std r0, 16(r1)
+; CHECK-LE-NEXT:clrldi r0, r1, 59
+; CHECK-LE-NEXT:subfic r0, r0, -96
+; CHECK-LE-NEXT:stdux r1, r1, r0
+; CHECK-LE-NEXT:addis r3, r2, .LCPI0_0@toc@ha
+; CHECK-LE-NEXT:addis r4, r2, .LCPI0_1@toc@ha
+; CHECK-LE-NEXT:addi r3, r3, .LCPI0_0@toc@l
+; CHECK-LE-NEXT:addi r4, r4, .LCPI0_1@toc@l
+; CHECK-LE-NEXT:lvx v2, 0, r3
+; CHECK-LE-NEXT:lvx v3, 0, r4
+; CHECK-LE-NEXT:addi r4, r1, 48
+; CHECK-LE-NEXT:addi r3, r1, 32
+; CHECK-LE-NEXT:stvx v2, 0, r4
+; CHECK-LE-NEXT:stvx v3, 0, r3
+; CHECK-LE-NEXT:bl test
+; CHECK-LE-NEXT:nop
+; CHECK-LE-NEXT:lwa r3, 32(r1)
+; CHECK-LE-NEXT:mr r1, r30
+; CHECK-LE-NEXT:ld r0, 16(r1)
+; CHECK-LE-NEXT:ld r30, -16(r1)
+; CHECK-LE-NEXT:mtlr r0
+; CHECK-LE-NEXT:blr
+;
+; CHECK-BE-LABEL: test_32byte_vector:
+; CHECK-BE:   # %bb.0: # %entry
+; CHECK-BE-NEXT:mflr r0
+; CHECK-BE-NEXT:std r30, -16(r1)
+; CHECK-BE-NEXT:std r0, 16(r1)
+; CHECK-BE-NEXT:clrldi r0, r1, 59
+; CHECK-BE-NEXT:mr r30, r1
+; CHECK-BE-NEXT:subfic r0, r0, -192
+; CHECK-BE-NEXT:stdux r1, r1, r0
+; CHECK-BE-NEXT:lis r3, -8192
+; CHECK-BE-NEXT:li r4, 5
+; CHECK-BE-NEXT:lis r5, -16384
+; CHECK-BE-NEXT:lis r6, -32768
+; CHECK-BE-NEXT:ori r3, r3, 1
+; CHECK-BE-NEXT:rldic r4, r4, 32, 29
+; CHECK-BE-NEXT:ori r5, r5, 1
+; CHECK-BE-NEXT:ori r6, r6, 1
+; CHECK-BE-NEXT:rldic r3, r3, 3, 29
+; CHECK-BE-NEXT:ori r4, r4, 6
+; CHECK-BE-NEXT:rldic r5, r5, 2, 30
+; CHECK-BE-NEXT:rldic r6, r6, 1, 31
+; CHECK-BE-NEXT:std r3, 152(r1)
+; CHECK-BE-NEXT:addi r3, r1, 128
+; CHECK-BE-NEXT:std r4, 144(r1)
+; CHECK-BE-NEXT:std r5, 136(r1)
+; CHECK-BE-NEXT:std r6, 128(r1)
+; CHECK-BE-NEXT:bl test
+; CHECK-BE-NEXT:nop
+; CHECK-BE-NEXT:lwa r3, 128(r1)
+; CHECK-BE-NEXT:mr r1, r30
+; CHECK-BE-NEXT:ld r0, 16(r1)
+; CHECK-BE-NEXT:ld r30, -16(r1)
+; CHECK-BE-NEXT:mtlr r0
+; CHECK-BE-NEXT:blr
+entry:
+  %a = alloca <8 x i32>, align 32
+  %0 = bitcast <8 x i32>* %a to i8*
+  call void @llvm.lifetime.start.p0i8(i64 32, i8* %0)
+  store <8 x i32> , <8 x i32>* %a, align 32
+  call void @test(<8 x i32>* %a)
+  %1 = load <8 x i32>, <8 x i32>* %a, align 32
+  %vecext = extractelement <8 x i32> %1, i32 0
+  %2 = bitcast <8 x i32>* %a to i8*
+  call void @llvm.lifetime.end.p0i8(i64 32, i8* %2)
+  ret i32 %vecext
+}
+
+define dso_local signext i32 @test_32byte_aligned_vector() nounwind {
+; CHECK-LE-LABEL: test_32byte_aligned_vector:
+; CHECK-LE:   # %bb.0: # %entry
+; CHECK-LE-NEXT:mflr r0
+; CHECK-LE-NEXT:std r30, -16(r1)
+; CHECK-LE-NEXT:mr r30, r1
+; CHECK-LE-NEXT:std r0, 16(r1)
+; CHECK-LE-NEXT:clrldi r0, r1, 59
+; CHECK-LE-NEXT:subfic r0, r0, -64
+; CHECK-LE-NEXT:stdux r1, r1, r0
+; CHECK-LE-NEXT:addis r3, r2, .LCPI1_0@toc@ha
+; CHECK-LE-NEXT:addi r3, r3, .LCPI1_0@toc@l
+; CHECK-LE-NEXT:lvx v2, 0, r3
+; CHECK-LE-NEXT:addi r3, r1, 32
+; CHECK-LE-NEXT:stvx v2, 0, r3
+; CHECK-LE-NEXT:bl test1
+; CHECK-LE-NEXT:nop
+; CHECK-LE-NEXT:lwa r3, 32(r1)
+; CHECK-LE-NEXT:mr r1, r30
+; CHECK-LE-NEXT:ld r0, 16(r1)
+; CHECK-LE-NEXT:ld r30, -16(r1)
+; CHECK-LE-NEXT:mtlr r0
+; CHECK-LE-NEXT:blr
+;
+; CHECK-BE-LABEL: 

[PATCH] D96265: [PowerPC] Change target data layout for 16-byte stack alignment

[Ahsan Saghir via Phabricator via cfe-commits]

saghir updated this revision to Diff 323307.
saghir added a comment.

Merged tests into one file.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D96265/new/

https://reviews.llvm.org/D96265

Files:
  clang/lib/Basic/Targets/PPC.h
  clang/test/CodeGen/target-data.c
  lld/test/ELF/common-archive-lookup.s
  llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
  llvm/test/CodeGen/PowerPC/P10-stack-alignment.ll

Index: llvm/test/CodeGen/PowerPC/P10-stack-alignment.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/P10-stack-alignment.ll
@@ -0,0 +1,106 @@
+; RUN: opt --passes=sroa,loop-vectorize,loop-unroll,instcombine -S \
+; RUN: -vectorizer-maximize-bandwidth --mtriple=powerpc64le-- < %s | \
+; RUN: FileCheck %s
+
+
+define dso_local signext i32 @test_32byte_vector() nounwind {
+; CHECK-LABEL: @test_32byte_vector(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = alloca <8 x i32>, align 32
+; CHECK: store <8 x i32> , <8 x i32>* [[TMP0:%.*]], align 32
+; CHECK: load <8 x i32>, <8 x i32>* [[TMP0:%.*]], align 32
+entry:
+  %a = alloca <8 x i32>, align 32
+  %0 = bitcast <8 x i32>* %a to i8*
+  call void @llvm.lifetime.start.p0i8(i64 32, i8* %0)
+  store <8 x i32> , <8 x i32>* %a, align 32
+  call void @test(<8 x i32>* %a)
+  %1 = load <8 x i32>, <8 x i32>* %a, align 32
+  %vecext = extractelement <8 x i32> %1, i32 0
+  %2 = bitcast <8 x i32>* %a to i8*
+  call void @llvm.lifetime.end.p0i8(i64 32, i8* %2)
+  ret i32 %vecext
+}
+
+define dso_local signext i32 @test_32byte_aligned_vector() nounwind {
+; CHECK-LABEL: @test_32byte_aligned_vector(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = alloca <4 x i32>, align 32
+; CHECK: store <4 x i32> , <4 x i32>* [[TMP0:%.*]], align 32
+
+entry:
+  %a = alloca <4 x i32>, align 32
+  %0 = bitcast <4 x i32>* %a to i8*
+  call void @llvm.lifetime.start.p0i8(i64 16, i8* %0)
+  store <4 x i32> , <4 x i32>* %a, align 32
+  call void @test1(<4 x i32>* %a)
+  %1 = load <4 x i32>, <4 x i32>* %a, align 32
+  %vecext = extractelement <4 x i32> %1, i32 0
+  %2 = bitcast <4 x i32>* %a to i8*
+  call void @llvm.lifetime.end.p0i8(i64 16, i8* %2)
+  ret i32 %vecext
+}
+
+
+@Arr1 = dso_local global [64 x i8] zeroinitializer, align 1
+
+define dso_local void @test_Array() nounwind {
+; CHECK-LABEL: @test_Array(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: %Arr2 = alloca [64 x i16], align 32
+; CHECK: store <16 x i16> [[TMP0:%.*]], <16 x i16>* [[TMP0:%.*]], align 32
+entry:
+  %Arr2 = alloca [64 x i16], align 2
+  %i = alloca i32, align 4
+  %0 = bitcast [64 x i16]* %Arr2 to i8*
+  call void @llvm.lifetime.start.p0i8(i64 128, i8* %0)
+  %1 = bitcast i32* %i to i8*
+  call void @llvm.lifetime.start.p0i8(i64 4, i8* %1)
+  store i32 0, i32* %i, align 4
+  br label %for.cond
+
+for.cond: ; preds = %for.inc, %entry
+  %2 = load i32, i32* %i, align 4
+  %cmp = icmp slt i32 %2, 64
+  br i1 %cmp, label %for.body, label %for.cond.cleanup
+
+for.cond.cleanup: ; preds = %for.cond
+  %3 = bitcast i32* %i to i8*
+  call void @llvm.lifetime.end.p0i8(i64 4, i8* %3)
+  br label %for.end
+
+for.body: ; preds = %for.cond
+  %4 = load i32, i32* %i, align 4
+  %idxprom = sext i32 %4 to i64
+  %arrayidx = getelementptr inbounds [64 x i8], [64 x i8]* @Arr1, i64 0, i64 %idxprom
+  %5 = load i8, i8* %arrayidx, align 1
+  %conv = zext i8 %5 to i16
+  %6 = load i32, i32* %i, align 4
+  %idxprom1 = sext i32 %6 to i64
+  %arrayidx2 = getelementptr inbounds [64 x i16], [64 x i16]* %Arr2, i64 0, i64 %idxprom1
+  store i16 %conv, i16* %arrayidx2, align 2
+  br label %for.inc
+
+for.inc:  ; preds = %for.body
+  %7 = load i32, i32* %i, align 4
+  %inc = add nsw i32 %7, 1
+  store i32 %inc, i32* %i, align 4
+  br label %for.cond
+
+for.end:  ; preds = %for.cond.cleanup
+  %arraydecay = getelementptr inbounds [64 x i16], [64 x i16]* %Arr2, i64 0, i64 0
+  call void @test_arr(i16* %arraydecay)
+  %8 = bitcast [64 x i16]* %Arr2 to i8*
+  call void @llvm.lifetime.end.p0i8(i64 128, i8* %8)
+  ret void
+}
+
+declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture) nounwind
+
+declare void @test(<8 x i32>*) nounwind
+declare void @test1(<4 x i32>*) nounwind
+declare void @test_arr(i16*)
+
+declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture) nounwind
+
+
Index: llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
===
--- llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
+++ llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
@@ -157,9 +157,8 @@
   // Specify the vector alignment explicitly. For v256i1 and v512i1, the
   // calculated alignment would be 256*alignment(i1) and 512*alignment(i1),
   // which is 256 and 512 bytes - way over aligned.
-  if ((T.getArch() == 

[PATCH] D96265: [PowerPC] Change target data layout for 16-byte stack alignment

[Ahsan Saghir via Phabricator via cfe-commits]

saghir created this revision.
Herald added subscribers: shchenz, kbarton, hiraditya, nemanjai, emaste.
saghir requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, MaskRay.
Herald added projects: clang, LLVM.

This changes the target data layout to make stack align to 16 bytes
on Power10. Before this change, stack was being aligned to 32 bytes.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D96265

Files:
  clang/lib/Basic/Targets/PPC.h
  clang/test/CodeGen/target-data.c
  lld/test/ELF/common-archive-lookup.s
  llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
  llvm/test/CodeGen/PowerPC/32byte-aligned-vector-stack-alignment.ll
  llvm/test/CodeGen/PowerPC/32byte-array-stack-alignment.ll
  llvm/test/CodeGen/PowerPC/32byte-vector-stack-alignment.ll
  llvm/test/CodeGen/PowerPC/P10-stack-alignment.ll

Index: llvm/test/CodeGen/PowerPC/P10-stack-alignment.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/P10-stack-alignment.ll
@@ -0,0 +1,316 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN:   FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN:   FileCheck %s --check-prefix=CHECK-BE
+
+@.str = private unnamed_addr constant [7 x i8] c"%d %d\0A\00", align 1
+
+define dso_local signext i32 @test() local_unnamed_addr nounwind {
+; CHECK-LABEL: test:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mflr r0
+; CHECK-NEXT:std r30, -16(r1)
+; CHECK-NEXT:mr r30, r1
+; CHECK-NEXT:std r0, 16(r1)
+; CHECK-NEXT:clrldi r0, r1, 59
+; CHECK-NEXT:subfic r0, r0, -448
+; CHECK-NEXT:stdux r1, r1, r0
+; CHECK-NEXT:addi r3, r1, 96
+; CHECK-NEXT:li r4, 0
+; CHECK-NEXT:li r5, 200
+; CHECK-NEXT:bl memset@notoc
+; CHECK-NEXT:plxv v2, .LCPI0_1@PCREL(0), 1
+; CHECK-NEXT:plxv v5, .LCPI0_0@PCREL(0), 1
+; CHECK-NEXT:pli r3, 1684234849
+; CHECK-NEXT:plxv v1, .LCPI0_3@PCREL(0), 1
+; CHECK-NEXT:plxv v0, .LCPI0_2@PCREL(0), 1
+; CHECK-NEXT:plxv v7, .LCPI0_5@PCREL(0), 1
+; CHECK-NEXT:plxv v6, .LCPI0_4@PCREL(0), 1
+; CHECK-NEXT:stw r3, 416(r1)
+; CHECK-NEXT:vmrghb v4, v2, v2
+; CHECK-NEXT:vmrglb v3, v2, v2
+; CHECK-NEXT:stxv v2, 320(r1)
+; CHECK-NEXT:xxspltiw v2, 524296
+; CHECK-NEXT:stxv v5, 336(r1)
+; CHECK-NEXT:stxv v0, 368(r1)
+; CHECK-NEXT:stxv v1, 352(r1)
+; CHECK-NEXT:stxv v6, 400(r1)
+; CHECK-NEXT:stxv v7, 384(r1)
+; CHECK-NEXT:vslh v4, v4, v2
+; CHECK-NEXT:vslh v3, v3, v2
+; CHECK-NEXT:vsrh v4, v4, v2
+; CHECK-NEXT:vsrh v3, v3, v2
+; CHECK-NEXT:stxv v4, 112(r1)
+; CHECK-NEXT:vmrglb v4, v5, v5
+; CHECK-NEXT:stxv v3, 96(r1)
+; CHECK-NEXT:vmrglb v3, v1, v1
+; CHECK-NEXT:li r3, 97
+; CHECK-NEXT:vmrghb v5, v5, v5
+; CHECK-NEXT:lha r5, 96(r1)
+; CHECK-NEXT:sth r3, 288(r1)
+; CHECK-NEXT:pli r3, 6488162
+; CHECK-NEXT:vslh v4, v4, v2
+; CHECK-NEXT:vslh v3, v3, v2
+; CHECK-NEXT:stw r3, 290(r1)
+; CHECK-NEXT:li r3, 100
+; CHECK-NEXT:vslh v5, v5, v2
+; CHECK-NEXT:vsrh v4, v4, v2
+; CHECK-NEXT:vsrh v3, v3, v2
+; CHECK-NEXT:sth r3, 294(r1)
+; CHECK-NEXT:lbz r3, 320(r1)
+; CHECK-NEXT:vsrh v5, v5, v2
+; CHECK-NEXT:stxv v4, 128(r1)
+; CHECK-NEXT:vmrghb v4, v1, v1
+; CHECK-NEXT:stxv v3, 160(r1)
+; CHECK-NEXT:vmrglb v3, v0, v0
+; CHECK-NEXT:stxv v5, 144(r1)
+; CHECK-NEXT:extsb r4, r3
+; CHECK-NEXT:paddi r3, 0, .L.str@PCREL, 1
+; CHECK-NEXT:vslh v4, v4, v2
+; CHECK-NEXT:vslh v3, v3, v2
+; CHECK-NEXT:vsrh v4, v4, v2
+; CHECK-NEXT:vsrh v3, v3, v2
+; CHECK-NEXT:stxv v4, 176(r1)
+; CHECK-NEXT:vmrghb v4, v0, v0
+; CHECK-NEXT:stxv v3, 192(r1)
+; CHECK-NEXT:vslh v4, v4, v2
+; CHECK-NEXT:vsrh v4, v4, v2
+; CHECK-NEXT:stxv v4, 208(r1)
+; CHECK-NEXT:vmrglb v4, v7, v7
+; CHECK-NEXT:vslh v4, v4, v2
+; CHECK-NEXT:vsrh v3, v4, v2
+; CHECK-NEXT:vmrghb v4, v7, v7
+; CHECK-NEXT:stxv v3, 224(r1)
+; CHECK-NEXT:vmrglb v3, v6, v6
+; CHECK-NEXT:vslh v4, v4, v2
+; CHECK-NEXT:vsrh v4, v4, v2
+; CHECK-NEXT:vslh v3, v3, v2
+; CHECK-NEXT:stxv v4, 240(r1)
+; CHECK-NEXT:vmrghb v4, v6, v6
+; CHECK-NEXT:vsrh v3, v3, v2
+; CHECK-NEXT:stxv v3, 256(r1)
+; CHECK-NEXT:vslh v4, v4, v2
+; CHECK-NEXT:vsrh v2, v4, v2
+; CHECK-NEXT:stxv v2, 272(r1)
+; CHECK-NEXT:bl printf@notoc
+; CHECK-NEXT:li r3, 0
+; CHECK-NEXT:mr r1, r30
+; CHECK-NEXT:ld r0, 16(r1)
+; CHECK-NEXT:ld r30, -16(r1)
+; CHECK-NEXT:mtlr r0
+; CHECK-NEXT:blr
+;
+; CHECK-BE-LABEL: test:
+; CHECK-BE:   # %bb.0: # %entry
+; CHECK-BE-NEXT:mflr r0
+; CHECK-BE-NEXT:   

[PATCH] D91819: [PowerPC] Enable paired vector type and intrinsics when MMA is disabled

[Ahsan Saghir via Phabricator via cfe-commits]

saghir accepted this revision.
saghir added a comment.
This revision is now accepted and ready to land.

LGTM.


Repository:
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[PATCH] D91974: [PowerPC] Rename the vector pair intrinsics and builtins to replace the _mma_ prefix by _vsx_

[Ahsan Saghir via Phabricator via cfe-commits]

saghir accepted this revision.
saghir added a comment.

LGTM. A minor nit regarding an incomplete comment in 
`llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll` which can be addressed 
when committing the patch.


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[PATCH] D90799: [PowerPC] Add paired vector load and store builtins and intrinsics

[Ahsan Saghir via Phabricator via cfe-commits]

saghir accepted this revision.
saghir added a comment.

LGTM.


Repository:
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[PATCH] D87921: Fix -funique-internal-linkage-names to work with -O2 and new pass manager

[Ahsan Saghir via Phabricator via cfe-commits]

saghir added a comment.

In D87921#2288096 , @morehouse wrote:

> Thanks for looking.  Indeed, it looks like an issue with the disk being full 
> on the bot.

Hi, I checked the disk is not full on the bot. I am not sure what is going on 
here but its definitely not a disk space issue.


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[PATCH] D81816: [PowerPC] Add support for vector bool __int128 for Power10

[Ahsan Saghir via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
saghir marked an inline comment as done.
Closed by commit rGf4c337ab85c0: [PowerPC] Add support for vector bool __int128 
for Power10 (authored by saghir).

Changed prior to commit:
  https://reviews.llvm.org/D81816?vs=271874=272896#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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Files:
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Sema/DeclSpec.cpp
  clang/test/Parser/altivec-bool-128.c
  clang/test/Parser/cxx-altivec-bool-128.cpp
  clang/test/Parser/p10-vector-bool-128.c

Index: clang/test/Parser/p10-vector-bool-128.c
===
--- /dev/null
+++ clang/test/Parser/p10-vector-bool-128.c
@@ -0,0 +1,12 @@
+// RUN: %clang_cc1 -triple=powerpc64-unknown-linux-gnu -target-cpu pwr10 \
+// RUN:-target-feature +vsx -target-feature +power10-vector \
+// RUN:-fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu -target-cpu pwr10 \
+// RUN:-target-feature +power10-vector -fsyntax-only -verify %s
+// expected-no-diagnostics
+
+// Test legitimate uses of 'vector bool __int128' with VSX.
+__vector bool __int128 v1_bi128;
+__vector __bool __int128 v2_bi128;
+vector bool __int128 v3_bi128;
+vector __bool __int128 v4_bi128;
Index: clang/test/Parser/cxx-altivec-bool-128.cpp
===
--- /dev/null
+++ clang/test/Parser/cxx-altivec-bool-128.cpp
@@ -0,0 +1,23 @@
+// RUN: %clang_cc1 -triple=powerpc64-unknown-linux-gnu \
+// RUN:-target-feature +altivec -fsyntax-only -verify -std=c++11 %s
+// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu \
+// RUN:-target-feature +altivec -fsyntax-only -verify -std=c++11 %s
+// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu -target-cpu pwr10 \
+// RUN:-target-feature +altivec -target-feature +vsx \
+// RUN:-target-feature -power10-vector -fsyntax-only -verify %s
+
+#include 
+
+// Test 'vector bool __int128' type.
+
+// These should have errors.
+__vector bool __int128 v1_bi128;  // expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+__vector __bool __int128 v2_bi128;// expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector bool __int128 v3_bi128;// expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector __bool __int128 v4_bi128;  // expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+__vector bool unsigned __int128 v5_bi128; // expected-error {{cannot use 'unsigned' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+__vector bool signed __int128 v6_bi128;   // expected-error {{cannot use 'signed' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector bool unsigned __int128 v7_bi128;   // expected-error {{cannot use 'unsigned' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector bool signed __int128 v8_bi128; // expected-error {{cannot use 'signed' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+__vector __bool signed __int128 v9_bi128; // expected-error {{cannot use 'signed' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector __bool signed __int128 v10_bi128;  // expected-error {{cannot use 'signed' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
Index: clang/test/Parser/altivec-bool-128.c
===
--- /dev/null
+++ clang/test/Parser/altivec-bool-128.c
@@ -0,0 +1,21 @@
+// RUN: %clang_cc1 -triple=powerpc64-unknown-linux-gnu \
+// RUN:-target-feature +altivec -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu \
+// RUN:-target-feature +altivec -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu -target-cpu pwr10 \
+// RUN:-target-feature +vsx -target-feature -power10-vector \
+// RUN:-fsyntax-only -verify %s
+
+// Test 'vector bool __int128' type.
+
+// These should have errors.
+__vector bool __int128 v1_bi128;  // expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}

[PATCH] D81816: [PowerPC] Add support for vector bool __int128 for Power10

[Ahsan Saghir via Phabricator via cfe-commits]

saghir marked 2 inline comments as done.
saghir added inline comments.



Comment at: clang/test/Parser/p10-vector-bool-128.c:6
+// RUN:-target-feature +power10-vector -fsyntax-only -verify %s
+// expected-no-diagnostics
+

amyk wrote:
> I believe this comment still needs to be addressed (of the line not being 
> needed).
I think this was for a line removed earlier.


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[PATCH] D81816: [PowerPC] Add support for vector bool __int128 for Power10

[Ahsan Saghir via Phabricator via cfe-commits]

saghir updated this revision to Diff 271874.
saghir added a reviewer: stefanp.
saghir added a comment.

Updated comment.


Repository:
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Files:
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Sema/DeclSpec.cpp
  clang/test/Parser/altivec-bool-128.c
  clang/test/Parser/cxx-altivec-bool-128.cpp
  clang/test/Parser/p10-vector-bool-128.c

Index: clang/test/Parser/p10-vector-bool-128.c
===
--- /dev/null
+++ clang/test/Parser/p10-vector-bool-128.c
@@ -0,0 +1,12 @@
+// RUN: %clang_cc1 -triple=powerpc64-unknown-linux-gnu -target-cpu pwr10 \
+// RUN:-target-feature +vsx -target-feature +power10-vector \
+// RUN:-fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu -target-cpu pwr10 \
+// RUN:-target-feature +power10-vector -fsyntax-only -verify %s
+// expected-no-diagnostics
+
+// Test legitimate uses of 'vector bool __int128' with VSX.
+__vector bool __int128 v1_bi128;
+__vector __bool __int128 v2_bi128;
+vector bool __int128 v3_bi128;
+vector __bool __int128 v4_bi128;
Index: clang/test/Parser/cxx-altivec-bool-128.cpp
===
--- /dev/null
+++ clang/test/Parser/cxx-altivec-bool-128.cpp
@@ -0,0 +1,23 @@
+// RUN: %clang_cc1 -triple=powerpc64-unknown-linux-gnu \
+// RUN:-target-feature +altivec -fsyntax-only -verify -std=c++11 %s
+// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu \
+// RUN:-target-feature +altivec -fsyntax-only -verify -std=c++11 %s
+// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu -target-cpu pwr10 \
+// RUN:-target-feature +altivec -target-feature +vsx \
+// RUN:-target-feature -power10-vector -fsyntax-only -verify %s
+
+#include 
+
+// Test 'vector bool __int128' type.
+
+// These should have errors.
+__vector bool __int128 v1_bi128;  // expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+__vector __bool __int128 v2_bi128;// expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector bool __int128 v3_bi128;// expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector __bool __int128 v4_bi128;  // expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+__vector bool unsigned __int128 v5_bi128; // expected-error {{cannot use 'unsigned' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+__vector bool signed __int128 v6_bi128;   // expected-error {{cannot use 'signed' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector bool unsigned __int128 v7_bi128;   // expected-error {{cannot use 'unsigned' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector bool signed __int128 v8_bi128; // expected-error {{cannot use 'signed' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+__vector __bool signed __int128 v9_bi128; // expected-error {{cannot use 'signed' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector __bool signed __int128 v10_bi128;  // expected-error {{cannot use 'signed' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
Index: clang/test/Parser/altivec-bool-128.c
===
--- /dev/null
+++ clang/test/Parser/altivec-bool-128.c
@@ -0,0 +1,21 @@
+// RUN: %clang_cc1 -triple=powerpc64-unknown-linux-gnu \
+// RUN:-target-feature +altivec -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu \
+// RUN:-target-feature +altivec -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu -target-cpu pwr10 \
+// RUN:-target-feature +altivec -target-feature +vsx \
+// RUN:-target-feature -power10-vector -fsyntax-only -verify %s
+
+// Test 'vector bool __int128' type.
+
+// These should have errors.
+__vector bool __int128 v1_bi128;  // expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+__vector __bool __int128 v2_bi128;// expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector 

[PATCH] D81816: [PowerPC] Add support for vector bool __int128 for Power10

[Ahsan Saghir via Phabricator via cfe-commits]

saghir updated this revision to Diff 271860.
saghir edited the summary of this revision.
saghir added a comment.

Updated comment to reflect the change in allowed types.


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Files:
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Sema/DeclSpec.cpp
  clang/test/Parser/altivec-bool-128.c
  clang/test/Parser/cxx-altivec-bool-128.cpp
  clang/test/Parser/p10-vector-bool-128.c

Index: clang/test/Parser/p10-vector-bool-128.c
===
--- /dev/null
+++ clang/test/Parser/p10-vector-bool-128.c
@@ -0,0 +1,12 @@
+// RUN: %clang_cc1 -triple=powerpc64-unknown-linux-gnu -target-cpu pwr10 \
+// RUN:-target-feature +vsx -target-feature +power10-vector \
+// RUN:-fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu -target-cpu pwr10 \
+// RUN:-target-feature +power10-vector -fsyntax-only -verify %s
+// expected-no-diagnostics
+
+// Test legitimate uses of 'vector bool __int128' with VSX.
+__vector bool __int128 v1_bi128;
+__vector __bool __int128 v2_bi128;
+vector bool __int128 v3_bi128;
+vector __bool __int128 v4_bi128;
Index: clang/test/Parser/cxx-altivec-bool-128.cpp
===
--- /dev/null
+++ clang/test/Parser/cxx-altivec-bool-128.cpp
@@ -0,0 +1,23 @@
+// RUN: %clang_cc1 -triple=powerpc64-unknown-linux-gnu \
+// RUN:-target-feature +altivec -fsyntax-only -verify -std=c++11 %s
+// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu \
+// RUN:-target-feature +altivec -fsyntax-only -verify -std=c++11 %s
+// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu -target-cpu pwr10 \
+// RUN:-target-feature +altivec -target-feature +vsx \
+// RUN:-target-feature -power10-vector -fsyntax-only -verify %s
+
+#include 
+
+// Test 'vector bool __int128' type.
+
+// These should have errors.
+__vector bool __int128 v1_bi128;  // expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+__vector __bool __int128 v2_bi128;// expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector bool __int128 v3_bi128;// expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector __bool __int128 v4_bi128;  // expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+__vector bool unsigned __int128 v5_bi128; // expected-error {{cannot use 'unsigned' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+__vector bool signed __int128 v6_bi128;   // expected-error {{cannot use 'signed' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector bool unsigned __int128 v7_bi128;   // expected-error {{cannot use 'unsigned' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector bool signed __int128 v8_bi128; // expected-error {{cannot use 'signed' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+__vector __bool signed __int128 v9_bi128; // expected-error {{cannot use 'signed' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector __bool signed __int128 v10_bi128;  // expected-error {{cannot use 'signed' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
Index: clang/test/Parser/altivec-bool-128.c
===
--- /dev/null
+++ clang/test/Parser/altivec-bool-128.c
@@ -0,0 +1,21 @@
+// RUN: %clang_cc1 -triple=powerpc64-unknown-linux-gnu \
+// RUN:-target-feature +altivec -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu \
+// RUN:-target-feature +altivec -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu -target-cpu pwr10 \
+// RUN:-target-feature +altivec -target-feature +vsx \
+// RUN:-target-feature -power10-vector -fsyntax-only -verify %s
+
+// Test 'vector bool __int128' type.
+
+// These should have errors.
+__vector bool __int128 v1_bi128;  // expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+__vector __bool __int128 v2_bi128;// expected-error {{use of '__int128' with '__vector bool' requires VSX 

[PATCH] D81816: [PowerPC] Add support for vector bool __int128 for Power10

[Ahsan Saghir via Phabricator via cfe-commits]

saghir updated this revision to Diff 271498.
saghir marked an inline comment as done.
saghir added a comment.

Updated tests features to check.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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Files:
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Sema/DeclSpec.cpp
  clang/test/Parser/altivec-bool-128.c
  clang/test/Parser/cxx-altivec-bool-128.cpp
  clang/test/Parser/p10-vector-bool-128.c

Index: clang/test/Parser/p10-vector-bool-128.c
===
--- /dev/null
+++ clang/test/Parser/p10-vector-bool-128.c
@@ -0,0 +1,12 @@
+// RUN: %clang_cc1 -triple=powerpc64-unknown-linux-gnu -target-cpu pwr10 \
+// RUN:-target-feature +vsx -target-feature +power10-vector \
+// RUN:-fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu -target-cpu pwr10 \
+// RUN:-target-feature +power10-vector -fsyntax-only -verify %s
+// expected-no-diagnostics
+
+// Test legitimate uses of 'vector bool __int128' with VSX.
+__vector bool __int128 v1_bi128;
+__vector __bool __int128 v2_bi128;
+vector bool __int128 v3_bi128;
+vector __bool __int128 v4_bi128;
Index: clang/test/Parser/cxx-altivec-bool-128.cpp
===
--- /dev/null
+++ clang/test/Parser/cxx-altivec-bool-128.cpp
@@ -0,0 +1,23 @@
+// RUN: %clang_cc1 -triple=powerpc64-unknown-linux-gnu \
+// RUN:-target-feature +altivec -fsyntax-only -verify -std=c++11 %s
+// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu \
+// RUN:-target-feature +altivec -fsyntax-only -verify -std=c++11 %s
+// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu -target-cpu pwr10 \
+// RUN:-target-feature +altivec -target-feature +vsx \
+// RUN:-target-feature -power10-vector -fsyntax-only -verify %s
+
+#include 
+
+// Test 'vector bool __int128' type.
+
+// These should have errors.
+__vector bool __int128 v1_bi128;  // expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+__vector __bool __int128 v2_bi128;// expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector bool __int128 v3_bi128;// expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector __bool __int128 v4_bi128;  // expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+__vector bool unsigned __int128 v5_bi128; // expected-error {{cannot use 'unsigned' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+__vector bool signed __int128 v6_bi128;   // expected-error {{cannot use 'signed' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector bool unsigned __int128 v7_bi128;   // expected-error {{cannot use 'unsigned' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector bool signed __int128 v8_bi128; // expected-error {{cannot use 'signed' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+__vector __bool signed __int128 v9_bi128; // expected-error {{cannot use 'signed' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector __bool signed __int128 v10_bi128;  // expected-error {{cannot use 'signed' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
Index: clang/test/Parser/altivec-bool-128.c
===
--- /dev/null
+++ clang/test/Parser/altivec-bool-128.c
@@ -0,0 +1,21 @@
+// RUN: %clang_cc1 -triple=powerpc64-unknown-linux-gnu \
+// RUN:-target-feature +altivec -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu \
+// RUN:-target-feature +altivec -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu -target-cpu pwr10 \
+// RUN:-target-feature +altivec -target-feature +vsx \
+// RUN:-target-feature -power10-vector -fsyntax-only -verify %s
+
+// Test 'vector bool __int128' type.
+
+// These should have errors.
+__vector bool __int128 v1_bi128;  // expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+__vector __bool __int128 v2_bi128;// expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on 

[PATCH] D81816: [PowerPC] Add support for vector bool __int128 for Power10

[Ahsan Saghir via Phabricator via cfe-commits]

saghir marked 2 inline comments as done.
saghir added inline comments.



Comment at: clang/test/Parser/p10-vector-bool-128.c:2
+// RUN: %clang_cc1 -triple=powerpc64-unknown-linux-gnu -target-feature 
+altivec -target-feature +vsx -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu -target-feature 
+altivec -target-feature +vsx -fsyntax-only -verify %s
+// expected-no-diagnostics

lei wrote:
> saghir wrote:
> > lei wrote:
> > > saghir wrote:
> > > > lei wrote:
> > > > > add run line for feature `cpu=pwr10 +power10-vector`
> > > > Added `pwr10`.
> > > > `vector bool __int128` type should work with `pwr10` and `vsx` enabled, 
> > > > `power10-vector` is not needed explicitly.
> > > `cpu=pwr10 -vsx +power10-vector`
> > I have now added both `-target-cpu pwr10` and `-target-feature 
> > +power10-vector` as you mentioned in the first comment. 
> > However, I am not quite sure what you are looking to test here by adding 
> > `-vsx` because that would disable `vsx`, which in turn would disable 
> > `power10-vector` and we would not be able to test the legitimate use here.
> `-vsx` diable it, but the following `+power10-vector` should enable it.
> So:
> ```
> // RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu -target-cpu pwr10 \
> // RUN:-target-feature -vsx -target-feature +power10-vector
> ```
Sorry, I did not accurately explain what happens if we disable `vsx`. 
We cannot enable `power10-vector` and disable `vsx` at the same time, well we 
can but the compiler would give the following error:
`error: option '-mpower10-vector' cannot be specified with '-mno-vsx'`
 
`ppcUserFeaturesCheck` function in `PPC.cpp` ensures that any `vsx` dependant 
option cannot be turned on while simultaneously disabling `vsx`. So for this 
reason the above test line that you mentioned would not work.


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[PATCH] D81816: [PowerPC] Add support for vector bool __int128 for Power10

[Ahsan Saghir via Phabricator via cfe-commits]

saghir marked 2 inline comments as done.
saghir added inline comments.



Comment at: clang/lib/Sema/DeclSpec.cpp:1170
 
   // Only 'short' and 'long long' are valid with vector bool. (PIM 2.1)
   if ((TypeSpecWidth != TSW_unspecified) && (TypeSpecWidth != TSW_short) &&

lei wrote:
> Do we not need to add a check for int128 to this check as well? 
No need here because this checks for type `TST_int` only.


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[PATCH] D81816: [PowerPC] Add support for vector bool __int128 for Power10

[Ahsan Saghir via Phabricator via cfe-commits]

saghir marked 3 inline comments as done.
saghir added inline comments.



Comment at: clang/lib/Sema/DeclSpec.cpp:1155
+  // TODO: Update comment with correct Programming Interface Manual
+  // version once it is available. __int128 has also been added
+  // to vector bool for Power10.

lei wrote:
> saghir wrote:
> > lei wrote:
> > > Not sure what you mean here.
> > Earlier comment had the Programming Interface Manual version number (PIM 
> > 2.1); asserting only char/int were valid with vector bool. 
> > This patch adds __int128, so the comment needs to be updated with the 
> > latest version of the document once it is available.
> Maybe need to add a TODO in all the sections of code, that you update, where 
> it mentions PIM 2.1
I have changed comment such that it does not need the document version. 



Comment at: clang/test/Parser/altivec-bool-128.c:2
+// RUN: %clang_cc1 -triple=powerpc64-unknown-linux-gnu -target-feature 
+altivec -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu -target-feature 
+altivec -fsyntax-only -verify %s
+

lei wrote:
> saghir wrote:
> > lei wrote:
> > > test for `-mcpu=pwr10 -target-feature -power10-vector` and `-mcpu=pwr10 
> > > -target-feature -vsx`
> > > same for cxx-altivec-bool-128.cpp
> > This test basically checks that `VSX` needs to be enabled to have `vector 
> > bool __int128` type work.
> Yes.   I am asking you to add a test to check that `power10-vector` is also 
> needed to be enabled for this type to work.
> eg. this type should not be enabled for `-mcpu=pwr10 -target-feature +vsx 
> -target-feature -power10-vector`
Done, added a line for `pwr10`, `+vsx` and `-power10-vector`.



Comment at: clang/test/Parser/p10-vector-bool-128.c:2
+// RUN: %clang_cc1 -triple=powerpc64-unknown-linux-gnu -target-feature 
+altivec -target-feature +vsx -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu -target-feature 
+altivec -target-feature +vsx -fsyntax-only -verify %s
+// expected-no-diagnostics

lei wrote:
> saghir wrote:
> > lei wrote:
> > > add run line for feature `cpu=pwr10 +power10-vector`
> > Added `pwr10`.
> > `vector bool __int128` type should work with `pwr10` and `vsx` enabled, 
> > `power10-vector` is not needed explicitly.
> `cpu=pwr10 -vsx +power10-vector`
I have now added both `-target-cpu pwr10` and `-target-feature +power10-vector` 
as you mentioned in the first comment. 
However, I am not quite sure what you are looking to test here by adding `-vsx` 
because that would disable `vsx`, which in turn would disable `power10-vector` 
and we would not be able to test the legitimate use here.


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[PATCH] D81816: [PowerPC] Add support for vector bool __int128 for Power10

[Ahsan Saghir via Phabricator via cfe-commits]

saghir updated this revision to Diff 271459.
saghir marked 2 inline comments as done.
saghir added a comment.

Updated tests.


Repository:
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CHANGES SINCE LAST ACTION
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Files:
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Sema/DeclSpec.cpp
  clang/test/Parser/altivec-bool-128.c
  clang/test/Parser/cxx-altivec-bool-128.cpp
  clang/test/Parser/p10-vector-bool-128.c

Index: clang/test/Parser/p10-vector-bool-128.c
===
--- /dev/null
+++ clang/test/Parser/p10-vector-bool-128.c
@@ -0,0 +1,13 @@
+// RUN: %clang_cc1 -triple=powerpc64-unknown-linux-gnu -target-cpu pwr10 \
+// RUN:-target-feature +altivec -target-feature +vsx \
+// RUN:-target-feature +power10-vector -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu -target-cpu pwr10 \
+// RUN:-target-feature +altivec -target-feature +vsx \
+// RUN:-target-feature +power10-vector -fsyntax-only -verify %s
+// expected-no-diagnostics
+
+// Test legitimate uses of 'vector bool __int128' with VSX.
+__vector bool __int128 v1_bi128;
+__vector __bool __int128 v2_bi128;
+vector bool __int128 v3_bi128;
+vector __bool __int128 v4_bi128;
Index: clang/test/Parser/cxx-altivec-bool-128.cpp
===
--- /dev/null
+++ clang/test/Parser/cxx-altivec-bool-128.cpp
@@ -0,0 +1,23 @@
+// RUN: %clang_cc1 -triple=powerpc64-unknown-linux-gnu \
+// RUN:-target-feature +altivec -fsyntax-only -verify -std=c++11 %s
+// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu \
+// RUN:-target-feature +altivec -fsyntax-only -verify -std=c++11 %s
+// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu -target-cpu pwr10 \
+// RUN:-target-feature +altivec -target-feature +vsx \
+// RUN:-target-feature -power10-vector -fsyntax-only -verify %s
+
+#include 
+
+// Test 'vector bool __int128' type.
+
+// These should have errors.
+__vector bool __int128 v1_bi128;  // expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+__vector __bool __int128 v2_bi128;// expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector bool __int128 v3_bi128;// expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector __bool __int128 v4_bi128;  // expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+__vector bool unsigned __int128 v5_bi128; // expected-error {{cannot use 'unsigned' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+__vector bool signed __int128 v6_bi128;   // expected-error {{cannot use 'signed' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector bool unsigned __int128 v7_bi128;   // expected-error {{cannot use 'unsigned' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector bool signed __int128 v8_bi128; // expected-error {{cannot use 'signed' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+__vector __bool signed __int128 v9_bi128; // expected-error {{cannot use 'signed' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector __bool signed __int128 v10_bi128;  // expected-error {{cannot use 'signed' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
Index: clang/test/Parser/altivec-bool-128.c
===
--- /dev/null
+++ clang/test/Parser/altivec-bool-128.c
@@ -0,0 +1,23 @@
+// RUN: %clang_cc1 -triple=powerpc64-unknown-linux-gnu \
+// RUN:-target-feature +altivec -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu \
+// RUN:-target-feature +altivec -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu -target-cpu pwr10 \
+// RUN:-target-feature +altivec -target-feature +vsx \
+// RUN:-target-feature -power10-vector -fsyntax-only -verify %s
+
+
+
+// Test 'vector bool __int128' type.
+
+// These should have errors.
+__vector bool __int128 v1_bi128;  // expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+__vector __bool __int128 v2_bi128;// expected-error 

[PATCH] D80758: [PowerPC] Add -m[no-]power10-vector clang and llvm option

[Ahsan Saghir via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG37e72f47a41d: [PowerPC] Add -m[no-]power10-vector clang and 
llvm option (authored by saghir).

Changed prior to commit:
  https://reviews.llvm.org/D80758?vs=268893=271179#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D80758/new/

https://reviews.llvm.org/D80758

Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/test/Driver/ppc-dependent-options.cpp
  clang/test/Driver/ppc-features.cpp
  llvm/lib/Target/PowerPC/PPC.td
  llvm/lib/Target/PowerPC/PPCSubtarget.cpp
  llvm/lib/Target/PowerPC/PPCSubtarget.h

Index: llvm/lib/Target/PowerPC/PPCSubtarget.h
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -105,6 +105,7 @@
   bool HasP8Crypto;
   bool HasP9Vector;
   bool HasP9Altivec;
+  bool HasP10Vector;
   bool HasPrefixInstrs;
   bool HasPCRelativeMemops;
   bool HasFCPSGN;
@@ -262,6 +263,7 @@
   bool hasP8Crypto() const { return HasP8Crypto; }
   bool hasP9Vector() const { return HasP9Vector; }
   bool hasP9Altivec() const { return HasP9Altivec; }
+  bool hasP10Vector() const { return HasP10Vector; }
   bool hasPrefixInstrs() const { return HasPrefixInstrs; }
   bool hasPCRelativeMemops() const { return HasPCRelativeMemops; }
   bool hasMFOCRF() const { return HasMFOCRF; }
Index: llvm/lib/Target/PowerPC/PPCSubtarget.cpp
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -78,6 +78,7 @@
   HasP8Crypto = false;
   HasP9Vector = false;
   HasP9Altivec = false;
+  HasP10Vector = false;
   HasPrefixInstrs = false;
   HasPCRelativeMemops = false;
   HasFCPSGN = false;
Index: llvm/lib/Target/PowerPC/PPC.td
===
--- llvm/lib/Target/PowerPC/PPC.td
+++ llvm/lib/Target/PowerPC/PPC.td
@@ -216,6 +216,10 @@
 "Enable POWER9 vector instructions",
 [FeatureISA3_0, FeatureP8Vector,
  FeatureP9Altivec]>;
+def FeatureP10Vector  : SubtargetFeature<"power10-vector", "HasP10Vector",
+ "true",
+ "Enable POWER10 vector instructions",
+ [FeatureISA3_1, FeatureP9Vector]>;
 // A separate feature for this even though it is equivalent to P9Vector
 // because this is a feature of the implementation rather than the architecture
 // and may go away with future CPU's.
@@ -337,7 +341,7 @@
   // still exist with the exception of those we know are Power9 specific.
   list P10AdditionalFeatures =
 [DirectivePwr10, FeatureISA3_1, FeaturePrefixInstrs,
- FeaturePCRelativeMemops];
+ FeaturePCRelativeMemops, FeatureP10Vector];
   list P10SpecificFeatures = [];
   list P10InheritableFeatures =
 !listconcat(P9InheritableFeatures, P10AdditionalFeatures);
Index: clang/test/Driver/ppc-features.cpp
===
--- clang/test/Driver/ppc-features.cpp
+++ clang/test/Driver/ppc-features.cpp
@@ -150,6 +150,12 @@
 // RUN: %clang -target powerpc64-unknown-linux-gnu %s -mno-power8-vector -mpower8-vector -### -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-P8VECTOR %s
 // CHECK-P8VECTOR: "-target-feature" "+power8-vector"
 
+// RUN: %clang -target powerpc64-unknown-linux-gnu %s -mno-power10-vector -### -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-NOP10VECTOR %s
+// CHECK-NOP10VECTOR: "-target-feature" "-power10-vector"
+
+// RUN: %clang -target powerpc64-unknown-linux-gnu %s -mno-power10-vector -mpower10-vector -### -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-P10VECTOR %s
+// CHECK-P10VECTOR: "-target-feature" "+power10-vector"
+
 // RUN: %clang -target powerpc64-unknown-linux-gnu %s -mno-crbits -### -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-NOCRBITS %s
 // CHECK-NOCRBITS: "-target-feature" "-crbits"
 
Index: clang/test/Driver/ppc-dependent-options.cpp
===
--- clang/test/Driver/ppc-dependent-options.cpp
+++ clang/test/Driver/ppc-dependent-options.cpp
@@ -58,6 +58,14 @@
 // RUN: -mcpu=power9 -std=c++11 -mno-vsx -mfloat128 -mpower9-vector %s 2>&1 | \
 // RUN: FileCheck %s -check-prefix=CHECK-NVSX-MULTI
 
+// RUN: not %clang -target powerpc64le-unknown-unknown -fsyntax-only \
+// RUN: -mcpu=power10 -std=c++11 %s 2>&1 | FileCheck %s \
+// RUN: -check-prefix=CHECK-DEFAULT-P10
+
+// RUN: not %clang -target powerpc64le-unknown-unknown -fsyntax-only \
+// RUN: -mcpu=power10 -std=c++11 -mno-vsx -mpower10-vector %s 2>&1 | \
+// RUN: FileCheck %s -check-prefix=CHECK-NVSX-P10V
+
 #ifdef __VSX__
 static_assert(false, "VSX 

[PATCH] D81816: [PowerPC] Add support for vector bool __int128 for Power10

[Ahsan Saghir via Phabricator via cfe-commits]

saghir updated this revision to Diff 271164.
saghir added a comment.

Updated comment for allowing __int128 for vector bool.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D81816/new/

https://reviews.llvm.org/D81816

Files:
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Sema/DeclSpec.cpp
  clang/test/Parser/altivec-bool-128.c
  clang/test/Parser/cxx-altivec-bool-128.cpp
  clang/test/Parser/p10-vector-bool-128.c

Index: clang/test/Parser/p10-vector-bool-128.c
===
--- /dev/null
+++ clang/test/Parser/p10-vector-bool-128.c
@@ -0,0 +1,9 @@
+// RUN: %clang_cc1 -triple=powerpc64-unknown-linux-gnu -target-cpu pwr10 -target-feature +altivec -target-feature +vsx -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu -target-cpu pwr10 -target-feature +altivec -target-feature +vsx -fsyntax-only -verify %s
+// expected-no-diagnostics
+
+// Test legitimate uses of 'vector bool __int128' with VSX.
+__vector bool __int128 v1_bi128;
+__vector __bool __int128 v2_bi128;
+vector bool __int128 v3_bi128;
+vector __bool __int128 v4_bi128;
Index: clang/test/Parser/cxx-altivec-bool-128.cpp
===
--- /dev/null
+++ clang/test/Parser/cxx-altivec-bool-128.cpp
@@ -0,0 +1,17 @@
+// RUN: %clang_cc1 -triple=powerpc64-unknown-linux-gnu -target-feature +altivec -fsyntax-only -verify -std=c++11 %s
+// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu -target-feature +altivec -fsyntax-only -verify -std=c++11 %s
+#include 
+
+// Test 'vector bool __int128' type.
+
+// These should have errors.
+__vector bool __int128 v1_bi128;  // expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+__vector __bool __int128 v2_bi128;// expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector bool __int128 v3_bi128;// expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector __bool __int128 v4_bi128;  // expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+__vector bool unsigned __int128 v5_bi128; // expected-error {{cannot use 'unsigned' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+__vector bool signed __int128 v6_bi128;   // expected-error {{cannot use 'signed' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector bool unsigned __int128 v7_bi128;   // expected-error {{cannot use 'unsigned' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector bool signed __int128 v8_bi128; // expected-error {{cannot use 'signed' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+__vector __bool signed __int128 v9_bi128; // expected-error {{cannot use 'signed' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector __bool signed __int128 v10_bi128;  // expected-error {{cannot use 'signed' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
Index: clang/test/Parser/altivec-bool-128.c
===
--- /dev/null
+++ clang/test/Parser/altivec-bool-128.c
@@ -0,0 +1,16 @@
+// RUN: %clang_cc1 -triple=powerpc64-unknown-linux-gnu -target-feature +altivec -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu -target-feature +altivec -fsyntax-only -verify %s
+
+// Test 'vector bool __int128' type.
+
+// These should have errors.
+__vector bool __int128 v1_bi128;  // expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+__vector __bool __int128 v2_bi128;// expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector bool __int128 v3_bi128;// expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector __bool __int128 v4_bi128;  // expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+__vector bool unsigned __int128 v5_bi128; // expected-error {{cannot use 'unsigned' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+__vector bool signed __int128 v6_bi128;   // expected-error {{cannot use 

[PATCH] D81816: [PowerPC] Add support for vector bool __int128 for Power10

[Ahsan Saghir via Phabricator via cfe-commits]

saghir updated this revision to Diff 271144.
saghir added a comment.

Addressed comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D81816/new/

https://reviews.llvm.org/D81816

Files:
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Sema/DeclSpec.cpp
  clang/test/Parser/altivec-bool-128.c
  clang/test/Parser/cxx-altivec-bool-128.cpp
  clang/test/Parser/p10-vector-bool-128.c

Index: clang/test/Parser/p10-vector-bool-128.c
===
--- /dev/null
+++ clang/test/Parser/p10-vector-bool-128.c
@@ -0,0 +1,9 @@
+// RUN: %clang_cc1 -triple=powerpc64-unknown-linux-gnu -target-cpu pwr10 -target-feature +altivec -target-feature +vsx -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu -target-cpu pwr10 -target-feature +altivec -target-feature +vsx -fsyntax-only -verify %s
+// expected-no-diagnostics
+
+// Test legitimate uses of 'vector bool __int128' with VSX.
+__vector bool __int128 v1_bi128;
+__vector __bool __int128 v2_bi128;
+vector bool __int128 v3_bi128;
+vector __bool __int128 v4_bi128;
Index: clang/test/Parser/cxx-altivec-bool-128.cpp
===
--- /dev/null
+++ clang/test/Parser/cxx-altivec-bool-128.cpp
@@ -0,0 +1,17 @@
+// RUN: %clang_cc1 -triple=powerpc64-unknown-linux-gnu -target-feature +altivec -fsyntax-only -verify -std=c++11 %s
+// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu -target-feature +altivec -fsyntax-only -verify -std=c++11 %s
+#include 
+
+// Test 'vector bool __int128' type.
+
+// These should have errors.
+__vector bool __int128 v1_bi128;  // expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+__vector __bool __int128 v2_bi128;// expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector bool __int128 v3_bi128;// expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector __bool __int128 v4_bi128;  // expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+__vector bool unsigned __int128 v5_bi128; // expected-error {{cannot use 'unsigned' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+__vector bool signed __int128 v6_bi128;   // expected-error {{cannot use 'signed' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector bool unsigned __int128 v7_bi128;   // expected-error {{cannot use 'unsigned' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector bool signed __int128 v8_bi128; // expected-error {{cannot use 'signed' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+__vector __bool signed __int128 v9_bi128; // expected-error {{cannot use 'signed' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector __bool signed __int128 v10_bi128;  // expected-error {{cannot use 'signed' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
Index: clang/test/Parser/altivec-bool-128.c
===
--- /dev/null
+++ clang/test/Parser/altivec-bool-128.c
@@ -0,0 +1,16 @@
+// RUN: %clang_cc1 -triple=powerpc64-unknown-linux-gnu -target-feature +altivec -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu -target-feature +altivec -fsyntax-only -verify %s
+
+// Test 'vector bool __int128' type.
+
+// These should have errors.
+__vector bool __int128 v1_bi128;  // expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+__vector __bool __int128 v2_bi128;// expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector bool __int128 v3_bi128;// expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector __bool __int128 v4_bi128;  // expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+__vector bool unsigned __int128 v5_bi128; // expected-error {{cannot use 'unsigned' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+__vector bool signed __int128 v6_bi128;   // expected-error {{cannot use 'signed' with '__vector bool'}} 

[PATCH] D81816: [PowerPC] Add support for vector bool __int128 for Power10

[Ahsan Saghir via Phabricator via cfe-commits]

saghir updated this revision to Diff 271137.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D81816/new/

https://reviews.llvm.org/D81816

Files:
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Sema/DeclSpec.cpp
  clang/test/Parser/altivec-bool-128.c
  clang/test/Parser/cxx-altivec-bool-128.cpp
  clang/test/Parser/p10-vector-bool-128.c

Index: clang/test/Parser/p10-vector-bool-128.c
===
--- /dev/null
+++ clang/test/Parser/p10-vector-bool-128.c
@@ -0,0 +1,9 @@
+// RUN: %clang_cc1 -triple=powerpc64-unknown-linux-gnu -target-cpu pwr10 -target-feature +altivec -target-feature +vsx -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu -target-cpu pwr10 -target-feature +altivec -target-feature +vsx -fsyntax-only -verify %s
+// expected-no-diagnostics
+
+// Test legitimate uses of 'vector bool __int128' with VSX.
+__vector bool __int128 v1_bi128;
+__vector __bool __int128 v2_bi128;
+vector bool __int128 v3_bi128;
+vector __bool __int128 v4_bi128;
Index: clang/test/Parser/cxx-altivec-bool-128.cpp
===
--- /dev/null
+++ clang/test/Parser/cxx-altivec-bool-128.cpp
@@ -0,0 +1,17 @@
+// RUN: %clang_cc1 -triple=powerpc64-unknown-linux-gnu -target-feature +altivec -fsyntax-only -verify -std=c++11 %s
+// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu -target-feature +altivec -fsyntax-only -verify -std=c++11 %s
+#include 
+
+// Test 'vector bool __int128' type.
+
+// These should have errors.
+__vector bool __int128 v1_bi128;  // expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+__vector __bool __int128 v2_bi128;// expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector bool __int128 v3_bi128;// expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector __bool __int128 v4_bi128;  // expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+__vector bool unsigned __int128 v5_bi128; // expected-error {{cannot use 'unsigned' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+__vector bool signed __int128 v6_bi128;   // expected-error {{cannot use 'signed' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector bool unsigned __int128 v7_bi128;   // expected-error {{cannot use 'unsigned' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector bool signed __int128 v8_bi128; // expected-error {{cannot use 'signed' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+__vector __bool signed __int128 v9_bi128; // expected-error {{cannot use 'signed' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector __bool signed __int128 v10_bi128;  // expected-error {{cannot use 'signed' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
Index: clang/test/Parser/altivec-bool-128.c
===
--- /dev/null
+++ clang/test/Parser/altivec-bool-128.c
@@ -0,0 +1,16 @@
+// RUN: %clang_cc1 -triple=powerpc64-unknown-linux-gnu -target-feature +altivec -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu -target-feature +altivec -fsyntax-only -verify %s
+
+// Test 'vector bool __int128' type.
+
+// These should have errors.
+__vector bool __int128 v1_bi128;  // expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+__vector __bool __int128 v2_bi128;// expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector bool __int128 v3_bi128;// expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector __bool __int128 v4_bi128;  // expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+__vector bool unsigned __int128 v5_bi128; // expected-error {{cannot use 'unsigned' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+__vector bool signed __int128 v6_bi128;   // expected-error {{cannot use 'signed' with '__vector bool'}} expected-error {{use of '__int128' with '__vector 

[PATCH] D81816: [PowerPC] Add support for vector bool __int128 for Power10

[Ahsan Saghir via Phabricator via cfe-commits]

saghir marked 4 inline comments as done.
saghir added inline comments.



Comment at: clang/lib/Sema/DeclSpec.cpp:1155
+  // TODO: Update comment with correct Programming Interface Manual
+  // version once it is available. __int128 has also been added
+  // to vector bool for Power10.

lei wrote:
> Not sure what you mean here.
Earlier comment had the Programming Interface Manual version number (PIM 2.1); 
asserting only char/int were valid with vector bool. 
This patch adds __int128, so the comment needs to be updated with the latest 
version of the document once it is available.



Comment at: clang/test/Parser/altivec-bool-128.c:2
+// RUN: %clang_cc1 -triple=powerpc64-unknown-linux-gnu -target-feature 
+altivec -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu -target-feature 
+altivec -fsyntax-only -verify %s
+

lei wrote:
> test for `-mcpu=pwr10 -target-feature -power10-vector` and `-mcpu=pwr10 
> -target-feature -vsx`
> same for cxx-altivec-bool-128.cpp
This test basically checks that `VSX` needs to be enabled to have `vector bool 
__int128` type work.



Comment at: clang/test/Parser/p10-vector-bool-128.c:1
+// RUN: %clang_cc1 -triple=powerpc64-unknown-linux-gnu -target-feature 
+altivec -target-feature +vsx -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu -target-feature 
+altivec -target-feature +vsx -fsyntax-only -verify %s

amyk wrote:
> Just curious but does the RUN line require `pwr10`?
Added `pwr10`.



Comment at: clang/test/Parser/p10-vector-bool-128.c:2
+// RUN: %clang_cc1 -triple=powerpc64-unknown-linux-gnu -target-feature 
+altivec -target-feature +vsx -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu -target-feature 
+altivec -target-feature +vsx -fsyntax-only -verify %s
+// expected-no-diagnostics

lei wrote:
> add run line for feature `cpu=pwr10 +power10-vector`
Added `pwr10`.
`vector bool __int128` type should work with `pwr10` and `vsx` enabled, 
`power10-vector` is not needed explicitly.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D81816/new/

https://reviews.llvm.org/D81816



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[PATCH] D81816: [PowerPC] Add support for vector bool __int128 for Power10

[Ahsan Saghir via Phabricator via cfe-commits]

saghir created this revision.
saghir added reviewers: PowerPC, hfinkel.
saghir added projects: LLVM, PowerPC.
Herald added subscribers: cfe-commits, shchenz, nemanjai.
Herald added a project: clang.
saghir added a parent revision: D80758: [PowerPC] Add -m[no-]power10-vector 
clang and llvm option.
Herald added a subscriber: wuzish.

This patch adds support for `vector bool __int128` type for Power10.

Note: This patch depends on https://reviews.llvm.org/D80758 that adds support 
for `-m[no-]power10-vector` option.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D81816

Files:
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Sema/DeclSpec.cpp
  clang/test/Parser/altivec-bool-128.c
  clang/test/Parser/cxx-altivec-bool-128.cpp
  clang/test/Parser/p10-vector-bool-128.c

Index: clang/test/Parser/p10-vector-bool-128.c
===
--- /dev/null
+++ clang/test/Parser/p10-vector-bool-128.c
@@ -0,0 +1,9 @@
+// RUN: %clang_cc1 -triple=powerpc64-unknown-linux-gnu -target-feature +altivec -target-feature +vsx -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu -target-feature +altivec -target-feature +vsx -fsyntax-only -verify %s
+// expected-no-diagnostics
+
+// Test legitimate uses of 'vector bool __int128' with VSX.
+__vector bool __int128 v1_bi128;
+__vector __bool __int128 v2_bi128;
+vector bool __int128 v3_bi128;
+vector __bool __int128 v4_bi128;
Index: clang/test/Parser/cxx-altivec-bool-128.cpp
===
--- /dev/null
+++ clang/test/Parser/cxx-altivec-bool-128.cpp
@@ -0,0 +1,17 @@
+// RUN: %clang_cc1 -triple=powerpc64-unknown-linux-gnu -target-feature +altivec -fsyntax-only -verify -std=c++11 %s
+// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu -target-feature +altivec -fsyntax-only -verify -std=c++11 %s
+#include 
+
+// Test 'vector bool __int128' type.
+
+// These should have errors.
+__vector bool __int128 v1_bi128;  // expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+__vector __bool __int128 v2_bi128;// expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector bool __int128 v3_bi128;// expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector __bool __int128 v4_bi128;  // expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+__vector bool unsigned __int128 v5_bi128; // expected-error {{cannot use 'unsigned' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+__vector bool signed __int128 v6_bi128;   // expected-error {{cannot use 'signed' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector bool unsigned __int128 v7_bi128;   // expected-error {{cannot use 'unsigned' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector bool signed __int128 v8_bi128; // expected-error {{cannot use 'signed' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+__vector __bool signed __int128 v9_bi128; // expected-error {{cannot use 'signed' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector __bool signed __int128 v10_bi128;  // expected-error {{cannot use 'signed' with '__vector bool'}} expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
Index: clang/test/Parser/altivec-bool-128.c
===
--- /dev/null
+++ clang/test/Parser/altivec-bool-128.c
@@ -0,0 +1,16 @@
+// RUN: %clang_cc1 -triple=powerpc64-unknown-linux-gnu -target-feature +altivec -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu -target-feature +altivec -fsyntax-only -verify %s
+
+// Test 'vector bool __int128' type.
+
+// These should have errors.
+__vector bool __int128 v1_bi128;  // expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+__vector __bool __int128 v2_bi128;// expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector bool __int128 v3_bi128;// expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or later)}}
+vector __bool __int128 v4_bi128;  // expected-error {{use of '__int128' with '__vector bool' requires VSX support enabled (on POWER10 or 

[PATCH] D80758: [PowerPC] Add -m[no-]power10-vector clang and llvm option

[Ahsan Saghir via Phabricator via cfe-commits]

saghir updated this revision to Diff 268893.
saghir added a comment.

Updated the diff based on latest changes in master.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D80758/new/

https://reviews.llvm.org/D80758

Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/test/Driver/ppc-dependent-options.cpp
  clang/test/Driver/ppc-features.cpp
  llvm/lib/Target/PowerPC/PPC.td
  llvm/lib/Target/PowerPC/PPCSubtarget.cpp
  llvm/lib/Target/PowerPC/PPCSubtarget.h

Index: llvm/lib/Target/PowerPC/PPCSubtarget.h
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -105,6 +105,7 @@
   bool HasP8Crypto;
   bool HasP9Vector;
   bool HasP9Altivec;
+  bool HasP10Vector;
   bool HasPrefixInstrs;
   bool HasPCRelativeMemops;
   bool HasFCPSGN;
@@ -262,6 +263,7 @@
   bool hasP8Crypto() const { return HasP8Crypto; }
   bool hasP9Vector() const { return HasP9Vector; }
   bool hasP9Altivec() const { return HasP9Altivec; }
+  bool hasP10Vector() const { return HasP10Vector; }
   bool hasPrefixInstrs() const { return HasPrefixInstrs; }
   bool hasPCRelativeMemops() const { return HasPCRelativeMemops; }
   bool hasMFOCRF() const { return HasMFOCRF; }
Index: llvm/lib/Target/PowerPC/PPCSubtarget.cpp
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -78,6 +78,7 @@
   HasP8Crypto = false;
   HasP9Vector = false;
   HasP9Altivec = false;
+  HasP10Vector = false;
   HasPrefixInstrs = false;
   HasPCRelativeMemops = false;
   HasFCPSGN = false;
Index: llvm/lib/Target/PowerPC/PPC.td
===
--- llvm/lib/Target/PowerPC/PPC.td
+++ llvm/lib/Target/PowerPC/PPC.td
@@ -216,6 +216,10 @@
 "Enable POWER9 vector instructions",
 [FeatureISA3_0, FeatureP8Vector,
  FeatureP9Altivec]>;
+def FeatureP10Vector  : SubtargetFeature<"power10-vector", "HasP10Vector",
+ "true",
+ "Enable POWER10 vector instructions",
+ [FeatureISA3_1, FeatureP9Vector]>;
 // A separate feature for this even though it is equivalent to P9Vector
 // because this is a feature of the implementation rather than the architecture
 // and may go away with future CPU's.
@@ -337,7 +341,7 @@
   // still exist with the exception of those we know are Power9 specific.
   list P10AdditionalFeatures =
 [DirectivePwr10, FeatureISA3_1, FeaturePrefixInstrs,
- FeaturePCRelativeMemops];
+ FeaturePCRelativeMemops, FeatureP10Vector];
   list P10SpecificFeatures = [];
   list P10InheritableFeatures =
 !listconcat(P9InheritableFeatures, P10AdditionalFeatures);
Index: clang/test/Driver/ppc-features.cpp
===
--- clang/test/Driver/ppc-features.cpp
+++ clang/test/Driver/ppc-features.cpp
@@ -150,6 +150,12 @@
 // RUN: %clang -target powerpc64-unknown-linux-gnu %s -mno-power8-vector -mpower8-vector -### -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-P8VECTOR %s
 // CHECK-P8VECTOR: "-target-feature" "+power8-vector"
 
+// RUN: %clang -target powerpc64-unknown-linux-gnu %s -mno-power10-vector -### -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-NOP10VECTOR %s
+// CHECK-NOP10VECTOR: "-target-feature" "-power10-vector"
+
+// RUN: %clang -target powerpc64-unknown-linux-gnu %s -mno-power10-vector -mpower10-vector -### -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-P10VECTOR %s
+// CHECK-P10VECTOR: "-target-feature" "+power10-vector"
+
 // RUN: %clang -target powerpc64-unknown-linux-gnu %s -mno-crbits -### -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-NOCRBITS %s
 // CHECK-NOCRBITS: "-target-feature" "-crbits"
 
Index: clang/test/Driver/ppc-dependent-options.cpp
===
--- clang/test/Driver/ppc-dependent-options.cpp
+++ clang/test/Driver/ppc-dependent-options.cpp
@@ -58,6 +58,14 @@
 // RUN: -mcpu=power9 -std=c++11 -mno-vsx -mfloat128 -mpower9-vector %s 2>&1 | \
 // RUN: FileCheck %s -check-prefix=CHECK-NVSX-MULTI
 
+// RUN: not %clang -target powerpc64le-unknown-unknown -fsyntax-only \
+// RUN: -mcpu=power10 -std=c++11 %s 2>&1 | FileCheck %s \
+// RUN: -check-prefix=CHECK-DEFAULT-P10
+
+// RUN: not %clang -target powerpc64le-unknown-unknown -fsyntax-only \
+// RUN: -mcpu=power10 -std=c++11 -mno-vsx -mpower10-vector %s 2>&1 | \
+// RUN: FileCheck %s -check-prefix=CHECK-NVSX-P10V
+
 #ifdef __VSX__
 static_assert(false, "VSX enabled");
 #endif
@@ -70,6 +78,10 @@
 static_assert(false, "P9V enabled");
 #endif
 
+#ifdef __POWER10_VECTOR__
+static_assert(false, "P10V 

[PATCH] D80758: [PowerPC] Add -m[no-]power10-vector clang and llvm option

[Ahsan Saghir via Phabricator via cfe-commits]

saghir updated this revision to Diff 268031.
saghir marked an inline comment as done.
saghir removed a reviewer: power-llvm-team.
saghir added a comment.
Herald added a subscriber: kbarton.

Addressed nit


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D80758/new/

https://reviews.llvm.org/D80758

Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/test/Driver/ppc-dependent-options.cpp
  clang/test/Driver/ppc-features.cpp
  llvm/lib/Target/PowerPC/PPC.td
  llvm/lib/Target/PowerPC/PPCSubtarget.cpp
  llvm/lib/Target/PowerPC/PPCSubtarget.h

Index: llvm/lib/Target/PowerPC/PPCSubtarget.h
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -105,6 +105,7 @@
   bool HasP8Crypto;
   bool HasP9Vector;
   bool HasP9Altivec;
+  bool HasP10Vector;
   bool HasPrefixInstrs;
   bool HasPCRelativeMemops;
   bool HasFCPSGN;
@@ -262,6 +263,7 @@
   bool hasP8Crypto() const { return HasP8Crypto; }
   bool hasP9Vector() const { return HasP9Vector; }
   bool hasP9Altivec() const { return HasP9Altivec; }
+  bool hasP10Vector() const { return HasP10Vector; }
   bool hasPrefixInstrs() const { return HasPrefixInstrs; }
   bool hasPCRelativeMemops() const { return HasPCRelativeMemops; }
   bool hasMFOCRF() const { return HasMFOCRF; }
Index: llvm/lib/Target/PowerPC/PPCSubtarget.cpp
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -78,6 +78,7 @@
   HasP8Crypto = false;
   HasP9Vector = false;
   HasP9Altivec = false;
+  HasP10Vector = false;
   HasPrefixInstrs = false;
   HasPCRelativeMemops = false;
   HasFCPSGN = false;
Index: llvm/lib/Target/PowerPC/PPC.td
===
--- llvm/lib/Target/PowerPC/PPC.td
+++ llvm/lib/Target/PowerPC/PPC.td
@@ -216,6 +216,10 @@
 "Enable POWER9 vector instructions",
 [FeatureISA3_0, FeatureP8Vector,
  FeatureP9Altivec]>;
+def FeatureP10Vector  : SubtargetFeature<"power10-vector", "HasP10Vector",
+ "true",
+ "Enable POWER10 vector instructions",
+ [FeatureISA3_1, FeatureP9Vector]>;
 // A separate feature for this even though it is equivalent to P9Vector
 // because this is a feature of the implementation rather than the architecture
 // and may go away with future CPU's.
@@ -337,7 +341,7 @@
   // still exist with the exception of those we know are Power9 specific.
   list P10AdditionalFeatures =
 [DirectivePwr10, FeatureISA3_1, FeaturePrefixInstrs,
- FeaturePCRelativeMemops];
+ FeaturePCRelativeMemops, FeatureP10Vector];
   list P10SpecificFeatures = [];
   list P10InheritableFeatures =
 !listconcat(P9InheritableFeatures, P10AdditionalFeatures);
Index: clang/test/Driver/ppc-features.cpp
===
--- clang/test/Driver/ppc-features.cpp
+++ clang/test/Driver/ppc-features.cpp
@@ -150,6 +150,12 @@
 // RUN: %clang -target powerpc64-unknown-linux-gnu %s -mno-power8-vector -mpower8-vector -### -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-P8VECTOR %s
 // CHECK-P8VECTOR: "-target-feature" "+power8-vector"
 
+// RUN: %clang -target powerpc64-unknown-linux-gnu %s -mno-power10-vector -### -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-NOP10VECTOR %s
+// CHECK-NOP10VECTOR: "-target-feature" "-power10-vector"
+
+// RUN: %clang -target powerpc64-unknown-linux-gnu %s -mno-power10-vector -mpower10-vector -### -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-P10VECTOR %s
+// CHECK-P10VECTOR: "-target-feature" "+power10-vector"
+
 // RUN: %clang -target powerpc64-unknown-linux-gnu %s -mno-crbits -### -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-NOCRBITS %s
 // CHECK-NOCRBITS: "-target-feature" "-crbits"
 
Index: clang/test/Driver/ppc-dependent-options.cpp
===
--- clang/test/Driver/ppc-dependent-options.cpp
+++ clang/test/Driver/ppc-dependent-options.cpp
@@ -58,6 +58,14 @@
 // RUN: -mcpu=power9 -std=c++11 -mno-vsx -mfloat128 -mpower9-vector %s 2>&1 | \
 // RUN: FileCheck %s -check-prefix=CHECK-NVSX-MULTI
 
+// RUN: not %clang -target powerpc64le-unknown-unknown -fsyntax-only \
+// RUN: -mcpu=power10 -std=c++11 %s 2>&1 | FileCheck %s \
+// RUN: -check-prefix=CHECK-DEFAULT-P10
+
+// RUN: not %clang -target powerpc64le-unknown-unknown -fsyntax-only \
+// RUN: -mcpu=power10 -std=c++11 -mno-vsx -mpower10-vector %s 2>&1 | \
+// RUN: FileCheck %s -check-prefix=CHECK-NVSX-P10V
+
 #ifdef __VSX__
 static_assert(false, "VSX enabled");
 #endif
@@ -70,6 +78,10 @@
 static_assert(false, "P9V 

[PATCH] D80758: [PowerPC] Add -m[no-]power10-vector clang and llvm option

[Ahsan Saghir via Phabricator via cfe-commits]

saghir updated this revision to Diff 267859.
saghir added a comment.

Removed `P10Altivec`.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D80758/new/

https://reviews.llvm.org/D80758

Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/test/Driver/ppc-dependent-options.cpp
  clang/test/Driver/ppc-features.cpp
  llvm/lib/Target/PowerPC/PPC.td
  llvm/lib/Target/PowerPC/PPCSubtarget.cpp
  llvm/lib/Target/PowerPC/PPCSubtarget.h

Index: llvm/lib/Target/PowerPC/PPCSubtarget.h
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -105,6 +105,7 @@
   bool HasP8Crypto;
   bool HasP9Vector;
   bool HasP9Altivec;
+  bool HasP10Vector;
   bool HasPrefixInstrs;
   bool HasPCRelativeMemops;
   bool HasFCPSGN;
@@ -262,6 +263,7 @@
   bool hasP8Crypto() const { return HasP8Crypto; }
   bool hasP9Vector() const { return HasP9Vector; }
   bool hasP9Altivec() const { return HasP9Altivec; }
+  bool hasP10Vector() const { return HasP10Vector; }
   bool hasPrefixInstrs() const { return HasPrefixInstrs; }
   bool hasPCRelativeMemops() const { return HasPCRelativeMemops; }
   bool hasMFOCRF() const { return HasMFOCRF; }
Index: llvm/lib/Target/PowerPC/PPCSubtarget.cpp
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -78,6 +78,7 @@
   HasP8Crypto = false;
   HasP9Vector = false;
   HasP9Altivec = false;
+  HasP10Vector = false;
   HasPrefixInstrs = false;
   HasPCRelativeMemops = false;
   HasFCPSGN = false;
Index: llvm/lib/Target/PowerPC/PPC.td
===
--- llvm/lib/Target/PowerPC/PPC.td
+++ llvm/lib/Target/PowerPC/PPC.td
@@ -216,6 +216,10 @@
 "Enable POWER9 vector instructions",
 [FeatureISA3_0, FeatureP8Vector,
  FeatureP9Altivec]>;
+def FeatureP10Vector  : SubtargetFeature<"power10-vector", "HasP10Vector",
+ "true",
+ "Enable POWER10 vector instructions",
+ [FeatureISA3_1, FeatureP9Vector]>;
 // A separate feature for this even though it is equivalent to P9Vector
 // because this is a feature of the implementation rather than the architecture
 // and may go away with future CPU's.
@@ -337,7 +341,7 @@
   // still exist with the exception of those we know are Power9 specific.
   list P10AdditionalFeatures =
 [DirectivePwr10, FeatureISA3_1, FeaturePrefixInstrs,
- FeaturePCRelativeMemops];
+ FeaturePCRelativeMemops, FeatureP10Vector];
   list P10SpecificFeatures = [];
   list P10InheritableFeatures =
 !listconcat(P9InheritableFeatures, P10AdditionalFeatures);
Index: clang/test/Driver/ppc-features.cpp
===
--- clang/test/Driver/ppc-features.cpp
+++ clang/test/Driver/ppc-features.cpp
@@ -150,6 +150,12 @@
 // RUN: %clang -target powerpc64-unknown-linux-gnu %s -mno-power8-vector -mpower8-vector -### -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-P8VECTOR %s
 // CHECK-P8VECTOR: "-target-feature" "+power8-vector"
 
+// RUN: %clang -target powerpc64-unknown-linux-gnu %s -mno-power10-vector -### -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-NOP10VECTOR %s
+// CHECK-NOP10VECTOR: "-target-feature" "-power10-vector"
+
+// RUN: %clang -target powerpc64-unknown-linux-gnu %s -mno-power10-vector -mpower10-vector -### -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-P10VECTOR %s
+// CHECK-P10VECTOR: "-target-feature" "+power10-vector"
+
 // RUN: %clang -target powerpc64-unknown-linux-gnu %s -mno-crbits -### -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-NOCRBITS %s
 // CHECK-NOCRBITS: "-target-feature" "-crbits"
 
Index: clang/test/Driver/ppc-dependent-options.cpp
===
--- clang/test/Driver/ppc-dependent-options.cpp
+++ clang/test/Driver/ppc-dependent-options.cpp
@@ -58,6 +58,14 @@
 // RUN: -mcpu=power9 -std=c++11 -mno-vsx -mfloat128 -mpower9-vector %s 2>&1 | \
 // RUN: FileCheck %s -check-prefix=CHECK-NVSX-MULTI
 
+// RUN: not %clang -target powerpc64le-unknown-unknown -fsyntax-only \
+// RUN: -mcpu=power10 -std=c++11 %s 2>&1 | FileCheck %s \
+// RUN: -check-prefix=CHECK-DEFAULT-P10
+
+// RUN: not %clang -target powerpc64le-unknown-unknown -fsyntax-only \
+// RUN: -mcpu=power10 -std=c++11 -mno-vsx -mpower10-vector %s 2>&1 | \
+// RUN: FileCheck %s -check-prefix=CHECK-NVSX-P10V
+
 #ifdef __VSX__
 static_assert(false, "VSX enabled");
 #endif
@@ -70,6 +78,10 @@
 static_assert(false, "P9V enabled");
 #endif
 
+#ifdef __POWER10_VECTOR__
+static_assert(false, "P10V enabled");
+#endif
+
 #if 

[PATCH] D80758: [PowerPC] Add -m[no-]power10-vector clang and llvm option

[Ahsan Saghir via Phabricator via cfe-commits]

saghir marked 2 inline comments as done.
saghir added inline comments.



Comment at: clang/lib/Basic/Targets/PPC.cpp:414
+if (Name == "power9-vector")
+  Features["power10-vector"] = false;
 Features[Name] = false;

lei wrote:
> I think it would be good to change this into a switch-stmt as there are 
> enough conditional changed based on `Name` and probably more to come.
Adding string switch here would complicate it more, so sticking with the 
current approach.



Comment at: llvm/lib/Target/PowerPC/PPC.td:219
  FeatureP9Altivec]>;
+def FeatureP10Altivec : SubtargetFeature<"power10-altivec", "HasP10Altivec",
+ "true",

lei wrote:
> what's the relationship between this and p10 vector support?
Removed P10Altivec since this is not really needed for P10.


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[PATCH] D80757: [PowerPC] Add clang option -m[no-]pcrel

[Ahsan Saghir via Phabricator via cfe-commits]

saghir added inline comments.



Comment at: clang/test/Driver/ppc-pcrel.cpp:1
+// RUN: %clang -target powerpc64-unknown-linux-gnu %s -### -mcpu=pwr10 -mpcrel 
-o %t.o 2>&1 | FileCheck -check-prefix=CHECK-PCREL %s
+// RUN: %clang -target powerpc64-unknown-linux-gnu %s -### -mcpu=pwr10 
-mno-pcrel -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-NOPCREL %s

lei wrote:
> saghir wrote:
> > nit: would the first two checks be better off in 
> > `clang/test/Driver/ppc-features.cpp`?
> I think it's better to keep all tests for pcrel within this specific pcrel 
> test file.
I don't feel too strongly about where to keep it... there are checks for other 
target features in `ppc-features.cpp` so felt pcrel feature check could be put 
there along with other feature checks. 
But feel free to keep them here if you feel that's more appropriate.


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[PATCH] D80757: [PowerPC] Add clang option -m[no-]pcrel

[Ahsan Saghir via Phabricator via cfe-commits]

saghir accepted this revision.
saghir added a comment.
This revision is now accepted and ready to land.

Other than the nit, this looks good to me.




Comment at: clang/test/Driver/ppc-pcrel.cpp:1
+// RUN: %clang -target powerpc64-unknown-linux-gnu %s -### -mcpu=pwr10 -mpcrel 
-o %t.o 2>&1 | FileCheck -check-prefix=CHECK-PCREL %s
+// RUN: %clang -target powerpc64-unknown-linux-gnu %s -### -mcpu=pwr10 
-mno-pcrel -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-NOPCREL %s

nit: would the first two checks be better off in 
`clang/test/Driver/ppc-features.cpp`?


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[PATCH] D80758: [PowerPC] Add -m[no-]power10-vector clang and llvm option

[Ahsan Saghir via Phabricator via cfe-commits]

saghir created this revision.
saghir added reviewers: hfinkel, nemanjai, lei, power-llvm-team, amyk.
saghir added projects: LLVM, clang.
Herald added subscribers: llvm-commits, cfe-commits, shchenz, hiraditya.
jsji added a reviewer: PowerPC.
jsji added a project: PowerPC.

This patch adds command line option for enabling power10-vector support.


Repository:
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https://reviews.llvm.org/D80758

Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/test/Driver/ppc-dependent-options.cpp
  clang/test/Driver/ppc-features.cpp
  llvm/lib/Target/PowerPC/PPC.td
  llvm/lib/Target/PowerPC/PPCSubtarget.cpp
  llvm/lib/Target/PowerPC/PPCSubtarget.h

Index: llvm/lib/Target/PowerPC/PPCSubtarget.h
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -105,6 +105,8 @@
   bool HasP8Crypto;
   bool HasP9Vector;
   bool HasP9Altivec;
+  bool HasP10Vector;
+  bool HasP10Altivec;
   bool HasPrefixInstrs;
   bool HasPCRelativeMemops;
   bool HasFCPSGN;
@@ -262,6 +264,8 @@
   bool hasP8Crypto() const { return HasP8Crypto; }
   bool hasP9Vector() const { return HasP9Vector; }
   bool hasP9Altivec() const { return HasP9Altivec; }
+  bool hasP10Vector() const { return HasP10Vector; }
+  bool hasP10Altivec() const { return HasP10Altivec; }
   bool hasPrefixInstrs() const { return HasPrefixInstrs; }
   bool hasPCRelativeMemops() const { return HasPCRelativeMemops; }
   bool hasMFOCRF() const { return HasMFOCRF; }
Index: llvm/lib/Target/PowerPC/PPCSubtarget.cpp
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -78,6 +78,8 @@
   HasP8Crypto = false;
   HasP9Vector = false;
   HasP9Altivec = false;
+  HasP10Vector = false;
+  HasP10Altivec = false;
   HasPrefixInstrs = false;
   HasPCRelativeMemops = false;
   HasFCPSGN = false;
Index: llvm/lib/Target/PowerPC/PPC.td
===
--- llvm/lib/Target/PowerPC/PPC.td
+++ llvm/lib/Target/PowerPC/PPC.td
@@ -216,6 +216,15 @@
 "Enable POWER9 vector instructions",
 [FeatureISA3_0, FeatureP8Vector,
  FeatureP9Altivec]>;
+def FeatureP10Altivec : SubtargetFeature<"power10-altivec", "HasP10Altivec",
+ "true",
+ "Enable POWER10 Altivec instructions",
+ [FeatureISA3_1, FeatureP9Altivec]>;
+def FeatureP10Vector  : SubtargetFeature<"power10-vector", "HasP10Vector",
+ "true",
+ "Enable POWER10 vector instructions",
+ [FeatureISA3_1, FeatureP9Vector,
+ FeatureP10Altivec]>;
 // A separate feature for this even though it is equivalent to P9Vector
 // because this is a feature of the implementation rather than the architecture
 // and may go away with future CPU's.
@@ -337,7 +346,7 @@
   // still exist with the exception of those we know are Power9 specific.
   list P10AdditionalFeatures =
 [DirectivePwr10, FeatureISA3_1, FeaturePrefixInstrs,
- FeaturePCRelativeMemops];
+ FeaturePCRelativeMemops, FeatureP10Altivec, FeatureP10Vector];
   list P10SpecificFeatures = [];
   list P10InheritableFeatures =
 !listconcat(P9InheritableFeatures, P10AdditionalFeatures);
Index: clang/test/Driver/ppc-features.cpp
===
--- clang/test/Driver/ppc-features.cpp
+++ clang/test/Driver/ppc-features.cpp
@@ -150,6 +150,12 @@
 // RUN: %clang -target powerpc64-unknown-linux-gnu %s -mno-power8-vector -mpower8-vector -### -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-P8VECTOR %s
 // CHECK-P8VECTOR: "-target-feature" "+power8-vector"
 
+// RUN: %clang -target powerpc64-unknown-linux-gnu %s -mno-power10-vector -### -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-NOP10VECTOR %s
+// CHECK-NOP10VECTOR: "-target-feature" "-power10-vector"
+
+// RUN: %clang -target powerpc64-unknown-linux-gnu %s -mno-power10-vector -mpower10-vector -### -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-P10VECTOR %s
+// CHECK-P10VECTOR: "-target-feature" "+power10-vector"
+
 // RUN: %clang -target powerpc64-unknown-linux-gnu %s -mno-crbits -### -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-NOCRBITS %s
 // CHECK-NOCRBITS: "-target-feature" "-crbits"
 
Index: clang/test/Driver/ppc-dependent-options.cpp
===
--- clang/test/Driver/ppc-dependent-options.cpp
+++ clang/test/Driver/ppc-dependent-options.cpp
@@ -58,6 +58,14 @@
 // RUN: -mcpu=power9 -std=c++11 -mno-vsx -mfloat128 -mpower9-vector 

[PATCH] D80294: Add support for vmsumudm

[Ahsan Saghir via Phabricator via cfe-commits]

saghir marked an inline comment as done.
saghir added inline comments.



Comment at: llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1365
 
+// Vector Multiply-Sum
+def VMSUMUDM : VA1a_Int_Ty3<35, "vmsumudm", int_ppc_altivec_vmsumudm,

amyk wrote:
> Maybe we can put this definition near the other VMSUM instructions? Since 
> it's also nearby them in `BuiltinsPPC.def` and `IntrinsicsPowerPC.td`. 
This needed to be in the block for Power9 Altivec instructions, the other vmsum 
instructions are outside the P9 block.


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[PATCH] D80294: Add support for vmsumudm

[Ahsan Saghir via Phabricator via cfe-commits]

saghir added a comment.

In D80294#2048049 , @amyk wrote:

> I think this overall looks good, but just curious, why was the builtin 
> support removed?


I was hitting some errors with that, so removed it and would add that later on.


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[PATCH] D80294: Add support for vmsumudm

[Ahsan Saghir via Phabricator via cfe-commits]

saghir updated this revision to Diff 265332.
saghir edited the summary of this revision.
saghir added a comment.

Removing the builtin support.


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Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/P9InstrResources.td
  llvm/lib/Target/PowerPC/PPCInstrAltivec.td
  llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt
  llvm/test/MC/PowerPC/ppc64-encoding-vmx.s


Index: llvm/test/MC/PowerPC/ppc64-encoding-vmx.s
===
--- llvm/test/MC/PowerPC/ppc64-encoding-vmx.s
+++ llvm/test/MC/PowerPC/ppc64-encoding-vmx.s
@@ -366,6 +366,9 @@
 # CHECK-BE: vmsumuhm 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x66]
 # CHECK-LE: vmsumuhm 2, 3, 4, 5 # encoding: [0x66,0x21,0x43,0x10]
 vmsumuhm 2, 3, 4, 5
+# CHECK-BE: vmsumudm 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x63]
+# CHECK-LE: vmsumudm 2, 3, 4, 5 # encoding: [0x63,0x21,0x43,0x10]
+vmsumudm 2, 3, 4, 5
 # CHECK-BE: vmsumuhs 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x67]
 # CHECK-LE: vmsumuhs 2, 3, 4, 5 # encoding: [0x67,0x21,0x43,0x10]
 vmsumuhs 2, 3, 4, 5
Index: llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt
===
--- llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt
+++ llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt
@@ -333,6 +333,9 @@
 # CHECK: vmsumuhm 2, 3, 4, 5 
 0x10 0x43 0x21 0x66
 
+# CHECK: vmsumudm 2, 3, 4, 5
+0x10 0x43 0x21 0x63
+
 # CHECK: vmsumuhs 2, 3, 4, 5 
 0x10 0x43 0x21 0x67
 
Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
===
--- llvm/lib/Target/PowerPC/PPCInstrAltivec.td
+++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td
@@ -1362,6 +1362,10 @@
 def HasP9Altivec : Predicate<"PPCSubTarget->hasP9Altivec()">;
 let Predicates = [HasP9Altivec] in {
 
+// Vector Multiply-Sum
+def VMSUMUDM : VA1a_Int_Ty3<35, "vmsumudm", int_ppc_altivec_vmsumudm,
+v1i128, v2i64, v1i128>;
+
 // i8 element comparisons.
 def VCMPNEB   : VCMP   <  7, "vcmpneb $vD, $vA, $vB"  , v16i8>;
 def VCMPNEB_rec  : VCMPo  <  7, "vcmpneb. $vD, $vA, $vB" , v16i8>;
Index: llvm/lib/Target/PowerPC/P9InstrResources.td
===
--- llvm/lib/Target/PowerPC/P9InstrResources.td
+++ llvm/lib/Target/PowerPC/P9InstrResources.td
@@ -373,6 +373,7 @@
 VMSUMSHS,
 VMSUMUBM,
 VMSUMUHM,
+VMSUMUDM,
 VMSUMUHS,
 VMULESB,
 VMULESH,
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -495,6 +495,9 @@
   def int_ppc_altivec_vmsumuhm : GCCBuiltin<"__builtin_altivec_vmsumuhm">,
 Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty,
llvm_v4i32_ty], [IntrNoMem]>;
+  def int_ppc_altivec_vmsumudm : GCCBuiltin<"__builtin_altivec_vmsumudm">,
+Intrinsic<[llvm_v1i128_ty], [llvm_v2i64_ty, llvm_v2i64_ty,
+   llvm_v1i128_ty], [IntrNoMem]>;
   def int_ppc_altivec_vmsumuhs : GCCBuiltin<"__builtin_altivec_vmsumuhs">,
 Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty,
llvm_v4i32_ty], [IntrNoMem]>;
Index: clang/include/clang/Basic/BuiltinsPPC.def
===
--- clang/include/clang/Basic/BuiltinsPPC.def
+++ clang/include/clang/Basic/BuiltinsPPC.def
@@ -84,6 +84,7 @@
 BUILTIN(__builtin_altivec_vmsumubm, "V4UiV16UcV16UcV4Ui", "")
 BUILTIN(__builtin_altivec_vmsummbm, "V4SiV16ScV16UcV4Si", "")
 BUILTIN(__builtin_altivec_vmsumuhm, "V4UiV8UsV8UsV4Ui", "")
+BUILTIN(__builtin_altivec_vmsumudm, "V1ULLLiV2ULLV2ULLV1ULLLi", "")
 BUILTIN(__builtin_altivec_vmsumshm, "V4SiV8SsV8SsV4Si", "")
 BUILTIN(__builtin_altivec_vmsumuhs, "V4UiV8UsV8UsV4Ui", "")
 BUILTIN(__builtin_altivec_vmsumshs, "V4SiV8SsV8SsV4Si", "")


Index: llvm/test/MC/PowerPC/ppc64-encoding-vmx.s
===
--- llvm/test/MC/PowerPC/ppc64-encoding-vmx.s
+++ llvm/test/MC/PowerPC/ppc64-encoding-vmx.s
@@ -366,6 +366,9 @@
 # CHECK-BE: vmsumuhm 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x66]
 # CHECK-LE: vmsumuhm 2, 3, 4, 5 # encoding: [0x66,0x21,0x43,0x10]
 vmsumuhm 2, 3, 4, 5
+# CHECK-BE: vmsumudm 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x63]
+# CHECK-LE: vmsumudm 2, 3, 4, 5 # encoding: [0x63,0x21,0x43,0x10]
+vmsumudm 2, 3, 4, 5
 # CHECK-BE: vmsumuhs 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x67]
 # CHECK-LE: vmsumuhs 

[PATCH] D80294: Add support for vmsumudm

[Ahsan Saghir via Phabricator via cfe-commits]

saghir updated this revision to Diff 265281.
saghir added a comment.

Added vec_msum builtin for vmsumudm.


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Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Headers/altivec.h
  clang/test/CodeGen/builtins-ppc-altivec.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/P9InstrResources.td
  llvm/lib/Target/PowerPC/PPCInstrAltivec.td
  llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt
  llvm/test/MC/PowerPC/ppc64-encoding-vmx.s

Index: llvm/test/MC/PowerPC/ppc64-encoding-vmx.s
===
--- llvm/test/MC/PowerPC/ppc64-encoding-vmx.s
+++ llvm/test/MC/PowerPC/ppc64-encoding-vmx.s
@@ -366,6 +366,9 @@
 # CHECK-BE: vmsumuhm 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x66]
 # CHECK-LE: vmsumuhm 2, 3, 4, 5 # encoding: [0x66,0x21,0x43,0x10]
 vmsumuhm 2, 3, 4, 5
+# CHECK-BE: vmsumudm 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x63]
+# CHECK-LE: vmsumudm 2, 3, 4, 5 # encoding: [0x63,0x21,0x43,0x10]
+vmsumudm 2, 3, 4, 5
 # CHECK-BE: vmsumuhs 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x67]
 # CHECK-LE: vmsumuhs 2, 3, 4, 5 # encoding: [0x67,0x21,0x43,0x10]
 vmsumuhs 2, 3, 4, 5
Index: llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt
===
--- llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt
+++ llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt
@@ -333,6 +333,9 @@
 # CHECK: vmsumuhm 2, 3, 4, 5 
 0x10 0x43 0x21 0x66
 
+# CHECK: vmsumudm 2, 3, 4, 5
+0x10 0x43 0x21 0x63
+
 # CHECK: vmsumuhs 2, 3, 4, 5 
 0x10 0x43 0x21 0x67
 
Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
===
--- llvm/lib/Target/PowerPC/PPCInstrAltivec.td
+++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td
@@ -614,6 +614,8 @@
 v4i32, v16i8, v4i32>;
 def VMSUMUHM : VA1a_Int_Ty3<38, "vmsumuhm", int_ppc_altivec_vmsumuhm,
 v4i32, v8i16, v4i32>;
+def VMSUMUDM : VA1a_Int_Ty3<35, "vmsumudm", int_ppc_altivec_vmsumudm,
+v1i128, v2i64, v1i128>;
 def VMSUMUHS : VA1a_Int_Ty3<39, "vmsumuhs", int_ppc_altivec_vmsumuhs,
 v4i32, v8i16, v4i32>;
 
Index: llvm/lib/Target/PowerPC/P9InstrResources.td
===
--- llvm/lib/Target/PowerPC/P9InstrResources.td
+++ llvm/lib/Target/PowerPC/P9InstrResources.td
@@ -373,6 +373,7 @@
 VMSUMSHS,
 VMSUMUBM,
 VMSUMUHM,
+VMSUMUDM,
 VMSUMUHS,
 VMULESB,
 VMULESH,
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -495,6 +495,9 @@
   def int_ppc_altivec_vmsumuhm : GCCBuiltin<"__builtin_altivec_vmsumuhm">,
 Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty,
llvm_v4i32_ty], [IntrNoMem]>;
+  def int_ppc_altivec_vmsumudm : GCCBuiltin<"__builtin_altivec_vmsumudm">,
+  Intrinsic<[llvm_v1i128_ty], [llvm_v2i64_ty, llvm_v2i64_ty,
+ llvm_v1i128_ty], [IntrNoMem]>;
   def int_ppc_altivec_vmsumuhs : GCCBuiltin<"__builtin_altivec_vmsumuhs">,
 Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty,
llvm_v4i32_ty], [IntrNoMem]>;
Index: clang/test/CodeGen/builtins-ppc-altivec.c
===
--- clang/test/CodeGen/builtins-ppc-altivec.c
+++ clang/test/CodeGen/builtins-ppc-altivec.c
@@ -22,6 +22,9 @@
 vector bool int vbi = { 1, 0, 1, 0 };
 vector int vi = { -1, 2, -3, 4 };
 vector unsigned int vui = { 1, 2, 3, 4 };
+vector unsigned long long vulla = {1, 2};
+vector unsigned long long vullb = {3, 4};
+vector unsigned __int128 vui128a = {1};
 vector float vf = { -1.5, 2.5, -3.5, 4.5 };
 
 vector bool char res_vbc;
@@ -33,6 +36,7 @@
 vector pixel res_vp;
 vector bool int res_vbi;
 vector int res_vi;
+vector unsigned __int128 res_vui128;
 vector unsigned int res_vui;
 vector float res_vf;
 
@@ -2232,6 +2236,10 @@
 // CHECK: @llvm.ppc.altivec.vmsumuhm
 // CHECK-LE: @llvm.ppc.altivec.vmsumuhm
 
+  res_vui128 = vec_msum(vulla, vullb, vui128a);
+// CHECK: @llvm.ppc.altivec.vmsumudm
+// CHECK-LE: @llvm.ppc.altivec.vmsumudm
+
   res_vi  = vec_vmsummbm(vsc, vuc, vi);
 // CHECK: @llvm.ppc.altivec.vmsummbm
 // CHECK-LE: @llvm.ppc.altivec.vmsummbm
Index: clang/lib/Headers/altivec.h
===
--- clang/lib/Headers/altivec.h
+++ clang/lib/Headers/altivec.h
@@ -5465,6 +5465,14 @@
 vec_msum(vector unsigned short __a, vector unsigned 

[PATCH] D80294: Add support for vmsumudm

[Ahsan Saghir via Phabricator via cfe-commits]

saghir created this revision.
saghir added reviewers: power-llvm-team, nemanjai, stefanp, amyk, lei, hfinkel, 
PowerPC.
Herald added subscribers: llvm-commits, cfe-commits, hiraditya.
Herald added projects: clang, LLVM.

This patch adds support for Vector Multiply-Sum Unsigned Doubleword Modulo 
instruction; vmsumudm. This instruction is available on POWER 9.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D80294

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/P9InstrResources.td
  llvm/lib/Target/PowerPC/PPCInstrAltivec.td
  llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt
  llvm/test/MC/PowerPC/ppc64-encoding-vmx.s


Index: llvm/test/MC/PowerPC/ppc64-encoding-vmx.s
===
--- llvm/test/MC/PowerPC/ppc64-encoding-vmx.s
+++ llvm/test/MC/PowerPC/ppc64-encoding-vmx.s
@@ -366,6 +366,9 @@
 # CHECK-BE: vmsumuhm 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x66]
 # CHECK-LE: vmsumuhm 2, 3, 4, 5 # encoding: [0x66,0x21,0x43,0x10]
 vmsumuhm 2, 3, 4, 5
+# CHECK-BE: vmsumudm 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x63]
+# CHECK-LE: vmsumudm 2, 3, 4, 5 # encoding: [0x63,0x21,0x43,0x10]
+vmsumudm 2, 3, 4, 5
 # CHECK-BE: vmsumuhs 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x67]
 # CHECK-LE: vmsumuhs 2, 3, 4, 5 # encoding: [0x67,0x21,0x43,0x10]
 vmsumuhs 2, 3, 4, 5
Index: llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt
===
--- llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt
+++ llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt
@@ -333,6 +333,9 @@
 # CHECK: vmsumuhm 2, 3, 4, 5 
 0x10 0x43 0x21 0x66
 
+# CHECK: vmsumudm 2, 3, 4, 5
+0x10 0x43 0x21 0x63
+
 # CHECK: vmsumuhs 2, 3, 4, 5 
 0x10 0x43 0x21 0x67
 
Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
===
--- llvm/lib/Target/PowerPC/PPCInstrAltivec.td
+++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td
@@ -614,6 +614,8 @@
 v4i32, v16i8, v4i32>;
 def VMSUMUHM : VA1a_Int_Ty3<38, "vmsumuhm", int_ppc_altivec_vmsumuhm,
 v4i32, v8i16, v4i32>;
+def VMSUMUDM : VA1a_Int_Ty3<35, "vmsumudm", int_ppc_altivec_vmsumudm,
+v1i128, v2i64, v1i128>;
 def VMSUMUHS : VA1a_Int_Ty3<39, "vmsumuhs", int_ppc_altivec_vmsumuhs,
 v4i32, v8i16, v4i32>;
 
Index: llvm/lib/Target/PowerPC/P9InstrResources.td
===
--- llvm/lib/Target/PowerPC/P9InstrResources.td
+++ llvm/lib/Target/PowerPC/P9InstrResources.td
@@ -373,6 +373,7 @@
 VMSUMSHS,
 VMSUMUBM,
 VMSUMUHM,
+VMSUMUDM,
 VMSUMUHS,
 VMULESB,
 VMULESH,
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -574,6 +574,9 @@
   def int_ppc_altivec_vmsumuhm : GCCBuiltin<"__builtin_altivec_vmsumuhm">,
 Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty,
llvm_v4i32_ty], [IntrNoMem]>;
+  def int_ppc_altivec_vmsumudm : GCCBuiltin<"__builtin_altivec_vmsumudm">,
+Intrinsic<[llvm_v1i128_ty], [llvm_v2i64_ty, llvm_v2i64_ty,
+   llvm_v1i128_ty], [IntrNoMem]>;
   def int_ppc_altivec_vmsumuhs : GCCBuiltin<"__builtin_altivec_vmsumuhs">,
 Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty,
llvm_v4i32_ty], [IntrNoMem]>;
Index: clang/include/clang/Basic/BuiltinsPPC.def
===
--- clang/include/clang/Basic/BuiltinsPPC.def
+++ clang/include/clang/Basic/BuiltinsPPC.def
@@ -84,6 +84,7 @@
 BUILTIN(__builtin_altivec_vmsumubm, "V4UiV16UcV16UcV4Ui", "")
 BUILTIN(__builtin_altivec_vmsummbm, "V4SiV16ScV16UcV4Si", "")
 BUILTIN(__builtin_altivec_vmsumuhm, "V4UiV8UsV8UsV4Ui", "")
+BUILTIN(__builtin_altivec_vmsumudm, "V1ULLLiV2ULLV2ULLV1ULLLi", "")
 BUILTIN(__builtin_altivec_vmsumshm, "V4SiV8SsV8SsV4Si", "")
 BUILTIN(__builtin_altivec_vmsumuhs, "V4UiV8UsV8UsV4Ui", "")
 BUILTIN(__builtin_altivec_vmsumshs, "V4SiV8SsV8SsV4Si", "")


Index: llvm/test/MC/PowerPC/ppc64-encoding-vmx.s
===
--- llvm/test/MC/PowerPC/ppc64-encoding-vmx.s
+++ llvm/test/MC/PowerPC/ppc64-encoding-vmx.s
@@ -366,6 +366,9 @@
 # CHECK-BE: vmsumuhm 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x66]
 # CHECK-LE: vmsumuhm 2, 3, 4, 5 # encoding: [0x66,0x21,0x43,0x10]
 vmsumuhm 2, 3, 4, 5
+# CHECK-BE: vmsumudm 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x63]
+# CHECK-LE: 

[PATCH] D55892: [OpenMP] 'close' map-type-modifier code generation

[Ahsan Saghir via Phabricator via cfe-commits]

saghir closed this revision.
saghir added a comment.
Herald added subscribers: sstefan1, yaxunl.

Support for  'close' map-type-modifier code generation in clang has been added 
by patch D65341 . This revision can be closed.


Repository:
  rC Clang

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D55892/new/

https://reviews.llvm.org/D55892



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[PATCH] D59843: [PowerPC] Add support for __dcbf builtin

[Ahsan Saghir via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rC359517: Add __builtin_dcbf support for PPC (authored by 
saghir, committed by ).
Herald added subscribers: cfe-commits, kristina.
Herald added a project: clang.

Changed prior to commit:
  https://reviews.llvm.org/D59843?vs=195094=197218#toc

Repository:
  rC Clang

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D59843/new/

https://reviews.llvm.org/D59843

Files:
  docs/LanguageExtensions.rst
  include/clang/Basic/BuiltinsPPC.def
  test/CodeGen/builtins-ppc-cache.c

Index: include/clang/Basic/BuiltinsPPC.def
===
--- include/clang/Basic/BuiltinsPPC.def
+++ include/clang/Basic/BuiltinsPPC.def
@@ -478,6 +478,9 @@
 // Set the floating point rounding mode
 BUILTIN(__builtin_setrnd, "di", "")
 
+// Cache built-ins
+BUILTIN(__builtin_dcbf, "vvC*", "")
+
 // FIXME: Obviously incomplete.
 
 #undef BUILTIN
Index: test/CodeGen/builtins-ppc-cache.c
===
--- test/CodeGen/builtins-ppc-cache.c
+++ test/CodeGen/builtins-ppc-cache.c
@@ -0,0 +1,47 @@
+// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu -emit-llvm \
+// RUN:   -o - %s | FileCheck %s
+
+int A;
+int B[5];
+float C;
+float D[5];
+double E;
+double F[5];
+
+void func(int a, int b[], float c, float d[], double e, double f[]) {
+  __builtin_dcbf ();
+  // CHECK: @llvm.ppc.dcbf(i8*
+
+  __builtin_dcbf ();
+  // CHECK: @llvm.ppc.dcbf(i8*
+
+  __builtin_dcbf ([2]);
+  // CHECK: @llvm.ppc.dcbf(i8*
+
+  __builtin_dcbf ([2]);
+  // CHECK: @llvm.ppc.dcbf(i8*
+
+  __builtin_dcbf ();
+  // CHECK: @llvm.ppc.dcbf(i8*
+
+  __builtin_dcbf ();
+  // CHECK: @llvm.ppc.dcbf(i8*
+
+  __builtin_dcbf ([2]);
+  // CHECK: @llvm.ppc.dcbf(i8*
+
+  __builtin_dcbf ([2]);
+  // CHECK: @llvm.ppc.dcbf(i8*
+
+  __builtin_dcbf ();
+  // CHECK: @llvm.ppc.dcbf(i8*
+
+  __builtin_dcbf ();
+  // CHECK: @llvm.ppc.dcbf(i8*
+
+  __builtin_dcbf ([0]);
+  // CHECK: @llvm.ppc.dcbf(i8*
+
+  __builtin_dcbf ([0]);
+  // CHECK: @llvm.ppc.dcbf(i8*
+}
Index: docs/LanguageExtensions.rst
===
--- docs/LanguageExtensions.rst
+++ docs/LanguageExtensions.rst
@@ -2448,6 +2448,31 @@
 than 3, it will only use the least significant two bits of the mode. 
 Namely, ``__builtin_setrnd(102))`` is equal to ``__builtin_setrnd(2)``.
 
+PowerPC cache builtins
+^^
+
+The PowerPC architecture specifies instructions implementing cache operations.
+Clang provides builtins that give direct programmer access to these cache
+instructions.
+
+Currently the following builtins are implemented in clang:
+
+``__builtin_dcbf`` copies the contents of a modified block from the data cache
+to main memory and flushes the copy from the data cache.
+
+**Syntax**:
+
+.. code-block:: c
+
+  void __dcbf(const void* addr); /* Data Cache Block Flush */
+
+**Example of Use**:
+
+.. code-block:: c
+
+  int a = 1;
+  __builtin_dcbf ();
+
 Extensions for Static Analysis
 ==
 
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[PATCH] D55892: [OpenMP] 'close' map-type-modifier code generation

[Ahsan Saghir via Phabricator via cfe-commits]

saghir created this revision.
saghir added reviewers: ABataev, kkwli0, Hahnfeld, RaviNarayanaswamy, mikerice, 
hfinkel, gtbercea.
saghir added a project: OpenMP.
Herald added subscribers: cfe-commits, guansong.

This patch provides codegen support for close map-type-modifier in map clause.

A map clause with the close map-type-modifier is a hint to prefer that the 
variables are mapped using a copy into faster memory.

[NOTE: This will be committed to trunk after support for close 
map-type-modifier is added in libomptarget. This revision is being created to 
avoid duplication of work by other people.]


Repository:
  rC Clang

https://reviews.llvm.org/D55892

Files:
  clang/lib/CodeGen/CGOpenMPRuntime.cpp
  clang/test/OpenMP/target_data_codegen.cpp
  clang/test/OpenMP/target_enter_data_codegen.cpp
  clang/test/OpenMP/target_exit_data_codegen.cpp
  clang/test/OpenMP/target_map_codegen.cpp

Index: clang/test/OpenMP/target_map_codegen.cpp
===
--- clang/test/OpenMP/target_map_codegen.cpp
+++ clang/test/OpenMP/target_map_codegen.cpp
@@ -5258,4 +5258,76 @@
 }
 
 #endif
+///==///
+// RUN: %clang_cc1 -DCK31 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix CK31 --check-prefix CK31-64
+// RUN: %clang_cc1 -DCK31 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s
+// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s  --check-prefix CK31 --check-prefix CK31-64
+// RUN: %clang_cc1 -DCK31 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s  --check-prefix CK31 --check-prefix CK31-32
+// RUN: %clang_cc1 -DCK31 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s
+// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s  --check-prefix CK31 --check-prefix CK31-32
+
+// RUN: %clang_cc1 -DCK31 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  --check-prefix SIMD-ONLY18 %s
+// RUN: %clang_cc1 -DCK31 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s
+// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  --check-prefix SIMD-ONLY18 %s
+// RUN: %clang_cc1 -DCK31 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  --check-prefix SIMD-ONLY18 %s
+// RUN: %clang_cc1 -DCK31 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s
+// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  --check-prefix SIMD-ONLY18 %s
+// SIMD-ONLY18-NOT: {{__kmpc|__tgt}}
+#ifdef CK31
+
+// CK31-LABEL: @.__omp_offloading_{{.*}}explicit_maps_single{{.*}}_l5305.region_id = weak constant i8 0
+// CK31: [[SIZE00:@.+]] = private {{.*}}constant [1 x i[[Z:64|32]]] [i[[Z:64|32]] 4]
+// CK31: [[MTYPE00:@.+]] = private {{.*}}constant [1 x i64] [i64 1059]
+
+// CK31-LABEL: @.__omp_offloading_{{.*}}explicit_maps_single{{.*}}_l5324.region_id = weak constant i8 0
+// CK31: [[SIZE01:@.+]] = private {{.*}}constant [1 x i[[Z:64|32]]] [i[[Z:64|32]] 4]
+// CK31: [[MTYPE01:@.+]] = private {{.*}}constant [1 x i64] [i64 1063]
+
+// CK31-LABEL: explicit_maps_single{{.*}}(
+void explicit_maps_single (int ii){
+  // Map of a scalar.
+  int a = ii;
+
+  // Close.
+  // Region 00
+  // CK31-DAG: call i32 @__tgt_target(i64 {{[^,]+}}, i8* {{[^,]+}}, i32 1, i8** [[GEPBP:%.+]], i8** [[GEPP:%.+]], {{.+}}getelementptr {{.+}}[1 x i{{.+}}]* [[SIZE00]], {{.+}}getelementptr {{.+}}[1 x i{{.+}}]* [[MTYPE00]]{{.+}})
+  // CK31-DAG: [[GEPBP]] = getelementptr inbounds {{.+}}[[BP:%[^,]+]]
+  // CK31-DAG: [[GEPP]] = getelementptr inbounds {{.+}}[[P:%[^,]+]]
+
+  // CK31-DAG: [[BP0:%.+]] = getelementptr inbounds {{.+}}[[BP]], i{{.+}} 0, i{{.+}} 0
+  // CK31-DAG: [[P0:%.+]] = getelementptr inbounds {{.+}}[[P]], i{{.+}} 0, i{{.+}} 0
+  // CK31-DAG: 

[PATCH] D55719: [OpenMP] parsing and sema support for 'close' map-type-modifier

[Ahsan Saghir via Phabricator via cfe-commits]

saghir updated this revision to Diff 178336.
saghir added a comment.

Made following changes:

- added more tests for checking diagnostic error messages.
- added initialization of modifiers' location in OMPMapClause.
- improved variable names to depict multiple modifiers as opposed to a single 
modifier.
- improved comments.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D55719/new/

https://reviews.llvm.org/D55719

Files:
  clang/include/clang/AST/OpenMPClause.h
  clang/include/clang/Basic/DiagnosticParseKinds.td
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Basic/OpenMPKinds.def
  clang/include/clang/Basic/OpenMPKinds.h
  clang/include/clang/Parse/Parser.h
  clang/include/clang/Sema/Sema.h
  clang/lib/AST/OpenMPClause.cpp
  clang/lib/Basic/OpenMPKinds.cpp
  clang/lib/CodeGen/CGOpenMPRuntime.cpp
  clang/lib/Parse/ParseOpenMP.cpp
  clang/lib/Sema/SemaOpenMP.cpp
  clang/lib/Sema/TreeTransform.h
  clang/lib/Serialization/ASTReader.cpp
  clang/lib/Serialization/ASTWriter.cpp
  clang/test/OpenMP/target_ast_print.cpp
  clang/test/OpenMP/target_data_ast_print.cpp
  clang/test/OpenMP/target_map_messages.cpp
  clang/test/OpenMP/target_parallel_for_map_messages.cpp
  clang/test/OpenMP/target_parallel_for_simd_map_messages.cpp
  clang/test/OpenMP/target_parallel_map_messages.cpp
  clang/test/OpenMP/target_simd_map_messages.cpp
  clang/test/OpenMP/target_teams_distribute_map_messages.cpp
  clang/test/OpenMP/target_teams_distribute_parallel_for_map_messages.cpp
  clang/test/OpenMP/target_teams_distribute_parallel_for_simd_map_messages.cpp
  clang/test/OpenMP/target_teams_distribute_simd_map_messages.cpp
  clang/test/OpenMP/target_teams_map_messages.cpp

Index: clang/test/OpenMP/target_teams_map_messages.cpp
===
--- clang/test/OpenMP/target_teams_map_messages.cpp
+++ clang/test/OpenMP/target_teams_map_messages.cpp
@@ -454,7 +454,7 @@
 
 #pragma omp target data map(always, tofrom: x)
 #pragma omp target data map(always: x) // expected-error {{missing map type}}
-#pragma omp target data map(tofrom, always: x) // expected-error {{incorrect map type modifier, expected 'always'}} expected-error {{incorrect map type, expected one of 'to', 'from', 'tofrom', 'alloc', 'release', or 'delete'}}
+#pragma omp target data map(tofrom, always: x) // expected-error {{incorrect map type modifier, expected 'always' or 'close'}} expected-error {{missing map type}}
 #pragma omp target data map(always, tofrom: always, tofrom, x)
 #pragma omp target teams map(tofrom j) // expected-error {{expected ',' or ')' in 'map' clause}}
   foo();
@@ -529,7 +529,7 @@
 
 #pragma omp target data map(always, tofrom: x)
 #pragma omp target data map(always: x) // expected-error {{missing map type}}
-#pragma omp target data map(tofrom, always: x) // expected-error {{incorrect map type modifier, expected 'always'}} expected-error {{incorrect map type, expected one of 'to', 'from', 'tofrom', 'alloc', 'release', or 'delete'}}
+#pragma omp target data map(tofrom, always: x) // expected-error {{incorrect map type modifier, expected 'always' or 'close'}} expected-error {{missing map type}}
 #pragma omp target data map(always, tofrom: always, tofrom, x)
 #pragma omp target teams map(tofrom j) // expected-error {{expected ',' or ')' in 'map' clause}}
   foo();
Index: clang/test/OpenMP/target_teams_distribute_simd_map_messages.cpp
===
--- clang/test/OpenMP/target_teams_distribute_simd_map_messages.cpp
+++ clang/test/OpenMP/target_teams_distribute_simd_map_messages.cpp
@@ -163,7 +163,7 @@
   for (i = 0; i < argc; ++i) foo();
 #pragma omp target teams distribute simd map(always: x) // expected-error {{missing map type}}
   for (i = 0; i < argc; ++i) foo();
-#pragma omp target teams distribute simd map(tofrom, always: x) // expected-error {{incorrect map type modifier, expected 'always'}} expected-error {{incorrect map type, expected one of 'to', 'from', 'tofrom', 'alloc', 'release', or 'delete'}}
+#pragma omp target teams distribute simd map(tofrom, always: x) // expected-error {{incorrect map type modifier, expected 'always' or 'close'}} expected-error {{missing map type}}
   for (i = 0; i < argc; ++i) foo();
 #pragma omp target teams distribute simd map(always, tofrom: always, tofrom, x)
   for (i = 0; i < argc; ++i) foo();
@@ -271,7 +271,7 @@
   for (i = 0; i < argc; ++i) foo();
 #pragma omp target teams distribute simd map(always: x) // expected-error {{missing map type}}
   for (i = 0; i < argc; ++i) foo();
-#pragma omp target teams distribute simd map(tofrom, always: x) // expected-error {{incorrect map type modifier, expected 'always'}} expected-error {{incorrect map type, expected one of 'to', 'from', 'tofrom', 'alloc', 'release', or 'delete'}}
+#pragma omp target teams distribute simd map(tofrom, always: x) // expected-error {{incorrect map type modifier, expected 'always' or 'close'}} expected-error 

[PATCH] D55719: [OpenMP] parsing and sema support for 'close' map-type-modifier

[Ahsan Saghir via Phabricator via cfe-commits]

saghir created this revision.
saghir added reviewers: ABataev, kkwli0, Hahnfeld, RaviNarayanaswamy, mikerice, 
hfinkel, gtbercea.
saghir added a project: clang.
Herald added subscribers: cfe-commits, guansong.

A map clause with the close map-type-modifier is a hint to prefer that the 
variables are mapped using a copy into faster memory.

Reference: TR7 Section 2.15.8 and 2.22.7.1


Repository:
  rC Clang

https://reviews.llvm.org/D55719

Files:
  clang/include/clang/AST/OpenMPClause.h
  clang/include/clang/Basic/DiagnosticParseKinds.td
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Basic/OpenMPKinds.def
  clang/include/clang/Basic/OpenMPKinds.h
  clang/include/clang/Parse/Parser.h
  clang/include/clang/Sema/Sema.h
  clang/lib/AST/OpenMPClause.cpp
  clang/lib/Basic/OpenMPKinds.cpp
  clang/lib/CodeGen/CGOpenMPRuntime.cpp
  clang/lib/Parse/ParseOpenMP.cpp
  clang/lib/Sema/SemaOpenMP.cpp
  clang/lib/Sema/TreeTransform.h
  clang/lib/Serialization/ASTReader.cpp
  clang/lib/Serialization/ASTWriter.cpp
  clang/test/OpenMP/target_ast_print.cpp
  clang/test/OpenMP/target_data_ast_print.cpp
  clang/test/OpenMP/target_map_messages.cpp
  clang/test/OpenMP/target_parallel_for_map_messages.cpp
  clang/test/OpenMP/target_parallel_for_simd_map_messages.cpp
  clang/test/OpenMP/target_parallel_map_messages.cpp
  clang/test/OpenMP/target_simd_map_messages.cpp
  clang/test/OpenMP/target_teams_distribute_map_messages.cpp
  clang/test/OpenMP/target_teams_distribute_parallel_for_map_messages.cpp
  clang/test/OpenMP/target_teams_distribute_parallel_for_simd_map_messages.cpp
  clang/test/OpenMP/target_teams_distribute_simd_map_messages.cpp
  clang/test/OpenMP/target_teams_map_messages.cpp

Index: clang/test/OpenMP/target_teams_map_messages.cpp
===
--- clang/test/OpenMP/target_teams_map_messages.cpp
+++ clang/test/OpenMP/target_teams_map_messages.cpp
@@ -454,7 +454,7 @@
 
 #pragma omp target data map(always, tofrom: x)
 #pragma omp target data map(always: x) // expected-error {{missing map type}}
-#pragma omp target data map(tofrom, always: x) // expected-error {{incorrect map type modifier, expected 'always'}} expected-error {{incorrect map type, expected one of 'to', 'from', 'tofrom', 'alloc', 'release', or 'delete'}}
+#pragma omp target data map(tofrom, always: x) // expected-error {{incorrect map type modifier, expected 'always' or 'close'}} expected-error {{missing map type}}
 #pragma omp target data map(always, tofrom: always, tofrom, x)
 #pragma omp target teams map(tofrom j) // expected-error {{expected ',' or ')' in 'map' clause}}
   foo();
@@ -529,7 +529,7 @@
 
 #pragma omp target data map(always, tofrom: x)
 #pragma omp target data map(always: x) // expected-error {{missing map type}}
-#pragma omp target data map(tofrom, always: x) // expected-error {{incorrect map type modifier, expected 'always'}} expected-error {{incorrect map type, expected one of 'to', 'from', 'tofrom', 'alloc', 'release', or 'delete'}}
+#pragma omp target data map(tofrom, always: x) // expected-error {{incorrect map type modifier, expected 'always' or 'close'}} expected-error {{missing map type}}
 #pragma omp target data map(always, tofrom: always, tofrom, x)
 #pragma omp target teams map(tofrom j) // expected-error {{expected ',' or ')' in 'map' clause}}
   foo();
Index: clang/test/OpenMP/target_teams_distribute_simd_map_messages.cpp
===
--- clang/test/OpenMP/target_teams_distribute_simd_map_messages.cpp
+++ clang/test/OpenMP/target_teams_distribute_simd_map_messages.cpp
@@ -163,7 +163,7 @@
   for (i = 0; i < argc; ++i) foo();
 #pragma omp target teams distribute simd map(always: x) // expected-error {{missing map type}}
   for (i = 0; i < argc; ++i) foo();
-#pragma omp target teams distribute simd map(tofrom, always: x) // expected-error {{incorrect map type modifier, expected 'always'}} expected-error {{incorrect map type, expected one of 'to', 'from', 'tofrom', 'alloc', 'release', or 'delete'}}
+#pragma omp target teams distribute simd map(tofrom, always: x) // expected-error {{incorrect map type modifier, expected 'always' or 'close'}} expected-error {{missing map type}}
   for (i = 0; i < argc; ++i) foo();
 #pragma omp target teams distribute simd map(always, tofrom: always, tofrom, x)
   for (i = 0; i < argc; ++i) foo();
@@ -271,7 +271,7 @@
   for (i = 0; i < argc; ++i) foo();
 #pragma omp target teams distribute simd map(always: x) // expected-error {{missing map type}}
   for (i = 0; i < argc; ++i) foo();
-#pragma omp target teams distribute simd map(tofrom, always: x) // expected-error {{incorrect map type modifier, expected 'always'}} expected-error {{incorrect map type, expected one of 'to', 'from', 'tofrom', 'alloc', 'release', or 'delete'}}
+#pragma omp target teams distribute simd map(tofrom, always: x) // expected-error {{incorrect map type modifier, expected 'always' or 

[PATCH] D54958: [OPENMP] remove redundant ColonExpected flag in ParseOpenMP.cpp - (NFC)

[Ahsan Saghir via Phabricator via cfe-commits]

saghir created this revision.
saghir added reviewers: ABataev, kkwli0, RaviNarayanaswamy, mikerice, Hahnfeld, 
hfinkel, gtbercea.
saghir added a project: OpenMP.
Herald added subscribers: cfe-commits, guansong.

In ParseOpenMP.cpp:

bool ColonExpected = false;
...
...
...
else if (ColonExpected)

  Diag(Tok, diag::warn_pragma_expected_colon) << "map type";

The flag ColonExpected is not changed after being initialized to false at 
declaration. Hence, the code within the else if is never executed.

We should remove all instances of this flag.


Repository:
  rC Clang

https://reviews.llvm.org/D54958

Files:
  clang/lib/Parse/ParseOpenMP.cpp


Index: clang/lib/Parse/ParseOpenMP.cpp
===
--- clang/lib/Parse/ParseOpenMP.cpp
+++ clang/lib/Parse/ParseOpenMP.cpp
@@ -1867,7 +1867,6 @@
   getOpenMPSimpleClauseType(Kind, PP.getSpelling(Tok)))
 : OMPC_MAP_unknown;
 Data.DepLinMapLoc = Tok.getLocation();
-bool ColonExpected = false;
 
 if (IsMapClauseModifierToken(Tok)) {
   if (PP.LookAhead(0).is(tok::colon)) {
@@ -1935,8 +1934,6 @@
 
 if (Tok.is(tok::colon))
   Data.ColonLoc = ConsumeToken();
-else if (ColonExpected)
-  Diag(Tok, diag::warn_pragma_expected_colon) << "map type";
   }
 
   bool IsComma =


Index: clang/lib/Parse/ParseOpenMP.cpp
===
--- clang/lib/Parse/ParseOpenMP.cpp
+++ clang/lib/Parse/ParseOpenMP.cpp
@@ -1867,7 +1867,6 @@
   getOpenMPSimpleClauseType(Kind, PP.getSpelling(Tok)))
 : OMPC_MAP_unknown;
 Data.DepLinMapLoc = Tok.getLocation();
-bool ColonExpected = false;
 
 if (IsMapClauseModifierToken(Tok)) {
   if (PP.LookAhead(0).is(tok::colon)) {
@@ -1935,8 +1934,6 @@
 
 if (Tok.is(tok::colon))
   Data.ColonLoc = ConsumeToken();
-else if (ColonExpected)
-  Diag(Tok, diag::warn_pragma_expected_colon) << "map type";
   }
 
   bool IsComma =
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[PATCH] D54638: OpenMP: remove redundant MapTypeModifierSpecified flag in ParseOpenMP.cpp

[Ahsan Saghir via Phabricator via cfe-commits]

saghir created this revision.
saghir added reviewers: cfe-commits, ABataev, kkwli0.
saghir added a project: OpenMP.
Herald added a subscriber: guansong.

In the below statement in ParseOpenMP.cpp:

bool IsComma =
1942 (Kind != OMPC_reduction && Kind != OMPC_task_reduction &&
1943 Kind != OMPC_in_reduction && Kind != OMPC_depend && Kind != OMPC_map) ||
1944 (Kind == OMPC_reduction && !InvalidReductionId) ||
1945 (Kind == OMPC_map && Data.MapType != OMPC_MAP_unknown &&
1946 (!MapTypeModifierSpecified ||
1947 Data.MapTypeModifier == OMPC_MAP_always)) ||
1948 (Kind == OMPC_depend && Data.DepKind != OMPC_DEPEND_unknown);

Whenever a map type modifier is specified, the flag MapTypeModifierSpecified is 
set to true.

In the above statement,

1. when there is no map type modifier specified, !MapTypeModifierSpecified 
portion evaluates to true.
2. when the map type modifier is specified, Data.MapTypeModifier == 
OMPC_MAP_always is set to true.

So whether a modifier is specified or not, the condition (highlighted in bold) 
always evaluates to true.

Check for this condition is redundant. Consequently, declaration and all uses 
of MapTypeModifierSpecified should be removed.


Repository:
  rC Clang

https://reviews.llvm.org/D54638

Files:
  clang/lib/Parse/ParseOpenMP.cpp


Index: clang/lib/Parse/ParseOpenMP.cpp
===
--- clang/lib/Parse/ParseOpenMP.cpp
+++ clang/lib/Parse/ParseOpenMP.cpp
@@ -1775,7 +1775,6 @@
 OpenMPVarListDataTy ) {
   UnqualifiedId UnqualifiedReductionId;
   bool InvalidReductionId = false;
-  bool MapTypeModifierSpecified = false;
 
   // Parse '('.
   BalancedDelimiterTracker T(*this, tok::l_paren, 
tok::annot_pragma_openmp_end);
@@ -1878,8 +1877,6 @@
   if (Data.MapTypeModifier != OMPC_MAP_always) {
 Diag(Tok, diag::err_omp_unknown_map_type_modifier);
 Data.MapTypeModifier = OMPC_MAP_unknown;
-  } else {
-MapTypeModifierSpecified = true;
   }
 
   ConsumeToken();
@@ -1904,8 +1901,6 @@
   if (Data.MapTypeModifier != OMPC_MAP_always) {
 Diag(Tok, diag::err_omp_unknown_map_type_modifier);
 Data.MapTypeModifier = OMPC_MAP_unknown;
-  } else {
-MapTypeModifierSpecified = true;
   }
 
   ConsumeToken();
@@ -1942,9 +1937,7 @@
   (Kind != OMPC_reduction && Kind != OMPC_task_reduction &&
Kind != OMPC_in_reduction && Kind != OMPC_depend && Kind != OMPC_map) ||
   (Kind == OMPC_reduction && !InvalidReductionId) ||
-  (Kind == OMPC_map && Data.MapType != OMPC_MAP_unknown &&
-   (!MapTypeModifierSpecified ||
-Data.MapTypeModifier == OMPC_MAP_always)) ||
+  (Kind == OMPC_map && Data.MapType != OMPC_MAP_unknown) ||
   (Kind == OMPC_depend && Data.DepKind != OMPC_DEPEND_unknown);
   const bool MayHaveTail = (Kind == OMPC_linear || Kind == OMPC_aligned);
   while (IsComma || (Tok.isNot(tok::r_paren) && Tok.isNot(tok::colon) &&


Index: clang/lib/Parse/ParseOpenMP.cpp
===
--- clang/lib/Parse/ParseOpenMP.cpp
+++ clang/lib/Parse/ParseOpenMP.cpp
@@ -1775,7 +1775,6 @@
 OpenMPVarListDataTy ) {
   UnqualifiedId UnqualifiedReductionId;
   bool InvalidReductionId = false;
-  bool MapTypeModifierSpecified = false;
 
   // Parse '('.
   BalancedDelimiterTracker T(*this, tok::l_paren, tok::annot_pragma_openmp_end);
@@ -1878,8 +1877,6 @@
   if (Data.MapTypeModifier != OMPC_MAP_always) {
 Diag(Tok, diag::err_omp_unknown_map_type_modifier);
 Data.MapTypeModifier = OMPC_MAP_unknown;
-  } else {
-MapTypeModifierSpecified = true;
   }
 
   ConsumeToken();
@@ -1904,8 +1901,6 @@
   if (Data.MapTypeModifier != OMPC_MAP_always) {
 Diag(Tok, diag::err_omp_unknown_map_type_modifier);
 Data.MapTypeModifier = OMPC_MAP_unknown;
-  } else {
-MapTypeModifierSpecified = true;
   }
 
   ConsumeToken();
@@ -1942,9 +1937,7 @@
   (Kind != OMPC_reduction && Kind != OMPC_task_reduction &&
Kind != OMPC_in_reduction && Kind != OMPC_depend && Kind != OMPC_map) ||
   (Kind == OMPC_reduction && !InvalidReductionId) ||
-  (Kind == OMPC_map && Data.MapType != OMPC_MAP_unknown &&
-   (!MapTypeModifierSpecified ||
-Data.MapTypeModifier == OMPC_MAP_always)) ||
+  (Kind == OMPC_map && Data.MapType != OMPC_MAP_unknown) ||
   (Kind == OMPC_depend && Data.DepKind != OMPC_DEPEND_unknown);
   const bool MayHaveTail = (Kind == OMPC_linear || Kind == OMPC_aligned);
   while (IsComma || (Tok.isNot(tok::r_paren) && Tok.isNot(tok::colon) &&
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